Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PWM device driver for ST SoCs
4 *
5 * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
6 *
7 * Author: Ajit Pal Singh <ajitpal.singh@st.com>
8 * Lee Jones <lee.jones@linaro.org>
9 */
10
11#include <linux/clk.h>
12#include <linux/interrupt.h>
13#include <linux/math64.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/regmap.h>
20#include <linux/sched.h>
21#include <linux/slab.h>
22#include <linux/time.h>
23#include <linux/wait.h>
24
25#define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */
26#define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */
27#define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */
28
29#define STI_PWM_CTRL 0x50 /* Control/Config register */
30#define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */
31#define STI_INT_STA 0x58 /* Interrupt Status register */
32#define PWM_INT_ACK 0x5c
33#define PWM_PRESCALE_LOW_MASK 0x0f
34#define PWM_PRESCALE_HIGH_MASK 0xf0
35#define PWM_CPT_EDGE_MASK 0x03
36#define PWM_INT_ACK_MASK 0x1ff
37
38#define STI_MAX_CPT_DEVS 4
39#define CPT_DC_MAX 0xff
40
41/* Regfield IDs */
42enum {
43 /* Bits in PWM_CTRL*/
44 PWMCLK_PRESCALE_LOW,
45 PWMCLK_PRESCALE_HIGH,
46 CPTCLK_PRESCALE,
47
48 PWM_OUT_EN,
49 PWM_CPT_EN,
50
51 PWM_CPT_INT_EN,
52 PWM_CPT_INT_STAT,
53
54 /* Keep last */
55 MAX_REGFIELDS
56};
57
58/*
59 * Each capture input can be programmed to detect rising-edge, falling-edge,
60 * either edge or neither egde.
61 */
62enum sti_cpt_edge {
63 CPT_EDGE_DISABLED,
64 CPT_EDGE_RISING,
65 CPT_EDGE_FALLING,
66 CPT_EDGE_BOTH,
67};
68
69struct sti_cpt_ddata {
70 u32 snapshot[3];
71 unsigned int index;
72 struct mutex lock;
73 wait_queue_head_t wait;
74};
75
76struct sti_pwm_chip {
77 struct device *dev;
78 struct clk *pwm_clk;
79 struct clk *cpt_clk;
80 struct regmap *regmap;
81 unsigned int pwm_num_devs;
82 unsigned int cpt_num_devs;
83 unsigned int max_pwm_cnt;
84 unsigned int max_prescale;
85 struct sti_cpt_ddata *ddata;
86 struct regmap_field *prescale_low;
87 struct regmap_field *prescale_high;
88 struct regmap_field *pwm_out_en;
89 struct regmap_field *pwm_cpt_en;
90 struct regmap_field *pwm_cpt_int_en;
91 struct regmap_field *pwm_cpt_int_stat;
92 struct pwm_device *cur;
93 unsigned long configured;
94 unsigned int en_count;
95 struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
96 void __iomem *mmio;
97};
98
99static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
100 [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
101 [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
102 [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
103 [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
104 [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
105 [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
106 [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
107};
108
109static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
110{
111 return pwmchip_get_drvdata(chip);
112}
113
114/*
115 * Calculate the prescaler value corresponding to the period.
116 */
117static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
118 unsigned int *prescale)
119{
120 unsigned long clk_rate;
121 unsigned long value;
122 unsigned int ps;
123
124 clk_rate = clk_get_rate(pc->pwm_clk);
125 if (!clk_rate) {
126 dev_err(pc->dev, "failed to get clock rate\n");
127 return -EINVAL;
128 }
129
130 /*
131 * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1
132 */
133 value = NSEC_PER_SEC / clk_rate;
134 value *= pc->max_pwm_cnt + 1;
135
136 if (period % value)
137 return -EINVAL;
138
139 ps = period / value - 1;
140 if (ps > pc->max_prescale)
141 return -EINVAL;
142
143 *prescale = ps;
144
145 return 0;
146}
147
148/*
149 * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The
150 * only way to change the period (apart from changing the PWM input clock) is
151 * to change the PWM clock prescaler.
152 *
153 * The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible
154 * period values are supported (for a particular clock rate). The requested
155 * period will be applied only if it matches one of these 256 values.
156 */
157static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
158 int duty_ns, int period_ns)
159{
160 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
161 unsigned int ncfg, value, prescale = 0;
162 struct pwm_device *cur = pc->cur;
163 struct device *dev = pc->dev;
164 bool period_same = false;
165 int ret;
166
167 ncfg = hweight_long(pc->configured);
168 if (ncfg)
169 period_same = (period_ns == pwm_get_period(cur));
170
171 /*
172 * Allow configuration changes if one of the following conditions
173 * satisfy.
174 * 1. No devices have been configured.
175 * 2. Only one device has been configured and the new request is for
176 * the same device.
177 * 3. Only one device has been configured and the new request is for
178 * a new device and period of the new device is same as the current
179 * configured period.
180 * 4. More than one devices are configured and period of the new
181 * requestis the same as the current period.
182 */
183 if (!ncfg ||
184 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
185 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
186 ((ncfg > 1) && period_same)) {
187 /* Enable clock before writing to PWM registers. */
188 ret = clk_enable(pc->pwm_clk);
189 if (ret)
190 return ret;
191
192 ret = clk_enable(pc->cpt_clk);
193 if (ret)
194 return ret;
195
196 if (!period_same) {
197 ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
198 if (ret)
199 goto clk_dis;
200
201 value = prescale & PWM_PRESCALE_LOW_MASK;
202
203 ret = regmap_field_write(pc->prescale_low, value);
204 if (ret)
205 goto clk_dis;
206
207 value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4;
208
209 ret = regmap_field_write(pc->prescale_high, value);
210 if (ret)
211 goto clk_dis;
212 }
213
214 /*
215 * When PWMVal == 0, PWM pulse = 1 local clock cycle.
216 * When PWMVal == max_pwm_count,
217 * PWM pulse = (max_pwm_count + 1) local cycles,
218 * that is continuous pulse: signal never goes low.
219 */
220 value = pc->max_pwm_cnt * duty_ns / period_ns;
221
222 ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value);
223 if (ret)
224 goto clk_dis;
225
226 ret = regmap_field_write(pc->pwm_cpt_int_en, 0);
227
228 set_bit(pwm->hwpwm, &pc->configured);
229 pc->cur = pwm;
230
231 dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n",
232 prescale, period_ns, duty_ns, value);
233 } else {
234 return -EINVAL;
235 }
236
237clk_dis:
238 clk_disable(pc->pwm_clk);
239 clk_disable(pc->cpt_clk);
240 return ret;
241}
242
243static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
244{
245 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
246 struct device *dev = pc->dev;
247 int ret = 0;
248
249 /*
250 * Since we have a common enable for all PWM devices, do not enable if
251 * already enabled.
252 */
253 mutex_lock(&pc->sti_pwm_lock);
254
255 if (!pc->en_count) {
256 ret = clk_enable(pc->pwm_clk);
257 if (ret)
258 goto out;
259
260 ret = clk_enable(pc->cpt_clk);
261 if (ret)
262 goto out;
263
264 ret = regmap_field_write(pc->pwm_out_en, 1);
265 if (ret) {
266 dev_err(dev, "failed to enable PWM device %u: %d\n",
267 pwm->hwpwm, ret);
268 goto out;
269 }
270 }
271
272 pc->en_count++;
273
274out:
275 mutex_unlock(&pc->sti_pwm_lock);
276 return ret;
277}
278
279static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
280{
281 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
282
283 mutex_lock(&pc->sti_pwm_lock);
284
285 if (--pc->en_count) {
286 mutex_unlock(&pc->sti_pwm_lock);
287 return;
288 }
289
290 regmap_field_write(pc->pwm_out_en, 0);
291
292 clk_disable(pc->pwm_clk);
293 clk_disable(pc->cpt_clk);
294
295 mutex_unlock(&pc->sti_pwm_lock);
296}
297
298static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
299{
300 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
301
302 clear_bit(pwm->hwpwm, &pc->configured);
303}
304
305static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
306 struct pwm_capture *result, unsigned long timeout)
307{
308 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
309 struct sti_cpt_ddata *ddata = &pc->ddata[pwm->hwpwm];
310 struct device *dev = pc->dev;
311 unsigned int effective_ticks;
312 unsigned long long high, low;
313 int ret;
314
315 if (pwm->hwpwm >= pc->cpt_num_devs) {
316 dev_err(dev, "device %u is not valid\n", pwm->hwpwm);
317 return -EINVAL;
318 }
319
320 mutex_lock(&ddata->lock);
321 ddata->index = 0;
322
323 /* Prepare capture measurement */
324 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING);
325 regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm));
326
327 /* Enable capture */
328 ret = regmap_field_write(pc->pwm_cpt_en, 1);
329 if (ret) {
330 dev_err(dev, "failed to enable PWM capture %u: %d\n",
331 pwm->hwpwm, ret);
332 goto out;
333 }
334
335 ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1,
336 msecs_to_jiffies(timeout));
337
338 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED);
339
340 if (ret == -ERESTARTSYS)
341 goto out;
342
343 switch (ddata->index) {
344 case 0:
345 case 1:
346 /*
347 * Getting here could mean:
348 * - input signal is constant of less than 1 Hz
349 * - there is no input signal at all
350 *
351 * In such case the frequency is rounded down to 0
352 */
353 result->period = 0;
354 result->duty_cycle = 0;
355
356 break;
357
358 case 2:
359 /* We have everying we need */
360 high = ddata->snapshot[1] - ddata->snapshot[0];
361 low = ddata->snapshot[2] - ddata->snapshot[1];
362
363 effective_ticks = clk_get_rate(pc->cpt_clk);
364
365 result->period = (high + low) * NSEC_PER_SEC;
366 result->period /= effective_ticks;
367
368 result->duty_cycle = high * NSEC_PER_SEC;
369 result->duty_cycle /= effective_ticks;
370
371 break;
372
373 default:
374 dev_err(dev, "internal error\n");
375 break;
376 }
377
378out:
379 /* Disable capture */
380 regmap_field_write(pc->pwm_cpt_en, 0);
381
382 mutex_unlock(&ddata->lock);
383 return ret;
384}
385
386static int sti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
387 const struct pwm_state *state)
388{
389 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
390 struct device *dev = pc->dev;
391 int err;
392
393 if (pwm->hwpwm >= pc->pwm_num_devs) {
394 dev_err(dev, "device %u is not valid for pwm mode\n",
395 pwm->hwpwm);
396 return -EINVAL;
397 }
398
399 if (state->polarity != PWM_POLARITY_NORMAL)
400 return -EINVAL;
401
402 if (!state->enabled) {
403 if (pwm->state.enabled)
404 sti_pwm_disable(chip, pwm);
405
406 return 0;
407 }
408
409 err = sti_pwm_config(chip, pwm, state->duty_cycle, state->period);
410 if (err)
411 return err;
412
413 if (!pwm->state.enabled)
414 err = sti_pwm_enable(chip, pwm);
415
416 return err;
417}
418
419static const struct pwm_ops sti_pwm_ops = {
420 .capture = sti_pwm_capture,
421 .apply = sti_pwm_apply,
422 .free = sti_pwm_free,
423};
424
425static irqreturn_t sti_pwm_interrupt(int irq, void *data)
426{
427 struct sti_pwm_chip *pc = data;
428 struct device *dev = pc->dev;
429 struct sti_cpt_ddata *ddata;
430 int devicenum;
431 unsigned int cpt_int_stat;
432 unsigned int reg;
433 int ret = IRQ_NONE;
434
435 ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat);
436 if (ret)
437 return ret;
438
439 while (cpt_int_stat) {
440 devicenum = ffs(cpt_int_stat) - 1;
441
442 ddata = &pc->ddata[devicenum];
443
444 /*
445 * Capture input:
446 * _______ _______
447 * | | | |
448 * __| |_________________| |________
449 * ^0 ^1 ^2
450 *
451 * Capture start by the first available rising edge. When a
452 * capture event occurs, capture value (CPT_VALx) is stored,
453 * index incremented, capture edge changed.
454 *
455 * After the capture, if the index > 1, we have collected the
456 * necessary data so we signal the thread waiting for it and
457 * disable the capture by setting capture edge to none
458 */
459
460 regmap_read(pc->regmap,
461 PWM_CPT_VAL(devicenum),
462 &ddata->snapshot[ddata->index]);
463
464 switch (ddata->index) {
465 case 0:
466 case 1:
467 regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), ®);
468 reg ^= PWM_CPT_EDGE_MASK;
469 regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg);
470
471 ddata->index++;
472 break;
473
474 case 2:
475 regmap_write(pc->regmap,
476 PWM_CPT_EDGE(devicenum),
477 CPT_EDGE_DISABLED);
478 wake_up(&ddata->wait);
479 break;
480
481 default:
482 dev_err(dev, "Internal error\n");
483 }
484
485 cpt_int_stat &= ~BIT_MASK(devicenum);
486
487 ret = IRQ_HANDLED;
488 }
489
490 /* Just ACK everything */
491 regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK);
492
493 return ret;
494}
495
496static int sti_pwm_probe_regmap(struct sti_pwm_chip *pc)
497{
498 struct device *dev = pc->dev;
499
500 pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
501 sti_pwm_regfields[PWMCLK_PRESCALE_LOW]);
502 if (IS_ERR(pc->prescale_low))
503 return PTR_ERR(pc->prescale_low);
504
505 pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
506 sti_pwm_regfields[PWMCLK_PRESCALE_HIGH]);
507 if (IS_ERR(pc->prescale_high))
508 return PTR_ERR(pc->prescale_high);
509
510 pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
511 sti_pwm_regfields[PWM_OUT_EN]);
512 if (IS_ERR(pc->pwm_out_en))
513 return PTR_ERR(pc->pwm_out_en);
514
515 pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap,
516 sti_pwm_regfields[PWM_CPT_EN]);
517 if (IS_ERR(pc->pwm_cpt_en))
518 return PTR_ERR(pc->pwm_cpt_en);
519
520 pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
521 sti_pwm_regfields[PWM_CPT_INT_EN]);
522 if (IS_ERR(pc->pwm_cpt_int_en))
523 return PTR_ERR(pc->pwm_cpt_int_en);
524
525 pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap,
526 sti_pwm_regfields[PWM_CPT_INT_STAT]);
527 if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat))
528 return PTR_ERR(pc->pwm_cpt_int_stat);
529
530 return 0;
531}
532
533static const struct regmap_config sti_pwm_regmap_config = {
534 .reg_bits = 32,
535 .val_bits = 32,
536 .reg_stride = 4,
537};
538
539static int sti_pwm_probe(struct platform_device *pdev)
540{
541 struct device *dev = &pdev->dev;
542 struct device_node *np = dev->of_node;
543 u32 num_devs;
544 unsigned int pwm_num_devs = 0;
545 unsigned int cpt_num_devs = 0;
546 struct pwm_chip *chip;
547 struct sti_pwm_chip *pc;
548 unsigned int i;
549 int irq, ret;
550
551 ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
552 if (!ret)
553 pwm_num_devs = num_devs;
554
555 ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs);
556 if (!ret)
557 cpt_num_devs = num_devs;
558
559 if (!pwm_num_devs && !cpt_num_devs)
560 return dev_err_probe(dev, -EINVAL, "No channels configured\n");
561
562 chip = devm_pwmchip_alloc(dev, max(pwm_num_devs, cpt_num_devs), sizeof(*pc));
563 if (IS_ERR(chip))
564 return PTR_ERR(chip);
565 pc = to_sti_pwmchip(chip);
566
567 pc->mmio = devm_platform_ioremap_resource(pdev, 0);
568 if (IS_ERR(pc->mmio))
569 return PTR_ERR(pc->mmio);
570
571 pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
572 &sti_pwm_regmap_config);
573 if (IS_ERR(pc->regmap))
574 return dev_err_probe(dev, PTR_ERR(pc->regmap),
575 "Failed to initialize regmap\n");
576
577 irq = platform_get_irq(pdev, 0);
578 if (irq < 0)
579 return irq;
580
581 ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0,
582 pdev->name, pc);
583 if (ret < 0)
584 dev_err_probe(&pdev->dev, ret, "Failed to request IRQ\n");
585
586 /*
587 * Setup PWM data with default values: some values could be replaced
588 * with specific ones provided from Device Tree.
589 */
590 pc->max_prescale = 0xff;
591 pc->max_pwm_cnt = 255;
592 pc->pwm_num_devs = pwm_num_devs;
593 pc->cpt_num_devs = cpt_num_devs;
594
595 pc->dev = dev;
596 pc->en_count = 0;
597 mutex_init(&pc->sti_pwm_lock);
598
599 ret = sti_pwm_probe_regmap(pc);
600 if (ret)
601 return dev_err_probe(dev, ret, "Failed to initialize regmap fields\n");
602
603 if (pwm_num_devs) {
604 pc->pwm_clk = devm_clk_get_prepared(dev, "pwm");
605 if (IS_ERR(pc->pwm_clk))
606 return dev_err_probe(dev, PTR_ERR(pc->pwm_clk),
607 "failed to get PWM clock\n");
608 }
609
610 if (cpt_num_devs) {
611 pc->cpt_clk = devm_clk_get_prepared(dev, "capture");
612 if (IS_ERR(pc->cpt_clk))
613 return dev_err_probe(dev, PTR_ERR(pc->cpt_clk),
614 "failed to get PWM capture clock\n");
615
616 pc->ddata = devm_kcalloc(dev, cpt_num_devs,
617 sizeof(*pc->ddata), GFP_KERNEL);
618 if (!pc->ddata)
619 return -ENOMEM;
620
621 for (i = 0; i < cpt_num_devs; i++) {
622 struct sti_cpt_ddata *ddata = &pc->ddata[i];
623
624 init_waitqueue_head(&ddata->wait);
625 mutex_init(&ddata->lock);
626 }
627 }
628
629 chip->ops = &sti_pwm_ops;
630
631 ret = devm_pwmchip_add(dev, chip);
632 if (ret)
633 return dev_err_probe(dev, ret, "Failed to register pwm chip\n");
634
635 return 0;
636}
637
638static const struct of_device_id sti_pwm_of_match[] = {
639 { .compatible = "st,sti-pwm", },
640 { /* sentinel */ }
641};
642MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
643
644static struct platform_driver sti_pwm_driver = {
645 .driver = {
646 .name = "sti-pwm",
647 .of_match_table = sti_pwm_of_match,
648 },
649 .probe = sti_pwm_probe,
650};
651module_platform_driver(sti_pwm_driver);
652
653MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
654MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
655MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PWM device driver for ST SoCs
4 *
5 * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
6 *
7 * Author: Ajit Pal Singh <ajitpal.singh@st.com>
8 * Lee Jones <lee.jones@linaro.org>
9 */
10
11#include <linux/clk.h>
12#include <linux/interrupt.h>
13#include <linux/math64.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/regmap.h>
20#include <linux/sched.h>
21#include <linux/slab.h>
22#include <linux/time.h>
23#include <linux/wait.h>
24
25#define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */
26#define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */
27#define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */
28
29#define STI_PWM_CTRL 0x50 /* Control/Config register */
30#define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */
31#define STI_INT_STA 0x58 /* Interrupt Status register */
32#define PWM_INT_ACK 0x5c
33#define PWM_PRESCALE_LOW_MASK 0x0f
34#define PWM_PRESCALE_HIGH_MASK 0xf0
35#define PWM_CPT_EDGE_MASK 0x03
36#define PWM_INT_ACK_MASK 0x1ff
37
38#define STI_MAX_CPT_DEVS 4
39#define CPT_DC_MAX 0xff
40
41/* Regfield IDs */
42enum {
43 /* Bits in PWM_CTRL*/
44 PWMCLK_PRESCALE_LOW,
45 PWMCLK_PRESCALE_HIGH,
46 CPTCLK_PRESCALE,
47
48 PWM_OUT_EN,
49 PWM_CPT_EN,
50
51 PWM_CPT_INT_EN,
52 PWM_CPT_INT_STAT,
53
54 /* Keep last */
55 MAX_REGFIELDS
56};
57
58/*
59 * Each capture input can be programmed to detect rising-edge, falling-edge,
60 * either edge or neither egde.
61 */
62enum sti_cpt_edge {
63 CPT_EDGE_DISABLED,
64 CPT_EDGE_RISING,
65 CPT_EDGE_FALLING,
66 CPT_EDGE_BOTH,
67};
68
69struct sti_cpt_ddata {
70 u32 snapshot[3];
71 unsigned int index;
72 struct mutex lock;
73 wait_queue_head_t wait;
74};
75
76struct sti_pwm_compat_data {
77 const struct reg_field *reg_fields;
78 unsigned int pwm_num_devs;
79 unsigned int cpt_num_devs;
80 unsigned int max_pwm_cnt;
81 unsigned int max_prescale;
82 struct sti_cpt_ddata *ddata;
83};
84
85struct sti_pwm_chip {
86 struct device *dev;
87 struct clk *pwm_clk;
88 struct clk *cpt_clk;
89 struct regmap *regmap;
90 struct sti_pwm_compat_data *cdata;
91 struct regmap_field *prescale_low;
92 struct regmap_field *prescale_high;
93 struct regmap_field *pwm_out_en;
94 struct regmap_field *pwm_cpt_en;
95 struct regmap_field *pwm_cpt_int_en;
96 struct regmap_field *pwm_cpt_int_stat;
97 struct pwm_chip chip;
98 struct pwm_device *cur;
99 unsigned long configured;
100 unsigned int en_count;
101 struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
102 void __iomem *mmio;
103};
104
105static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
106 [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
107 [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
108 [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
109 [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
110 [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
111 [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
112 [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
113};
114
115static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
116{
117 return container_of(chip, struct sti_pwm_chip, chip);
118}
119
120/*
121 * Calculate the prescaler value corresponding to the period.
122 */
123static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
124 unsigned int *prescale)
125{
126 struct sti_pwm_compat_data *cdata = pc->cdata;
127 unsigned long clk_rate;
128 unsigned long value;
129 unsigned int ps;
130
131 clk_rate = clk_get_rate(pc->pwm_clk);
132 if (!clk_rate) {
133 dev_err(pc->dev, "failed to get clock rate\n");
134 return -EINVAL;
135 }
136
137 /*
138 * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1
139 */
140 value = NSEC_PER_SEC / clk_rate;
141 value *= cdata->max_pwm_cnt + 1;
142
143 if (period % value)
144 return -EINVAL;
145
146 ps = period / value - 1;
147 if (ps > cdata->max_prescale)
148 return -EINVAL;
149
150 *prescale = ps;
151
152 return 0;
153}
154
155/*
156 * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The
157 * only way to change the period (apart from changing the PWM input clock) is
158 * to change the PWM clock prescaler.
159 *
160 * The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible
161 * period values are supported (for a particular clock rate). The requested
162 * period will be applied only if it matches one of these 256 values.
163 */
164static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
165 int duty_ns, int period_ns)
166{
167 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
168 struct sti_pwm_compat_data *cdata = pc->cdata;
169 unsigned int ncfg, value, prescale = 0;
170 struct pwm_device *cur = pc->cur;
171 struct device *dev = pc->dev;
172 bool period_same = false;
173 int ret;
174
175 ncfg = hweight_long(pc->configured);
176 if (ncfg)
177 period_same = (period_ns == pwm_get_period(cur));
178
179 /*
180 * Allow configuration changes if one of the following conditions
181 * satisfy.
182 * 1. No devices have been configured.
183 * 2. Only one device has been configured and the new request is for
184 * the same device.
185 * 3. Only one device has been configured and the new request is for
186 * a new device and period of the new device is same as the current
187 * configured period.
188 * 4. More than one devices are configured and period of the new
189 * requestis the same as the current period.
190 */
191 if (!ncfg ||
192 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
193 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
194 ((ncfg > 1) && period_same)) {
195 /* Enable clock before writing to PWM registers. */
196 ret = clk_enable(pc->pwm_clk);
197 if (ret)
198 return ret;
199
200 ret = clk_enable(pc->cpt_clk);
201 if (ret)
202 return ret;
203
204 if (!period_same) {
205 ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
206 if (ret)
207 goto clk_dis;
208
209 value = prescale & PWM_PRESCALE_LOW_MASK;
210
211 ret = regmap_field_write(pc->prescale_low, value);
212 if (ret)
213 goto clk_dis;
214
215 value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4;
216
217 ret = regmap_field_write(pc->prescale_high, value);
218 if (ret)
219 goto clk_dis;
220 }
221
222 /*
223 * When PWMVal == 0, PWM pulse = 1 local clock cycle.
224 * When PWMVal == max_pwm_count,
225 * PWM pulse = (max_pwm_count + 1) local cycles,
226 * that is continuous pulse: signal never goes low.
227 */
228 value = cdata->max_pwm_cnt * duty_ns / period_ns;
229
230 ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value);
231 if (ret)
232 goto clk_dis;
233
234 ret = regmap_field_write(pc->pwm_cpt_int_en, 0);
235
236 set_bit(pwm->hwpwm, &pc->configured);
237 pc->cur = pwm;
238
239 dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n",
240 prescale, period_ns, duty_ns, value);
241 } else {
242 return -EINVAL;
243 }
244
245clk_dis:
246 clk_disable(pc->pwm_clk);
247 clk_disable(pc->cpt_clk);
248 return ret;
249}
250
251static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
252{
253 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
254 struct device *dev = pc->dev;
255 int ret = 0;
256
257 /*
258 * Since we have a common enable for all PWM devices, do not enable if
259 * already enabled.
260 */
261 mutex_lock(&pc->sti_pwm_lock);
262
263 if (!pc->en_count) {
264 ret = clk_enable(pc->pwm_clk);
265 if (ret)
266 goto out;
267
268 ret = clk_enable(pc->cpt_clk);
269 if (ret)
270 goto out;
271
272 ret = regmap_field_write(pc->pwm_out_en, 1);
273 if (ret) {
274 dev_err(dev, "failed to enable PWM device %u: %d\n",
275 pwm->hwpwm, ret);
276 goto out;
277 }
278 }
279
280 pc->en_count++;
281
282out:
283 mutex_unlock(&pc->sti_pwm_lock);
284 return ret;
285}
286
287static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
288{
289 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
290
291 mutex_lock(&pc->sti_pwm_lock);
292
293 if (--pc->en_count) {
294 mutex_unlock(&pc->sti_pwm_lock);
295 return;
296 }
297
298 regmap_field_write(pc->pwm_out_en, 0);
299
300 clk_disable(pc->pwm_clk);
301 clk_disable(pc->cpt_clk);
302
303 mutex_unlock(&pc->sti_pwm_lock);
304}
305
306static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
307{
308 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
309
310 clear_bit(pwm->hwpwm, &pc->configured);
311}
312
313static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
314 struct pwm_capture *result, unsigned long timeout)
315{
316 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
317 struct sti_pwm_compat_data *cdata = pc->cdata;
318 struct sti_cpt_ddata *ddata = &cdata->ddata[pwm->hwpwm];
319 struct device *dev = pc->dev;
320 unsigned int effective_ticks;
321 unsigned long long high, low;
322 int ret;
323
324 if (pwm->hwpwm >= cdata->cpt_num_devs) {
325 dev_err(dev, "device %u is not valid\n", pwm->hwpwm);
326 return -EINVAL;
327 }
328
329 mutex_lock(&ddata->lock);
330 ddata->index = 0;
331
332 /* Prepare capture measurement */
333 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING);
334 regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm));
335
336 /* Enable capture */
337 ret = regmap_field_write(pc->pwm_cpt_en, 1);
338 if (ret) {
339 dev_err(dev, "failed to enable PWM capture %u: %d\n",
340 pwm->hwpwm, ret);
341 goto out;
342 }
343
344 ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1,
345 msecs_to_jiffies(timeout));
346
347 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED);
348
349 if (ret == -ERESTARTSYS)
350 goto out;
351
352 switch (ddata->index) {
353 case 0:
354 case 1:
355 /*
356 * Getting here could mean:
357 * - input signal is constant of less than 1 Hz
358 * - there is no input signal at all
359 *
360 * In such case the frequency is rounded down to 0
361 */
362 result->period = 0;
363 result->duty_cycle = 0;
364
365 break;
366
367 case 2:
368 /* We have everying we need */
369 high = ddata->snapshot[1] - ddata->snapshot[0];
370 low = ddata->snapshot[2] - ddata->snapshot[1];
371
372 effective_ticks = clk_get_rate(pc->cpt_clk);
373
374 result->period = (high + low) * NSEC_PER_SEC;
375 result->period /= effective_ticks;
376
377 result->duty_cycle = high * NSEC_PER_SEC;
378 result->duty_cycle /= effective_ticks;
379
380 break;
381
382 default:
383 dev_err(dev, "internal error\n");
384 break;
385 }
386
387out:
388 /* Disable capture */
389 regmap_field_write(pc->pwm_cpt_en, 0);
390
391 mutex_unlock(&ddata->lock);
392 return ret;
393}
394
395static int sti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
396 const struct pwm_state *state)
397{
398 int err;
399
400 if (state->polarity != PWM_POLARITY_NORMAL)
401 return -EINVAL;
402
403 if (!state->enabled) {
404 if (pwm->state.enabled)
405 sti_pwm_disable(chip, pwm);
406
407 return 0;
408 }
409
410 err = sti_pwm_config(chip, pwm, state->duty_cycle, state->period);
411 if (err)
412 return err;
413
414 if (!pwm->state.enabled)
415 err = sti_pwm_enable(chip, pwm);
416
417 return err;
418}
419
420static const struct pwm_ops sti_pwm_ops = {
421 .capture = sti_pwm_capture,
422 .apply = sti_pwm_apply,
423 .free = sti_pwm_free,
424};
425
426static irqreturn_t sti_pwm_interrupt(int irq, void *data)
427{
428 struct sti_pwm_chip *pc = data;
429 struct device *dev = pc->dev;
430 struct sti_cpt_ddata *ddata;
431 int devicenum;
432 unsigned int cpt_int_stat;
433 unsigned int reg;
434 int ret = IRQ_NONE;
435
436 ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat);
437 if (ret)
438 return ret;
439
440 while (cpt_int_stat) {
441 devicenum = ffs(cpt_int_stat) - 1;
442
443 ddata = &pc->cdata->ddata[devicenum];
444
445 /*
446 * Capture input:
447 * _______ _______
448 * | | | |
449 * __| |_________________| |________
450 * ^0 ^1 ^2
451 *
452 * Capture start by the first available rising edge. When a
453 * capture event occurs, capture value (CPT_VALx) is stored,
454 * index incremented, capture edge changed.
455 *
456 * After the capture, if the index > 1, we have collected the
457 * necessary data so we signal the thread waiting for it and
458 * disable the capture by setting capture edge to none
459 */
460
461 regmap_read(pc->regmap,
462 PWM_CPT_VAL(devicenum),
463 &ddata->snapshot[ddata->index]);
464
465 switch (ddata->index) {
466 case 0:
467 case 1:
468 regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), ®);
469 reg ^= PWM_CPT_EDGE_MASK;
470 regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg);
471
472 ddata->index++;
473 break;
474
475 case 2:
476 regmap_write(pc->regmap,
477 PWM_CPT_EDGE(devicenum),
478 CPT_EDGE_DISABLED);
479 wake_up(&ddata->wait);
480 break;
481
482 default:
483 dev_err(dev, "Internal error\n");
484 }
485
486 cpt_int_stat &= ~BIT_MASK(devicenum);
487
488 ret = IRQ_HANDLED;
489 }
490
491 /* Just ACK everything */
492 regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK);
493
494 return ret;
495}
496
497static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
498{
499 struct device *dev = pc->dev;
500 const struct reg_field *reg_fields;
501 struct device_node *np = dev->of_node;
502 struct sti_pwm_compat_data *cdata = pc->cdata;
503 u32 num_devs;
504 int ret;
505
506 ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
507 if (!ret)
508 cdata->pwm_num_devs = num_devs;
509
510 ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs);
511 if (!ret)
512 cdata->cpt_num_devs = num_devs;
513
514 if (!cdata->pwm_num_devs && !cdata->cpt_num_devs) {
515 dev_err(dev, "No channels configured\n");
516 return -EINVAL;
517 }
518
519 reg_fields = cdata->reg_fields;
520
521 pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
522 reg_fields[PWMCLK_PRESCALE_LOW]);
523 if (IS_ERR(pc->prescale_low))
524 return PTR_ERR(pc->prescale_low);
525
526 pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
527 reg_fields[PWMCLK_PRESCALE_HIGH]);
528 if (IS_ERR(pc->prescale_high))
529 return PTR_ERR(pc->prescale_high);
530
531 pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
532 reg_fields[PWM_OUT_EN]);
533 if (IS_ERR(pc->pwm_out_en))
534 return PTR_ERR(pc->pwm_out_en);
535
536 pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap,
537 reg_fields[PWM_CPT_EN]);
538 if (IS_ERR(pc->pwm_cpt_en))
539 return PTR_ERR(pc->pwm_cpt_en);
540
541 pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
542 reg_fields[PWM_CPT_INT_EN]);
543 if (IS_ERR(pc->pwm_cpt_int_en))
544 return PTR_ERR(pc->pwm_cpt_int_en);
545
546 pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap,
547 reg_fields[PWM_CPT_INT_STAT]);
548 if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat))
549 return PTR_ERR(pc->pwm_cpt_int_stat);
550
551 return 0;
552}
553
554static const struct regmap_config sti_pwm_regmap_config = {
555 .reg_bits = 32,
556 .val_bits = 32,
557 .reg_stride = 4,
558};
559
560static int sti_pwm_probe(struct platform_device *pdev)
561{
562 struct device *dev = &pdev->dev;
563 struct sti_pwm_compat_data *cdata;
564 struct sti_pwm_chip *pc;
565 unsigned int i;
566 int irq, ret;
567
568 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
569 if (!pc)
570 return -ENOMEM;
571
572 cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
573 if (!cdata)
574 return -ENOMEM;
575
576 pc->mmio = devm_platform_ioremap_resource(pdev, 0);
577 if (IS_ERR(pc->mmio))
578 return PTR_ERR(pc->mmio);
579
580 pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
581 &sti_pwm_regmap_config);
582 if (IS_ERR(pc->regmap))
583 return PTR_ERR(pc->regmap);
584
585 irq = platform_get_irq(pdev, 0);
586 if (irq < 0)
587 return irq;
588
589 ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0,
590 pdev->name, pc);
591 if (ret < 0) {
592 dev_err(&pdev->dev, "Failed to request IRQ\n");
593 return ret;
594 }
595
596 /*
597 * Setup PWM data with default values: some values could be replaced
598 * with specific ones provided from Device Tree.
599 */
600 cdata->reg_fields = sti_pwm_regfields;
601 cdata->max_prescale = 0xff;
602 cdata->max_pwm_cnt = 255;
603 cdata->pwm_num_devs = 0;
604 cdata->cpt_num_devs = 0;
605
606 pc->cdata = cdata;
607 pc->dev = dev;
608 pc->en_count = 0;
609 mutex_init(&pc->sti_pwm_lock);
610
611 ret = sti_pwm_probe_dt(pc);
612 if (ret)
613 return ret;
614
615 if (cdata->pwm_num_devs) {
616 pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm");
617 if (IS_ERR(pc->pwm_clk)) {
618 dev_err(dev, "failed to get PWM clock\n");
619 return PTR_ERR(pc->pwm_clk);
620 }
621
622 ret = clk_prepare(pc->pwm_clk);
623 if (ret) {
624 dev_err(dev, "failed to prepare clock\n");
625 return ret;
626 }
627 }
628
629 if (cdata->cpt_num_devs) {
630 pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture");
631 if (IS_ERR(pc->cpt_clk)) {
632 dev_err(dev, "failed to get PWM capture clock\n");
633 return PTR_ERR(pc->cpt_clk);
634 }
635
636 ret = clk_prepare(pc->cpt_clk);
637 if (ret) {
638 dev_err(dev, "failed to prepare clock\n");
639 return ret;
640 }
641
642 cdata->ddata = devm_kzalloc(dev, cdata->cpt_num_devs * sizeof(*cdata->ddata), GFP_KERNEL);
643 if (!cdata->ddata)
644 return -ENOMEM;
645 }
646
647 pc->chip.dev = dev;
648 pc->chip.ops = &sti_pwm_ops;
649 pc->chip.npwm = pc->cdata->pwm_num_devs;
650
651 for (i = 0; i < cdata->cpt_num_devs; i++) {
652 struct sti_cpt_ddata *ddata = &cdata->ddata[i];
653
654 init_waitqueue_head(&ddata->wait);
655 mutex_init(&ddata->lock);
656 }
657
658 ret = pwmchip_add(&pc->chip);
659 if (ret < 0) {
660 clk_unprepare(pc->pwm_clk);
661 clk_unprepare(pc->cpt_clk);
662 return ret;
663 }
664
665 platform_set_drvdata(pdev, pc);
666
667 return 0;
668}
669
670static void sti_pwm_remove(struct platform_device *pdev)
671{
672 struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
673
674 pwmchip_remove(&pc->chip);
675
676 clk_unprepare(pc->pwm_clk);
677 clk_unprepare(pc->cpt_clk);
678}
679
680static const struct of_device_id sti_pwm_of_match[] = {
681 { .compatible = "st,sti-pwm", },
682 { /* sentinel */ }
683};
684MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
685
686static struct platform_driver sti_pwm_driver = {
687 .driver = {
688 .name = "sti-pwm",
689 .of_match_table = sti_pwm_of_match,
690 },
691 .probe = sti_pwm_probe,
692 .remove_new = sti_pwm_remove,
693};
694module_platform_driver(sti_pwm_driver);
695
696MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
697MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
698MODULE_LICENSE("GPL");