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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2015 - 2016 Cavium, Inc.
4 */
5
6#include <linux/bitfield.h>
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/of_address.h>
11#include <linux/of_pci.h>
12#include <linux/pci-acpi.h>
13#include <linux/pci-ecam.h>
14#include <linux/platform_device.h>
15#include <linux/io-64-nonatomic-lo-hi.h>
16#include "../pci.h"
17
18#if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
19
20#define PEM_CFG_WR 0x28
21#define PEM_CFG_RD 0x30
22
23/*
24 * Enhanced Configuration Access Mechanism (ECAM)
25 *
26 * N.B. This is a non-standard platform-specific ECAM bus shift value. For
27 * standard values defined in the PCI Express Base Specification see
28 * include/linux/pci-ecam.h.
29 */
30#define THUNDER_PCIE_ECAM_BUS_SHIFT 24
31
32struct thunder_pem_pci {
33 u32 ea_entry[3];
34 void __iomem *pem_reg_base;
35};
36
37static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
38 int where, int size, u32 *val)
39{
40 u64 read_val, tmp_val;
41 struct pci_config_window *cfg = bus->sysdata;
42 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
43
44 if (devfn != 0 || where >= 2048)
45 return PCIBIOS_DEVICE_NOT_FOUND;
46
47 /*
48 * 32-bit accesses only. Write the address to the low order
49 * bits of PEM_CFG_RD, then trigger the read by reading back.
50 * The config data lands in the upper 32-bits of PEM_CFG_RD.
51 */
52 read_val = where & ~3ull;
53 writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
54 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
55 read_val >>= 32;
56
57 /*
58 * The config space contains some garbage, fix it up. Also
59 * synthesize an EA capability for the BAR used by MSI-X.
60 */
61 switch (where & ~3) {
62 case 0x40:
63 read_val &= 0xffff00ff;
64 read_val |= 0x00007000; /* Skip MSI CAP */
65 break;
66 case 0x70: /* Express Cap */
67 /*
68 * Change PME interrupt to vector 2 on T88 where it
69 * reads as 0, else leave it alone.
70 */
71 if (!(read_val & (0x1f << 25)))
72 read_val |= (2u << 25);
73 break;
74 case 0xb0: /* MSI-X Cap */
75 /* TableSize=2 or 4, Next Cap is EA */
76 read_val &= 0xc00000ff;
77 /*
78 * If Express Cap(0x70) raw PME vector reads as 0 we are on
79 * T88 and TableSize is reported as 4, else TableSize
80 * is 2.
81 */
82 writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
83 tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
84 tmp_val >>= 32;
85 if (!(tmp_val & (0x1f << 25)))
86 read_val |= 0x0003bc00;
87 else
88 read_val |= 0x0001bc00;
89 break;
90 case 0xb4:
91 /* Table offset=0, BIR=0 */
92 read_val = 0x00000000;
93 break;
94 case 0xb8:
95 /* BPA offset=0xf0000, BIR=0 */
96 read_val = 0x000f0000;
97 break;
98 case 0xbc:
99 /* EA, 1 entry, no next Cap */
100 read_val = 0x00010014;
101 break;
102 case 0xc0:
103 /* DW2 for type-1 */
104 read_val = 0x00000000;
105 break;
106 case 0xc4:
107 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
108 read_val = 0x80ff0003;
109 break;
110 case 0xc8:
111 read_val = pem_pci->ea_entry[0];
112 break;
113 case 0xcc:
114 read_val = pem_pci->ea_entry[1];
115 break;
116 case 0xd0:
117 read_val = pem_pci->ea_entry[2];
118 break;
119 default:
120 break;
121 }
122 read_val >>= (8 * (where & 3));
123 switch (size) {
124 case 1:
125 read_val &= 0xff;
126 break;
127 case 2:
128 read_val &= 0xffff;
129 break;
130 default:
131 break;
132 }
133 *val = read_val;
134 return PCIBIOS_SUCCESSFUL;
135}
136
137static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
138 int where, int size, u32 *val)
139{
140 struct pci_config_window *cfg = bus->sysdata;
141
142 if (bus->number < cfg->busr.start ||
143 bus->number > cfg->busr.end)
144 return PCIBIOS_DEVICE_NOT_FOUND;
145
146 /*
147 * The first device on the bus is the PEM PCIe bridge.
148 * Special case its config access.
149 */
150 if (bus->number == cfg->busr.start)
151 return thunder_pem_bridge_read(bus, devfn, where, size, val);
152
153 return pci_generic_config_read(bus, devfn, where, size, val);
154}
155
156/*
157 * Some of the w1c_bits below also include read-only or non-writable
158 * reserved bits, this makes the code simpler and is OK as the bits
159 * are not affected by writing zeros to them.
160 */
161static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
162{
163 u32 w1c_bits = 0;
164
165 switch (where_aligned) {
166 case 0x04: /* Command/Status */
167 case 0x1c: /* Base and I/O Limit/Secondary Status */
168 w1c_bits = 0xff000000;
169 break;
170 case 0x44: /* Power Management Control and Status */
171 w1c_bits = 0xfffffe00;
172 break;
173 case 0x78: /* Device Control/Device Status */
174 case 0x80: /* Link Control/Link Status */
175 case 0x88: /* Slot Control/Slot Status */
176 case 0x90: /* Root Status */
177 case 0xa0: /* Link Control 2 Registers/Link Status 2 */
178 w1c_bits = 0xffff0000;
179 break;
180 case 0x104: /* Uncorrectable Error Status */
181 case 0x110: /* Correctable Error Status */
182 case 0x130: /* Error Status */
183 case 0x160: /* Link Control 4 */
184 w1c_bits = 0xffffffff;
185 break;
186 default:
187 break;
188 }
189 return w1c_bits;
190}
191
192/* Some bits must be written to one so they appear to be read-only. */
193static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
194{
195 u32 w1_bits;
196
197 switch (where_aligned) {
198 case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
199 /* Force 32-bit I/O addressing. */
200 w1_bits = 0x0101;
201 break;
202 case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
203 /* Force 64-bit addressing */
204 w1_bits = 0x00010001;
205 break;
206 default:
207 w1_bits = 0;
208 break;
209 }
210 return w1_bits;
211}
212
213static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
214 int where, int size, u32 val)
215{
216 struct pci_config_window *cfg = bus->sysdata;
217 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
218 u64 write_val, read_val;
219 u64 where_aligned = where & ~3ull;
220 u32 mask = 0;
221
222
223 if (devfn != 0 || where >= 2048)
224 return PCIBIOS_DEVICE_NOT_FOUND;
225
226 /*
227 * 32-bit accesses only. If the write is for a size smaller
228 * than 32-bits, we must first read the 32-bit value and merge
229 * in the desired bits and then write the whole 32-bits back
230 * out.
231 */
232 switch (size) {
233 case 1:
234 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
235 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
236 read_val >>= 32;
237 mask = ~(0xff << (8 * (where & 3)));
238 read_val &= mask;
239 val = (val & 0xff) << (8 * (where & 3));
240 val |= (u32)read_val;
241 break;
242 case 2:
243 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
244 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
245 read_val >>= 32;
246 mask = ~(0xffff << (8 * (where & 3)));
247 read_val &= mask;
248 val = (val & 0xffff) << (8 * (where & 3));
249 val |= (u32)read_val;
250 break;
251 default:
252 break;
253 }
254
255 /*
256 * By expanding the write width to 32 bits, we may
257 * inadvertently hit some W1C bits that were not intended to
258 * be written. Calculate the mask that must be applied to the
259 * data to be written to avoid these cases.
260 */
261 if (mask) {
262 u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
263
264 if (w1c_bits) {
265 mask &= w1c_bits;
266 val &= ~mask;
267 }
268 }
269
270 /*
271 * Some bits must be read-only with value of one. Since the
272 * access method allows these to be cleared if a zero is
273 * written, force them to one before writing.
274 */
275 val |= thunder_pem_bridge_w1_bits(where_aligned);
276
277 /*
278 * Low order bits are the config address, the high order 32
279 * bits are the data to be written.
280 */
281 write_val = (((u64)val) << 32) | where_aligned;
282 writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
283 return PCIBIOS_SUCCESSFUL;
284}
285
286static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
287 int where, int size, u32 val)
288{
289 struct pci_config_window *cfg = bus->sysdata;
290
291 if (bus->number < cfg->busr.start ||
292 bus->number > cfg->busr.end)
293 return PCIBIOS_DEVICE_NOT_FOUND;
294 /*
295 * The first device on the bus is the PEM PCIe bridge.
296 * Special case its config access.
297 */
298 if (bus->number == cfg->busr.start)
299 return thunder_pem_bridge_write(bus, devfn, where, size, val);
300
301
302 return pci_generic_config_write(bus, devfn, where, size, val);
303}
304
305static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
306 struct resource *res_pem)
307{
308 struct thunder_pem_pci *pem_pci;
309 resource_size_t bar4_start;
310
311 pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
312 if (!pem_pci)
313 return -ENOMEM;
314
315 pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
316 if (!pem_pci->pem_reg_base)
317 return -ENOMEM;
318
319 /*
320 * The MSI-X BAR for the PEM and AER interrupts is located at
321 * a fixed offset from the PEM register base. Generate a
322 * fragment of the synthesized Enhanced Allocation capability
323 * structure here for the BAR.
324 */
325 bar4_start = res_pem->start + 0xf00000;
326 pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
327 pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
328 pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
329
330 cfg->priv = pem_pci;
331 return 0;
332}
333
334#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
335
336#define PEM_RES_BASE 0x87e0c0000000ULL
337#define PEM_NODE_MASK GENMASK_ULL(45, 44)
338#define PEM_INDX_MASK GENMASK_ULL(26, 24)
339#define PEM_MIN_DOM_IN_NODE 4
340#define PEM_MAX_DOM_IN_NODE 10
341
342static void thunder_pem_reserve_range(struct device *dev, int seg,
343 struct resource *r)
344{
345 resource_size_t start = r->start, end = r->end;
346 struct resource *res;
347 const char *regionid;
348
349 regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
350 if (!regionid)
351 return;
352
353 res = request_mem_region(start, end - start + 1, regionid);
354 if (res)
355 res->flags &= ~IORESOURCE_BUSY;
356 else
357 kfree(regionid);
358
359 dev_info(dev, "%pR %s reserved\n", r,
360 res ? "has been" : "could not be");
361}
362
363static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
364 struct resource *res_pem)
365{
366 int node = acpi_get_node(root->device->handle);
367 int index;
368
369 if (node == NUMA_NO_NODE)
370 node = 0;
371
372 index = root->segment - PEM_MIN_DOM_IN_NODE;
373 index -= node * PEM_MAX_DOM_IN_NODE;
374 res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
375 FIELD_PREP(PEM_INDX_MASK, index);
376 res_pem->flags = IORESOURCE_MEM;
377}
378
379static int thunder_pem_acpi_init(struct pci_config_window *cfg)
380{
381 struct device *dev = cfg->parent;
382 struct acpi_device *adev = to_acpi_device(dev);
383 struct acpi_pci_root *root = acpi_driver_data(adev);
384 struct resource *res_pem;
385 int ret;
386
387 res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
388 if (!res_pem)
389 return -ENOMEM;
390
391 ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
392
393 /*
394 * If we fail to gather resources it means that we run with old
395 * FW where we need to calculate PEM-specific resources manually.
396 */
397 if (ret) {
398 thunder_pem_legacy_fw(root, res_pem);
399 /*
400 * Reserve 64K size PEM specific resources. The full 16M range
401 * size is required for thunder_pem_init() call.
402 */
403 resource_set_size(res_pem, SZ_64K);
404 thunder_pem_reserve_range(dev, root->segment, res_pem);
405 resource_set_size(res_pem, SZ_16M);
406
407 /* Reserve PCI configuration space as well. */
408 thunder_pem_reserve_range(dev, root->segment, &cfg->res);
409 }
410
411 return thunder_pem_init(dev, cfg, res_pem);
412}
413
414const struct pci_ecam_ops thunder_pem_ecam_ops = {
415 .bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT,
416 .init = thunder_pem_acpi_init,
417 .pci_ops = {
418 .map_bus = pci_ecam_map_bus,
419 .read = thunder_pem_config_read,
420 .write = thunder_pem_config_write,
421 }
422};
423
424#endif
425
426#ifdef CONFIG_PCI_HOST_THUNDER_PEM
427
428static int thunder_pem_platform_init(struct pci_config_window *cfg)
429{
430 struct device *dev = cfg->parent;
431 struct platform_device *pdev = to_platform_device(dev);
432 struct resource *res_pem;
433
434 if (!dev->of_node)
435 return -EINVAL;
436
437 /*
438 * The second register range is the PEM bridge to the PCIe
439 * bus. It has a different config access method than those
440 * devices behind the bridge.
441 */
442 res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
443 if (!res_pem) {
444 dev_err(dev, "missing \"reg[1]\"property\n");
445 return -EINVAL;
446 }
447
448 return thunder_pem_init(dev, cfg, res_pem);
449}
450
451static const struct pci_ecam_ops pci_thunder_pem_ops = {
452 .bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT,
453 .init = thunder_pem_platform_init,
454 .pci_ops = {
455 .map_bus = pci_ecam_map_bus,
456 .read = thunder_pem_config_read,
457 .write = thunder_pem_config_write,
458 }
459};
460
461static const struct of_device_id thunder_pem_of_match[] = {
462 {
463 .compatible = "cavium,pci-host-thunder-pem",
464 .data = &pci_thunder_pem_ops,
465 },
466 { },
467};
468
469static struct platform_driver thunder_pem_driver = {
470 .driver = {
471 .name = KBUILD_MODNAME,
472 .of_match_table = thunder_pem_of_match,
473 .suppress_bind_attrs = true,
474 },
475 .probe = pci_host_common_probe,
476};
477builtin_platform_driver(thunder_pem_driver);
478
479#endif
480#endif
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2015 - 2016 Cavium, Inc.
4 */
5
6#include <linux/bitfield.h>
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/of_address.h>
11#include <linux/of_pci.h>
12#include <linux/pci-acpi.h>
13#include <linux/pci-ecam.h>
14#include <linux/platform_device.h>
15#include <linux/io-64-nonatomic-lo-hi.h>
16#include "../pci.h"
17
18#if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
19
20#define PEM_CFG_WR 0x28
21#define PEM_CFG_RD 0x30
22
23/*
24 * Enhanced Configuration Access Mechanism (ECAM)
25 *
26 * N.B. This is a non-standard platform-specific ECAM bus shift value. For
27 * standard values defined in the PCI Express Base Specification see
28 * include/linux/pci-ecam.h.
29 */
30#define THUNDER_PCIE_ECAM_BUS_SHIFT 24
31
32struct thunder_pem_pci {
33 u32 ea_entry[3];
34 void __iomem *pem_reg_base;
35};
36
37static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
38 int where, int size, u32 *val)
39{
40 u64 read_val, tmp_val;
41 struct pci_config_window *cfg = bus->sysdata;
42 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
43
44 if (devfn != 0 || where >= 2048)
45 return PCIBIOS_DEVICE_NOT_FOUND;
46
47 /*
48 * 32-bit accesses only. Write the address to the low order
49 * bits of PEM_CFG_RD, then trigger the read by reading back.
50 * The config data lands in the upper 32-bits of PEM_CFG_RD.
51 */
52 read_val = where & ~3ull;
53 writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
54 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
55 read_val >>= 32;
56
57 /*
58 * The config space contains some garbage, fix it up. Also
59 * synthesize an EA capability for the BAR used by MSI-X.
60 */
61 switch (where & ~3) {
62 case 0x40:
63 read_val &= 0xffff00ff;
64 read_val |= 0x00007000; /* Skip MSI CAP */
65 break;
66 case 0x70: /* Express Cap */
67 /*
68 * Change PME interrupt to vector 2 on T88 where it
69 * reads as 0, else leave it alone.
70 */
71 if (!(read_val & (0x1f << 25)))
72 read_val |= (2u << 25);
73 break;
74 case 0xb0: /* MSI-X Cap */
75 /* TableSize=2 or 4, Next Cap is EA */
76 read_val &= 0xc00000ff;
77 /*
78 * If Express Cap(0x70) raw PME vector reads as 0 we are on
79 * T88 and TableSize is reported as 4, else TableSize
80 * is 2.
81 */
82 writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
83 tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
84 tmp_val >>= 32;
85 if (!(tmp_val & (0x1f << 25)))
86 read_val |= 0x0003bc00;
87 else
88 read_val |= 0x0001bc00;
89 break;
90 case 0xb4:
91 /* Table offset=0, BIR=0 */
92 read_val = 0x00000000;
93 break;
94 case 0xb8:
95 /* BPA offset=0xf0000, BIR=0 */
96 read_val = 0x000f0000;
97 break;
98 case 0xbc:
99 /* EA, 1 entry, no next Cap */
100 read_val = 0x00010014;
101 break;
102 case 0xc0:
103 /* DW2 for type-1 */
104 read_val = 0x00000000;
105 break;
106 case 0xc4:
107 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
108 read_val = 0x80ff0003;
109 break;
110 case 0xc8:
111 read_val = pem_pci->ea_entry[0];
112 break;
113 case 0xcc:
114 read_val = pem_pci->ea_entry[1];
115 break;
116 case 0xd0:
117 read_val = pem_pci->ea_entry[2];
118 break;
119 default:
120 break;
121 }
122 read_val >>= (8 * (where & 3));
123 switch (size) {
124 case 1:
125 read_val &= 0xff;
126 break;
127 case 2:
128 read_val &= 0xffff;
129 break;
130 default:
131 break;
132 }
133 *val = read_val;
134 return PCIBIOS_SUCCESSFUL;
135}
136
137static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
138 int where, int size, u32 *val)
139{
140 struct pci_config_window *cfg = bus->sysdata;
141
142 if (bus->number < cfg->busr.start ||
143 bus->number > cfg->busr.end)
144 return PCIBIOS_DEVICE_NOT_FOUND;
145
146 /*
147 * The first device on the bus is the PEM PCIe bridge.
148 * Special case its config access.
149 */
150 if (bus->number == cfg->busr.start)
151 return thunder_pem_bridge_read(bus, devfn, where, size, val);
152
153 return pci_generic_config_read(bus, devfn, where, size, val);
154}
155
156/*
157 * Some of the w1c_bits below also include read-only or non-writable
158 * reserved bits, this makes the code simpler and is OK as the bits
159 * are not affected by writing zeros to them.
160 */
161static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
162{
163 u32 w1c_bits = 0;
164
165 switch (where_aligned) {
166 case 0x04: /* Command/Status */
167 case 0x1c: /* Base and I/O Limit/Secondary Status */
168 w1c_bits = 0xff000000;
169 break;
170 case 0x44: /* Power Management Control and Status */
171 w1c_bits = 0xfffffe00;
172 break;
173 case 0x78: /* Device Control/Device Status */
174 case 0x80: /* Link Control/Link Status */
175 case 0x88: /* Slot Control/Slot Status */
176 case 0x90: /* Root Status */
177 case 0xa0: /* Link Control 2 Registers/Link Status 2 */
178 w1c_bits = 0xffff0000;
179 break;
180 case 0x104: /* Uncorrectable Error Status */
181 case 0x110: /* Correctable Error Status */
182 case 0x130: /* Error Status */
183 case 0x160: /* Link Control 4 */
184 w1c_bits = 0xffffffff;
185 break;
186 default:
187 break;
188 }
189 return w1c_bits;
190}
191
192/* Some bits must be written to one so they appear to be read-only. */
193static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
194{
195 u32 w1_bits;
196
197 switch (where_aligned) {
198 case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
199 /* Force 32-bit I/O addressing. */
200 w1_bits = 0x0101;
201 break;
202 case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
203 /* Force 64-bit addressing */
204 w1_bits = 0x00010001;
205 break;
206 default:
207 w1_bits = 0;
208 break;
209 }
210 return w1_bits;
211}
212
213static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
214 int where, int size, u32 val)
215{
216 struct pci_config_window *cfg = bus->sysdata;
217 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
218 u64 write_val, read_val;
219 u64 where_aligned = where & ~3ull;
220 u32 mask = 0;
221
222
223 if (devfn != 0 || where >= 2048)
224 return PCIBIOS_DEVICE_NOT_FOUND;
225
226 /*
227 * 32-bit accesses only. If the write is for a size smaller
228 * than 32-bits, we must first read the 32-bit value and merge
229 * in the desired bits and then write the whole 32-bits back
230 * out.
231 */
232 switch (size) {
233 case 1:
234 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
235 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
236 read_val >>= 32;
237 mask = ~(0xff << (8 * (where & 3)));
238 read_val &= mask;
239 val = (val & 0xff) << (8 * (where & 3));
240 val |= (u32)read_val;
241 break;
242 case 2:
243 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
244 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
245 read_val >>= 32;
246 mask = ~(0xffff << (8 * (where & 3)));
247 read_val &= mask;
248 val = (val & 0xffff) << (8 * (where & 3));
249 val |= (u32)read_val;
250 break;
251 default:
252 break;
253 }
254
255 /*
256 * By expanding the write width to 32 bits, we may
257 * inadvertently hit some W1C bits that were not intended to
258 * be written. Calculate the mask that must be applied to the
259 * data to be written to avoid these cases.
260 */
261 if (mask) {
262 u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
263
264 if (w1c_bits) {
265 mask &= w1c_bits;
266 val &= ~mask;
267 }
268 }
269
270 /*
271 * Some bits must be read-only with value of one. Since the
272 * access method allows these to be cleared if a zero is
273 * written, force them to one before writing.
274 */
275 val |= thunder_pem_bridge_w1_bits(where_aligned);
276
277 /*
278 * Low order bits are the config address, the high order 32
279 * bits are the data to be written.
280 */
281 write_val = (((u64)val) << 32) | where_aligned;
282 writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
283 return PCIBIOS_SUCCESSFUL;
284}
285
286static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
287 int where, int size, u32 val)
288{
289 struct pci_config_window *cfg = bus->sysdata;
290
291 if (bus->number < cfg->busr.start ||
292 bus->number > cfg->busr.end)
293 return PCIBIOS_DEVICE_NOT_FOUND;
294 /*
295 * The first device on the bus is the PEM PCIe bridge.
296 * Special case its config access.
297 */
298 if (bus->number == cfg->busr.start)
299 return thunder_pem_bridge_write(bus, devfn, where, size, val);
300
301
302 return pci_generic_config_write(bus, devfn, where, size, val);
303}
304
305static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
306 struct resource *res_pem)
307{
308 struct thunder_pem_pci *pem_pci;
309 resource_size_t bar4_start;
310
311 pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
312 if (!pem_pci)
313 return -ENOMEM;
314
315 pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
316 if (!pem_pci->pem_reg_base)
317 return -ENOMEM;
318
319 /*
320 * The MSI-X BAR for the PEM and AER interrupts is located at
321 * a fixed offset from the PEM register base. Generate a
322 * fragment of the synthesized Enhanced Allocation capability
323 * structure here for the BAR.
324 */
325 bar4_start = res_pem->start + 0xf00000;
326 pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
327 pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
328 pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
329
330 cfg->priv = pem_pci;
331 return 0;
332}
333
334#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
335
336#define PEM_RES_BASE 0x87e0c0000000ULL
337#define PEM_NODE_MASK GENMASK_ULL(45, 44)
338#define PEM_INDX_MASK GENMASK_ULL(26, 24)
339#define PEM_MIN_DOM_IN_NODE 4
340#define PEM_MAX_DOM_IN_NODE 10
341
342static void thunder_pem_reserve_range(struct device *dev, int seg,
343 struct resource *r)
344{
345 resource_size_t start = r->start, end = r->end;
346 struct resource *res;
347 const char *regionid;
348
349 regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
350 if (!regionid)
351 return;
352
353 res = request_mem_region(start, end - start + 1, regionid);
354 if (res)
355 res->flags &= ~IORESOURCE_BUSY;
356 else
357 kfree(regionid);
358
359 dev_info(dev, "%pR %s reserved\n", r,
360 res ? "has been" : "could not be");
361}
362
363static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
364 struct resource *res_pem)
365{
366 int node = acpi_get_node(root->device->handle);
367 int index;
368
369 if (node == NUMA_NO_NODE)
370 node = 0;
371
372 index = root->segment - PEM_MIN_DOM_IN_NODE;
373 index -= node * PEM_MAX_DOM_IN_NODE;
374 res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
375 FIELD_PREP(PEM_INDX_MASK, index);
376 res_pem->flags = IORESOURCE_MEM;
377}
378
379static int thunder_pem_acpi_init(struct pci_config_window *cfg)
380{
381 struct device *dev = cfg->parent;
382 struct acpi_device *adev = to_acpi_device(dev);
383 struct acpi_pci_root *root = acpi_driver_data(adev);
384 struct resource *res_pem;
385 int ret;
386
387 res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
388 if (!res_pem)
389 return -ENOMEM;
390
391 ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
392
393 /*
394 * If we fail to gather resources it means that we run with old
395 * FW where we need to calculate PEM-specific resources manually.
396 */
397 if (ret) {
398 thunder_pem_legacy_fw(root, res_pem);
399 /*
400 * Reserve 64K size PEM specific resources. The full 16M range
401 * size is required for thunder_pem_init() call.
402 */
403 res_pem->end = res_pem->start + SZ_64K - 1;
404 thunder_pem_reserve_range(dev, root->segment, res_pem);
405 res_pem->end = res_pem->start + SZ_16M - 1;
406
407 /* Reserve PCI configuration space as well. */
408 thunder_pem_reserve_range(dev, root->segment, &cfg->res);
409 }
410
411 return thunder_pem_init(dev, cfg, res_pem);
412}
413
414const struct pci_ecam_ops thunder_pem_ecam_ops = {
415 .bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT,
416 .init = thunder_pem_acpi_init,
417 .pci_ops = {
418 .map_bus = pci_ecam_map_bus,
419 .read = thunder_pem_config_read,
420 .write = thunder_pem_config_write,
421 }
422};
423
424#endif
425
426#ifdef CONFIG_PCI_HOST_THUNDER_PEM
427
428static int thunder_pem_platform_init(struct pci_config_window *cfg)
429{
430 struct device *dev = cfg->parent;
431 struct platform_device *pdev = to_platform_device(dev);
432 struct resource *res_pem;
433
434 if (!dev->of_node)
435 return -EINVAL;
436
437 /*
438 * The second register range is the PEM bridge to the PCIe
439 * bus. It has a different config access method than those
440 * devices behind the bridge.
441 */
442 res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
443 if (!res_pem) {
444 dev_err(dev, "missing \"reg[1]\"property\n");
445 return -EINVAL;
446 }
447
448 return thunder_pem_init(dev, cfg, res_pem);
449}
450
451static const struct pci_ecam_ops pci_thunder_pem_ops = {
452 .bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT,
453 .init = thunder_pem_platform_init,
454 .pci_ops = {
455 .map_bus = pci_ecam_map_bus,
456 .read = thunder_pem_config_read,
457 .write = thunder_pem_config_write,
458 }
459};
460
461static const struct of_device_id thunder_pem_of_match[] = {
462 {
463 .compatible = "cavium,pci-host-thunder-pem",
464 .data = &pci_thunder_pem_ops,
465 },
466 { },
467};
468
469static struct platform_driver thunder_pem_driver = {
470 .driver = {
471 .name = KBUILD_MODNAME,
472 .of_match_table = thunder_pem_of_match,
473 .suppress_bind_attrs = true,
474 },
475 .probe = pci_host_common_probe,
476};
477builtin_platform_driver(thunder_pem_driver);
478
479#endif
480#endif