1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * PCIe host controller driver for Freescale i.MX6 SoCs
   4 *
   5 * Copyright (C) 2013 Kosagi
   6 *		https://www.kosagi.com
   7 *
   8 * Author: Sean Cross <xobs@kosagi.com>
   9 */
  10
  11#include <linux/bitfield.h>
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/gpio/consumer.h>
  15#include <linux/kernel.h>
  16#include <linux/mfd/syscon.h>
  17#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  18#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
  19#include <linux/module.h>
  20#include <linux/of.h>
 
  21#include <linux/of_address.h>
  22#include <linux/pci.h>
  23#include <linux/platform_device.h>
  24#include <linux/regmap.h>
  25#include <linux/regulator/consumer.h>
  26#include <linux/resource.h>
  27#include <linux/signal.h>
  28#include <linux/types.h>
  29#include <linux/interrupt.h>
  30#include <linux/reset.h>
  31#include <linux/phy/pcie.h>
  32#include <linux/phy/phy.h>
  33#include <linux/pm_domain.h>
  34#include <linux/pm_runtime.h>
  35
  36#include "pcie-designware.h"
  37
  38#define IMX8MQ_GPR_PCIE_REF_USE_PAD		BIT(9)
  39#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN	BIT(10)
  40#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE	BIT(11)
  41#define IMX8MQ_GPR_PCIE_VREG_BYPASS		BIT(12)
  42#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE	GENMASK(11, 8)
  43#define IMX8MQ_PCIE2_BASE_ADDR			0x33c00000
  44
  45#define IMX95_PCIE_PHY_GEN_CTRL			0x0
  46#define IMX95_PCIE_REF_USE_PAD			BIT(17)
  47
  48#define IMX95_PCIE_SS_RW_REG_0			0xf0
  49#define IMX95_PCIE_REF_CLKEN			BIT(23)
  50#define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
  51
  52#define IMX95_PE0_GEN_CTRL_1			0x1050
  53#define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
  54
  55#define IMX95_PE0_GEN_CTRL_3			0x1058
  56#define IMX95_PCIE_LTSSM_EN			BIT(0)
  57
  58#define to_imx_pcie(x)	dev_get_drvdata((x)->dev)
  59
  60enum imx_pcie_variants {
  61	IMX6Q,
  62	IMX6SX,
  63	IMX6QP,
  64	IMX7D,
  65	IMX8MQ,
  66	IMX8MM,
  67	IMX8MP,
  68	IMX8Q,
  69	IMX95,
  70	IMX8MQ_EP,
  71	IMX8MM_EP,
  72	IMX8MP_EP,
  73	IMX95_EP,
  74};
  75
  76#define IMX_PCIE_FLAG_IMX_PHY			BIT(0)
  77#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE		BIT(1)
  78#define IMX_PCIE_FLAG_SUPPORTS_SUSPEND		BIT(2)
  79#define IMX_PCIE_FLAG_HAS_PHYDRV		BIT(3)
  80#define IMX_PCIE_FLAG_HAS_APP_RESET		BIT(4)
  81#define IMX_PCIE_FLAG_HAS_PHY_RESET		BIT(5)
  82#define IMX_PCIE_FLAG_HAS_SERDES		BIT(6)
  83#define IMX_PCIE_FLAG_SUPPORT_64BIT		BIT(7)
  84#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP		BIT(8)
  85/*
  86 * Because of ERR005723 (PCIe does not support L2 power down) we need to
  87 * workaround suspend resume on some devices which are affected by this errata.
  88 */
  89#define IMX_PCIE_FLAG_BROKEN_SUSPEND		BIT(9)
  90
  91#define imx_check_flag(pci, val)	(pci->drvdata->flags & val)
  92
  93#define IMX_PCIE_MAX_CLKS	6
  94#define IMX_PCIE_MAX_INSTANCES	2
  95
  96struct imx_pcie;
  97
  98struct imx_pcie_drvdata {
  99	enum imx_pcie_variants variant;
 100	enum dw_pcie_device_mode mode;
 101	u32 flags;
 102	int dbi_length;
 103	const char *gpr;
 104	const char * const *clk_names;
 105	const u32 clks_cnt;
 106	const u32 ltssm_off;
 107	const u32 ltssm_mask;
 108	const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
 109	const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
 110	const struct pci_epc_features *epc_features;
 111	int (*init_phy)(struct imx_pcie *pcie);
 112	int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
 113	int (*core_reset)(struct imx_pcie *pcie, bool assert);
 114};
 115
 116struct imx_pcie {
 117	struct dw_pcie		*pci;
 118	struct gpio_desc	*reset_gpiod;
 
 119	bool			link_is_up;
 120	struct clk_bulk_data	clks[IMX_PCIE_MAX_CLKS];
 
 
 
 
 121	struct regmap		*iomuxc_gpr;
 122	u16			msi_ctrl;
 123	u32			controller_id;
 124	struct reset_control	*pciephy_reset;
 125	struct reset_control	*apps_reset;
 126	struct reset_control	*turnoff_reset;
 127	u32			tx_deemph_gen1;
 128	u32			tx_deemph_gen2_3p5db;
 129	u32			tx_deemph_gen2_6db;
 130	u32			tx_swing_full;
 131	u32			tx_swing_low;
 132	struct regulator	*vpcie;
 133	struct regulator	*vph;
 134	void __iomem		*phy_base;
 135
 136	/* power domain for pcie */
 137	struct device		*pd_pcie;
 138	/* power domain for pcie phy */
 139	struct device		*pd_pcie_phy;
 140	struct phy		*phy;
 141	const struct imx_pcie_drvdata *drvdata;
 142};
 143
 144/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
 145#define PHY_PLL_LOCK_WAIT_USLEEP_MAX	200
 146#define PHY_PLL_LOCK_WAIT_TIMEOUT	(2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
 147
 148/* PCIe Port Logic registers (memory-mapped) */
 149#define PL_OFFSET 0x700
 150
 151#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
 152#define PCIE_PHY_CTRL_DATA(x)		FIELD_PREP(GENMASK(15, 0), (x))
 153#define PCIE_PHY_CTRL_CAP_ADR		BIT(16)
 154#define PCIE_PHY_CTRL_CAP_DAT		BIT(17)
 155#define PCIE_PHY_CTRL_WR		BIT(18)
 156#define PCIE_PHY_CTRL_RD		BIT(19)
 157
 158#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
 159#define PCIE_PHY_STAT_ACK		BIT(16)
 160
 161/* PHY registers (not memory-mapped) */
 162#define PCIE_PHY_ATEOVRD			0x10
 163#define  PCIE_PHY_ATEOVRD_EN			BIT(2)
 164#define  PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT	0
 165#define  PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK	0x1
 166
 167#define PCIE_PHY_MPLL_OVRD_IN_LO		0x11
 168#define  PCIE_PHY_MPLL_MULTIPLIER_SHIFT		2
 169#define  PCIE_PHY_MPLL_MULTIPLIER_MASK		0x7f
 170#define  PCIE_PHY_MPLL_MULTIPLIER_OVRD		BIT(9)
 171
 172#define PCIE_PHY_RX_ASIC_OUT 0x100D
 173#define PCIE_PHY_RX_ASIC_OUT_VALID	(1 << 0)
 174
 175/* iMX7 PCIe PHY registers */
 176#define PCIE_PHY_CMN_REG4		0x14
 177/* These are probably the bits that *aren't* DCC_FB_EN */
 178#define PCIE_PHY_CMN_REG4_DCC_FB_EN	0x29
 179
 180#define PCIE_PHY_CMN_REG15	        0x54
 181#define PCIE_PHY_CMN_REG15_DLY_4	BIT(2)
 182#define PCIE_PHY_CMN_REG15_PLL_PD	BIT(5)
 183#define PCIE_PHY_CMN_REG15_OVRD_PLL_PD	BIT(7)
 184
 185#define PCIE_PHY_CMN_REG24		0x90
 186#define PCIE_PHY_CMN_REG24_RX_EQ	BIT(6)
 187#define PCIE_PHY_CMN_REG24_RX_EQ_SEL	BIT(3)
 188
 189#define PCIE_PHY_CMN_REG26		0x98
 190#define PCIE_PHY_CMN_REG26_ATT_MODE	0xBC
 191
 192#define PHY_RX_OVRD_IN_LO 0x1005
 193#define PHY_RX_OVRD_IN_LO_RX_DATA_EN		BIT(5)
 194#define PHY_RX_OVRD_IN_LO_RX_PLL_EN		BIT(3)
 195
 196static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 197{
 198	WARN_ON(imx_pcie->drvdata->variant != IMX8MQ &&
 199		imx_pcie->drvdata->variant != IMX8MQ_EP &&
 200		imx_pcie->drvdata->variant != IMX8MM &&
 201		imx_pcie->drvdata->variant != IMX8MM_EP &&
 202		imx_pcie->drvdata->variant != IMX8MP &&
 203		imx_pcie->drvdata->variant != IMX8MP_EP);
 204	return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 205}
 206
 207static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 208{
 209	regmap_update_bits(imx_pcie->iomuxc_gpr,
 210			IMX95_PCIE_SS_RW_REG_0,
 211			IMX95_PCIE_PHY_CR_PARA_SEL,
 212			IMX95_PCIE_PHY_CR_PARA_SEL);
 213
 214	regmap_update_bits(imx_pcie->iomuxc_gpr,
 215			   IMX95_PCIE_PHY_GEN_CTRL,
 216			   IMX95_PCIE_REF_USE_PAD, 0);
 217	regmap_update_bits(imx_pcie->iomuxc_gpr,
 218			   IMX95_PCIE_SS_RW_REG_0,
 219			   IMX95_PCIE_REF_CLKEN,
 220			   IMX95_PCIE_REF_CLKEN);
 221
 222	return 0;
 223}
 224
 225static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
 226{
 227	const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
 228	unsigned int mask, val, mode, id;
 229
 230	if (drvdata->mode == DW_PCIE_EP_TYPE)
 231		mode = PCI_EXP_TYPE_ENDPOINT;
 232	else
 233		mode = PCI_EXP_TYPE_ROOT_PORT;
 234
 235	id = imx_pcie->controller_id;
 236
 237	/* If mode_mask is 0, then generic PHY driver is used to set the mode */
 238	if (!drvdata->mode_mask[0])
 239		return;
 240
 241	/* If mode_mask[id] is zero, means each controller have its individual gpr */
 242	if (!drvdata->mode_mask[id])
 243		id = 0;
 244
 245	mask = drvdata->mode_mask[id];
 246	val = mode << (ffs(mask) - 1);
 
 
 
 
 
 247
 248	regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
 249}
 250
 251static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, bool exp_val)
 252{
 253	struct dw_pcie *pci = imx_pcie->pci;
 254	bool val;
 255	u32 max_iterations = 10;
 256	u32 wait_counter = 0;
 257
 258	do {
 259		val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
 260			PCIE_PHY_STAT_ACK;
 261		wait_counter++;
 262
 263		if (val == exp_val)
 264			return 0;
 265
 266		udelay(1);
 267	} while (wait_counter < max_iterations);
 268
 269	return -ETIMEDOUT;
 270}
 271
 272static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr)
 273{
 274	struct dw_pcie *pci = imx_pcie->pci;
 275	u32 val;
 276	int ret;
 277
 278	val = PCIE_PHY_CTRL_DATA(addr);
 279	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 280
 281	val |= PCIE_PHY_CTRL_CAP_ADR;
 282	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 283
 284	ret = pcie_phy_poll_ack(imx_pcie, true);
 285	if (ret)
 286		return ret;
 287
 288	val = PCIE_PHY_CTRL_DATA(addr);
 289	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 290
 291	return pcie_phy_poll_ack(imx_pcie, false);
 292}
 293
 294/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
 295static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, u16 *data)
 296{
 297	struct dw_pcie *pci = imx_pcie->pci;
 298	u32 phy_ctl;
 299	int ret;
 300
 301	ret = pcie_phy_wait_ack(imx_pcie, addr);
 302	if (ret)
 303		return ret;
 304
 305	/* assert Read signal */
 306	phy_ctl = PCIE_PHY_CTRL_RD;
 307	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
 308
 309	ret = pcie_phy_poll_ack(imx_pcie, true);
 310	if (ret)
 311		return ret;
 312
 313	*data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
 314
 315	/* deassert Read signal */
 316	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
 317
 318	return pcie_phy_poll_ack(imx_pcie, false);
 319}
 320
 321static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data)
 322{
 323	struct dw_pcie *pci = imx_pcie->pci;
 324	u32 var;
 325	int ret;
 326
 327	/* write addr */
 328	/* cap addr */
 329	ret = pcie_phy_wait_ack(imx_pcie, addr);
 330	if (ret)
 331		return ret;
 332
 333	var = PCIE_PHY_CTRL_DATA(data);
 334	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 335
 336	/* capture data */
 337	var |= PCIE_PHY_CTRL_CAP_DAT;
 338	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 339
 340	ret = pcie_phy_poll_ack(imx_pcie, true);
 341	if (ret)
 342		return ret;
 343
 344	/* deassert cap data */
 345	var = PCIE_PHY_CTRL_DATA(data);
 346	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 347
 348	/* wait for ack de-assertion */
 349	ret = pcie_phy_poll_ack(imx_pcie, false);
 350	if (ret)
 351		return ret;
 352
 353	/* assert wr signal */
 354	var = PCIE_PHY_CTRL_WR;
 355	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 356
 357	/* wait for ack */
 358	ret = pcie_phy_poll_ack(imx_pcie, true);
 359	if (ret)
 360		return ret;
 361
 362	/* deassert wr signal */
 363	var = PCIE_PHY_CTRL_DATA(data);
 364	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 365
 366	/* wait for ack de-assertion */
 367	ret = pcie_phy_poll_ack(imx_pcie, false);
 368	if (ret)
 369		return ret;
 370
 371	dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
 372
 373	return 0;
 374}
 375
 376static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie)
 377{
 378	/* TODO: Currently this code assumes external oscillator is being used */
 379	regmap_update_bits(imx_pcie->iomuxc_gpr,
 380			   imx_pcie_grp_offset(imx_pcie),
 381			   IMX8MQ_GPR_PCIE_REF_USE_PAD,
 382			   IMX8MQ_GPR_PCIE_REF_USE_PAD);
 383	/*
 384	 * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is
 385	 * supplied by 3.3V, the VREG_BYPASS should be cleared to zero.
 386	 */
 387	if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000)
 388		regmap_update_bits(imx_pcie->iomuxc_gpr,
 389				   imx_pcie_grp_offset(imx_pcie),
 390				   IMX8MQ_GPR_PCIE_VREG_BYPASS,
 391				   0);
 392
 393	return 0;
 394}
 395
 396static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie)
 397{
 398	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
 399
 400	return 0;
 401}
 402
 403static int imx_pcie_init_phy(struct imx_pcie *imx_pcie)
 404{
 405	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 406				   IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 407
 408	/* configure constant input signal to the pcie ctrl and phy */
 409	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
 410			   IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
 411
 412	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
 413			   IMX6Q_GPR8_TX_DEEMPH_GEN1,
 414			   imx_pcie->tx_deemph_gen1 << 0);
 415	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
 416			   IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
 417			   imx_pcie->tx_deemph_gen2_3p5db << 6);
 418	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
 419			   IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
 420			   imx_pcie->tx_deemph_gen2_6db << 12);
 421	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
 422			   IMX6Q_GPR8_TX_SWING_FULL,
 423			   imx_pcie->tx_swing_full << 18);
 424	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
 425			   IMX6Q_GPR8_TX_SWING_LOW,
 426			   imx_pcie->tx_swing_low << 25);
 427	return 0;
 428}
 429
 430static int imx6sx_pcie_init_phy(struct imx_pcie *imx_pcie)
 431{
 432	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
 433			   IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2);
 434
 435	return imx_pcie_init_phy(imx_pcie);
 436}
 437
 438static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
 439{
 440	u32 val;
 441	struct device *dev = imx_pcie->pci->dev;
 442
 443	if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
 444				     IOMUXC_GPR22, val,
 445				     val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
 446				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
 447				     PHY_PLL_LOCK_WAIT_TIMEOUT))
 448		dev_err(dev, "PCIe PLL lock timeout\n");
 449}
 450
 451static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)
 452{
 453	unsigned long phy_rate = 0;
 454	int mult, div;
 455	u16 val;
 456	int i;
 457
 458	if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
 459		return 0;
 460
 461	for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
 462		if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0)
 463			phy_rate = clk_get_rate(imx_pcie->clks[i].clk);
 464
 465	switch (phy_rate) {
 466	case 125000000:
 467		/*
 468		 * The default settings of the MPLL are for a 125MHz input
 469		 * clock, so no need to reconfigure anything in that case.
 470		 */
 471		return 0;
 472	case 100000000:
 473		mult = 25;
 474		div = 0;
 475		break;
 476	case 200000000:
 477		mult = 25;
 478		div = 1;
 479		break;
 480	default:
 481		dev_err(imx_pcie->pci->dev,
 482			"Unsupported PHY reference clock rate %lu\n", phy_rate);
 483		return -EINVAL;
 484	}
 485
 486	pcie_phy_read(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
 487	val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
 488		 PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
 489	val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
 490	val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
 491	pcie_phy_write(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
 492
 493	pcie_phy_read(imx_pcie, PCIE_PHY_ATEOVRD, &val);
 494	val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
 495		 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
 496	val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
 497	val |= PCIE_PHY_ATEOVRD_EN;
 498	pcie_phy_write(imx_pcie, PCIE_PHY_ATEOVRD, val);
 499
 500	return 0;
 501}
 502
 503static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie)
 504{
 505	u16 tmp;
 506
 507	if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
 508		return;
 509
 510	pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
 511	tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 512		PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 513	pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
 514
 515	usleep_range(2000, 3000);
 516
 517	pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
 518	tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 519		  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 520	pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
 521}
 522
 523#ifdef CONFIG_ARM
 524/*  Added for PCI abort handling */
 525static int imx6q_pcie_abort_handler(unsigned long addr,
 526		unsigned int fsr, struct pt_regs *regs)
 527{
 528	unsigned long pc = instruction_pointer(regs);
 529	unsigned long instr = *(unsigned long *)pc;
 530	int reg = (instr >> 12) & 15;
 531
 532	/*
 533	 * If the instruction being executed was a read,
 534	 * make it look like it read all-ones.
 535	 */
 536	if ((instr & 0x0c100000) == 0x04100000) {
 537		unsigned long val;
 538
 539		if (instr & 0x00400000)
 540			val = 255;
 541		else
 542			val = -1;
 543
 544		regs->uregs[reg] = val;
 545		regs->ARM_pc += 4;
 546		return 0;
 547	}
 548
 549	if ((instr & 0x0e100090) == 0x00100090) {
 550		regs->uregs[reg] = -1;
 551		regs->ARM_pc += 4;
 552		return 0;
 553	}
 554
 555	return 1;
 556}
 557#endif
 558
 559static int imx_pcie_attach_pd(struct device *dev)
 560{
 561	struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
 562	struct device_link *link;
 563
 564	/* Do nothing when in a single power domain */
 565	if (dev->pm_domain)
 566		return 0;
 567
 568	imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
 569	if (IS_ERR(imx_pcie->pd_pcie))
 570		return PTR_ERR(imx_pcie->pd_pcie);
 571	/* Do nothing when power domain missing */
 572	if (!imx_pcie->pd_pcie)
 573		return 0;
 574	link = device_link_add(dev, imx_pcie->pd_pcie,
 575			DL_FLAG_STATELESS |
 576			DL_FLAG_PM_RUNTIME |
 577			DL_FLAG_RPM_ACTIVE);
 578	if (!link) {
 579		dev_err(dev, "Failed to add device_link to pcie pd.\n");
 580		return -EINVAL;
 581	}
 582
 583	imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
 584	if (IS_ERR(imx_pcie->pd_pcie_phy))
 585		return PTR_ERR(imx_pcie->pd_pcie_phy);
 586
 587	link = device_link_add(dev, imx_pcie->pd_pcie_phy,
 588			DL_FLAG_STATELESS |
 589			DL_FLAG_PM_RUNTIME |
 590			DL_FLAG_RPM_ACTIVE);
 591	if (!link) {
 592		dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
 593		return -EINVAL;
 594	}
 595
 596	return 0;
 597}
 598
 599static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 600{
 601	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
 602			   IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
 603			   enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
 604	return 0;
 605}
 606
 607static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 608{
 609	if (enable) {
 
 
 
 
 
 
 
 
 
 
 610		/* power up core phy and enable ref clock */
 611		regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
 
 612		/*
 613		 * the async reset input need ref clock to sync internally,
 614		 * when the ref clock comes after reset, internal synced
 615		 * reset time is too short, cannot meet the requirement.
 616		 * add one ~10us delay here.
 617		 */
 618		usleep_range(10, 100);
 619		regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
 620	} else {
 621		regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
 622		regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
 623	}
 624
 625	return 0;
 626}
 
 
 
 
 
 
 
 
 627
 628static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 629{
 630	int offset = imx_pcie_grp_offset(imx_pcie);
 
 
 
 
 
 
 
 
 
 
 631
 632	regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
 633			   IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
 634			   enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
 635	regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
 636			   IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
 637			   enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
 638	return 0;
 639}
 640
 641static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 642{
 643	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
 644			   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
 645			   enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
 646	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 647}
 648
 649static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
 650{
 651	struct dw_pcie *pci = imx_pcie->pci;
 652	struct device *dev = pci->dev;
 653	int ret;
 654
 655	ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
 656	if (ret)
 
 657		return ret;
 
 658
 659	if (imx_pcie->drvdata->enable_ref_clk) {
 660		ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true);
 661		if (ret) {
 662			dev_err(dev, "Failed to enable PCIe REFCLK\n");
 663			goto err_ref_clk;
 664		}
 
 
 
 
 
 
 
 
 
 
 665	}
 666
 667	/* allow the clocks to stabilize */
 668	usleep_range(200, 500);
 669	return 0;
 670
 671err_ref_clk:
 672	clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
 
 
 
 
 673
 674	return ret;
 675}
 676
 677static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
 678{
 679	if (imx_pcie->drvdata->enable_ref_clk)
 680		imx_pcie->drvdata->enable_ref_clk(imx_pcie, false);
 681	clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
 682}
 683
 684static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
 685{
 686	if (assert)
 687		regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
 688				IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
 689
 690	/* Force PCIe PHY reset */
 691	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET,
 692			   assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0);
 693	return 0;
 694}
 695
 696static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
 697{
 698	regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST,
 699			   assert ? IMX6Q_GPR1_PCIE_SW_RST : 0);
 700	if (!assert)
 701		usleep_range(200, 500);
 702
 703	return 0;
 704}
 705
 706static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
 707{
 708	if (!assert)
 709		return 0;
 710
 711	regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
 712	regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 713
 714	return 0;
 
 
 
 715}
 716
 717static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
 718{
 719	struct dw_pcie *pci = imx_pcie->pci;
 720	struct device *dev = pci->dev;
 721
 722	if (assert)
 723		return 0;
 724
 725	/*
 726	 * Workaround for ERR010728 (IMX7DS_2N09P, Rev. 1.1, 4/2023):
 727	 *
 728	 * PCIe: PLL may fail to lock under corner conditions.
 729	 *
 730	 * Initial VCO oscillation may fail under corner conditions such as
 731	 * cold temperature which will cause the PCIe PLL fail to lock in the
 732	 * initialization phase.
 733	 *
 734	 * The Duty-cycle Corrector calibration must be disabled.
 735	 *
 736	 * 1. De-assert the G_RST signal by clearing
 737	 *    SRC_PCIEPHY_RCR[PCIEPHY_G_RST].
 738	 * 2. De-assert DCC_FB_EN by writing data “0x29” to the register
 739	 *    address 0x306d0014 (PCIE_PHY_CMN_REG4).
 740	 * 3. Assert RX_EQS, RX_EQ_SEL by writing data “0x48” to the register
 741	 *    address 0x306d0090 (PCIE_PHY_CMN_REG24).
 742	 * 4. Assert ATT_MODE by writing data “0xbc” to the register
 743	 *    address 0x306d0098 (PCIE_PHY_CMN_REG26).
 744	 * 5. De-assert the CMN_RST signal by clearing register bit
 745	 *    SRC_PCIEPHY_RCR[PCIEPHY_BTN]
 746	 */
 747
 748	if (likely(imx_pcie->phy_base)) {
 749		/* De-assert DCC_FB_EN */
 750		writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
 751		/* Assert RX_EQS and RX_EQS_SEL */
 752		writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ,
 753		       imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
 754		/* Assert ATT_MODE */
 755		writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
 756	} else {
 757		dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
 758	}
 759	imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
 760	return 0;
 761}
 762
 763static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
 764{
 765	reset_control_assert(imx_pcie->pciephy_reset);
 766	reset_control_assert(imx_pcie->apps_reset);
 767
 768	if (imx_pcie->drvdata->core_reset)
 769		imx_pcie->drvdata->core_reset(imx_pcie, true);
 770
 771	/* Some boards don't have PCIe reset GPIO. */
 772	gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);
 773}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 774
 775static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
 776{
 777	reset_control_deassert(imx_pcie->pciephy_reset);
 778	reset_control_deassert(imx_pcie->apps_reset);
 
 
 
 
 
 779
 780	if (imx_pcie->drvdata->core_reset)
 781		imx_pcie->drvdata->core_reset(imx_pcie, false);
 
 
 
 
 
 
 
 782
 783	/* Some boards don't have PCIe reset GPIO. */
 784	if (imx_pcie->reset_gpiod) {
 785		msleep(100);
 786		gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);
 
 787		/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
 788		msleep(100);
 789	}
 790
 791	return 0;
 792}
 793
 794static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie)
 795{
 796	struct dw_pcie *pci = imx_pcie->pci;
 797	struct device *dev = pci->dev;
 798	u32 tmp;
 799	unsigned int retries;
 800
 801	for (retries = 0; retries < 200; retries++) {
 802		tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 803		/* Test if the speed change finished. */
 804		if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
 805			return 0;
 806		usleep_range(100, 1000);
 807	}
 808
 809	dev_err(dev, "Speed change timeout\n");
 810	return -ETIMEDOUT;
 811}
 812
 813static void imx_pcie_ltssm_enable(struct device *dev)
 814{
 815	struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
 816	const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
 817	u8 offset = dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP);
 818	u32 tmp;
 819
 820	tmp = dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP);
 821	phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp));
 822	if (drvdata->ltssm_mask)
 823		regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
 824				   drvdata->ltssm_mask);
 825
 826	reset_control_deassert(imx_pcie->apps_reset);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 827}
 828
 829static void imx_pcie_ltssm_disable(struct device *dev)
 830{
 831	struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
 832	const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
 833
 834	phy_set_speed(imx_pcie->phy, 0);
 835	if (drvdata->ltssm_mask)
 836		regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
 837				   drvdata->ltssm_mask, 0);
 838
 839	reset_control_assert(imx_pcie->apps_reset);
 
 
 
 
 
 
 
 
 
 
 
 840}
 841
 842static int imx_pcie_start_link(struct dw_pcie *pci)
 843{
 844	struct imx_pcie *imx_pcie = to_imx_pcie(pci);
 845	struct device *dev = pci->dev;
 846	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 847	u32 tmp;
 848	int ret;
 849
 850	/*
 851	 * Force Gen1 operation when starting the link.  In case the link is
 852	 * started in Gen2 mode, there is a possibility the devices on the
 853	 * bus will not be detected at all.  This happens with PCIe switches.
 854	 */
 855	dw_pcie_dbi_ro_wr_en(pci);
 856	tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
 857	tmp &= ~PCI_EXP_LNKCAP_SLS;
 858	tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
 859	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
 860	dw_pcie_dbi_ro_wr_dis(pci);
 861
 862	/* Start LTSSM. */
 863	imx_pcie_ltssm_enable(dev);
 864
 865	ret = dw_pcie_wait_for_link(pci);
 866	if (ret)
 867		goto err_reset_phy;
 868
 869	if (pci->max_link_speed > 1) {
 870		/* Allow faster modes after the link is up */
 871		dw_pcie_dbi_ro_wr_en(pci);
 872		tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
 873		tmp &= ~PCI_EXP_LNKCAP_SLS;
 874		tmp |= pci->max_link_speed;
 875		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
 876
 877		/*
 878		 * Start Directed Speed Change so the best possible
 879		 * speed both link partners support can be negotiated.
 880		 */
 881		tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 882		tmp |= PORT_LOGIC_SPEED_CHANGE;
 883		dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
 884		dw_pcie_dbi_ro_wr_dis(pci);
 885
 886		if (imx_pcie->drvdata->flags &
 887		    IMX_PCIE_FLAG_IMX_SPEED_CHANGE) {
 888			/*
 889			 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
 890			 * from i.MX6 family when no link speed transition
 891			 * occurs and we go Gen1 -> yep, Gen1. The difference
 892			 * is that, in such case, it will not be cleared by HW
 893			 * which will cause the following code to report false
 894			 * failure.
 895			 */
 896
 897			ret = imx_pcie_wait_for_speed_change(imx_pcie);
 898			if (ret) {
 899				dev_err(dev, "Failed to bring link up!\n");
 900				goto err_reset_phy;
 901			}
 902		}
 903
 904		/* Make sure link training is finished as well! */
 905		ret = dw_pcie_wait_for_link(pci);
 906		if (ret)
 907			goto err_reset_phy;
 908	} else {
 909		dev_info(dev, "Link: Only Gen1 is enabled\n");
 910	}
 911
 912	imx_pcie->link_is_up = true;
 913	tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
 914	dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
 915	return 0;
 916
 917err_reset_phy:
 918	imx_pcie->link_is_up = false;
 919	dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
 920		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
 921		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
 922	imx_pcie_reset_phy(imx_pcie);
 923	return 0;
 924}
 925
 926static void imx_pcie_stop_link(struct dw_pcie *pci)
 927{
 928	struct device *dev = pci->dev;
 929
 930	/* Turn off PCIe LTSSM */
 931	imx_pcie_ltssm_disable(dev);
 932}
 933
 934static int imx_pcie_host_init(struct dw_pcie_rp *pp)
 935{
 936	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 937	struct device *dev = pci->dev;
 938	struct imx_pcie *imx_pcie = to_imx_pcie(pci);
 939	int ret;
 940
 941	if (imx_pcie->vpcie) {
 942		ret = regulator_enable(imx_pcie->vpcie);
 943		if (ret) {
 944			dev_err(dev, "failed to enable vpcie regulator: %d\n",
 945				ret);
 946			return ret;
 947		}
 948	}
 949
 950	imx_pcie_assert_core_reset(imx_pcie);
 951
 952	if (imx_pcie->drvdata->init_phy)
 953		imx_pcie->drvdata->init_phy(imx_pcie);
 954
 955	imx_pcie_configure_type(imx_pcie);
 956
 957	ret = imx_pcie_clk_enable(imx_pcie);
 958	if (ret) {
 959		dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
 960		goto err_reg_disable;
 961	}
 962
 963	if (imx_pcie->phy) {
 964		ret = phy_init(imx_pcie->phy);
 965		if (ret) {
 966			dev_err(dev, "pcie PHY power up failed\n");
 967			goto err_clk_disable;
 968		}
 
 969
 970		ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE,
 971				       imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ?
 972						PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC);
 973		if (ret) {
 974			dev_err(dev, "unable to set PCIe PHY mode\n");
 975			goto err_phy_exit;
 976		}
 977
 978		ret = phy_power_on(imx_pcie->phy);
 979		if (ret) {
 980			dev_err(dev, "waiting for PHY ready timeout!\n");
 981			goto err_phy_exit;
 982		}
 983	}
 984
 985	ret = imx_pcie_deassert_core_reset(imx_pcie);
 986	if (ret < 0) {
 987		dev_err(dev, "pcie deassert core reset failed: %d\n", ret);
 988		goto err_phy_off;
 989	}
 990
 991	imx_setup_phy_mpll(imx_pcie);
 992
 993	return 0;
 994
 995err_phy_off:
 996	phy_power_off(imx_pcie->phy);
 997err_phy_exit:
 998	phy_exit(imx_pcie->phy);
 999err_clk_disable:
1000	imx_pcie_clk_disable(imx_pcie);
1001err_reg_disable:
1002	if (imx_pcie->vpcie)
1003		regulator_disable(imx_pcie->vpcie);
1004	return ret;
1005}
1006
1007static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
1008{
1009	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1010	struct imx_pcie *imx_pcie = to_imx_pcie(pci);
1011
1012	if (imx_pcie->phy) {
1013		if (phy_power_off(imx_pcie->phy))
1014			dev_err(pci->dev, "unable to power off PHY\n");
1015		phy_exit(imx_pcie->phy);
1016	}
1017	imx_pcie_clk_disable(imx_pcie);
1018
1019	if (imx_pcie->vpcie)
1020		regulator_disable(imx_pcie->vpcie);
1021}
1022
1023static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr)
1024{
1025	struct imx_pcie *imx_pcie = to_imx_pcie(pcie);
1026	struct dw_pcie_rp *pp = &pcie->pp;
1027	struct resource_entry *entry;
1028
1029	if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP))
1030		return cpu_addr;
1031
1032	entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
1033	if (!entry)
1034		return cpu_addr;
1035
1036	return cpu_addr - entry->offset;
1037}
1038
1039static const struct dw_pcie_host_ops imx_pcie_host_ops = {
1040	.init = imx_pcie_host_init,
1041	.deinit = imx_pcie_host_exit,
1042};
1043
1044static const struct dw_pcie_ops dw_pcie_ops = {
1045	.start_link = imx_pcie_start_link,
1046	.stop_link = imx_pcie_stop_link,
1047	.cpu_addr_fixup = imx_pcie_cpu_addr_fixup,
1048};
1049
1050static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
1051{
1052	enum pci_barno bar;
1053	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1054
1055	for (bar = BAR_0; bar <= BAR_5; bar++)
1056		dw_pcie_ep_reset_bar(pci, bar);
1057}
1058
1059static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1060				  unsigned int type, u16 interrupt_num)
1061{
1062	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1063
1064	switch (type) {
1065	case PCI_IRQ_INTX:
1066		return dw_pcie_ep_raise_intx_irq(ep, func_no);
1067	case PCI_IRQ_MSI:
1068		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
1069	case PCI_IRQ_MSIX:
1070		return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
1071	default:
1072		dev_err(pci->dev, "UNKNOWN IRQ type\n");
1073		return -EINVAL;
1074	}
1075
1076	return 0;
1077}
1078
1079static const struct pci_epc_features imx8m_pcie_epc_features = {
1080	.linkup_notifier = false,
1081	.msi_capable = true,
1082	.msix_capable = false,
1083	.bar[BAR_1] = { .type = BAR_RESERVED, },
1084	.bar[BAR_3] = { .type = BAR_RESERVED, },
1085	.align = SZ_64K,
1086};
1087
1088/*
1089 * BAR#	| Default BAR enable	| Default BAR Type	| Default BAR Size	| BAR Sizing Scheme
1090 * ================================================================================================
1091 * BAR0	| Enable		| 64-bit		| 1 MB			| Programmable Size
1092 * BAR1	| Disable		| 32-bit		| 64 KB			| Fixed Size
1093 *        BAR1 should be disabled if BAR0 is 64bit.
1094 * BAR2	| Enable		| 32-bit		| 1 MB			| Programmable Size
1095 * BAR3	| Enable		| 32-bit		| 64 KB			| Programmable Size
1096 * BAR4	| Enable		| 32-bit		| 1M			| Programmable Size
1097 * BAR5	| Enable		| 32-bit		| 64 KB			| Programmable Size
1098 */
1099static const struct pci_epc_features imx95_pcie_epc_features = {
1100	.msi_capable = true,
1101	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
1102	.align = SZ_4K,
1103};
1104
1105static const struct pci_epc_features*
1106imx_pcie_ep_get_features(struct dw_pcie_ep *ep)
1107{
1108	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1109	struct imx_pcie *imx_pcie = to_imx_pcie(pci);
1110
1111	return imx_pcie->drvdata->epc_features;
1112}
1113
1114static const struct dw_pcie_ep_ops pcie_ep_ops = {
1115	.init = imx_pcie_ep_init,
1116	.raise_irq = imx_pcie_ep_raise_irq,
1117	.get_features = imx_pcie_ep_get_features,
1118};
1119
1120static int imx_add_pcie_ep(struct imx_pcie *imx_pcie,
1121			   struct platform_device *pdev)
1122{
1123	int ret;
1124	unsigned int pcie_dbi2_offset;
1125	struct dw_pcie_ep *ep;
1126	struct dw_pcie *pci = imx_pcie->pci;
 
1127	struct dw_pcie_rp *pp = &pci->pp;
1128	struct device *dev = pci->dev;
1129
1130	imx_pcie_host_init(pp);
1131	ep = &pci->ep;
1132	ep->ops = &pcie_ep_ops;
1133
1134	switch (imx_pcie->drvdata->variant) {
1135	case IMX8MQ_EP:
1136	case IMX8MM_EP:
1137	case IMX8MP_EP:
1138		pcie_dbi2_offset = SZ_1M;
1139		break;
1140	default:
1141		pcie_dbi2_offset = SZ_4K;
1142		break;
1143	}
1144
1145	pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset;
 
 
 
1146
1147	/*
1148	 * FIXME: Ideally, dbi2 base address should come from DT. But since only IMX95 is defining
1149	 * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone so that the DWC
1150	 * core code can fetch that from DT. But once all platform DTs were fixed, this and the
1151	 * above "dbi_base2" setting should be removed.
1152	 */
1153	if (device_property_match_string(dev, "reg-names", "dbi2") >= 0)
1154		pci->dbi_base2 = NULL;
1155
1156	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SUPPORT_64BIT))
1157		dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
1158
1159	ep->page_size = imx_pcie->drvdata->epc_features->align;
1160
1161	ret = dw_pcie_ep_init(ep);
1162	if (ret) {
1163		dev_err(dev, "failed to initialize endpoint\n");
1164		return ret;
1165	}
1166
1167	ret = dw_pcie_ep_init_registers(ep);
1168	if (ret) {
1169		dev_err(dev, "Failed to initialize DWC endpoint registers\n");
1170		dw_pcie_ep_deinit(ep);
1171		return ret;
1172	}
1173
1174	pci_epc_init_notify(ep->epc);
1175
1176	/* Start LTSSM. */
1177	imx_pcie_ltssm_enable(dev);
1178
1179	return 0;
1180}
1181
1182static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie)
1183{
1184	struct device *dev = imx_pcie->pci->dev;
1185
1186	/* Some variants have a turnoff reset in DT */
1187	if (imx_pcie->turnoff_reset) {
1188		reset_control_assert(imx_pcie->turnoff_reset);
1189		reset_control_deassert(imx_pcie->turnoff_reset);
1190		goto pm_turnoff_sleep;
1191	}
1192
1193	/* Others poke directly at IOMUXC registers */
1194	switch (imx_pcie->drvdata->variant) {
1195	case IMX6SX:
1196	case IMX6QP:
1197		regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
1198				IMX6SX_GPR12_PCIE_PM_TURN_OFF,
1199				IMX6SX_GPR12_PCIE_PM_TURN_OFF);
1200		regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
1201				IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
1202		break;
1203	default:
1204		dev_err(dev, "PME_Turn_Off not implemented\n");
1205		return;
1206	}
1207
1208	/*
1209	 * Components with an upstream port must respond to
1210	 * PME_Turn_Off with PME_TO_Ack but we can't check.
1211	 *
1212	 * The standard recommends a 1-10ms timeout after which to
1213	 * proceed anyway as if acks were received.
1214	 */
1215pm_turnoff_sleep:
1216	usleep_range(1000, 10000);
1217}
1218
1219static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save)
1220{
1221	u8 offset;
1222	u16 val;
1223	struct dw_pcie *pci = imx_pcie->pci;
1224
1225	if (pci_msi_enabled()) {
1226		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
1227		if (save) {
1228			val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
1229			imx_pcie->msi_ctrl = val;
1230		} else {
1231			dw_pcie_dbi_ro_wr_en(pci);
1232			val = imx_pcie->msi_ctrl;
1233			dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
1234			dw_pcie_dbi_ro_wr_dis(pci);
1235		}
1236	}
1237}
1238
1239static int imx_pcie_suspend_noirq(struct device *dev)
1240{
1241	struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
1242	struct dw_pcie_rp *pp = &imx_pcie->pci->pp;
1243
1244	if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
1245		return 0;
1246
1247	imx_pcie_msi_save_restore(imx_pcie, true);
1248	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_BROKEN_SUSPEND)) {
1249		/*
1250		 * The minimum for a workaround would be to set PERST# and to
1251		 * set the PCIE_TEST_PD flag. However, we can also disable the
1252		 * clock which saves some power.
1253		 */
1254		imx_pcie_assert_core_reset(imx_pcie);
1255		imx_pcie->drvdata->enable_ref_clk(imx_pcie, false);
1256	} else {
1257		imx_pcie_pm_turnoff(imx_pcie);
1258		imx_pcie_stop_link(imx_pcie->pci);
1259		imx_pcie_host_exit(pp);
1260	}
1261
1262	return 0;
1263}
1264
1265static int imx_pcie_resume_noirq(struct device *dev)
1266{
1267	int ret;
1268	struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
1269	struct dw_pcie_rp *pp = &imx_pcie->pci->pp;
1270
1271	if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
1272		return 0;
1273
1274	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_BROKEN_SUSPEND)) {
1275		ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true);
1276		if (ret)
1277			return ret;
1278		ret = imx_pcie_deassert_core_reset(imx_pcie);
1279		if (ret)
1280			return ret;
1281		/*
1282		 * Using PCIE_TEST_PD seems to disable MSI and powers down the
1283		 * root complex. This is why we have to setup the rc again and
1284		 * why we have to restore the MSI register.
1285		 */
1286		ret = dw_pcie_setup_rc(&imx_pcie->pci->pp);
1287		if (ret)
1288			return ret;
1289		imx_pcie_msi_save_restore(imx_pcie, false);
1290	} else {
1291		ret = imx_pcie_host_init(pp);
1292		if (ret)
1293			return ret;
1294		imx_pcie_msi_save_restore(imx_pcie, false);
1295		dw_pcie_setup_rc(pp);
1296
1297		if (imx_pcie->link_is_up)
1298			imx_pcie_start_link(imx_pcie->pci);
1299	}
1300
1301	return 0;
1302}
1303
1304static const struct dev_pm_ops imx_pcie_pm_ops = {
1305	NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_pcie_suspend_noirq,
1306				  imx_pcie_resume_noirq)
1307};
1308
1309static int imx_pcie_probe(struct platform_device *pdev)
1310{
1311	struct device *dev = &pdev->dev;
1312	struct dw_pcie *pci;
1313	struct imx_pcie *imx_pcie;
1314	struct device_node *np;
1315	struct resource *dbi_base;
1316	struct device_node *node = dev->of_node;
1317	int ret;
1318	u16 val;
1319	int i;
1320
1321	imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
1322	if (!imx_pcie)
1323		return -ENOMEM;
1324
1325	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1326	if (!pci)
1327		return -ENOMEM;
1328
1329	pci->dev = dev;
1330	pci->ops = &dw_pcie_ops;
1331	pci->pp.ops = &imx_pcie_host_ops;
1332
1333	imx_pcie->pci = pci;
1334	imx_pcie->drvdata = of_device_get_match_data(dev);
1335
1336	/* Find the PHY if one is defined, only imx7d uses it */
1337	np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1338	if (np) {
1339		struct resource res;
1340
1341		ret = of_address_to_resource(np, 0, &res);
1342		if (ret) {
1343			dev_err(dev, "Unable to map PCIe PHY\n");
1344			return ret;
1345		}
1346		imx_pcie->phy_base = devm_ioremap_resource(dev, &res);
1347		if (IS_ERR(imx_pcie->phy_base))
1348			return PTR_ERR(imx_pcie->phy_base);
1349	}
1350
1351	pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base);
1352	if (IS_ERR(pci->dbi_base))
1353		return PTR_ERR(pci->dbi_base);
1354
1355	/* Fetch GPIOs */
1356	imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1357	if (IS_ERR(imx_pcie->reset_gpiod))
1358		return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),
1359				     "unable to get reset gpio\n");
1360	gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
1361
1362	if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS)
1363		return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
1364
1365	for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
1366		imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i];
 
 
 
 
 
1367
1368	/* Fetch clocks */
1369	ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
1370	if (ret)
1371		return ret;
 
 
 
 
 
 
1372
1373	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
1374		imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
1375		if (IS_ERR(imx_pcie->phy))
1376			return dev_err_probe(dev, PTR_ERR(imx_pcie->phy),
1377					     "failed to get pcie phy\n");
1378	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1379
1380	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_APP_RESET)) {
1381		imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps");
1382		if (IS_ERR(imx_pcie->apps_reset))
1383			return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset),
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1384					     "failed to get pcie apps reset control\n");
1385	}
1386
1387	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHY_RESET)) {
1388		imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy");
1389		if (IS_ERR(imx_pcie->pciephy_reset))
1390			return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset),
1391					     "Failed to get PCIEPHY reset control\n");
1392	}
1393
1394	switch (imx_pcie->drvdata->variant) {
1395	case IMX8MQ:
1396	case IMX8MQ_EP:
1397		if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1398			imx_pcie->controller_id = 1;
1399		break;
1400	default:
1401		break;
1402	}
 
 
 
 
 
 
 
 
1403
1404	/* Grab turnoff reset */
1405	imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1406	if (IS_ERR(imx_pcie->turnoff_reset)) {
1407		dev_err(dev, "Failed to get TURNOFF reset control\n");
1408		return PTR_ERR(imx_pcie->turnoff_reset);
1409	}
1410
1411	if (imx_pcie->drvdata->gpr) {
1412	/* Grab GPR config register range */
1413		imx_pcie->iomuxc_gpr =
1414			 syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr);
1415		if (IS_ERR(imx_pcie->iomuxc_gpr))
1416			return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr),
1417					     "unable to find iomuxc registers\n");
1418	}
1419
1420	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_SERDES)) {
1421		void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
1422
1423		if (IS_ERR(off))
1424			return dev_err_probe(dev, PTR_ERR(off),
1425					     "unable to find serdes registers\n");
1426
1427		static const struct regmap_config regmap_config = {
1428			.reg_bits = 32,
1429			.val_bits = 32,
1430			.reg_stride = 4,
1431		};
1432
1433		imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, &regmap_config);
1434		if (IS_ERR(imx_pcie->iomuxc_gpr))
1435			return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr),
1436					     "unable to find iomuxc registers\n");
1437	}
1438
1439	/* Grab PCIe PHY Tx Settings */
1440	if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1441				 &imx_pcie->tx_deemph_gen1))
1442		imx_pcie->tx_deemph_gen1 = 0;
1443
1444	if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1445				 &imx_pcie->tx_deemph_gen2_3p5db))
1446		imx_pcie->tx_deemph_gen2_3p5db = 0;
1447
1448	if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1449				 &imx_pcie->tx_deemph_gen2_6db))
1450		imx_pcie->tx_deemph_gen2_6db = 20;
1451
1452	if (of_property_read_u32(node, "fsl,tx-swing-full",
1453				 &imx_pcie->tx_swing_full))
1454		imx_pcie->tx_swing_full = 127;
1455
1456	if (of_property_read_u32(node, "fsl,tx-swing-low",
1457				 &imx_pcie->tx_swing_low))
1458		imx_pcie->tx_swing_low = 127;
1459
1460	/* Limit link speed */
1461	pci->max_link_speed = 1;
1462	of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
1463
1464	imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1465	if (IS_ERR(imx_pcie->vpcie)) {
1466		if (PTR_ERR(imx_pcie->vpcie) != -ENODEV)
1467			return PTR_ERR(imx_pcie->vpcie);
1468		imx_pcie->vpcie = NULL;
1469	}
1470
1471	imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
1472	if (IS_ERR(imx_pcie->vph)) {
1473		if (PTR_ERR(imx_pcie->vph) != -ENODEV)
1474			return PTR_ERR(imx_pcie->vph);
1475		imx_pcie->vph = NULL;
1476	}
1477
1478	platform_set_drvdata(pdev, imx_pcie);
1479
1480	ret = imx_pcie_attach_pd(dev);
1481	if (ret)
1482		return ret;
1483
1484	if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
1485		ret = imx_add_pcie_ep(imx_pcie, pdev);
1486		if (ret < 0)
1487			return ret;
1488	} else {
1489		ret = dw_pcie_host_init(&pci->pp);
1490		if (ret < 0)
1491			return ret;
1492
1493		if (pci_msi_enabled()) {
1494			u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
1495
1496			val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
1497			val |= PCI_MSI_FLAGS_ENABLE;
1498			dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
1499		}
1500	}
1501
1502	return 0;
1503}
1504
1505static void imx_pcie_shutdown(struct platform_device *pdev)
1506{
1507	struct imx_pcie *imx_pcie = platform_get_drvdata(pdev);
1508
1509	/* bring down link, so bootloader gets clean state in case of reboot */
1510	imx_pcie_assert_core_reset(imx_pcie);
1511}
1512
1513static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
1514static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
1515static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
1516static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
1517static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"};
1518
1519static const struct imx_pcie_drvdata drvdata[] = {
1520	[IMX6Q] = {
1521		.variant = IMX6Q,
1522		.flags = IMX_PCIE_FLAG_IMX_PHY |
1523			 IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
1524			 IMX_PCIE_FLAG_BROKEN_SUSPEND |
1525			 IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1526		.dbi_length = 0x200,
1527		.gpr = "fsl,imx6q-iomuxc-gpr",
1528		.clk_names = imx6q_clks,
1529		.clks_cnt = ARRAY_SIZE(imx6q_clks),
1530		.ltssm_off = IOMUXC_GPR12,
1531		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1532		.mode_off[0] = IOMUXC_GPR12,
1533		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1534		.init_phy = imx_pcie_init_phy,
1535		.enable_ref_clk = imx6q_pcie_enable_ref_clk,
1536		.core_reset = imx6q_pcie_core_reset,
1537	},
1538	[IMX6SX] = {
1539		.variant = IMX6SX,
1540		.flags = IMX_PCIE_FLAG_IMX_PHY |
1541			 IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
1542			 IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1543		.gpr = "fsl,imx6q-iomuxc-gpr",
1544		.clk_names = imx6sx_clks,
1545		.clks_cnt = ARRAY_SIZE(imx6sx_clks),
1546		.ltssm_off = IOMUXC_GPR12,
1547		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1548		.mode_off[0] = IOMUXC_GPR12,
1549		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1550		.init_phy = imx6sx_pcie_init_phy,
1551		.enable_ref_clk = imx6sx_pcie_enable_ref_clk,
1552		.core_reset = imx6sx_pcie_core_reset,
1553	},
1554	[IMX6QP] = {
1555		.variant = IMX6QP,
1556		.flags = IMX_PCIE_FLAG_IMX_PHY |
1557			 IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
1558			 IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1559		.dbi_length = 0x200,
1560		.gpr = "fsl,imx6q-iomuxc-gpr",
1561		.clk_names = imx6q_clks,
1562		.clks_cnt = ARRAY_SIZE(imx6q_clks),
1563		.ltssm_off = IOMUXC_GPR12,
1564		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1565		.mode_off[0] = IOMUXC_GPR12,
1566		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1567		.init_phy = imx_pcie_init_phy,
1568		.enable_ref_clk = imx6q_pcie_enable_ref_clk,
1569		.core_reset = imx6qp_pcie_core_reset,
1570	},
1571	[IMX7D] = {
1572		.variant = IMX7D,
1573		.flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
1574			 IMX_PCIE_FLAG_HAS_APP_RESET |
1575			 IMX_PCIE_FLAG_HAS_PHY_RESET,
1576		.gpr = "fsl,imx7d-iomuxc-gpr",
1577		.clk_names = imx6q_clks,
1578		.clks_cnt = ARRAY_SIZE(imx6q_clks),
1579		.mode_off[0] = IOMUXC_GPR12,
1580		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1581		.init_phy = imx7d_pcie_init_phy,
1582		.enable_ref_clk = imx7d_pcie_enable_ref_clk,
1583		.core_reset = imx7d_pcie_core_reset,
1584	},
1585	[IMX8MQ] = {
1586		.variant = IMX8MQ,
1587		.flags = IMX_PCIE_FLAG_HAS_APP_RESET |
1588			 IMX_PCIE_FLAG_HAS_PHY_RESET,
1589		.gpr = "fsl,imx8mq-iomuxc-gpr",
1590		.clk_names = imx8mq_clks,
1591		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
1592		.mode_off[0] = IOMUXC_GPR12,
1593		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1594		.mode_off[1] = IOMUXC_GPR12,
1595		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
1596		.init_phy = imx8mq_pcie_init_phy,
1597		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
1598	},
1599	[IMX8MM] = {
1600		.variant = IMX8MM,
1601		.flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
1602			 IMX_PCIE_FLAG_HAS_PHYDRV |
1603			 IMX_PCIE_FLAG_HAS_APP_RESET,
1604		.gpr = "fsl,imx8mm-iomuxc-gpr",
1605		.clk_names = imx8mm_clks,
1606		.clks_cnt = ARRAY_SIZE(imx8mm_clks),
1607		.mode_off[0] = IOMUXC_GPR12,
1608		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1609		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
1610	},
1611	[IMX8MP] = {
1612		.variant = IMX8MP,
1613		.flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
1614			 IMX_PCIE_FLAG_HAS_PHYDRV |
1615			 IMX_PCIE_FLAG_HAS_APP_RESET,
1616		.gpr = "fsl,imx8mp-iomuxc-gpr",
1617		.clk_names = imx8mm_clks,
1618		.clks_cnt = ARRAY_SIZE(imx8mm_clks),
1619		.mode_off[0] = IOMUXC_GPR12,
1620		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1621		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
1622	},
1623	[IMX8Q] = {
1624		.variant = IMX8Q,
1625		.flags = IMX_PCIE_FLAG_HAS_PHYDRV |
1626			 IMX_PCIE_FLAG_CPU_ADDR_FIXUP,
1627		.clk_names = imx8q_clks,
1628		.clks_cnt = ARRAY_SIZE(imx8q_clks),
1629	},
1630	[IMX95] = {
1631		.variant = IMX95,
1632		.flags = IMX_PCIE_FLAG_HAS_SERDES,
1633		.clk_names = imx8mq_clks,
1634		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
1635		.ltssm_off = IMX95_PE0_GEN_CTRL_3,
1636		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
1637		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
1638		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
1639		.init_phy = imx95_pcie_init_phy,
1640	},
1641	[IMX8MQ_EP] = {
1642		.variant = IMX8MQ_EP,
1643		.flags = IMX_PCIE_FLAG_HAS_APP_RESET |
1644			 IMX_PCIE_FLAG_HAS_PHY_RESET,
1645		.mode = DW_PCIE_EP_TYPE,
1646		.gpr = "fsl,imx8mq-iomuxc-gpr",
1647		.clk_names = imx8mq_clks,
1648		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
1649		.mode_off[0] = IOMUXC_GPR12,
1650		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1651		.mode_off[1] = IOMUXC_GPR12,
1652		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
1653		.epc_features = &imx8m_pcie_epc_features,
1654		.init_phy = imx8mq_pcie_init_phy,
1655		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
1656	},
1657	[IMX8MM_EP] = {
1658		.variant = IMX8MM_EP,
1659		.flags = IMX_PCIE_FLAG_HAS_APP_RESET |
1660			 IMX_PCIE_FLAG_HAS_PHYDRV,
1661		.mode = DW_PCIE_EP_TYPE,
1662		.gpr = "fsl,imx8mm-iomuxc-gpr",
1663		.clk_names = imx8mm_clks,
1664		.clks_cnt = ARRAY_SIZE(imx8mm_clks),
1665		.mode_off[0] = IOMUXC_GPR12,
1666		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1667		.epc_features = &imx8m_pcie_epc_features,
1668		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
1669	},
1670	[IMX8MP_EP] = {
1671		.variant = IMX8MP_EP,
1672		.flags = IMX_PCIE_FLAG_HAS_APP_RESET |
1673			 IMX_PCIE_FLAG_HAS_PHYDRV,
1674		.mode = DW_PCIE_EP_TYPE,
1675		.gpr = "fsl,imx8mp-iomuxc-gpr",
1676		.clk_names = imx8mm_clks,
1677		.clks_cnt = ARRAY_SIZE(imx8mm_clks),
1678		.mode_off[0] = IOMUXC_GPR12,
1679		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1680		.epc_features = &imx8m_pcie_epc_features,
1681		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
1682	},
1683	[IMX95_EP] = {
1684		.variant = IMX95_EP,
1685		.flags = IMX_PCIE_FLAG_HAS_SERDES |
1686			 IMX_PCIE_FLAG_SUPPORT_64BIT,
1687		.clk_names = imx8mq_clks,
1688		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
1689		.ltssm_off = IMX95_PE0_GEN_CTRL_3,
1690		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
1691		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
1692		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
1693		.init_phy = imx95_pcie_init_phy,
1694		.epc_features = &imx95_pcie_epc_features,
1695		.mode = DW_PCIE_EP_TYPE,
1696	},
1697};
1698
1699static const struct of_device_id imx_pcie_of_match[] = {
1700	{ .compatible = "fsl,imx6q-pcie",  .data = &drvdata[IMX6Q],  },
1701	{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1702	{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1703	{ .compatible = "fsl,imx7d-pcie",  .data = &drvdata[IMX7D],  },
1704	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1705	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1706	{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
1707	{ .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], },
1708	{ .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
1709	{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
1710	{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
1711	{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
1712	{ .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
1713	{},
1714};
1715
1716static struct platform_driver imx_pcie_driver = {
1717	.driver = {
1718		.name	= "imx6q-pcie",
1719		.of_match_table = imx_pcie_of_match,
1720		.suppress_bind_attrs = true,
1721		.pm = &imx_pcie_pm_ops,
1722		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1723	},
1724	.probe    = imx_pcie_probe,
1725	.shutdown = imx_pcie_shutdown,
1726};
1727
1728static void imx_pcie_quirk(struct pci_dev *dev)
1729{
1730	struct pci_bus *bus = dev->bus;
1731	struct dw_pcie_rp *pp = bus->sysdata;
1732
1733	/* Bus parent is the PCI bridge, its parent is this platform driver */
1734	if (!bus->dev.parent || !bus->dev.parent->parent)
1735		return;
1736
1737	/* Make sure we only quirk devices associated with this driver */
1738	if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver)
1739		return;
1740
1741	if (pci_is_root_bus(bus)) {
1742		struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1743		struct imx_pcie *imx_pcie = to_imx_pcie(pci);
1744
1745		/*
1746		 * Limit config length to avoid the kernel reading beyond
1747		 * the register set and causing an abort on i.MX 6Quad
1748		 */
1749		if (imx_pcie->drvdata->dbi_length) {
1750			dev->cfg_size = imx_pcie->drvdata->dbi_length;
1751			dev_info(&dev->dev, "Limiting cfg_size to %d\n",
1752					dev->cfg_size);
1753		}
1754	}
1755}
1756DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
1757			PCI_CLASS_BRIDGE_PCI, 8, imx_pcie_quirk);
1758
1759static int __init imx_pcie_init(void)
1760{
1761#ifdef CONFIG_ARM
1762	struct device_node *np;
1763
1764	np = of_find_matching_node(NULL, imx_pcie_of_match);
1765	if (!np)
1766		return -ENODEV;
1767	of_node_put(np);
1768
1769	/*
1770	 * Since probe() can be deferred we need to make sure that
1771	 * hook_fault_code is not called after __init memory is freed
1772	 * by kernel and since imx6q_pcie_abort_handler() is a no-op,
1773	 * we can install the handler here without risking it
1774	 * accessing some uninitialized driver state.
1775	 */
1776	hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1777			"external abort on non-linefetch");
1778#endif
1779
1780	return platform_driver_register(&imx_pcie_driver);
1781}
1782device_initcall(imx_pcie_init);