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1// SPDX-License-Identifier: GPL-2.0
2/* Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 */
6
7#include <linux/ethtool.h>
8#include <linux/kernel.h>
9#include <linux/mii.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/phy.h>
13#include <linux/delay.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/bitfield.h>
17#include <linux/nvmem-consumer.h>
18
19#include <dt-bindings/net/ti-dp83867.h>
20
21#define DP83867_PHY_ID 0x2000a231
22#define DP83867_DEVADDR 0x1f
23
24#define MII_DP83867_PHYCTRL 0x10
25#define MII_DP83867_PHYSTS 0x11
26#define MII_DP83867_MICR 0x12
27#define MII_DP83867_ISR 0x13
28#define DP83867_CFG2 0x14
29#define DP83867_LEDCR1 0x18
30#define DP83867_LEDCR2 0x19
31#define DP83867_CFG3 0x1e
32#define DP83867_CTRL 0x1f
33
34/* Extended Registers */
35#define DP83867_FLD_THR_CFG 0x002e
36#define DP83867_CFG4 0x0031
37#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
38#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
39#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
40#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
41#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
42
43#define DP83867_RGMIICTL 0x0032
44#define DP83867_STRAP_STS1 0x006E
45#define DP83867_STRAP_STS2 0x006f
46#define DP83867_RGMIIDCTL 0x0086
47#define DP83867_DSP_FFE_CFG 0x012c
48#define DP83867_RXFCFG 0x0134
49#define DP83867_RXFPMD1 0x0136
50#define DP83867_RXFPMD2 0x0137
51#define DP83867_RXFPMD3 0x0138
52#define DP83867_RXFSOP1 0x0139
53#define DP83867_RXFSOP2 0x013A
54#define DP83867_RXFSOP3 0x013B
55#define DP83867_IO_MUX_CFG 0x0170
56#define DP83867_SGMIICTL 0x00D3
57#define DP83867_10M_SGMII_CFG 0x016F
58#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
59
60#define DP83867_SW_RESET BIT(15)
61#define DP83867_SW_RESTART BIT(14)
62
63/* MICR Interrupt bits */
64#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
65#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
66#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
67#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
68#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
69#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
70#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
71#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
72#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
73#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
74#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
75#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
76
77/* RGMIICTL bits */
78#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
79#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
80
81/* SGMIICTL bits */
82#define DP83867_SGMII_TYPE BIT(14)
83
84/* RXFCFG bits*/
85#define DP83867_WOL_MAGIC_EN BIT(0)
86#define DP83867_WOL_BCAST_EN BIT(2)
87#define DP83867_WOL_UCAST_EN BIT(4)
88#define DP83867_WOL_SEC_EN BIT(5)
89#define DP83867_WOL_ENH_MAC BIT(7)
90
91/* STRAP_STS1 bits */
92#define DP83867_STRAP_STS1_RESERVED BIT(11)
93
94/* STRAP_STS2 bits */
95#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
96#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
97#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
98#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
99#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
100#define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
101
102/* PHY CTRL bits */
103#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
104#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
105#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
106#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
107#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
108#define DP83867_PHYCR_RESERVED_MASK BIT(11)
109#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
110
111/* RGMIIDCTL bits */
112#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
113#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
114#define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
115#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
116#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
117#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
118
119/* IO_MUX_CFG bits */
120#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
121#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
122#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
123#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
124#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
125#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
126
127/* PHY STS bits */
128#define DP83867_PHYSTS_1000 BIT(15)
129#define DP83867_PHYSTS_100 BIT(14)
130#define DP83867_PHYSTS_DUPLEX BIT(13)
131#define DP83867_PHYSTS_LINK BIT(10)
132
133/* CFG2 bits */
134#define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
135#define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
136#define DP83867_DOWNSHIFT_1_COUNT_VAL 0
137#define DP83867_DOWNSHIFT_2_COUNT_VAL 1
138#define DP83867_DOWNSHIFT_4_COUNT_VAL 2
139#define DP83867_DOWNSHIFT_8_COUNT_VAL 3
140#define DP83867_DOWNSHIFT_1_COUNT 1
141#define DP83867_DOWNSHIFT_2_COUNT 2
142#define DP83867_DOWNSHIFT_4_COUNT 4
143#define DP83867_DOWNSHIFT_8_COUNT 8
144#define DP83867_SGMII_AUTONEG_EN BIT(7)
145
146/* CFG3 bits */
147#define DP83867_CFG3_INT_OE BIT(7)
148#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
149
150/* CFG4 bits */
151#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
152
153/* FLD_THR_CFG */
154#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
155
156#define DP83867_LED_COUNT 4
157
158/* LED_DRV bits */
159#define DP83867_LED_DRV_EN(x) BIT((x) * 4)
160#define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1)
161#define DP83867_LED_POLARITY(x) BIT((x) * 4 + 2)
162
163#define DP83867_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4))
164#define DP83867_LED_FN_MASK(idx) (0xf << ((idx) * 4))
165#define DP83867_LED_FN_RX_ERR 0xe /* Receive Error */
166#define DP83867_LED_FN_RX_TX_ERR 0xd /* Receive Error or Transmit Error */
167#define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */
168#define DP83867_LED_FN_FULL_DUPLEX 0xa /* Full duplex */
169#define DP83867_LED_FN_LINK_100_1000_BT 0x9 /* 100/1000BT link established */
170#define DP83867_LED_FN_LINK_10_100_BT 0x8 /* 10/100BT link established */
171#define DP83867_LED_FN_LINK_10_BT 0x7 /* 10BT link established */
172#define DP83867_LED_FN_LINK_100_BTX 0x6 /* 100 BTX link established */
173#define DP83867_LED_FN_LINK_1000_BT 0x5 /* 1000 BT link established */
174#define DP83867_LED_FN_COLLISION 0x4 /* Collision detected */
175#define DP83867_LED_FN_RX 0x3 /* Receive activity */
176#define DP83867_LED_FN_TX 0x2 /* Transmit activity */
177#define DP83867_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */
178#define DP83867_LED_FN_LINK 0x0 /* Link established */
179
180enum {
181 DP83867_PORT_MIRROING_KEEP,
182 DP83867_PORT_MIRROING_EN,
183 DP83867_PORT_MIRROING_DIS,
184};
185
186struct dp83867_private {
187 u32 rx_id_delay;
188 u32 tx_id_delay;
189 u32 tx_fifo_depth;
190 u32 rx_fifo_depth;
191 int io_impedance;
192 int port_mirroring;
193 bool rxctrl_strap_quirk;
194 bool set_clk_output;
195 u32 clk_output_sel;
196 bool sgmii_ref_clk_en;
197};
198
199static int dp83867_ack_interrupt(struct phy_device *phydev)
200{
201 int err = phy_read(phydev, MII_DP83867_ISR);
202
203 if (err < 0)
204 return err;
205
206 return 0;
207}
208
209static int dp83867_set_wol(struct phy_device *phydev,
210 struct ethtool_wolinfo *wol)
211{
212 struct net_device *ndev = phydev->attached_dev;
213 u16 val_rxcfg, val_micr;
214 const u8 *mac;
215
216 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
217 val_micr = phy_read(phydev, MII_DP83867_MICR);
218
219 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
220 WAKE_BCAST)) {
221 val_rxcfg |= DP83867_WOL_ENH_MAC;
222 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
223
224 if (wol->wolopts & WAKE_MAGIC) {
225 mac = (const u8 *)ndev->dev_addr;
226
227 if (!is_valid_ether_addr(mac))
228 return -EINVAL;
229
230 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
231 (mac[1] << 8 | mac[0]));
232 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
233 (mac[3] << 8 | mac[2]));
234 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
235 (mac[5] << 8 | mac[4]));
236
237 val_rxcfg |= DP83867_WOL_MAGIC_EN;
238 } else {
239 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
240 }
241
242 if (wol->wolopts & WAKE_MAGICSECURE) {
243 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
244 (wol->sopass[1] << 8) | wol->sopass[0]);
245 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
246 (wol->sopass[3] << 8) | wol->sopass[2]);
247 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
248 (wol->sopass[5] << 8) | wol->sopass[4]);
249
250 val_rxcfg |= DP83867_WOL_SEC_EN;
251 } else {
252 val_rxcfg &= ~DP83867_WOL_SEC_EN;
253 }
254
255 if (wol->wolopts & WAKE_UCAST)
256 val_rxcfg |= DP83867_WOL_UCAST_EN;
257 else
258 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
259
260 if (wol->wolopts & WAKE_BCAST)
261 val_rxcfg |= DP83867_WOL_BCAST_EN;
262 else
263 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
264 } else {
265 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
266 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
267 }
268
269 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
270 phy_write(phydev, MII_DP83867_MICR, val_micr);
271
272 return 0;
273}
274
275static void dp83867_get_wol(struct phy_device *phydev,
276 struct ethtool_wolinfo *wol)
277{
278 u16 value, sopass_val;
279
280 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
281 WAKE_MAGICSECURE);
282 wol->wolopts = 0;
283
284 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
285
286 if (value & DP83867_WOL_UCAST_EN)
287 wol->wolopts |= WAKE_UCAST;
288
289 if (value & DP83867_WOL_BCAST_EN)
290 wol->wolopts |= WAKE_BCAST;
291
292 if (value & DP83867_WOL_MAGIC_EN)
293 wol->wolopts |= WAKE_MAGIC;
294
295 if (value & DP83867_WOL_SEC_EN) {
296 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
297 DP83867_RXFSOP1);
298 wol->sopass[0] = (sopass_val & 0xff);
299 wol->sopass[1] = (sopass_val >> 8);
300
301 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
302 DP83867_RXFSOP2);
303 wol->sopass[2] = (sopass_val & 0xff);
304 wol->sopass[3] = (sopass_val >> 8);
305
306 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
307 DP83867_RXFSOP3);
308 wol->sopass[4] = (sopass_val & 0xff);
309 wol->sopass[5] = (sopass_val >> 8);
310
311 wol->wolopts |= WAKE_MAGICSECURE;
312 }
313
314 if (!(value & DP83867_WOL_ENH_MAC))
315 wol->wolopts = 0;
316}
317
318static int dp83867_config_intr(struct phy_device *phydev)
319{
320 int micr_status, err;
321
322 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
323 err = dp83867_ack_interrupt(phydev);
324 if (err)
325 return err;
326
327 micr_status = phy_read(phydev, MII_DP83867_MICR);
328 if (micr_status < 0)
329 return micr_status;
330
331 micr_status |=
332 (MII_DP83867_MICR_AN_ERR_INT_EN |
333 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
334 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
335 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
336 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
337 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
338
339 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
340 } else {
341 micr_status = 0x0;
342 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
343 if (err)
344 return err;
345
346 err = dp83867_ack_interrupt(phydev);
347 }
348
349 return err;
350}
351
352static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
353{
354 int irq_status, irq_enabled;
355
356 irq_status = phy_read(phydev, MII_DP83867_ISR);
357 if (irq_status < 0) {
358 phy_error(phydev);
359 return IRQ_NONE;
360 }
361
362 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
363 if (irq_enabled < 0) {
364 phy_error(phydev);
365 return IRQ_NONE;
366 }
367
368 if (!(irq_status & irq_enabled))
369 return IRQ_NONE;
370
371 phy_trigger_machine(phydev);
372
373 return IRQ_HANDLED;
374}
375
376static int dp83867_read_status(struct phy_device *phydev)
377{
378 int status = phy_read(phydev, MII_DP83867_PHYSTS);
379 int ret;
380
381 ret = genphy_read_status(phydev);
382 if (ret)
383 return ret;
384
385 if (status < 0)
386 return status;
387
388 if (status & DP83867_PHYSTS_DUPLEX)
389 phydev->duplex = DUPLEX_FULL;
390 else
391 phydev->duplex = DUPLEX_HALF;
392
393 if (status & DP83867_PHYSTS_1000)
394 phydev->speed = SPEED_1000;
395 else if (status & DP83867_PHYSTS_100)
396 phydev->speed = SPEED_100;
397 else
398 phydev->speed = SPEED_10;
399
400 return 0;
401}
402
403static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
404{
405 int val, cnt, enable, count;
406
407 val = phy_read(phydev, DP83867_CFG2);
408 if (val < 0)
409 return val;
410
411 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
412 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
413
414 switch (cnt) {
415 case DP83867_DOWNSHIFT_1_COUNT_VAL:
416 count = DP83867_DOWNSHIFT_1_COUNT;
417 break;
418 case DP83867_DOWNSHIFT_2_COUNT_VAL:
419 count = DP83867_DOWNSHIFT_2_COUNT;
420 break;
421 case DP83867_DOWNSHIFT_4_COUNT_VAL:
422 count = DP83867_DOWNSHIFT_4_COUNT;
423 break;
424 case DP83867_DOWNSHIFT_8_COUNT_VAL:
425 count = DP83867_DOWNSHIFT_8_COUNT;
426 break;
427 default:
428 return -EINVAL;
429 }
430
431 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
432
433 return 0;
434}
435
436static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
437{
438 int val, count;
439
440 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
441 return -E2BIG;
442
443 if (!cnt)
444 return phy_clear_bits(phydev, DP83867_CFG2,
445 DP83867_DOWNSHIFT_EN);
446
447 switch (cnt) {
448 case DP83867_DOWNSHIFT_1_COUNT:
449 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
450 break;
451 case DP83867_DOWNSHIFT_2_COUNT:
452 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
453 break;
454 case DP83867_DOWNSHIFT_4_COUNT:
455 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
456 break;
457 case DP83867_DOWNSHIFT_8_COUNT:
458 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
459 break;
460 default:
461 phydev_err(phydev,
462 "Downshift count must be 1, 2, 4 or 8\n");
463 return -EINVAL;
464 }
465
466 val = DP83867_DOWNSHIFT_EN;
467 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
468
469 return phy_modify(phydev, DP83867_CFG2,
470 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
471 val);
472}
473
474static int dp83867_get_tunable(struct phy_device *phydev,
475 struct ethtool_tunable *tuna, void *data)
476{
477 switch (tuna->id) {
478 case ETHTOOL_PHY_DOWNSHIFT:
479 return dp83867_get_downshift(phydev, data);
480 default:
481 return -EOPNOTSUPP;
482 }
483}
484
485static int dp83867_set_tunable(struct phy_device *phydev,
486 struct ethtool_tunable *tuna, const void *data)
487{
488 switch (tuna->id) {
489 case ETHTOOL_PHY_DOWNSHIFT:
490 return dp83867_set_downshift(phydev, *(const u8 *)data);
491 default:
492 return -EOPNOTSUPP;
493 }
494}
495
496static int dp83867_config_port_mirroring(struct phy_device *phydev)
497{
498 struct dp83867_private *dp83867 = phydev->priv;
499
500 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
501 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
502 DP83867_CFG4_PORT_MIRROR_EN);
503 else
504 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
505 DP83867_CFG4_PORT_MIRROR_EN);
506 return 0;
507}
508
509static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
510{
511 struct dp83867_private *dp83867 = phydev->priv;
512
513 /* Existing behavior was to use default pin strapping delay in rgmii
514 * mode, but rgmii should have meant no delay. Warn existing users.
515 */
516 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
517 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
518 DP83867_STRAP_STS2);
519 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
520 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
521 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
522 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
523
524 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
525 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
526 phydev_warn(phydev,
527 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
528 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
529 txskew, rxskew);
530 }
531
532 /* RX delay *must* be specified if internal delay of RX is used. */
533 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
534 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
535 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
536 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
537 return -EINVAL;
538 }
539
540 /* TX delay *must* be specified if internal delay of TX is used. */
541 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
542 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
543 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
544 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
545 return -EINVAL;
546 }
547
548 return 0;
549}
550
551#if IS_ENABLED(CONFIG_OF_MDIO)
552static int dp83867_of_init_io_impedance(struct phy_device *phydev)
553{
554 struct dp83867_private *dp83867 = phydev->priv;
555 struct device *dev = &phydev->mdio.dev;
556 struct device_node *of_node = dev->of_node;
557 struct nvmem_cell *cell;
558 u8 *buf, val;
559 int ret;
560
561 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl");
562 if (IS_ERR(cell)) {
563 ret = PTR_ERR(cell);
564 if (ret != -ENOENT && ret != -EOPNOTSUPP)
565 return phydev_err_probe(phydev, ret,
566 "failed to get nvmem cell io_impedance_ctrl\n");
567
568 /* If no nvmem cell, check for the boolean properties. */
569 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
570 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
571 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
572 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
573 else
574 dp83867->io_impedance = -1; /* leave at default */
575
576 return 0;
577 }
578
579 buf = nvmem_cell_read(cell, NULL);
580 nvmem_cell_put(cell);
581
582 if (IS_ERR(buf))
583 return PTR_ERR(buf);
584
585 val = *buf;
586 kfree(buf);
587
588 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) {
589 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
590 return -ERANGE;
591 }
592 dp83867->io_impedance = val;
593
594 return 0;
595}
596
597static int dp83867_of_init(struct phy_device *phydev)
598{
599 struct dp83867_private *dp83867 = phydev->priv;
600 struct device *dev = &phydev->mdio.dev;
601 struct device_node *of_node = dev->of_node;
602 int ret;
603
604 if (!of_node)
605 return -ENODEV;
606
607 /* Optional configuration */
608 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
609 &dp83867->clk_output_sel);
610 /* If not set, keep default */
611 if (!ret) {
612 dp83867->set_clk_output = true;
613 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
614 * DP83867_CLK_O_SEL_OFF.
615 */
616 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
617 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
618 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
619 dp83867->clk_output_sel);
620 return -EINVAL;
621 }
622 }
623
624 ret = dp83867_of_init_io_impedance(phydev);
625 if (ret)
626 return ret;
627
628 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
629 "ti,dp83867-rxctrl-strap-quirk");
630
631 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
632 "ti,sgmii-ref-clock-output-enable");
633
634 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
635 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
636 &dp83867->rx_id_delay);
637 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
638 phydev_err(phydev,
639 "ti,rx-internal-delay value of %u out of range\n",
640 dp83867->rx_id_delay);
641 return -EINVAL;
642 }
643
644 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
645 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
646 &dp83867->tx_id_delay);
647 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
648 phydev_err(phydev,
649 "ti,tx-internal-delay value of %u out of range\n",
650 dp83867->tx_id_delay);
651 return -EINVAL;
652 }
653
654 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
655 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
656
657 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
658 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
659
660 ret = of_property_read_u32(of_node, "ti,fifo-depth",
661 &dp83867->tx_fifo_depth);
662 if (ret) {
663 ret = of_property_read_u32(of_node, "tx-fifo-depth",
664 &dp83867->tx_fifo_depth);
665 if (ret)
666 dp83867->tx_fifo_depth =
667 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
668 }
669
670 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
671 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
672 dp83867->tx_fifo_depth);
673 return -EINVAL;
674 }
675
676 ret = of_property_read_u32(of_node, "rx-fifo-depth",
677 &dp83867->rx_fifo_depth);
678 if (ret)
679 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
680
681 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
682 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
683 dp83867->rx_fifo_depth);
684 return -EINVAL;
685 }
686
687 return 0;
688}
689#else
690static int dp83867_of_init(struct phy_device *phydev)
691{
692 struct dp83867_private *dp83867 = phydev->priv;
693 u16 delay;
694
695 /* For non-OF device, the RX and TX ID values are either strapped
696 * or take from default value. So, we init RX & TX ID values here
697 * so that the RGMIIDCTL is configured correctly later in
698 * dp83867_config_init();
699 */
700 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
701 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
702 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
703 DP83867_RGMII_TX_CLK_DELAY_MAX;
704
705 /* Per datasheet, IO impedance is default to 50-ohm, so we set the
706 * same here or else the default '0' means highest IO impedance
707 * which is wrong.
708 */
709 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
710
711 /* For non-OF device, the RX and TX FIFO depths are taken from
712 * default value. So, we init RX & TX FIFO depths here
713 * so that it is configured correctly later in dp83867_config_init();
714 */
715 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
716 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
717
718 return 0;
719}
720#endif /* CONFIG_OF_MDIO */
721
722static int dp83867_suspend(struct phy_device *phydev)
723{
724 /* Disable PHY Interrupts */
725 if (phy_interrupt_is_valid(phydev)) {
726 phydev->interrupts = PHY_INTERRUPT_DISABLED;
727 dp83867_config_intr(phydev);
728 }
729
730 return genphy_suspend(phydev);
731}
732
733static int dp83867_resume(struct phy_device *phydev)
734{
735 /* Enable PHY Interrupts */
736 if (phy_interrupt_is_valid(phydev)) {
737 phydev->interrupts = PHY_INTERRUPT_ENABLED;
738 dp83867_config_intr(phydev);
739 }
740
741 genphy_resume(phydev);
742
743 return 0;
744}
745
746static int dp83867_probe(struct phy_device *phydev)
747{
748 struct dp83867_private *dp83867;
749
750 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
751 GFP_KERNEL);
752 if (!dp83867)
753 return -ENOMEM;
754
755 phydev->priv = dp83867;
756
757 return dp83867_of_init(phydev);
758}
759
760static int dp83867_config_init(struct phy_device *phydev)
761{
762 struct dp83867_private *dp83867 = phydev->priv;
763 int ret, val, bs;
764 u16 delay;
765
766 /* Force speed optimization for the PHY even if it strapped */
767 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
768 DP83867_DOWNSHIFT_EN);
769 if (ret)
770 return ret;
771
772 ret = dp83867_verify_rgmii_cfg(phydev);
773 if (ret)
774 return ret;
775
776 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
777 if (dp83867->rxctrl_strap_quirk)
778 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
779 BIT(7));
780
781 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
782 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
783 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
784 * be set to 0x2. This may causes the PHY link to be unstable -
785 * the default value 0x1 need to be restored.
786 */
787 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
788 DP83867_FLD_THR_CFG,
789 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
790 0x1);
791 if (ret)
792 return ret;
793 }
794
795 if (phy_interface_is_rgmii(phydev) ||
796 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
797 val = phy_read(phydev, MII_DP83867_PHYCTRL);
798 if (val < 0)
799 return val;
800
801 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
802 val |= (dp83867->tx_fifo_depth <<
803 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
804
805 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
806 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
807 val |= (dp83867->rx_fifo_depth <<
808 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
809 }
810
811 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
812 if (ret)
813 return ret;
814 }
815
816 if (phy_interface_is_rgmii(phydev)) {
817 val = phy_read(phydev, MII_DP83867_PHYCTRL);
818 if (val < 0)
819 return val;
820
821 /* The code below checks if "port mirroring" N/A MODE4 has been
822 * enabled during power on bootstrap.
823 *
824 * Such N/A mode enabled by mistake can put PHY IC in some
825 * internal testing mode and disable RGMII transmission.
826 *
827 * In this particular case one needs to check STRAP_STS1
828 * register's bit 11 (marked as RESERVED).
829 */
830
831 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
832 if (bs & DP83867_STRAP_STS1_RESERVED)
833 val &= ~DP83867_PHYCR_RESERVED_MASK;
834
835 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
836 if (ret)
837 return ret;
838
839 /* If rgmii mode with no internal delay is selected, we do NOT use
840 * aligned mode as one might expect. Instead we use the PHY's default
841 * based on pin strapping. And the "mode 0" default is to *use*
842 * internal delay with a value of 7 (2.00 ns).
843 *
844 * Set up RGMII delays
845 */
846 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
847
848 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
849 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
850 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
851
852 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
853 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
854
855 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
856 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
857
858 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
859
860 delay = 0;
861 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
862 delay |= dp83867->rx_id_delay;
863 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
864 delay |= dp83867->tx_id_delay <<
865 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
866
867 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
868 delay);
869 }
870
871 /* If specified, set io impedance */
872 if (dp83867->io_impedance >= 0)
873 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
874 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
875 dp83867->io_impedance);
876
877 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
878 /* For support SPEED_10 in SGMII mode
879 * DP83867_10M_SGMII_RATE_ADAPT bit
880 * has to be cleared by software. That
881 * does not affect SPEED_100 and
882 * SPEED_1000.
883 */
884 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
885 DP83867_10M_SGMII_CFG,
886 DP83867_10M_SGMII_RATE_ADAPT_MASK,
887 0);
888 if (ret)
889 return ret;
890
891 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
892 * are 01). That is not enough to finalize autoneg on some
893 * devices. Increase this timer duration to maximum 16ms.
894 */
895 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
896 DP83867_CFG4,
897 DP83867_CFG4_SGMII_ANEG_MASK,
898 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
899
900 if (ret)
901 return ret;
902
903 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
904 /* SGMII type is set to 4-wire mode by default.
905 * If we place appropriate property in dts (see above)
906 * switch on 6-wire mode.
907 */
908 if (dp83867->sgmii_ref_clk_en)
909 val |= DP83867_SGMII_TYPE;
910 else
911 val &= ~DP83867_SGMII_TYPE;
912 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
913
914 /* This is a SW workaround for link instability if RX_CTRL is
915 * not strapped to mode 3 or 4 in HW. This is required for SGMII
916 * in addition to clearing bit 7, handled above.
917 */
918 if (dp83867->rxctrl_strap_quirk)
919 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
920 BIT(8));
921 }
922
923 val = phy_read(phydev, DP83867_CFG3);
924 /* Enable Interrupt output INT_OE in CFG3 register */
925 if (phy_interrupt_is_valid(phydev))
926 val |= DP83867_CFG3_INT_OE;
927
928 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
929 phy_write(phydev, DP83867_CFG3, val);
930
931 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
932 dp83867_config_port_mirroring(phydev);
933
934 /* Clock output selection if muxing property is set */
935 if (dp83867->set_clk_output) {
936 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
937
938 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
939 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
940 } else {
941 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
942 val = dp83867->clk_output_sel <<
943 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
944 }
945
946 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
947 mask, val);
948 }
949
950 return 0;
951}
952
953static int dp83867_phy_reset(struct phy_device *phydev)
954{
955 int err;
956
957 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
958 if (err < 0)
959 return err;
960
961 usleep_range(10, 20);
962
963 err = phy_modify(phydev, MII_DP83867_PHYCTRL,
964 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
965 if (err < 0)
966 return err;
967
968 /* Configure the DSP Feedforward Equalizer Configuration register to
969 * improve short cable (< 1 meter) performance. This will not affect
970 * long cable performance.
971 */
972 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,
973 0x0e81);
974 if (err < 0)
975 return err;
976
977 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
978 if (err < 0)
979 return err;
980
981 usleep_range(10, 20);
982
983 return 0;
984}
985
986static void dp83867_link_change_notify(struct phy_device *phydev)
987{
988 /* There is a limitation in DP83867 PHY device where SGMII AN is
989 * only triggered once after the device is booted up. Even after the
990 * PHY TPI is down and up again, SGMII AN is not triggered and
991 * hence no new in-band message from PHY to MAC side SGMII.
992 * This could cause an issue during power up, when PHY is up prior
993 * to MAC. At this condition, once MAC side SGMII is up, MAC side
994 * SGMII wouldn`t receive new in-band message from TI PHY with
995 * correct link status, speed and duplex info.
996 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
997 * whenever there is a link change.
998 */
999 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1000 int val = 0;
1001
1002 val = phy_clear_bits(phydev, DP83867_CFG2,
1003 DP83867_SGMII_AUTONEG_EN);
1004 if (val < 0)
1005 return;
1006
1007 phy_set_bits(phydev, DP83867_CFG2,
1008 DP83867_SGMII_AUTONEG_EN);
1009 }
1010}
1011
1012static int dp83867_loopback(struct phy_device *phydev, bool enable)
1013{
1014 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
1015 enable ? BMCR_LOOPBACK : 0);
1016}
1017
1018static int
1019dp83867_led_brightness_set(struct phy_device *phydev,
1020 u8 index, enum led_brightness brightness)
1021{
1022 u32 val;
1023
1024 if (index >= DP83867_LED_COUNT)
1025 return -EINVAL;
1026
1027 /* DRV_EN==1: output is DRV_VAL */
1028 val = DP83867_LED_DRV_EN(index);
1029
1030 if (brightness)
1031 val |= DP83867_LED_DRV_VAL(index);
1032
1033 return phy_modify(phydev, DP83867_LEDCR2,
1034 DP83867_LED_DRV_VAL(index) |
1035 DP83867_LED_DRV_EN(index),
1036 val);
1037}
1038
1039static int dp83867_led_mode(u8 index, unsigned long rules)
1040{
1041 if (index >= DP83867_LED_COUNT)
1042 return -EINVAL;
1043
1044 switch (rules) {
1045 case BIT(TRIGGER_NETDEV_LINK):
1046 return DP83867_LED_FN_LINK;
1047 case BIT(TRIGGER_NETDEV_LINK_10):
1048 return DP83867_LED_FN_LINK_10_BT;
1049 case BIT(TRIGGER_NETDEV_LINK_100):
1050 return DP83867_LED_FN_LINK_100_BTX;
1051 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
1052 return DP83867_LED_FN_FULL_DUPLEX;
1053 case BIT(TRIGGER_NETDEV_TX):
1054 return DP83867_LED_FN_TX;
1055 case BIT(TRIGGER_NETDEV_RX):
1056 return DP83867_LED_FN_RX;
1057 case BIT(TRIGGER_NETDEV_LINK_1000):
1058 return DP83867_LED_FN_LINK_1000_BT;
1059 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1060 return DP83867_LED_FN_RX_TX;
1061 case BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000):
1062 return DP83867_LED_FN_LINK_100_1000_BT;
1063 case BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100):
1064 return DP83867_LED_FN_LINK_10_100_BT;
1065 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1066 return DP83867_LED_FN_LINK_RX_TX;
1067 default:
1068 return -EOPNOTSUPP;
1069 }
1070}
1071
1072static int dp83867_led_hw_is_supported(struct phy_device *phydev, u8 index,
1073 unsigned long rules)
1074{
1075 int ret;
1076
1077 ret = dp83867_led_mode(index, rules);
1078 if (ret < 0)
1079 return ret;
1080
1081 return 0;
1082}
1083
1084static int dp83867_led_hw_control_set(struct phy_device *phydev, u8 index,
1085 unsigned long rules)
1086{
1087 int mode, ret;
1088
1089 mode = dp83867_led_mode(index, rules);
1090 if (mode < 0)
1091 return mode;
1092
1093 ret = phy_modify(phydev, DP83867_LEDCR1, DP83867_LED_FN_MASK(index),
1094 DP83867_LED_FN(index, mode));
1095 if (ret)
1096 return ret;
1097
1098 return phy_modify(phydev, DP83867_LEDCR2, DP83867_LED_DRV_EN(index), 0);
1099}
1100
1101static int dp83867_led_hw_control_get(struct phy_device *phydev, u8 index,
1102 unsigned long *rules)
1103{
1104 int val;
1105
1106 val = phy_read(phydev, DP83867_LEDCR1);
1107 if (val < 0)
1108 return val;
1109
1110 val &= DP83867_LED_FN_MASK(index);
1111 val >>= index * 4;
1112
1113 switch (val) {
1114 case DP83867_LED_FN_LINK:
1115 *rules = BIT(TRIGGER_NETDEV_LINK);
1116 break;
1117 case DP83867_LED_FN_LINK_10_BT:
1118 *rules = BIT(TRIGGER_NETDEV_LINK_10);
1119 break;
1120 case DP83867_LED_FN_LINK_100_BTX:
1121 *rules = BIT(TRIGGER_NETDEV_LINK_100);
1122 break;
1123 case DP83867_LED_FN_FULL_DUPLEX:
1124 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1125 break;
1126 case DP83867_LED_FN_TX:
1127 *rules = BIT(TRIGGER_NETDEV_TX);
1128 break;
1129 case DP83867_LED_FN_RX:
1130 *rules = BIT(TRIGGER_NETDEV_RX);
1131 break;
1132 case DP83867_LED_FN_LINK_1000_BT:
1133 *rules = BIT(TRIGGER_NETDEV_LINK_1000);
1134 break;
1135 case DP83867_LED_FN_RX_TX:
1136 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
1137 break;
1138 case DP83867_LED_FN_LINK_100_1000_BT:
1139 *rules = BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000);
1140 break;
1141 case DP83867_LED_FN_LINK_10_100_BT:
1142 *rules = BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100);
1143 break;
1144 case DP83867_LED_FN_LINK_RX_TX:
1145 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
1146 BIT(TRIGGER_NETDEV_RX);
1147 break;
1148 default:
1149 *rules = 0;
1150 break;
1151 }
1152
1153 return 0;
1154}
1155
1156static int dp83867_led_polarity_set(struct phy_device *phydev, int index,
1157 unsigned long modes)
1158{
1159 /* Default active high */
1160 u16 polarity = DP83867_LED_POLARITY(index);
1161 u32 mode;
1162
1163 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
1164 switch (mode) {
1165 case PHY_LED_ACTIVE_LOW:
1166 polarity = 0;
1167 break;
1168 default:
1169 return -EINVAL;
1170 }
1171 }
1172 return phy_modify(phydev, DP83867_LEDCR2,
1173 DP83867_LED_POLARITY(index), polarity);
1174}
1175
1176static struct phy_driver dp83867_driver[] = {
1177 {
1178 .phy_id = DP83867_PHY_ID,
1179 .phy_id_mask = 0xfffffff0,
1180 .name = "TI DP83867",
1181 /* PHY_GBIT_FEATURES */
1182
1183 .probe = dp83867_probe,
1184 .config_init = dp83867_config_init,
1185 .soft_reset = dp83867_phy_reset,
1186
1187 .read_status = dp83867_read_status,
1188 .get_tunable = dp83867_get_tunable,
1189 .set_tunable = dp83867_set_tunable,
1190
1191 .get_wol = dp83867_get_wol,
1192 .set_wol = dp83867_set_wol,
1193
1194 /* IRQ related */
1195 .config_intr = dp83867_config_intr,
1196 .handle_interrupt = dp83867_handle_interrupt,
1197
1198 .suspend = dp83867_suspend,
1199 .resume = dp83867_resume,
1200
1201 .link_change_notify = dp83867_link_change_notify,
1202 .set_loopback = dp83867_loopback,
1203
1204 .led_brightness_set = dp83867_led_brightness_set,
1205 .led_hw_is_supported = dp83867_led_hw_is_supported,
1206 .led_hw_control_set = dp83867_led_hw_control_set,
1207 .led_hw_control_get = dp83867_led_hw_control_get,
1208 .led_polarity_set = dp83867_led_polarity_set,
1209 },
1210};
1211module_phy_driver(dp83867_driver);
1212
1213static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
1214 { DP83867_PHY_ID, 0xfffffff0 },
1215 { }
1216};
1217
1218MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
1219
1220MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
1221MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
1222MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/* Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 */
6
7#include <linux/ethtool.h>
8#include <linux/kernel.h>
9#include <linux/mii.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/phy.h>
13#include <linux/delay.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/bitfield.h>
17#include <linux/nvmem-consumer.h>
18
19#include <dt-bindings/net/ti-dp83867.h>
20
21#define DP83867_PHY_ID 0x2000a231
22#define DP83867_DEVADDR 0x1f
23
24#define MII_DP83867_PHYCTRL 0x10
25#define MII_DP83867_PHYSTS 0x11
26#define MII_DP83867_MICR 0x12
27#define MII_DP83867_ISR 0x13
28#define DP83867_CFG2 0x14
29#define DP83867_LEDCR1 0x18
30#define DP83867_LEDCR2 0x19
31#define DP83867_CFG3 0x1e
32#define DP83867_CTRL 0x1f
33
34/* Extended Registers */
35#define DP83867_FLD_THR_CFG 0x002e
36#define DP83867_CFG4 0x0031
37#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
38#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
39#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
40#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
41#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
42
43#define DP83867_RGMIICTL 0x0032
44#define DP83867_STRAP_STS1 0x006E
45#define DP83867_STRAP_STS2 0x006f
46#define DP83867_RGMIIDCTL 0x0086
47#define DP83867_DSP_FFE_CFG 0x012c
48#define DP83867_RXFCFG 0x0134
49#define DP83867_RXFPMD1 0x0136
50#define DP83867_RXFPMD2 0x0137
51#define DP83867_RXFPMD3 0x0138
52#define DP83867_RXFSOP1 0x0139
53#define DP83867_RXFSOP2 0x013A
54#define DP83867_RXFSOP3 0x013B
55#define DP83867_IO_MUX_CFG 0x0170
56#define DP83867_SGMIICTL 0x00D3
57#define DP83867_10M_SGMII_CFG 0x016F
58#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
59
60#define DP83867_SW_RESET BIT(15)
61#define DP83867_SW_RESTART BIT(14)
62
63/* MICR Interrupt bits */
64#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
65#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
66#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
67#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
68#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
69#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
70#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
71#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
72#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
73#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
74#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
75#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
76
77/* RGMIICTL bits */
78#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
79#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
80
81/* SGMIICTL bits */
82#define DP83867_SGMII_TYPE BIT(14)
83
84/* RXFCFG bits*/
85#define DP83867_WOL_MAGIC_EN BIT(0)
86#define DP83867_WOL_BCAST_EN BIT(2)
87#define DP83867_WOL_UCAST_EN BIT(4)
88#define DP83867_WOL_SEC_EN BIT(5)
89#define DP83867_WOL_ENH_MAC BIT(7)
90
91/* STRAP_STS1 bits */
92#define DP83867_STRAP_STS1_RESERVED BIT(11)
93
94/* STRAP_STS2 bits */
95#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
96#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
97#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
98#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
99#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
100#define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
101
102/* PHY CTRL bits */
103#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
104#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
105#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
106#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
107#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
108#define DP83867_PHYCR_RESERVED_MASK BIT(11)
109#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
110
111/* RGMIIDCTL bits */
112#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
113#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
114#define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
115#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
116#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
117#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
118
119/* IO_MUX_CFG bits */
120#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
121#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
122#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
123#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
124#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
125#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
126
127/* PHY STS bits */
128#define DP83867_PHYSTS_1000 BIT(15)
129#define DP83867_PHYSTS_100 BIT(14)
130#define DP83867_PHYSTS_DUPLEX BIT(13)
131#define DP83867_PHYSTS_LINK BIT(10)
132
133/* CFG2 bits */
134#define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
135#define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
136#define DP83867_DOWNSHIFT_1_COUNT_VAL 0
137#define DP83867_DOWNSHIFT_2_COUNT_VAL 1
138#define DP83867_DOWNSHIFT_4_COUNT_VAL 2
139#define DP83867_DOWNSHIFT_8_COUNT_VAL 3
140#define DP83867_DOWNSHIFT_1_COUNT 1
141#define DP83867_DOWNSHIFT_2_COUNT 2
142#define DP83867_DOWNSHIFT_4_COUNT 4
143#define DP83867_DOWNSHIFT_8_COUNT 8
144#define DP83867_SGMII_AUTONEG_EN BIT(7)
145
146/* CFG3 bits */
147#define DP83867_CFG3_INT_OE BIT(7)
148#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
149
150/* CFG4 bits */
151#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
152
153/* FLD_THR_CFG */
154#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
155
156#define DP83867_LED_COUNT 4
157
158/* LED_DRV bits */
159#define DP83867_LED_DRV_EN(x) BIT((x) * 4)
160#define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1)
161
162#define DP83867_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4))
163#define DP83867_LED_FN_MASK(idx) (0xf << ((idx) * 4))
164#define DP83867_LED_FN_RX_ERR 0xe /* Receive Error */
165#define DP83867_LED_FN_RX_TX_ERR 0xd /* Receive Error or Transmit Error */
166#define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */
167#define DP83867_LED_FN_FULL_DUPLEX 0xa /* Full duplex */
168#define DP83867_LED_FN_LINK_100_1000_BT 0x9 /* 100/1000BT link established */
169#define DP83867_LED_FN_LINK_10_100_BT 0x8 /* 10/100BT link established */
170#define DP83867_LED_FN_LINK_10_BT 0x7 /* 10BT link established */
171#define DP83867_LED_FN_LINK_100_BTX 0x6 /* 100 BTX link established */
172#define DP83867_LED_FN_LINK_1000_BT 0x5 /* 1000 BT link established */
173#define DP83867_LED_FN_COLLISION 0x4 /* Collision detected */
174#define DP83867_LED_FN_RX 0x3 /* Receive activity */
175#define DP83867_LED_FN_TX 0x2 /* Transmit activity */
176#define DP83867_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */
177#define DP83867_LED_FN_LINK 0x0 /* Link established */
178
179enum {
180 DP83867_PORT_MIRROING_KEEP,
181 DP83867_PORT_MIRROING_EN,
182 DP83867_PORT_MIRROING_DIS,
183};
184
185struct dp83867_private {
186 u32 rx_id_delay;
187 u32 tx_id_delay;
188 u32 tx_fifo_depth;
189 u32 rx_fifo_depth;
190 int io_impedance;
191 int port_mirroring;
192 bool rxctrl_strap_quirk;
193 bool set_clk_output;
194 u32 clk_output_sel;
195 bool sgmii_ref_clk_en;
196};
197
198static int dp83867_ack_interrupt(struct phy_device *phydev)
199{
200 int err = phy_read(phydev, MII_DP83867_ISR);
201
202 if (err < 0)
203 return err;
204
205 return 0;
206}
207
208static int dp83867_set_wol(struct phy_device *phydev,
209 struct ethtool_wolinfo *wol)
210{
211 struct net_device *ndev = phydev->attached_dev;
212 u16 val_rxcfg, val_micr;
213 const u8 *mac;
214
215 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
216 val_micr = phy_read(phydev, MII_DP83867_MICR);
217
218 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
219 WAKE_BCAST)) {
220 val_rxcfg |= DP83867_WOL_ENH_MAC;
221 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
222
223 if (wol->wolopts & WAKE_MAGIC) {
224 mac = (const u8 *)ndev->dev_addr;
225
226 if (!is_valid_ether_addr(mac))
227 return -EINVAL;
228
229 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
230 (mac[1] << 8 | mac[0]));
231 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
232 (mac[3] << 8 | mac[2]));
233 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
234 (mac[5] << 8 | mac[4]));
235
236 val_rxcfg |= DP83867_WOL_MAGIC_EN;
237 } else {
238 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
239 }
240
241 if (wol->wolopts & WAKE_MAGICSECURE) {
242 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
243 (wol->sopass[1] << 8) | wol->sopass[0]);
244 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
245 (wol->sopass[3] << 8) | wol->sopass[2]);
246 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
247 (wol->sopass[5] << 8) | wol->sopass[4]);
248
249 val_rxcfg |= DP83867_WOL_SEC_EN;
250 } else {
251 val_rxcfg &= ~DP83867_WOL_SEC_EN;
252 }
253
254 if (wol->wolopts & WAKE_UCAST)
255 val_rxcfg |= DP83867_WOL_UCAST_EN;
256 else
257 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
258
259 if (wol->wolopts & WAKE_BCAST)
260 val_rxcfg |= DP83867_WOL_BCAST_EN;
261 else
262 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
263 } else {
264 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
265 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
266 }
267
268 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
269 phy_write(phydev, MII_DP83867_MICR, val_micr);
270
271 return 0;
272}
273
274static void dp83867_get_wol(struct phy_device *phydev,
275 struct ethtool_wolinfo *wol)
276{
277 u16 value, sopass_val;
278
279 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
280 WAKE_MAGICSECURE);
281 wol->wolopts = 0;
282
283 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
284
285 if (value & DP83867_WOL_UCAST_EN)
286 wol->wolopts |= WAKE_UCAST;
287
288 if (value & DP83867_WOL_BCAST_EN)
289 wol->wolopts |= WAKE_BCAST;
290
291 if (value & DP83867_WOL_MAGIC_EN)
292 wol->wolopts |= WAKE_MAGIC;
293
294 if (value & DP83867_WOL_SEC_EN) {
295 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
296 DP83867_RXFSOP1);
297 wol->sopass[0] = (sopass_val & 0xff);
298 wol->sopass[1] = (sopass_val >> 8);
299
300 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
301 DP83867_RXFSOP2);
302 wol->sopass[2] = (sopass_val & 0xff);
303 wol->sopass[3] = (sopass_val >> 8);
304
305 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
306 DP83867_RXFSOP3);
307 wol->sopass[4] = (sopass_val & 0xff);
308 wol->sopass[5] = (sopass_val >> 8);
309
310 wol->wolopts |= WAKE_MAGICSECURE;
311 }
312
313 if (!(value & DP83867_WOL_ENH_MAC))
314 wol->wolopts = 0;
315}
316
317static int dp83867_config_intr(struct phy_device *phydev)
318{
319 int micr_status, err;
320
321 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
322 err = dp83867_ack_interrupt(phydev);
323 if (err)
324 return err;
325
326 micr_status = phy_read(phydev, MII_DP83867_MICR);
327 if (micr_status < 0)
328 return micr_status;
329
330 micr_status |=
331 (MII_DP83867_MICR_AN_ERR_INT_EN |
332 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
333 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
334 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
335 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
336 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
337
338 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
339 } else {
340 micr_status = 0x0;
341 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
342 if (err)
343 return err;
344
345 err = dp83867_ack_interrupt(phydev);
346 }
347
348 return err;
349}
350
351static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
352{
353 int irq_status, irq_enabled;
354
355 irq_status = phy_read(phydev, MII_DP83867_ISR);
356 if (irq_status < 0) {
357 phy_error(phydev);
358 return IRQ_NONE;
359 }
360
361 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
362 if (irq_enabled < 0) {
363 phy_error(phydev);
364 return IRQ_NONE;
365 }
366
367 if (!(irq_status & irq_enabled))
368 return IRQ_NONE;
369
370 phy_trigger_machine(phydev);
371
372 return IRQ_HANDLED;
373}
374
375static int dp83867_read_status(struct phy_device *phydev)
376{
377 int status = phy_read(phydev, MII_DP83867_PHYSTS);
378 int ret;
379
380 ret = genphy_read_status(phydev);
381 if (ret)
382 return ret;
383
384 if (status < 0)
385 return status;
386
387 if (status & DP83867_PHYSTS_DUPLEX)
388 phydev->duplex = DUPLEX_FULL;
389 else
390 phydev->duplex = DUPLEX_HALF;
391
392 if (status & DP83867_PHYSTS_1000)
393 phydev->speed = SPEED_1000;
394 else if (status & DP83867_PHYSTS_100)
395 phydev->speed = SPEED_100;
396 else
397 phydev->speed = SPEED_10;
398
399 return 0;
400}
401
402static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
403{
404 int val, cnt, enable, count;
405
406 val = phy_read(phydev, DP83867_CFG2);
407 if (val < 0)
408 return val;
409
410 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
411 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
412
413 switch (cnt) {
414 case DP83867_DOWNSHIFT_1_COUNT_VAL:
415 count = DP83867_DOWNSHIFT_1_COUNT;
416 break;
417 case DP83867_DOWNSHIFT_2_COUNT_VAL:
418 count = DP83867_DOWNSHIFT_2_COUNT;
419 break;
420 case DP83867_DOWNSHIFT_4_COUNT_VAL:
421 count = DP83867_DOWNSHIFT_4_COUNT;
422 break;
423 case DP83867_DOWNSHIFT_8_COUNT_VAL:
424 count = DP83867_DOWNSHIFT_8_COUNT;
425 break;
426 default:
427 return -EINVAL;
428 }
429
430 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
431
432 return 0;
433}
434
435static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
436{
437 int val, count;
438
439 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
440 return -E2BIG;
441
442 if (!cnt)
443 return phy_clear_bits(phydev, DP83867_CFG2,
444 DP83867_DOWNSHIFT_EN);
445
446 switch (cnt) {
447 case DP83867_DOWNSHIFT_1_COUNT:
448 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
449 break;
450 case DP83867_DOWNSHIFT_2_COUNT:
451 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
452 break;
453 case DP83867_DOWNSHIFT_4_COUNT:
454 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
455 break;
456 case DP83867_DOWNSHIFT_8_COUNT:
457 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
458 break;
459 default:
460 phydev_err(phydev,
461 "Downshift count must be 1, 2, 4 or 8\n");
462 return -EINVAL;
463 }
464
465 val = DP83867_DOWNSHIFT_EN;
466 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
467
468 return phy_modify(phydev, DP83867_CFG2,
469 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
470 val);
471}
472
473static int dp83867_get_tunable(struct phy_device *phydev,
474 struct ethtool_tunable *tuna, void *data)
475{
476 switch (tuna->id) {
477 case ETHTOOL_PHY_DOWNSHIFT:
478 return dp83867_get_downshift(phydev, data);
479 default:
480 return -EOPNOTSUPP;
481 }
482}
483
484static int dp83867_set_tunable(struct phy_device *phydev,
485 struct ethtool_tunable *tuna, const void *data)
486{
487 switch (tuna->id) {
488 case ETHTOOL_PHY_DOWNSHIFT:
489 return dp83867_set_downshift(phydev, *(const u8 *)data);
490 default:
491 return -EOPNOTSUPP;
492 }
493}
494
495static int dp83867_config_port_mirroring(struct phy_device *phydev)
496{
497 struct dp83867_private *dp83867 = phydev->priv;
498
499 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
500 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
501 DP83867_CFG4_PORT_MIRROR_EN);
502 else
503 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
504 DP83867_CFG4_PORT_MIRROR_EN);
505 return 0;
506}
507
508static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
509{
510 struct dp83867_private *dp83867 = phydev->priv;
511
512 /* Existing behavior was to use default pin strapping delay in rgmii
513 * mode, but rgmii should have meant no delay. Warn existing users.
514 */
515 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
516 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
517 DP83867_STRAP_STS2);
518 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
519 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
520 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
521 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
522
523 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
524 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
525 phydev_warn(phydev,
526 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
527 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
528 txskew, rxskew);
529 }
530
531 /* RX delay *must* be specified if internal delay of RX is used. */
532 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
533 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
534 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
535 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
536 return -EINVAL;
537 }
538
539 /* TX delay *must* be specified if internal delay of TX is used. */
540 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
541 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
542 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
543 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
544 return -EINVAL;
545 }
546
547 return 0;
548}
549
550#if IS_ENABLED(CONFIG_OF_MDIO)
551static int dp83867_of_init_io_impedance(struct phy_device *phydev)
552{
553 struct dp83867_private *dp83867 = phydev->priv;
554 struct device *dev = &phydev->mdio.dev;
555 struct device_node *of_node = dev->of_node;
556 struct nvmem_cell *cell;
557 u8 *buf, val;
558 int ret;
559
560 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl");
561 if (IS_ERR(cell)) {
562 ret = PTR_ERR(cell);
563 if (ret != -ENOENT && ret != -EOPNOTSUPP)
564 return phydev_err_probe(phydev, ret,
565 "failed to get nvmem cell io_impedance_ctrl\n");
566
567 /* If no nvmem cell, check for the boolean properties. */
568 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
569 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
570 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
571 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
572 else
573 dp83867->io_impedance = -1; /* leave at default */
574
575 return 0;
576 }
577
578 buf = nvmem_cell_read(cell, NULL);
579 nvmem_cell_put(cell);
580
581 if (IS_ERR(buf))
582 return PTR_ERR(buf);
583
584 val = *buf;
585 kfree(buf);
586
587 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) {
588 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
589 return -ERANGE;
590 }
591 dp83867->io_impedance = val;
592
593 return 0;
594}
595
596static int dp83867_of_init(struct phy_device *phydev)
597{
598 struct dp83867_private *dp83867 = phydev->priv;
599 struct device *dev = &phydev->mdio.dev;
600 struct device_node *of_node = dev->of_node;
601 int ret;
602
603 if (!of_node)
604 return -ENODEV;
605
606 /* Optional configuration */
607 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
608 &dp83867->clk_output_sel);
609 /* If not set, keep default */
610 if (!ret) {
611 dp83867->set_clk_output = true;
612 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
613 * DP83867_CLK_O_SEL_OFF.
614 */
615 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
616 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
617 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
618 dp83867->clk_output_sel);
619 return -EINVAL;
620 }
621 }
622
623 ret = dp83867_of_init_io_impedance(phydev);
624 if (ret)
625 return ret;
626
627 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
628 "ti,dp83867-rxctrl-strap-quirk");
629
630 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
631 "ti,sgmii-ref-clock-output-enable");
632
633 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
634 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
635 &dp83867->rx_id_delay);
636 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
637 phydev_err(phydev,
638 "ti,rx-internal-delay value of %u out of range\n",
639 dp83867->rx_id_delay);
640 return -EINVAL;
641 }
642
643 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
644 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
645 &dp83867->tx_id_delay);
646 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
647 phydev_err(phydev,
648 "ti,tx-internal-delay value of %u out of range\n",
649 dp83867->tx_id_delay);
650 return -EINVAL;
651 }
652
653 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
654 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
655
656 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
657 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
658
659 ret = of_property_read_u32(of_node, "ti,fifo-depth",
660 &dp83867->tx_fifo_depth);
661 if (ret) {
662 ret = of_property_read_u32(of_node, "tx-fifo-depth",
663 &dp83867->tx_fifo_depth);
664 if (ret)
665 dp83867->tx_fifo_depth =
666 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
667 }
668
669 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
670 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
671 dp83867->tx_fifo_depth);
672 return -EINVAL;
673 }
674
675 ret = of_property_read_u32(of_node, "rx-fifo-depth",
676 &dp83867->rx_fifo_depth);
677 if (ret)
678 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
679
680 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
681 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
682 dp83867->rx_fifo_depth);
683 return -EINVAL;
684 }
685
686 return 0;
687}
688#else
689static int dp83867_of_init(struct phy_device *phydev)
690{
691 struct dp83867_private *dp83867 = phydev->priv;
692 u16 delay;
693
694 /* For non-OF device, the RX and TX ID values are either strapped
695 * or take from default value. So, we init RX & TX ID values here
696 * so that the RGMIIDCTL is configured correctly later in
697 * dp83867_config_init();
698 */
699 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
700 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
701 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
702 DP83867_RGMII_TX_CLK_DELAY_MAX;
703
704 /* Per datasheet, IO impedance is default to 50-ohm, so we set the
705 * same here or else the default '0' means highest IO impedance
706 * which is wrong.
707 */
708 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
709
710 /* For non-OF device, the RX and TX FIFO depths are taken from
711 * default value. So, we init RX & TX FIFO depths here
712 * so that it is configured correctly later in dp83867_config_init();
713 */
714 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
715 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
716
717 return 0;
718}
719#endif /* CONFIG_OF_MDIO */
720
721static int dp83867_suspend(struct phy_device *phydev)
722{
723 /* Disable PHY Interrupts */
724 if (phy_interrupt_is_valid(phydev)) {
725 phydev->interrupts = PHY_INTERRUPT_DISABLED;
726 dp83867_config_intr(phydev);
727 }
728
729 return genphy_suspend(phydev);
730}
731
732static int dp83867_resume(struct phy_device *phydev)
733{
734 /* Enable PHY Interrupts */
735 if (phy_interrupt_is_valid(phydev)) {
736 phydev->interrupts = PHY_INTERRUPT_ENABLED;
737 dp83867_config_intr(phydev);
738 }
739
740 genphy_resume(phydev);
741
742 return 0;
743}
744
745static int dp83867_probe(struct phy_device *phydev)
746{
747 struct dp83867_private *dp83867;
748
749 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
750 GFP_KERNEL);
751 if (!dp83867)
752 return -ENOMEM;
753
754 phydev->priv = dp83867;
755
756 return dp83867_of_init(phydev);
757}
758
759static int dp83867_config_init(struct phy_device *phydev)
760{
761 struct dp83867_private *dp83867 = phydev->priv;
762 int ret, val, bs;
763 u16 delay;
764
765 /* Force speed optimization for the PHY even if it strapped */
766 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
767 DP83867_DOWNSHIFT_EN);
768 if (ret)
769 return ret;
770
771 ret = dp83867_verify_rgmii_cfg(phydev);
772 if (ret)
773 return ret;
774
775 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
776 if (dp83867->rxctrl_strap_quirk)
777 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
778 BIT(7));
779
780 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
781 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
782 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
783 * be set to 0x2. This may causes the PHY link to be unstable -
784 * the default value 0x1 need to be restored.
785 */
786 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
787 DP83867_FLD_THR_CFG,
788 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
789 0x1);
790 if (ret)
791 return ret;
792 }
793
794 if (phy_interface_is_rgmii(phydev) ||
795 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
796 val = phy_read(phydev, MII_DP83867_PHYCTRL);
797 if (val < 0)
798 return val;
799
800 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
801 val |= (dp83867->tx_fifo_depth <<
802 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
803
804 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
805 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
806 val |= (dp83867->rx_fifo_depth <<
807 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
808 }
809
810 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
811 if (ret)
812 return ret;
813 }
814
815 if (phy_interface_is_rgmii(phydev)) {
816 val = phy_read(phydev, MII_DP83867_PHYCTRL);
817 if (val < 0)
818 return val;
819
820 /* The code below checks if "port mirroring" N/A MODE4 has been
821 * enabled during power on bootstrap.
822 *
823 * Such N/A mode enabled by mistake can put PHY IC in some
824 * internal testing mode and disable RGMII transmission.
825 *
826 * In this particular case one needs to check STRAP_STS1
827 * register's bit 11 (marked as RESERVED).
828 */
829
830 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
831 if (bs & DP83867_STRAP_STS1_RESERVED)
832 val &= ~DP83867_PHYCR_RESERVED_MASK;
833
834 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
835 if (ret)
836 return ret;
837
838 /* If rgmii mode with no internal delay is selected, we do NOT use
839 * aligned mode as one might expect. Instead we use the PHY's default
840 * based on pin strapping. And the "mode 0" default is to *use*
841 * internal delay with a value of 7 (2.00 ns).
842 *
843 * Set up RGMII delays
844 */
845 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
846
847 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
848 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
849 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
850
851 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
852 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
853
854 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
855 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
856
857 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
858
859 delay = 0;
860 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
861 delay |= dp83867->rx_id_delay;
862 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
863 delay |= dp83867->tx_id_delay <<
864 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
865
866 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
867 delay);
868 }
869
870 /* If specified, set io impedance */
871 if (dp83867->io_impedance >= 0)
872 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
873 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
874 dp83867->io_impedance);
875
876 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
877 /* For support SPEED_10 in SGMII mode
878 * DP83867_10M_SGMII_RATE_ADAPT bit
879 * has to be cleared by software. That
880 * does not affect SPEED_100 and
881 * SPEED_1000.
882 */
883 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
884 DP83867_10M_SGMII_CFG,
885 DP83867_10M_SGMII_RATE_ADAPT_MASK,
886 0);
887 if (ret)
888 return ret;
889
890 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
891 * are 01). That is not enough to finalize autoneg on some
892 * devices. Increase this timer duration to maximum 16ms.
893 */
894 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
895 DP83867_CFG4,
896 DP83867_CFG4_SGMII_ANEG_MASK,
897 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
898
899 if (ret)
900 return ret;
901
902 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
903 /* SGMII type is set to 4-wire mode by default.
904 * If we place appropriate property in dts (see above)
905 * switch on 6-wire mode.
906 */
907 if (dp83867->sgmii_ref_clk_en)
908 val |= DP83867_SGMII_TYPE;
909 else
910 val &= ~DP83867_SGMII_TYPE;
911 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
912
913 /* This is a SW workaround for link instability if RX_CTRL is
914 * not strapped to mode 3 or 4 in HW. This is required for SGMII
915 * in addition to clearing bit 7, handled above.
916 */
917 if (dp83867->rxctrl_strap_quirk)
918 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
919 BIT(8));
920 }
921
922 val = phy_read(phydev, DP83867_CFG3);
923 /* Enable Interrupt output INT_OE in CFG3 register */
924 if (phy_interrupt_is_valid(phydev))
925 val |= DP83867_CFG3_INT_OE;
926
927 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
928 phy_write(phydev, DP83867_CFG3, val);
929
930 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
931 dp83867_config_port_mirroring(phydev);
932
933 /* Clock output selection if muxing property is set */
934 if (dp83867->set_clk_output) {
935 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
936
937 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
938 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
939 } else {
940 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
941 val = dp83867->clk_output_sel <<
942 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
943 }
944
945 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
946 mask, val);
947 }
948
949 return 0;
950}
951
952static int dp83867_phy_reset(struct phy_device *phydev)
953{
954 int err;
955
956 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
957 if (err < 0)
958 return err;
959
960 usleep_range(10, 20);
961
962 err = phy_modify(phydev, MII_DP83867_PHYCTRL,
963 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
964 if (err < 0)
965 return err;
966
967 /* Configure the DSP Feedforward Equalizer Configuration register to
968 * improve short cable (< 1 meter) performance. This will not affect
969 * long cable performance.
970 */
971 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,
972 0x0e81);
973 if (err < 0)
974 return err;
975
976 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
977 if (err < 0)
978 return err;
979
980 usleep_range(10, 20);
981
982 return 0;
983}
984
985static void dp83867_link_change_notify(struct phy_device *phydev)
986{
987 /* There is a limitation in DP83867 PHY device where SGMII AN is
988 * only triggered once after the device is booted up. Even after the
989 * PHY TPI is down and up again, SGMII AN is not triggered and
990 * hence no new in-band message from PHY to MAC side SGMII.
991 * This could cause an issue during power up, when PHY is up prior
992 * to MAC. At this condition, once MAC side SGMII is up, MAC side
993 * SGMII wouldn`t receive new in-band message from TI PHY with
994 * correct link status, speed and duplex info.
995 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
996 * whenever there is a link change.
997 */
998 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
999 int val = 0;
1000
1001 val = phy_clear_bits(phydev, DP83867_CFG2,
1002 DP83867_SGMII_AUTONEG_EN);
1003 if (val < 0)
1004 return;
1005
1006 phy_set_bits(phydev, DP83867_CFG2,
1007 DP83867_SGMII_AUTONEG_EN);
1008 }
1009}
1010
1011static int dp83867_loopback(struct phy_device *phydev, bool enable)
1012{
1013 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
1014 enable ? BMCR_LOOPBACK : 0);
1015}
1016
1017static int
1018dp83867_led_brightness_set(struct phy_device *phydev,
1019 u8 index, enum led_brightness brightness)
1020{
1021 u32 val;
1022
1023 if (index >= DP83867_LED_COUNT)
1024 return -EINVAL;
1025
1026 /* DRV_EN==1: output is DRV_VAL */
1027 val = DP83867_LED_DRV_EN(index);
1028
1029 if (brightness)
1030 val |= DP83867_LED_DRV_VAL(index);
1031
1032 return phy_modify(phydev, DP83867_LEDCR2,
1033 DP83867_LED_DRV_VAL(index) |
1034 DP83867_LED_DRV_EN(index),
1035 val);
1036}
1037
1038static int dp83867_led_mode(u8 index, unsigned long rules)
1039{
1040 if (index >= DP83867_LED_COUNT)
1041 return -EINVAL;
1042
1043 switch (rules) {
1044 case BIT(TRIGGER_NETDEV_LINK):
1045 return DP83867_LED_FN_LINK;
1046 case BIT(TRIGGER_NETDEV_LINK_10):
1047 return DP83867_LED_FN_LINK_10_BT;
1048 case BIT(TRIGGER_NETDEV_LINK_100):
1049 return DP83867_LED_FN_LINK_100_BTX;
1050 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
1051 return DP83867_LED_FN_FULL_DUPLEX;
1052 case BIT(TRIGGER_NETDEV_TX):
1053 return DP83867_LED_FN_TX;
1054 case BIT(TRIGGER_NETDEV_RX):
1055 return DP83867_LED_FN_RX;
1056 case BIT(TRIGGER_NETDEV_LINK_1000):
1057 return DP83867_LED_FN_LINK_1000_BT;
1058 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1059 return DP83867_LED_FN_RX_TX;
1060 case BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000):
1061 return DP83867_LED_FN_LINK_100_1000_BT;
1062 case BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100):
1063 return DP83867_LED_FN_LINK_10_100_BT;
1064 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1065 return DP83867_LED_FN_LINK_RX_TX;
1066 default:
1067 return -EOPNOTSUPP;
1068 }
1069}
1070
1071static int dp83867_led_hw_is_supported(struct phy_device *phydev, u8 index,
1072 unsigned long rules)
1073{
1074 int ret;
1075
1076 ret = dp83867_led_mode(index, rules);
1077 if (ret < 0)
1078 return ret;
1079
1080 return 0;
1081}
1082
1083static int dp83867_led_hw_control_set(struct phy_device *phydev, u8 index,
1084 unsigned long rules)
1085{
1086 int mode, ret;
1087
1088 mode = dp83867_led_mode(index, rules);
1089 if (mode < 0)
1090 return mode;
1091
1092 ret = phy_modify(phydev, DP83867_LEDCR1, DP83867_LED_FN_MASK(index),
1093 DP83867_LED_FN(index, mode));
1094 if (ret)
1095 return ret;
1096
1097 return phy_modify(phydev, DP83867_LEDCR2, DP83867_LED_DRV_EN(index), 0);
1098}
1099
1100static int dp83867_led_hw_control_get(struct phy_device *phydev, u8 index,
1101 unsigned long *rules)
1102{
1103 int val;
1104
1105 val = phy_read(phydev, DP83867_LEDCR1);
1106 if (val < 0)
1107 return val;
1108
1109 val &= DP83867_LED_FN_MASK(index);
1110 val >>= index * 4;
1111
1112 switch (val) {
1113 case DP83867_LED_FN_LINK:
1114 *rules = BIT(TRIGGER_NETDEV_LINK);
1115 break;
1116 case DP83867_LED_FN_LINK_10_BT:
1117 *rules = BIT(TRIGGER_NETDEV_LINK_10);
1118 break;
1119 case DP83867_LED_FN_LINK_100_BTX:
1120 *rules = BIT(TRIGGER_NETDEV_LINK_100);
1121 break;
1122 case DP83867_LED_FN_FULL_DUPLEX:
1123 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1124 break;
1125 case DP83867_LED_FN_TX:
1126 *rules = BIT(TRIGGER_NETDEV_TX);
1127 break;
1128 case DP83867_LED_FN_RX:
1129 *rules = BIT(TRIGGER_NETDEV_RX);
1130 break;
1131 case DP83867_LED_FN_LINK_1000_BT:
1132 *rules = BIT(TRIGGER_NETDEV_LINK_1000);
1133 break;
1134 case DP83867_LED_FN_RX_TX:
1135 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
1136 break;
1137 case DP83867_LED_FN_LINK_100_1000_BT:
1138 *rules = BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000);
1139 break;
1140 case DP83867_LED_FN_LINK_10_100_BT:
1141 *rules = BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100);
1142 break;
1143 case DP83867_LED_FN_LINK_RX_TX:
1144 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
1145 BIT(TRIGGER_NETDEV_RX);
1146 break;
1147 default:
1148 *rules = 0;
1149 break;
1150 }
1151
1152 return 0;
1153}
1154
1155static struct phy_driver dp83867_driver[] = {
1156 {
1157 .phy_id = DP83867_PHY_ID,
1158 .phy_id_mask = 0xfffffff0,
1159 .name = "TI DP83867",
1160 /* PHY_GBIT_FEATURES */
1161
1162 .probe = dp83867_probe,
1163 .config_init = dp83867_config_init,
1164 .soft_reset = dp83867_phy_reset,
1165
1166 .read_status = dp83867_read_status,
1167 .get_tunable = dp83867_get_tunable,
1168 .set_tunable = dp83867_set_tunable,
1169
1170 .get_wol = dp83867_get_wol,
1171 .set_wol = dp83867_set_wol,
1172
1173 /* IRQ related */
1174 .config_intr = dp83867_config_intr,
1175 .handle_interrupt = dp83867_handle_interrupt,
1176
1177 .suspend = dp83867_suspend,
1178 .resume = dp83867_resume,
1179
1180 .link_change_notify = dp83867_link_change_notify,
1181 .set_loopback = dp83867_loopback,
1182
1183 .led_brightness_set = dp83867_led_brightness_set,
1184 .led_hw_is_supported = dp83867_led_hw_is_supported,
1185 .led_hw_control_set = dp83867_led_hw_control_set,
1186 .led_hw_control_get = dp83867_led_hw_control_get,
1187 },
1188};
1189module_phy_driver(dp83867_driver);
1190
1191static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
1192 { DP83867_PHY_ID, 0xfffffff0 },
1193 { }
1194};
1195
1196MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
1197
1198MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
1199MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
1200MODULE_LICENSE("GPL v2");