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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */
9
10#include <linux/phy.h>
11#include <linux/module.h>
12#include <linux/string.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/ethtool_netlink.h>
16#include <linux/bitfield.h>
17#include <linux/regulator/of_regulator.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/consumer.h>
20#include <linux/of.h>
21#include <linux/phylink.h>
22#include <linux/sfp.h>
23#include <dt-bindings/net/qca-ar803x.h>
24
25#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
26#define AT803X_SFC_ASSERT_CRS BIT(11)
27#define AT803X_SFC_FORCE_LINK BIT(10)
28#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
29#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
30#define AT803X_SFC_MANUAL_MDIX 0x1
31#define AT803X_SFC_MANUAL_MDI 0x0
32#define AT803X_SFC_SQE_TEST BIT(2)
33#define AT803X_SFC_POLARITY_REVERSAL BIT(1)
34#define AT803X_SFC_DISABLE_JABBER BIT(0)
35
36#define AT803X_SPECIFIC_STATUS 0x11
37#define AT803X_SS_SPEED_MASK GENMASK(15, 14)
38#define AT803X_SS_SPEED_1000 2
39#define AT803X_SS_SPEED_100 1
40#define AT803X_SS_SPEED_10 0
41#define AT803X_SS_DUPLEX BIT(13)
42#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
43#define AT803X_SS_MDIX BIT(6)
44
45#define QCA808X_SS_SPEED_MASK GENMASK(9, 7)
46#define QCA808X_SS_SPEED_2500 4
47
48#define AT803X_INTR_ENABLE 0x12
49#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
50#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
51#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
52#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
53#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
54#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
55#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8)
56#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7)
57#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
58#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
59#define AT803X_INTR_ENABLE_WOL BIT(0)
60
61#define AT803X_INTR_STATUS 0x13
62
63#define AT803X_SMART_SPEED 0x14
64#define AT803X_SMART_SPEED_ENABLE BIT(5)
65#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
66#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
67#define AT803X_CDT 0x16
68#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
69#define AT803X_CDT_ENABLE_TEST BIT(0)
70#define AT803X_CDT_STATUS 0x1c
71#define AT803X_CDT_STATUS_STAT_NORMAL 0
72#define AT803X_CDT_STATUS_STAT_SHORT 1
73#define AT803X_CDT_STATUS_STAT_OPEN 2
74#define AT803X_CDT_STATUS_STAT_FAIL 3
75#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
76#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
77#define AT803X_LED_CONTROL 0x18
78
79#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
80#define AT803X_WOL_EN BIT(5)
81#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
82#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
83#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
84#define AT803X_REG_CHIP_CONFIG 0x1f
85#define AT803X_BT_BX_REG_SEL 0x8000
86
87#define AT803X_DEBUG_ADDR 0x1D
88#define AT803X_DEBUG_DATA 0x1E
89
90#define AT803X_MODE_CFG_MASK 0x0F
91#define AT803X_MODE_CFG_BASET_RGMII 0x00
92#define AT803X_MODE_CFG_BASET_SGMII 0x01
93#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
94#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
95#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
96#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
97#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
98#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
99#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
100#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
101#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
102
103#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
104#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
105
106#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
107#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
108#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
109#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
110
111#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
112#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
113
114#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
115#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
116#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
117#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
118
119#define AT803X_DEBUG_REG_3C 0x3C
120
121#define AT803X_DEBUG_REG_GREEN 0x3D
122#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
123
124#define AT803X_DEBUG_REG_1F 0x1F
125#define AT803X_DEBUG_PLL_ON BIT(2)
126#define AT803X_DEBUG_RGMII_1V8 BIT(3)
127
128#define MDIO_AZ_DEBUG 0x800D
129
130/* AT803x supports either the XTAL input pad, an internal PLL or the
131 * DSP as clock reference for the clock output pad. The XTAL reference
132 * is only used for 25 MHz output, all other frequencies need the PLL.
133 * The DSP as a clock reference is used in synchronous ethernet
134 * applications.
135 *
136 * By default the PLL is only enabled if there is a link. Otherwise
137 * the PHY will go into low power state and disabled the PLL. You can
138 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
139 * enabled.
140 */
141#define AT803X_MMD7_CLK25M 0x8016
142#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
143#define AT803X_CLK_OUT_25MHZ_XTAL 0
144#define AT803X_CLK_OUT_25MHZ_DSP 1
145#define AT803X_CLK_OUT_50MHZ_PLL 2
146#define AT803X_CLK_OUT_50MHZ_DSP 3
147#define AT803X_CLK_OUT_62_5MHZ_PLL 4
148#define AT803X_CLK_OUT_62_5MHZ_DSP 5
149#define AT803X_CLK_OUT_125MHZ_PLL 6
150#define AT803X_CLK_OUT_125MHZ_DSP 7
151
152/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
153 * but doesn't support choosing between XTAL/PLL and DSP.
154 */
155#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
156
157#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
158#define AT803X_CLK_OUT_STRENGTH_FULL 0
159#define AT803X_CLK_OUT_STRENGTH_HALF 1
160#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
161
162#define AT803X_DEFAULT_DOWNSHIFT 5
163#define AT803X_MIN_DOWNSHIFT 2
164#define AT803X_MAX_DOWNSHIFT 9
165
166#define AT803X_MMD3_SMARTEEE_CTL1 0x805b
167#define AT803X_MMD3_SMARTEEE_CTL2 0x805c
168#define AT803X_MMD3_SMARTEEE_CTL3 0x805d
169#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
170
171#define ATH9331_PHY_ID 0x004dd041
172#define ATH8030_PHY_ID 0x004dd076
173#define ATH8031_PHY_ID 0x004dd074
174#define ATH8032_PHY_ID 0x004dd023
175#define ATH8035_PHY_ID 0x004dd072
176#define AT8030_PHY_ID_MASK 0xffffffef
177
178#define QCA8081_PHY_ID 0x004dd101
179
180#define QCA8327_A_PHY_ID 0x004dd033
181#define QCA8327_B_PHY_ID 0x004dd034
182#define QCA8337_PHY_ID 0x004dd036
183#define QCA9561_PHY_ID 0x004dd042
184#define QCA8K_PHY_ID_MASK 0xffffffff
185
186#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
187
188#define AT803X_PAGE_FIBER 0
189#define AT803X_PAGE_COPPER 1
190
191/* don't turn off internal PLL */
192#define AT803X_KEEP_PLL_ENABLED BIT(0)
193#define AT803X_DISABLE_SMARTEEE BIT(1)
194
195/* disable hibernation mode */
196#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
197
198/* ADC threshold */
199#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
200#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
201#define QCA808X_ADC_THRESHOLD_80MV 0
202#define QCA808X_ADC_THRESHOLD_100MV 0xf0
203#define QCA808X_ADC_THRESHOLD_200MV 0x0f
204#define QCA808X_ADC_THRESHOLD_300MV 0xff
205
206/* CLD control */
207#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
208#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)
209#define QCA808X_8023AZ_AFE_EN 0x90
210
211/* AZ control */
212#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
213#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32
214
215#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
216#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529
217
218#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
219#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341
220
221#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
222#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419
223
224#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
225#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341
226
227#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
228#define QCA808X_TOP_OPTION1_DATA 0x0
229
230#define QCA808X_PHY_MMD3_DEBUG_1 0xa100
231#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203
232#define QCA808X_PHY_MMD3_DEBUG_2 0xa101
233#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad
234#define QCA808X_PHY_MMD3_DEBUG_3 0xa103
235#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698
236#define QCA808X_PHY_MMD3_DEBUG_4 0xa105
237#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001
238#define QCA808X_PHY_MMD3_DEBUG_5 0xa106
239#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111
240#define QCA808X_PHY_MMD3_DEBUG_6 0xa011
241#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85
242
243/* master/slave seed config */
244#define QCA808X_PHY_DEBUG_LOCAL_SEED 9
245#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1)
246#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)
247#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
248
249/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
250 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
251 */
252#define QCA808X_DBG_AN_TEST 0xb
253#define QCA808X_HIBERNATION_EN BIT(15)
254
255#define QCA808X_CDT_ENABLE_TEST BIT(15)
256#define QCA808X_CDT_INTER_CHECK_DIS BIT(13)
257#define QCA808X_CDT_STATUS BIT(11)
258#define QCA808X_CDT_LENGTH_UNIT BIT(10)
259
260#define QCA808X_MMD3_CDT_STATUS 0x8064
261#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065
262#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066
263#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067
264#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068
265#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8)
266#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0)
267
268#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12)
269#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8)
270#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4)
271#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0)
272
273#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0)
274#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
275#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
276#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
277#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
278
279#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2)
280#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
281#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
282#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
283
284/* NORMAL are MDI with type set to 0 */
285#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1
286#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
287 QCA808X_CDT_STATUS_STAT_MDI1)
288#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
289 QCA808X_CDT_STATUS_STAT_MDI1)
290#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2
291#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
292 QCA808X_CDT_STATUS_STAT_MDI2)
293#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
294 QCA808X_CDT_STATUS_STAT_MDI2)
295#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3
296#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
297 QCA808X_CDT_STATUS_STAT_MDI3)
298#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
299 QCA808X_CDT_STATUS_STAT_MDI3)
300
301/* Added for reference of existence but should be handled by wait_for_completion already */
302#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3))
303
304/* QCA808X 1G chip type */
305#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
306#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
307
308#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
309#define QCA8081_PHY_FIFO_RSTN BIT(11)
310
311MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
312MODULE_AUTHOR("Matus Ujhelyi");
313MODULE_LICENSE("GPL");
314
315enum stat_access_type {
316 PHY,
317 MMD
318};
319
320struct at803x_hw_stat {
321 const char *string;
322 u8 reg;
323 u32 mask;
324 enum stat_access_type access_type;
325};
326
327static struct at803x_hw_stat qca83xx_hw_stats[] = {
328 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
329 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
330 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
331};
332
333struct at803x_ss_mask {
334 u16 speed_mask;
335 u8 speed_shift;
336};
337
338struct at803x_priv {
339 int flags;
340 u16 clk_25m_reg;
341 u16 clk_25m_mask;
342 u8 smarteee_lpi_tw_1g;
343 u8 smarteee_lpi_tw_100m;
344 bool is_fiber;
345 bool is_1000basex;
346 struct regulator_dev *vddio_rdev;
347 struct regulator_dev *vddh_rdev;
348 u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
349};
350
351struct at803x_context {
352 u16 bmcr;
353 u16 advertise;
354 u16 control1000;
355 u16 int_enable;
356 u16 smart_speed;
357 u16 led_control;
358};
359
360static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
361{
362 int ret;
363
364 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
365 if (ret < 0)
366 return ret;
367
368 return phy_write(phydev, AT803X_DEBUG_DATA, data);
369}
370
371static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
372{
373 int ret;
374
375 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
376 if (ret < 0)
377 return ret;
378
379 return phy_read(phydev, AT803X_DEBUG_DATA);
380}
381
382static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
383 u16 clear, u16 set)
384{
385 u16 val;
386 int ret;
387
388 ret = at803x_debug_reg_read(phydev, reg);
389 if (ret < 0)
390 return ret;
391
392 val = ret & 0xffff;
393 val &= ~clear;
394 val |= set;
395
396 return phy_write(phydev, AT803X_DEBUG_DATA, val);
397}
398
399static int at803x_write_page(struct phy_device *phydev, int page)
400{
401 int mask;
402 int set;
403
404 if (page == AT803X_PAGE_COPPER) {
405 set = AT803X_BT_BX_REG_SEL;
406 mask = 0;
407 } else {
408 set = 0;
409 mask = AT803X_BT_BX_REG_SEL;
410 }
411
412 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
413}
414
415static int at803x_read_page(struct phy_device *phydev)
416{
417 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
418
419 if (ccr < 0)
420 return ccr;
421
422 if (ccr & AT803X_BT_BX_REG_SEL)
423 return AT803X_PAGE_COPPER;
424
425 return AT803X_PAGE_FIBER;
426}
427
428static int at803x_enable_rx_delay(struct phy_device *phydev)
429{
430 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
431 AT803X_DEBUG_RX_CLK_DLY_EN);
432}
433
434static int at803x_enable_tx_delay(struct phy_device *phydev)
435{
436 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
437 AT803X_DEBUG_TX_CLK_DLY_EN);
438}
439
440static int at803x_disable_rx_delay(struct phy_device *phydev)
441{
442 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
443 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
444}
445
446static int at803x_disable_tx_delay(struct phy_device *phydev)
447{
448 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
449 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
450}
451
452/* save relevant PHY registers to private copy */
453static void at803x_context_save(struct phy_device *phydev,
454 struct at803x_context *context)
455{
456 context->bmcr = phy_read(phydev, MII_BMCR);
457 context->advertise = phy_read(phydev, MII_ADVERTISE);
458 context->control1000 = phy_read(phydev, MII_CTRL1000);
459 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
460 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
461 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
462}
463
464/* restore relevant PHY registers from private copy */
465static void at803x_context_restore(struct phy_device *phydev,
466 const struct at803x_context *context)
467{
468 phy_write(phydev, MII_BMCR, context->bmcr);
469 phy_write(phydev, MII_ADVERTISE, context->advertise);
470 phy_write(phydev, MII_CTRL1000, context->control1000);
471 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
472 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
473 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
474}
475
476static int at803x_set_wol(struct phy_device *phydev,
477 struct ethtool_wolinfo *wol)
478{
479 int ret, irq_enabled;
480
481 if (wol->wolopts & WAKE_MAGIC) {
482 struct net_device *ndev = phydev->attached_dev;
483 const u8 *mac;
484 unsigned int i;
485 static const unsigned int offsets[] = {
486 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
487 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
488 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
489 };
490
491 if (!ndev)
492 return -ENODEV;
493
494 mac = (const u8 *)ndev->dev_addr;
495
496 if (!is_valid_ether_addr(mac))
497 return -EINVAL;
498
499 for (i = 0; i < 3; i++)
500 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
501 mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
502
503 /* Enable WOL interrupt */
504 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
505 if (ret)
506 return ret;
507 } else {
508 /* Disable WOL interrupt */
509 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
510 if (ret)
511 return ret;
512 }
513
514 /* Clear WOL status */
515 ret = phy_read(phydev, AT803X_INTR_STATUS);
516 if (ret < 0)
517 return ret;
518
519 /* Check if there are other interrupts except for WOL triggered when PHY is
520 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
521 * be passed up to the interrupt PIN.
522 */
523 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
524 if (irq_enabled < 0)
525 return irq_enabled;
526
527 irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
528 if (ret & irq_enabled && !phy_polling_mode(phydev))
529 phy_trigger_machine(phydev);
530
531 return 0;
532}
533
534static void at803x_get_wol(struct phy_device *phydev,
535 struct ethtool_wolinfo *wol)
536{
537 int value;
538
539 wol->supported = WAKE_MAGIC;
540 wol->wolopts = 0;
541
542 value = phy_read(phydev, AT803X_INTR_ENABLE);
543 if (value < 0)
544 return;
545
546 if (value & AT803X_INTR_ENABLE_WOL)
547 wol->wolopts |= WAKE_MAGIC;
548}
549
550static int qca83xx_get_sset_count(struct phy_device *phydev)
551{
552 return ARRAY_SIZE(qca83xx_hw_stats);
553}
554
555static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
556{
557 int i;
558
559 for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
560 strscpy(data + i * ETH_GSTRING_LEN,
561 qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
562 }
563}
564
565static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
566{
567 struct at803x_hw_stat stat = qca83xx_hw_stats[i];
568 struct at803x_priv *priv = phydev->priv;
569 int val;
570 u64 ret;
571
572 if (stat.access_type == MMD)
573 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
574 else
575 val = phy_read(phydev, stat.reg);
576
577 if (val < 0) {
578 ret = U64_MAX;
579 } else {
580 val = val & stat.mask;
581 priv->stats[i] += val;
582 ret = priv->stats[i];
583 }
584
585 return ret;
586}
587
588static void qca83xx_get_stats(struct phy_device *phydev,
589 struct ethtool_stats *stats, u64 *data)
590{
591 int i;
592
593 for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
594 data[i] = qca83xx_get_stat(phydev, i);
595}
596
597static int at803x_suspend(struct phy_device *phydev)
598{
599 int value;
600 int wol_enabled;
601
602 value = phy_read(phydev, AT803X_INTR_ENABLE);
603 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
604
605 if (wol_enabled)
606 value = BMCR_ISOLATE;
607 else
608 value = BMCR_PDOWN;
609
610 phy_modify(phydev, MII_BMCR, 0, value);
611
612 return 0;
613}
614
615static int at803x_resume(struct phy_device *phydev)
616{
617 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
618}
619
620static int at803x_parse_dt(struct phy_device *phydev)
621{
622 struct device_node *node = phydev->mdio.dev.of_node;
623 struct at803x_priv *priv = phydev->priv;
624 u32 freq, strength, tw;
625 unsigned int sel;
626 int ret;
627
628 if (!IS_ENABLED(CONFIG_OF_MDIO))
629 return 0;
630
631 if (of_property_read_bool(node, "qca,disable-smarteee"))
632 priv->flags |= AT803X_DISABLE_SMARTEEE;
633
634 if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
635 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
636
637 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
638 if (!tw || tw > 255) {
639 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
640 return -EINVAL;
641 }
642 priv->smarteee_lpi_tw_1g = tw;
643 }
644
645 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
646 if (!tw || tw > 255) {
647 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
648 return -EINVAL;
649 }
650 priv->smarteee_lpi_tw_100m = tw;
651 }
652
653 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
654 if (!ret) {
655 switch (freq) {
656 case 25000000:
657 sel = AT803X_CLK_OUT_25MHZ_XTAL;
658 break;
659 case 50000000:
660 sel = AT803X_CLK_OUT_50MHZ_PLL;
661 break;
662 case 62500000:
663 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
664 break;
665 case 125000000:
666 sel = AT803X_CLK_OUT_125MHZ_PLL;
667 break;
668 default:
669 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
670 return -EINVAL;
671 }
672
673 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
674 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
675 }
676
677 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
678 if (!ret) {
679 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
680 switch (strength) {
681 case AR803X_STRENGTH_FULL:
682 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
683 break;
684 case AR803X_STRENGTH_HALF:
685 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
686 break;
687 case AR803X_STRENGTH_QUARTER:
688 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
689 break;
690 default:
691 phydev_err(phydev, "invalid qca,clk-out-strength\n");
692 return -EINVAL;
693 }
694 }
695
696 return 0;
697}
698
699static int at803x_probe(struct phy_device *phydev)
700{
701 struct device *dev = &phydev->mdio.dev;
702 struct at803x_priv *priv;
703 int ret;
704
705 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
706 if (!priv)
707 return -ENOMEM;
708
709 phydev->priv = priv;
710
711 ret = at803x_parse_dt(phydev);
712 if (ret)
713 return ret;
714
715 return 0;
716}
717
718static int at803x_get_features(struct phy_device *phydev)
719{
720 struct at803x_priv *priv = phydev->priv;
721 int err;
722
723 err = genphy_read_abilities(phydev);
724 if (err)
725 return err;
726
727 if (phydev->drv->phy_id != ATH8031_PHY_ID)
728 return 0;
729
730 /* AR8031/AR8033 have different status registers
731 * for copper and fiber operation. However, the
732 * extended status register is the same for both
733 * operation modes.
734 *
735 * As a result of that, ESTATUS_1000_XFULL is set
736 * to 1 even when operating in copper TP mode.
737 *
738 * Remove this mode from the supported link modes
739 * when not operating in 1000BaseX mode.
740 */
741 if (!priv->is_1000basex)
742 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
743 phydev->supported);
744
745 return 0;
746}
747
748static int at803x_smarteee_config(struct phy_device *phydev)
749{
750 struct at803x_priv *priv = phydev->priv;
751 u16 mask = 0, val = 0;
752 int ret;
753
754 if (priv->flags & AT803X_DISABLE_SMARTEEE)
755 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
756 AT803X_MMD3_SMARTEEE_CTL3,
757 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
758
759 if (priv->smarteee_lpi_tw_1g) {
760 mask |= 0xff00;
761 val |= priv->smarteee_lpi_tw_1g << 8;
762 }
763 if (priv->smarteee_lpi_tw_100m) {
764 mask |= 0x00ff;
765 val |= priv->smarteee_lpi_tw_100m;
766 }
767 if (!mask)
768 return 0;
769
770 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
771 mask, val);
772 if (ret)
773 return ret;
774
775 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
776 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
777 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
778}
779
780static int at803x_clk_out_config(struct phy_device *phydev)
781{
782 struct at803x_priv *priv = phydev->priv;
783
784 if (!priv->clk_25m_mask)
785 return 0;
786
787 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
788 priv->clk_25m_mask, priv->clk_25m_reg);
789}
790
791static int at8031_pll_config(struct phy_device *phydev)
792{
793 struct at803x_priv *priv = phydev->priv;
794
795 /* The default after hardware reset is PLL OFF. After a soft reset, the
796 * values are retained.
797 */
798 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
799 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
800 0, AT803X_DEBUG_PLL_ON);
801 else
802 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
803 AT803X_DEBUG_PLL_ON, 0);
804}
805
806static int at803x_hibernation_mode_config(struct phy_device *phydev)
807{
808 struct at803x_priv *priv = phydev->priv;
809
810 /* The default after hardware reset is hibernation mode enabled. After
811 * software reset, the value is retained.
812 */
813 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
814 return 0;
815
816 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
817 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
818}
819
820static int at803x_config_init(struct phy_device *phydev)
821{
822 int ret;
823
824 /* The RX and TX delay default is:
825 * after HW reset: RX delay enabled and TX delay disabled
826 * after SW reset: RX delay enabled, while TX delay retains the
827 * value before reset.
828 */
829 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
830 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
831 ret = at803x_enable_rx_delay(phydev);
832 else
833 ret = at803x_disable_rx_delay(phydev);
834 if (ret < 0)
835 return ret;
836
837 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
838 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
839 ret = at803x_enable_tx_delay(phydev);
840 else
841 ret = at803x_disable_tx_delay(phydev);
842 if (ret < 0)
843 return ret;
844
845 ret = at803x_smarteee_config(phydev);
846 if (ret < 0)
847 return ret;
848
849 ret = at803x_clk_out_config(phydev);
850 if (ret < 0)
851 return ret;
852
853 ret = at803x_hibernation_mode_config(phydev);
854 if (ret < 0)
855 return ret;
856
857 /* Ar803x extended next page bit is enabled by default. Cisco
858 * multigig switches read this bit and attempt to negotiate 10Gbps
859 * rates even if the next page bit is disabled. This is incorrect
860 * behaviour but we still need to accommodate it. XNP is only needed
861 * for 10Gbps support, so disable XNP.
862 */
863 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
864}
865
866static int at803x_ack_interrupt(struct phy_device *phydev)
867{
868 int err;
869
870 err = phy_read(phydev, AT803X_INTR_STATUS);
871
872 return (err < 0) ? err : 0;
873}
874
875static int at803x_config_intr(struct phy_device *phydev)
876{
877 int err;
878 int value;
879
880 value = phy_read(phydev, AT803X_INTR_ENABLE);
881
882 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
883 /* Clear any pending interrupts */
884 err = at803x_ack_interrupt(phydev);
885 if (err)
886 return err;
887
888 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
889 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
890 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
891 value |= AT803X_INTR_ENABLE_LINK_FAIL;
892 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
893
894 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
895 } else {
896 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
897 if (err)
898 return err;
899
900 /* Clear any pending interrupts */
901 err = at803x_ack_interrupt(phydev);
902 }
903
904 return err;
905}
906
907static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
908{
909 int irq_status, int_enabled;
910
911 irq_status = phy_read(phydev, AT803X_INTR_STATUS);
912 if (irq_status < 0) {
913 phy_error(phydev);
914 return IRQ_NONE;
915 }
916
917 /* Read the current enabled interrupts */
918 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
919 if (int_enabled < 0) {
920 phy_error(phydev);
921 return IRQ_NONE;
922 }
923
924 /* See if this was one of our enabled interrupts */
925 if (!(irq_status & int_enabled))
926 return IRQ_NONE;
927
928 phy_trigger_machine(phydev);
929
930 return IRQ_HANDLED;
931}
932
933static void at803x_link_change_notify(struct phy_device *phydev)
934{
935 /*
936 * Conduct a hardware reset for AT8030 every time a link loss is
937 * signalled. This is necessary to circumvent a hardware bug that
938 * occurs when the cable is unplugged while TX packets are pending
939 * in the FIFO. In such cases, the FIFO enters an error mode it
940 * cannot recover from by software.
941 */
942 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
943 struct at803x_context context;
944
945 at803x_context_save(phydev, &context);
946
947 phy_device_reset(phydev, 1);
948 usleep_range(1000, 2000);
949 phy_device_reset(phydev, 0);
950 usleep_range(1000, 2000);
951
952 at803x_context_restore(phydev, &context);
953
954 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
955 }
956}
957
958static int at803x_read_specific_status(struct phy_device *phydev,
959 struct at803x_ss_mask ss_mask)
960{
961 int ss;
962
963 /* Read the AT8035 PHY-Specific Status register, which indicates the
964 * speed and duplex that the PHY is actually using, irrespective of
965 * whether we are in autoneg mode or not.
966 */
967 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
968 if (ss < 0)
969 return ss;
970
971 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
972 int sfc, speed;
973
974 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
975 if (sfc < 0)
976 return sfc;
977
978 speed = ss & ss_mask.speed_mask;
979 speed >>= ss_mask.speed_shift;
980
981 switch (speed) {
982 case AT803X_SS_SPEED_10:
983 phydev->speed = SPEED_10;
984 break;
985 case AT803X_SS_SPEED_100:
986 phydev->speed = SPEED_100;
987 break;
988 case AT803X_SS_SPEED_1000:
989 phydev->speed = SPEED_1000;
990 break;
991 case QCA808X_SS_SPEED_2500:
992 phydev->speed = SPEED_2500;
993 break;
994 }
995 if (ss & AT803X_SS_DUPLEX)
996 phydev->duplex = DUPLEX_FULL;
997 else
998 phydev->duplex = DUPLEX_HALF;
999
1000 if (ss & AT803X_SS_MDIX)
1001 phydev->mdix = ETH_TP_MDI_X;
1002 else
1003 phydev->mdix = ETH_TP_MDI;
1004
1005 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
1006 case AT803X_SFC_MANUAL_MDI:
1007 phydev->mdix_ctrl = ETH_TP_MDI;
1008 break;
1009 case AT803X_SFC_MANUAL_MDIX:
1010 phydev->mdix_ctrl = ETH_TP_MDI_X;
1011 break;
1012 case AT803X_SFC_AUTOMATIC_CROSSOVER:
1013 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1014 break;
1015 }
1016 }
1017
1018 return 0;
1019}
1020
1021static int at803x_read_status(struct phy_device *phydev)
1022{
1023 struct at803x_ss_mask ss_mask = { 0 };
1024 int err, old_link = phydev->link;
1025
1026 /* Update the link, but return if there was an error */
1027 err = genphy_update_link(phydev);
1028 if (err)
1029 return err;
1030
1031 /* why bother the PHY if nothing can have changed */
1032 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
1033 return 0;
1034
1035 phydev->speed = SPEED_UNKNOWN;
1036 phydev->duplex = DUPLEX_UNKNOWN;
1037 phydev->pause = 0;
1038 phydev->asym_pause = 0;
1039
1040 err = genphy_read_lpa(phydev);
1041 if (err < 0)
1042 return err;
1043
1044 ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
1045 ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
1046 err = at803x_read_specific_status(phydev, ss_mask);
1047 if (err < 0)
1048 return err;
1049
1050 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1051 phy_resolve_aneg_pause(phydev);
1052
1053 return 0;
1054}
1055
1056static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1057{
1058 u16 val;
1059
1060 switch (ctrl) {
1061 case ETH_TP_MDI:
1062 val = AT803X_SFC_MANUAL_MDI;
1063 break;
1064 case ETH_TP_MDI_X:
1065 val = AT803X_SFC_MANUAL_MDIX;
1066 break;
1067 case ETH_TP_MDI_AUTO:
1068 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1069 break;
1070 default:
1071 return 0;
1072 }
1073
1074 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1075 AT803X_SFC_MDI_CROSSOVER_MODE_M,
1076 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1077}
1078
1079static int at803x_prepare_config_aneg(struct phy_device *phydev)
1080{
1081 int ret;
1082
1083 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1084 if (ret < 0)
1085 return ret;
1086
1087 /* Changes of the midx bits are disruptive to the normal operation;
1088 * therefore any changes to these registers must be followed by a
1089 * software reset to take effect.
1090 */
1091 if (ret == 1) {
1092 ret = genphy_soft_reset(phydev);
1093 if (ret < 0)
1094 return ret;
1095 }
1096
1097 return 0;
1098}
1099
1100static int at803x_config_aneg(struct phy_device *phydev)
1101{
1102 struct at803x_priv *priv = phydev->priv;
1103 int ret;
1104
1105 ret = at803x_prepare_config_aneg(phydev);
1106 if (ret)
1107 return ret;
1108
1109 if (priv->is_1000basex)
1110 return genphy_c37_config_aneg(phydev);
1111
1112 return genphy_config_aneg(phydev);
1113}
1114
1115static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1116{
1117 int val;
1118
1119 val = phy_read(phydev, AT803X_SMART_SPEED);
1120 if (val < 0)
1121 return val;
1122
1123 if (val & AT803X_SMART_SPEED_ENABLE)
1124 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1125 else
1126 *d = DOWNSHIFT_DEV_DISABLE;
1127
1128 return 0;
1129}
1130
1131static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1132{
1133 u16 mask, set;
1134 int ret;
1135
1136 switch (cnt) {
1137 case DOWNSHIFT_DEV_DEFAULT_COUNT:
1138 cnt = AT803X_DEFAULT_DOWNSHIFT;
1139 fallthrough;
1140 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1141 set = AT803X_SMART_SPEED_ENABLE |
1142 AT803X_SMART_SPEED_BYPASS_TIMER |
1143 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1144 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1145 break;
1146 case DOWNSHIFT_DEV_DISABLE:
1147 set = 0;
1148 mask = AT803X_SMART_SPEED_ENABLE |
1149 AT803X_SMART_SPEED_BYPASS_TIMER;
1150 break;
1151 default:
1152 return -EINVAL;
1153 }
1154
1155 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1156
1157 /* After changing the smart speed settings, we need to perform a
1158 * software reset, use phy_init_hw() to make sure we set the
1159 * reapply any values which might got lost during software reset.
1160 */
1161 if (ret == 1)
1162 ret = phy_init_hw(phydev);
1163
1164 return ret;
1165}
1166
1167static int at803x_get_tunable(struct phy_device *phydev,
1168 struct ethtool_tunable *tuna, void *data)
1169{
1170 switch (tuna->id) {
1171 case ETHTOOL_PHY_DOWNSHIFT:
1172 return at803x_get_downshift(phydev, data);
1173 default:
1174 return -EOPNOTSUPP;
1175 }
1176}
1177
1178static int at803x_set_tunable(struct phy_device *phydev,
1179 struct ethtool_tunable *tuna, const void *data)
1180{
1181 switch (tuna->id) {
1182 case ETHTOOL_PHY_DOWNSHIFT:
1183 return at803x_set_downshift(phydev, *(const u8 *)data);
1184 default:
1185 return -EOPNOTSUPP;
1186 }
1187}
1188
1189static int at803x_cable_test_result_trans(u16 status)
1190{
1191 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1192 case AT803X_CDT_STATUS_STAT_NORMAL:
1193 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1194 case AT803X_CDT_STATUS_STAT_SHORT:
1195 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1196 case AT803X_CDT_STATUS_STAT_OPEN:
1197 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1198 case AT803X_CDT_STATUS_STAT_FAIL:
1199 default:
1200 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1201 }
1202}
1203
1204static bool at803x_cdt_test_failed(u16 status)
1205{
1206 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1207 AT803X_CDT_STATUS_STAT_FAIL;
1208}
1209
1210static bool at803x_cdt_fault_length_valid(u16 status)
1211{
1212 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1213 case AT803X_CDT_STATUS_STAT_OPEN:
1214 case AT803X_CDT_STATUS_STAT_SHORT:
1215 return true;
1216 }
1217 return false;
1218}
1219
1220static int at803x_cdt_fault_length(int dt)
1221{
1222 /* According to the datasheet the distance to the fault is
1223 * DELTA_TIME * 0.824 meters.
1224 *
1225 * The author suspect the correct formula is:
1226 *
1227 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1228 *
1229 * where c is the speed of light, VF is the velocity factor of
1230 * the twisted pair cable, 125MHz the counter frequency and
1231 * we need to divide by 2 because the hardware will measure the
1232 * round trip time to the fault and back to the PHY.
1233 *
1234 * With a VF of 0.69 we get the factor 0.824 mentioned in the
1235 * datasheet.
1236 */
1237 return (dt * 824) / 10;
1238}
1239
1240static int at803x_cdt_start(struct phy_device *phydev,
1241 u32 cdt_start)
1242{
1243 return phy_write(phydev, AT803X_CDT, cdt_start);
1244}
1245
1246static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
1247 u32 cdt_en)
1248{
1249 int val, ret;
1250
1251 /* One test run takes about 25ms */
1252 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1253 !(val & cdt_en),
1254 30000, 100000, true);
1255
1256 return ret < 0 ? ret : 0;
1257}
1258
1259static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1260{
1261 static const int ethtool_pair[] = {
1262 ETHTOOL_A_CABLE_PAIR_A,
1263 ETHTOOL_A_CABLE_PAIR_B,
1264 ETHTOOL_A_CABLE_PAIR_C,
1265 ETHTOOL_A_CABLE_PAIR_D,
1266 };
1267 int ret, val;
1268
1269 val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1270 AT803X_CDT_ENABLE_TEST;
1271 ret = at803x_cdt_start(phydev, val);
1272 if (ret)
1273 return ret;
1274
1275 ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
1276 if (ret)
1277 return ret;
1278
1279 val = phy_read(phydev, AT803X_CDT_STATUS);
1280 if (val < 0)
1281 return val;
1282
1283 if (at803x_cdt_test_failed(val))
1284 return 0;
1285
1286 ethnl_cable_test_result(phydev, ethtool_pair[pair],
1287 at803x_cable_test_result_trans(val));
1288
1289 if (at803x_cdt_fault_length_valid(val)) {
1290 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
1291 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1292 at803x_cdt_fault_length(val));
1293 }
1294
1295 return 1;
1296}
1297
1298static int at803x_cable_test_get_status(struct phy_device *phydev,
1299 bool *finished, unsigned long pair_mask)
1300{
1301 int retries = 20;
1302 int pair, ret;
1303
1304 *finished = false;
1305
1306 /* According to the datasheet the CDT can be performed when
1307 * there is no link partner or when the link partner is
1308 * auto-negotiating. Starting the test will restart the AN
1309 * automatically. It seems that doing this repeatedly we will
1310 * get a slot where our link partner won't disturb our
1311 * measurement.
1312 */
1313 while (pair_mask && retries--) {
1314 for_each_set_bit(pair, &pair_mask, 4) {
1315 ret = at803x_cable_test_one_pair(phydev, pair);
1316 if (ret < 0)
1317 return ret;
1318 if (ret)
1319 clear_bit(pair, &pair_mask);
1320 }
1321 if (pair_mask)
1322 msleep(250);
1323 }
1324
1325 *finished = true;
1326
1327 return 0;
1328}
1329
1330static void at803x_cable_test_autoneg(struct phy_device *phydev)
1331{
1332 /* Enable auto-negotiation, but advertise no capabilities, no link
1333 * will be established. A restart of the auto-negotiation is not
1334 * required, because the cable test will automatically break the link.
1335 */
1336 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1337 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1338}
1339
1340static int at803x_cable_test_start(struct phy_device *phydev)
1341{
1342 at803x_cable_test_autoneg(phydev);
1343 /* we do all the (time consuming) work later */
1344 return 0;
1345}
1346
1347static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
1348 unsigned int selector)
1349{
1350 struct phy_device *phydev = rdev_get_drvdata(rdev);
1351
1352 if (selector)
1353 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
1354 0, AT803X_DEBUG_RGMII_1V8);
1355 else
1356 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
1357 AT803X_DEBUG_RGMII_1V8, 0);
1358}
1359
1360static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
1361{
1362 struct phy_device *phydev = rdev_get_drvdata(rdev);
1363 int val;
1364
1365 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
1366 if (val < 0)
1367 return val;
1368
1369 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
1370}
1371
1372static const struct regulator_ops vddio_regulator_ops = {
1373 .list_voltage = regulator_list_voltage_table,
1374 .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
1375 .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
1376};
1377
1378static const unsigned int vddio_voltage_table[] = {
1379 1500000,
1380 1800000,
1381};
1382
1383static const struct regulator_desc vddio_desc = {
1384 .name = "vddio",
1385 .of_match = of_match_ptr("vddio-regulator"),
1386 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
1387 .volt_table = vddio_voltage_table,
1388 .ops = &vddio_regulator_ops,
1389 .type = REGULATOR_VOLTAGE,
1390 .owner = THIS_MODULE,
1391};
1392
1393static const struct regulator_ops vddh_regulator_ops = {
1394};
1395
1396static const struct regulator_desc vddh_desc = {
1397 .name = "vddh",
1398 .of_match = of_match_ptr("vddh-regulator"),
1399 .n_voltages = 1,
1400 .fixed_uV = 2500000,
1401 .ops = &vddh_regulator_ops,
1402 .type = REGULATOR_VOLTAGE,
1403 .owner = THIS_MODULE,
1404};
1405
1406static int at8031_register_regulators(struct phy_device *phydev)
1407{
1408 struct at803x_priv *priv = phydev->priv;
1409 struct device *dev = &phydev->mdio.dev;
1410 struct regulator_config config = { };
1411
1412 config.dev = dev;
1413 config.driver_data = phydev;
1414
1415 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
1416 if (IS_ERR(priv->vddio_rdev)) {
1417 phydev_err(phydev, "failed to register VDDIO regulator\n");
1418 return PTR_ERR(priv->vddio_rdev);
1419 }
1420
1421 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
1422 if (IS_ERR(priv->vddh_rdev)) {
1423 phydev_err(phydev, "failed to register VDDH regulator\n");
1424 return PTR_ERR(priv->vddh_rdev);
1425 }
1426
1427 return 0;
1428}
1429
1430static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
1431{
1432 struct phy_device *phydev = upstream;
1433 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
1434 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
1435 DECLARE_PHY_INTERFACE_MASK(interfaces);
1436 phy_interface_t iface;
1437
1438 linkmode_zero(phy_support);
1439 phylink_set(phy_support, 1000baseX_Full);
1440 phylink_set(phy_support, 1000baseT_Full);
1441 phylink_set(phy_support, Autoneg);
1442 phylink_set(phy_support, Pause);
1443 phylink_set(phy_support, Asym_Pause);
1444
1445 linkmode_zero(sfp_support);
1446 sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
1447 /* Some modules support 10G modes as well as others we support.
1448 * Mask out non-supported modes so the correct interface is picked.
1449 */
1450 linkmode_and(sfp_support, phy_support, sfp_support);
1451
1452 if (linkmode_empty(sfp_support)) {
1453 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
1454 return -EINVAL;
1455 }
1456
1457 iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
1458
1459 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
1460 * interface for use with SFP modules.
1461 * However, some copper modules detected as having a preferred SGMII
1462 * interface do default to and function in 1000Base-X mode, so just
1463 * print a warning and allow such modules, as they may have some chance
1464 * of working.
1465 */
1466 if (iface == PHY_INTERFACE_MODE_SGMII)
1467 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
1468 else if (iface != PHY_INTERFACE_MODE_1000BASEX)
1469 return -EINVAL;
1470
1471 return 0;
1472}
1473
1474static const struct sfp_upstream_ops at8031_sfp_ops = {
1475 .attach = phy_sfp_attach,
1476 .detach = phy_sfp_detach,
1477 .module_insert = at8031_sfp_insert,
1478};
1479
1480static int at8031_parse_dt(struct phy_device *phydev)
1481{
1482 struct device_node *node = phydev->mdio.dev.of_node;
1483 struct at803x_priv *priv = phydev->priv;
1484 int ret;
1485
1486 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
1487 priv->flags |= AT803X_KEEP_PLL_ENABLED;
1488
1489 ret = at8031_register_regulators(phydev);
1490 if (ret < 0)
1491 return ret;
1492
1493 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
1494 "vddio");
1495 if (ret) {
1496 phydev_err(phydev, "failed to get VDDIO regulator\n");
1497 return ret;
1498 }
1499
1500 /* Only AR8031/8033 support 1000Base-X for SFP modules */
1501 return phy_sfp_probe(phydev, &at8031_sfp_ops);
1502}
1503
1504static int at8031_probe(struct phy_device *phydev)
1505{
1506 struct at803x_priv *priv = phydev->priv;
1507 int mode_cfg;
1508 int ccr;
1509 int ret;
1510
1511 ret = at803x_probe(phydev);
1512 if (ret)
1513 return ret;
1514
1515 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
1516 * options.
1517 */
1518 ret = at8031_parse_dt(phydev);
1519 if (ret)
1520 return ret;
1521
1522 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
1523 if (ccr < 0)
1524 return ccr;
1525 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
1526
1527 switch (mode_cfg) {
1528 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
1529 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
1530 priv->is_1000basex = true;
1531 fallthrough;
1532 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
1533 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
1534 priv->is_fiber = true;
1535 break;
1536 }
1537
1538 /* Disable WoL in 1588 register which is enabled
1539 * by default
1540 */
1541 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
1542 AT803X_PHY_MMD3_WOL_CTRL,
1543 AT803X_WOL_EN, 0);
1544}
1545
1546static int at8031_config_init(struct phy_device *phydev)
1547{
1548 struct at803x_priv *priv = phydev->priv;
1549 int ret;
1550
1551 /* Some bootloaders leave the fiber page selected.
1552 * Switch to the appropriate page (fiber or copper), as otherwise we
1553 * read the PHY capabilities from the wrong page.
1554 */
1555 phy_lock_mdio_bus(phydev);
1556 ret = at803x_write_page(phydev,
1557 priv->is_fiber ? AT803X_PAGE_FIBER :
1558 AT803X_PAGE_COPPER);
1559 phy_unlock_mdio_bus(phydev);
1560 if (ret)
1561 return ret;
1562
1563 ret = at8031_pll_config(phydev);
1564 if (ret < 0)
1565 return ret;
1566
1567 return at803x_config_init(phydev);
1568}
1569
1570static int at8031_set_wol(struct phy_device *phydev,
1571 struct ethtool_wolinfo *wol)
1572{
1573 int ret;
1574
1575 /* First setup MAC address and enable WOL interrupt */
1576 ret = at803x_set_wol(phydev, wol);
1577 if (ret)
1578 return ret;
1579
1580 if (wol->wolopts & WAKE_MAGIC)
1581 /* Enable WOL function for 1588 */
1582 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
1583 AT803X_PHY_MMD3_WOL_CTRL,
1584 0, AT803X_WOL_EN);
1585 else
1586 /* Disable WoL function for 1588 */
1587 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
1588 AT803X_PHY_MMD3_WOL_CTRL,
1589 AT803X_WOL_EN, 0);
1590
1591 return ret;
1592}
1593
1594static int at8031_config_intr(struct phy_device *phydev)
1595{
1596 struct at803x_priv *priv = phydev->priv;
1597 int err, value = 0;
1598
1599 if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
1600 priv->is_fiber) {
1601 /* Clear any pending interrupts */
1602 err = at803x_ack_interrupt(phydev);
1603 if (err)
1604 return err;
1605
1606 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
1607 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
1608
1609 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
1610 if (err)
1611 return err;
1612 }
1613
1614 return at803x_config_intr(phydev);
1615}
1616
1617/* AR8031 and AR8033 share the same read status logic */
1618static int at8031_read_status(struct phy_device *phydev)
1619{
1620 struct at803x_priv *priv = phydev->priv;
1621
1622 if (priv->is_1000basex)
1623 return genphy_c37_read_status(phydev);
1624
1625 return at803x_read_status(phydev);
1626}
1627
1628/* AR8031 and AR8035 share the same cable test get status reg */
1629static int at8031_cable_test_get_status(struct phy_device *phydev,
1630 bool *finished)
1631{
1632 return at803x_cable_test_get_status(phydev, finished, 0xf);
1633}
1634
1635/* AR8031 and AR8035 share the same cable test start logic */
1636static int at8031_cable_test_start(struct phy_device *phydev)
1637{
1638 at803x_cable_test_autoneg(phydev);
1639 phy_write(phydev, MII_CTRL1000, 0);
1640 /* we do all the (time consuming) work later */
1641 return 0;
1642}
1643
1644/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
1645static int at8032_cable_test_get_status(struct phy_device *phydev,
1646 bool *finished)
1647{
1648 return at803x_cable_test_get_status(phydev, finished, 0x3);
1649}
1650
1651static int at8035_parse_dt(struct phy_device *phydev)
1652{
1653 struct at803x_priv *priv = phydev->priv;
1654
1655 /* Mask is set by the generic at803x_parse_dt
1656 * if property is set. Assume property is set
1657 * with the mask not zero.
1658 */
1659 if (priv->clk_25m_mask) {
1660 /* Fixup for the AR8030/AR8035. This chip has another mask and
1661 * doesn't support the DSP reference. Eg. the lowest bit of the
1662 * mask. The upper two bits select the same frequencies. Mask
1663 * the lowest bit here.
1664 *
1665 * Warning:
1666 * There was no datasheet for the AR8030 available so this is
1667 * just a guess. But the AR8035 is listed as pin compatible
1668 * to the AR8030 so there might be a good chance it works on
1669 * the AR8030 too.
1670 */
1671 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
1672 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
1673 }
1674
1675 return 0;
1676}
1677
1678/* AR8030 and AR8035 shared the same special mask for clk_25m */
1679static int at8035_probe(struct phy_device *phydev)
1680{
1681 int ret;
1682
1683 ret = at803x_probe(phydev);
1684 if (ret)
1685 return ret;
1686
1687 return at8035_parse_dt(phydev);
1688}
1689
1690static int qca83xx_config_init(struct phy_device *phydev)
1691{
1692 u8 switch_revision;
1693
1694 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1695
1696 switch (switch_revision) {
1697 case 1:
1698 /* For 100M waveform */
1699 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
1700 /* Turn on Gigabit clock */
1701 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
1702 break;
1703
1704 case 2:
1705 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1706 fallthrough;
1707 case 4:
1708 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1709 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
1710 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
1711 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1712 break;
1713 }
1714
1715 /* Following original QCA sourcecode set port to prefer master */
1716 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
1717
1718 return 0;
1719}
1720
1721static int qca8327_config_init(struct phy_device *phydev)
1722{
1723 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
1724 * Disable on init and enable only with 100m speed following
1725 * qca original source code.
1726 */
1727 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1728 QCA8327_DEBUG_MANU_CTRL_EN, 0);
1729
1730 return qca83xx_config_init(phydev);
1731}
1732
1733static void qca83xx_link_change_notify(struct phy_device *phydev)
1734{
1735 /* Set DAC Amplitude adjustment to +6% for 100m on link running */
1736 if (phydev->state == PHY_RUNNING) {
1737 if (phydev->speed == SPEED_100)
1738 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1739 QCA8327_DEBUG_MANU_CTRL_EN,
1740 QCA8327_DEBUG_MANU_CTRL_EN);
1741 } else {
1742 /* Reset DAC Amplitude adjustment */
1743 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1744 QCA8327_DEBUG_MANU_CTRL_EN, 0);
1745 }
1746}
1747
1748static int qca83xx_resume(struct phy_device *phydev)
1749{
1750 int ret, val;
1751
1752 /* Skip reset if not suspended */
1753 if (!phydev->suspended)
1754 return 0;
1755
1756 /* Reinit the port, reset values set by suspend */
1757 qca83xx_config_init(phydev);
1758
1759 /* Reset the port on port resume */
1760 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1761
1762 /* On resume from suspend the switch execute a reset and
1763 * restart auto-negotiation. Wait for reset to complete.
1764 */
1765 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1766 50000, 600000, true);
1767 if (ret)
1768 return ret;
1769
1770 usleep_range(1000, 2000);
1771
1772 return 0;
1773}
1774
1775static int qca83xx_suspend(struct phy_device *phydev)
1776{
1777 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
1778 AT803X_DEBUG_GATE_CLK_IN1000, 0);
1779
1780 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1781 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
1782 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
1783
1784 return 0;
1785}
1786
1787static int qca8337_suspend(struct phy_device *phydev)
1788{
1789 /* Only QCA8337 support actual suspend. */
1790 genphy_suspend(phydev);
1791
1792 return qca83xx_suspend(phydev);
1793}
1794
1795static int qca8327_suspend(struct phy_device *phydev)
1796{
1797 u16 mask = 0;
1798
1799 /* QCA8327 cause port unreliability when phy suspend
1800 * is set.
1801 */
1802 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
1803 phy_modify(phydev, MII_BMCR, mask, 0);
1804
1805 return qca83xx_suspend(phydev);
1806}
1807
1808static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
1809{
1810 int ret;
1811
1812 /* Enable fast retrain */
1813 ret = genphy_c45_fast_retrain(phydev, true);
1814 if (ret)
1815 return ret;
1816
1817 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
1818 QCA808X_TOP_OPTION1_DATA);
1819 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
1820 QCA808X_MSE_THRESHOLD_20DB_VALUE);
1821 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
1822 QCA808X_MSE_THRESHOLD_17DB_VALUE);
1823 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
1824 QCA808X_MSE_THRESHOLD_27DB_VALUE);
1825 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
1826 QCA808X_MSE_THRESHOLD_28DB_VALUE);
1827 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
1828 QCA808X_MMD3_DEBUG_1_VALUE);
1829 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
1830 QCA808X_MMD3_DEBUG_4_VALUE);
1831 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
1832 QCA808X_MMD3_DEBUG_5_VALUE);
1833 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
1834 QCA808X_MMD3_DEBUG_3_VALUE);
1835 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
1836 QCA808X_MMD3_DEBUG_6_VALUE);
1837 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
1838 QCA808X_MMD3_DEBUG_2_VALUE);
1839
1840 return 0;
1841}
1842
1843static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
1844{
1845 u16 seed_value;
1846
1847 if (!enable)
1848 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1849 QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
1850
1851 seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE);
1852 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1853 QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
1854 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
1855 QCA808X_MASTER_SLAVE_SEED_ENABLE);
1856}
1857
1858static bool qca808x_is_prefer_master(struct phy_device *phydev)
1859{
1860 return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
1861 (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
1862}
1863
1864static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
1865{
1866 return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
1867}
1868
1869static int qca808x_config_init(struct phy_device *phydev)
1870{
1871 int ret;
1872
1873 /* Active adc&vga on 802.3az for the link 1000M and 100M */
1874 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
1875 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
1876 if (ret)
1877 return ret;
1878
1879 /* Adjust the threshold on 802.3az for the link 1000M */
1880 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
1881 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
1882 QCA808X_MMD3_AZ_TRAINING_VAL);
1883 if (ret)
1884 return ret;
1885
1886 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
1887 /* Config the fast retrain for the link 2500M */
1888 ret = qca808x_phy_fast_retrain_config(phydev);
1889 if (ret)
1890 return ret;
1891
1892 ret = genphy_read_master_slave(phydev);
1893 if (ret < 0)
1894 return ret;
1895
1896 if (!qca808x_is_prefer_master(phydev)) {
1897 /* Enable seed and configure lower ramdom seed to make phy
1898 * linked as slave mode.
1899 */
1900 ret = qca808x_phy_ms_seed_enable(phydev, true);
1901 if (ret)
1902 return ret;
1903 }
1904 }
1905
1906 /* Configure adc threshold as 100mv for the link 10M */
1907 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
1908 QCA808X_ADC_THRESHOLD_MASK,
1909 QCA808X_ADC_THRESHOLD_100MV);
1910}
1911
1912static int qca808x_read_status(struct phy_device *phydev)
1913{
1914 struct at803x_ss_mask ss_mask = { 0 };
1915 int ret;
1916
1917 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
1918 if (ret < 0)
1919 return ret;
1920
1921 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
1922 ret & MDIO_AN_10GBT_STAT_LP2_5G);
1923
1924 ret = genphy_read_status(phydev);
1925 if (ret)
1926 return ret;
1927
1928 /* qca8081 takes the different bits for speed value from at803x */
1929 ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
1930 ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
1931 ret = at803x_read_specific_status(phydev, ss_mask);
1932 if (ret < 0)
1933 return ret;
1934
1935 if (phydev->link) {
1936 if (phydev->speed == SPEED_2500)
1937 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1938 else
1939 phydev->interface = PHY_INTERFACE_MODE_SGMII;
1940 } else {
1941 /* generate seed as a lower random value to make PHY linked as SLAVE easily,
1942 * except for master/slave configuration fault detected or the master mode
1943 * preferred.
1944 *
1945 * the reason for not putting this code into the function link_change_notify is
1946 * the corner case where the link partner is also the qca8081 PHY and the seed
1947 * value is configured as the same value, the link can't be up and no link change
1948 * occurs.
1949 */
1950 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
1951 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
1952 qca808x_is_prefer_master(phydev)) {
1953 qca808x_phy_ms_seed_enable(phydev, false);
1954 } else {
1955 qca808x_phy_ms_seed_enable(phydev, true);
1956 }
1957 }
1958 }
1959
1960 return 0;
1961}
1962
1963static int qca808x_soft_reset(struct phy_device *phydev)
1964{
1965 int ret;
1966
1967 ret = genphy_soft_reset(phydev);
1968 if (ret < 0)
1969 return ret;
1970
1971 if (qca808x_has_fast_retrain_or_slave_seed(phydev))
1972 ret = qca808x_phy_ms_seed_enable(phydev, true);
1973
1974 return ret;
1975}
1976
1977static bool qca808x_cdt_fault_length_valid(int cdt_code)
1978{
1979 switch (cdt_code) {
1980 case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
1981 case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
1982 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
1983 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
1984 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
1985 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
1986 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
1987 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
1988 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
1989 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
1990 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
1991 return true;
1992 default:
1993 return false;
1994 }
1995}
1996
1997static int qca808x_cable_test_result_trans(int cdt_code)
1998{
1999 switch (cdt_code) {
2000 case QCA808X_CDT_STATUS_STAT_NORMAL:
2001 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2002 case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
2003 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2004 case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
2005 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2006 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
2007 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
2008 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
2009 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
2010 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
2011 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
2012 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
2013 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
2014 case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
2015 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2016 case QCA808X_CDT_STATUS_STAT_FAIL:
2017 default:
2018 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2019 }
2020}
2021
2022static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
2023 int result)
2024{
2025 int val;
2026 u32 cdt_length_reg = 0;
2027
2028 switch (pair) {
2029 case ETHTOOL_A_CABLE_PAIR_A:
2030 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
2031 break;
2032 case ETHTOOL_A_CABLE_PAIR_B:
2033 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
2034 break;
2035 case ETHTOOL_A_CABLE_PAIR_C:
2036 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
2037 break;
2038 case ETHTOOL_A_CABLE_PAIR_D:
2039 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
2040 break;
2041 default:
2042 return -EINVAL;
2043 }
2044
2045 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
2046 if (val < 0)
2047 return val;
2048
2049 if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
2050 val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
2051 else
2052 val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
2053
2054 return at803x_cdt_fault_length(val);
2055}
2056
2057static int qca808x_cable_test_start(struct phy_device *phydev)
2058{
2059 int ret;
2060
2061 /* perform CDT with the following configs:
2062 * 1. disable hibernation.
2063 * 2. force PHY working in MDI mode.
2064 * 3. for PHY working in 1000BaseT.
2065 * 4. configure the threshold.
2066 */
2067
2068 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
2069 if (ret < 0)
2070 return ret;
2071
2072 ret = at803x_config_mdix(phydev, ETH_TP_MDI);
2073 if (ret < 0)
2074 return ret;
2075
2076 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
2077 phydev->duplex = DUPLEX_FULL;
2078 phydev->speed = SPEED_1000;
2079 ret = genphy_c45_pma_setup_forced(phydev);
2080 if (ret < 0)
2081 return ret;
2082
2083 ret = genphy_setup_forced(phydev);
2084 if (ret < 0)
2085 return ret;
2086
2087 /* configure the thresholds for open, short, pair ok test */
2088 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
2089 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
2090 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
2091 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
2092 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
2093 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
2094
2095 return 0;
2096}
2097
2098static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
2099 u16 status)
2100{
2101 int length, result;
2102 u16 pair_code;
2103
2104 switch (pair) {
2105 case ETHTOOL_A_CABLE_PAIR_A:
2106 pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
2107 break;
2108 case ETHTOOL_A_CABLE_PAIR_B:
2109 pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
2110 break;
2111 case ETHTOOL_A_CABLE_PAIR_C:
2112 pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
2113 break;
2114 case ETHTOOL_A_CABLE_PAIR_D:
2115 pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
2116 break;
2117 default:
2118 return -EINVAL;
2119 }
2120
2121 result = qca808x_cable_test_result_trans(pair_code);
2122 ethnl_cable_test_result(phydev, pair, result);
2123
2124 if (qca808x_cdt_fault_length_valid(pair_code)) {
2125 length = qca808x_cdt_fault_length(phydev, pair, result);
2126 ethnl_cable_test_fault_length(phydev, pair, length);
2127 }
2128
2129 return 0;
2130}
2131
2132static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
2133{
2134 int ret, val;
2135
2136 *finished = false;
2137
2138 val = QCA808X_CDT_ENABLE_TEST |
2139 QCA808X_CDT_LENGTH_UNIT;
2140 ret = at803x_cdt_start(phydev, val);
2141 if (ret)
2142 return ret;
2143
2144 ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
2145 if (ret)
2146 return ret;
2147
2148 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
2149 if (val < 0)
2150 return val;
2151
2152 ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
2153 if (ret)
2154 return ret;
2155
2156 ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
2157 if (ret)
2158 return ret;
2159
2160 ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
2161 if (ret)
2162 return ret;
2163
2164 ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
2165 if (ret)
2166 return ret;
2167
2168 *finished = true;
2169
2170 return 0;
2171}
2172
2173static int qca808x_get_features(struct phy_device *phydev)
2174{
2175 int ret;
2176
2177 ret = genphy_c45_pma_read_abilities(phydev);
2178 if (ret)
2179 return ret;
2180
2181 /* The autoneg ability is not existed in bit3 of MMD7.1,
2182 * but it is supported by qca808x PHY, so we add it here
2183 * manually.
2184 */
2185 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
2186
2187 /* As for the qca8081 1G version chip, the 2500baseT ability is also
2188 * existed in the bit0 of MMD1.21, we need to remove it manually if
2189 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
2190 */
2191 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
2192 if (ret < 0)
2193 return ret;
2194
2195 if (QCA808X_PHY_CHIP_TYPE_1G & ret)
2196 linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
2197
2198 return 0;
2199}
2200
2201static int qca808x_config_aneg(struct phy_device *phydev)
2202{
2203 int phy_ctrl = 0;
2204 int ret;
2205
2206 ret = at803x_prepare_config_aneg(phydev);
2207 if (ret)
2208 return ret;
2209
2210 /* The reg MII_BMCR also needs to be configured for force mode, the
2211 * genphy_config_aneg is also needed.
2212 */
2213 if (phydev->autoneg == AUTONEG_DISABLE)
2214 genphy_c45_pma_setup_forced(phydev);
2215
2216 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
2217 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
2218
2219 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
2220 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
2221 if (ret < 0)
2222 return ret;
2223
2224 return __genphy_config_aneg(phydev, ret);
2225}
2226
2227static void qca808x_link_change_notify(struct phy_device *phydev)
2228{
2229 /* Assert interface sgmii fifo on link down, deassert it on link up,
2230 * the interface device address is always phy address added by 1.
2231 */
2232 mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
2233 MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
2234 QCA8081_PHY_FIFO_RSTN,
2235 phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
2236}
2237
2238static struct phy_driver at803x_driver[] = {
2239{
2240 /* Qualcomm Atheros AR8035 */
2241 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
2242 .name = "Qualcomm Atheros AR8035",
2243 .flags = PHY_POLL_CABLE_TEST,
2244 .probe = at8035_probe,
2245 .config_aneg = at803x_config_aneg,
2246 .config_init = at803x_config_init,
2247 .soft_reset = genphy_soft_reset,
2248 .set_wol = at803x_set_wol,
2249 .get_wol = at803x_get_wol,
2250 .suspend = at803x_suspend,
2251 .resume = at803x_resume,
2252 /* PHY_GBIT_FEATURES */
2253 .read_status = at803x_read_status,
2254 .config_intr = at803x_config_intr,
2255 .handle_interrupt = at803x_handle_interrupt,
2256 .get_tunable = at803x_get_tunable,
2257 .set_tunable = at803x_set_tunable,
2258 .cable_test_start = at8031_cable_test_start,
2259 .cable_test_get_status = at8031_cable_test_get_status,
2260}, {
2261 /* Qualcomm Atheros AR8030 */
2262 .phy_id = ATH8030_PHY_ID,
2263 .name = "Qualcomm Atheros AR8030",
2264 .phy_id_mask = AT8030_PHY_ID_MASK,
2265 .probe = at8035_probe,
2266 .config_init = at803x_config_init,
2267 .link_change_notify = at803x_link_change_notify,
2268 .set_wol = at803x_set_wol,
2269 .get_wol = at803x_get_wol,
2270 .suspend = at803x_suspend,
2271 .resume = at803x_resume,
2272 /* PHY_BASIC_FEATURES */
2273 .config_intr = at803x_config_intr,
2274 .handle_interrupt = at803x_handle_interrupt,
2275}, {
2276 /* Qualcomm Atheros AR8031/AR8033 */
2277 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
2278 .name = "Qualcomm Atheros AR8031/AR8033",
2279 .flags = PHY_POLL_CABLE_TEST,
2280 .probe = at8031_probe,
2281 .config_init = at8031_config_init,
2282 .config_aneg = at803x_config_aneg,
2283 .soft_reset = genphy_soft_reset,
2284 .set_wol = at8031_set_wol,
2285 .get_wol = at803x_get_wol,
2286 .suspend = at803x_suspend,
2287 .resume = at803x_resume,
2288 .read_page = at803x_read_page,
2289 .write_page = at803x_write_page,
2290 .get_features = at803x_get_features,
2291 .read_status = at8031_read_status,
2292 .config_intr = at8031_config_intr,
2293 .handle_interrupt = at803x_handle_interrupt,
2294 .get_tunable = at803x_get_tunable,
2295 .set_tunable = at803x_set_tunable,
2296 .cable_test_start = at8031_cable_test_start,
2297 .cable_test_get_status = at8031_cable_test_get_status,
2298}, {
2299 /* Qualcomm Atheros AR8032 */
2300 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
2301 .name = "Qualcomm Atheros AR8032",
2302 .probe = at803x_probe,
2303 .flags = PHY_POLL_CABLE_TEST,
2304 .config_init = at803x_config_init,
2305 .link_change_notify = at803x_link_change_notify,
2306 .suspend = at803x_suspend,
2307 .resume = at803x_resume,
2308 /* PHY_BASIC_FEATURES */
2309 .config_intr = at803x_config_intr,
2310 .handle_interrupt = at803x_handle_interrupt,
2311 .cable_test_start = at803x_cable_test_start,
2312 .cable_test_get_status = at8032_cable_test_get_status,
2313}, {
2314 /* ATHEROS AR9331 */
2315 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
2316 .name = "Qualcomm Atheros AR9331 built-in PHY",
2317 .probe = at803x_probe,
2318 .suspend = at803x_suspend,
2319 .resume = at803x_resume,
2320 .flags = PHY_POLL_CABLE_TEST,
2321 /* PHY_BASIC_FEATURES */
2322 .config_intr = at803x_config_intr,
2323 .handle_interrupt = at803x_handle_interrupt,
2324 .cable_test_start = at803x_cable_test_start,
2325 .cable_test_get_status = at8032_cable_test_get_status,
2326 .read_status = at803x_read_status,
2327 .soft_reset = genphy_soft_reset,
2328 .config_aneg = at803x_config_aneg,
2329}, {
2330 /* Qualcomm Atheros QCA9561 */
2331 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
2332 .name = "Qualcomm Atheros QCA9561 built-in PHY",
2333 .probe = at803x_probe,
2334 .suspend = at803x_suspend,
2335 .resume = at803x_resume,
2336 .flags = PHY_POLL_CABLE_TEST,
2337 /* PHY_BASIC_FEATURES */
2338 .config_intr = at803x_config_intr,
2339 .handle_interrupt = at803x_handle_interrupt,
2340 .cable_test_start = at803x_cable_test_start,
2341 .cable_test_get_status = at8032_cable_test_get_status,
2342 .read_status = at803x_read_status,
2343 .soft_reset = genphy_soft_reset,
2344 .config_aneg = at803x_config_aneg,
2345}, {
2346 /* QCA8337 */
2347 .phy_id = QCA8337_PHY_ID,
2348 .phy_id_mask = QCA8K_PHY_ID_MASK,
2349 .name = "Qualcomm Atheros 8337 internal PHY",
2350 /* PHY_GBIT_FEATURES */
2351 .probe = at803x_probe,
2352 .flags = PHY_IS_INTERNAL,
2353 .config_init = qca83xx_config_init,
2354 .soft_reset = genphy_soft_reset,
2355 .get_sset_count = qca83xx_get_sset_count,
2356 .get_strings = qca83xx_get_strings,
2357 .get_stats = qca83xx_get_stats,
2358 .suspend = qca8337_suspend,
2359 .resume = qca83xx_resume,
2360}, {
2361 /* QCA8327-A from switch QCA8327-AL1A */
2362 .phy_id = QCA8327_A_PHY_ID,
2363 .phy_id_mask = QCA8K_PHY_ID_MASK,
2364 .name = "Qualcomm Atheros 8327-A internal PHY",
2365 /* PHY_GBIT_FEATURES */
2366 .link_change_notify = qca83xx_link_change_notify,
2367 .probe = at803x_probe,
2368 .flags = PHY_IS_INTERNAL,
2369 .config_init = qca8327_config_init,
2370 .soft_reset = genphy_soft_reset,
2371 .get_sset_count = qca83xx_get_sset_count,
2372 .get_strings = qca83xx_get_strings,
2373 .get_stats = qca83xx_get_stats,
2374 .suspend = qca8327_suspend,
2375 .resume = qca83xx_resume,
2376}, {
2377 /* QCA8327-B from switch QCA8327-BL1A */
2378 .phy_id = QCA8327_B_PHY_ID,
2379 .phy_id_mask = QCA8K_PHY_ID_MASK,
2380 .name = "Qualcomm Atheros 8327-B internal PHY",
2381 /* PHY_GBIT_FEATURES */
2382 .link_change_notify = qca83xx_link_change_notify,
2383 .probe = at803x_probe,
2384 .flags = PHY_IS_INTERNAL,
2385 .config_init = qca8327_config_init,
2386 .soft_reset = genphy_soft_reset,
2387 .get_sset_count = qca83xx_get_sset_count,
2388 .get_strings = qca83xx_get_strings,
2389 .get_stats = qca83xx_get_stats,
2390 .suspend = qca8327_suspend,
2391 .resume = qca83xx_resume,
2392}, {
2393 /* Qualcomm QCA8081 */
2394 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
2395 .name = "Qualcomm QCA8081",
2396 .flags = PHY_POLL_CABLE_TEST,
2397 .probe = at803x_probe,
2398 .config_intr = at803x_config_intr,
2399 .handle_interrupt = at803x_handle_interrupt,
2400 .get_tunable = at803x_get_tunable,
2401 .set_tunable = at803x_set_tunable,
2402 .set_wol = at803x_set_wol,
2403 .get_wol = at803x_get_wol,
2404 .get_features = qca808x_get_features,
2405 .config_aneg = qca808x_config_aneg,
2406 .suspend = genphy_suspend,
2407 .resume = genphy_resume,
2408 .read_status = qca808x_read_status,
2409 .config_init = qca808x_config_init,
2410 .soft_reset = qca808x_soft_reset,
2411 .cable_test_start = qca808x_cable_test_start,
2412 .cable_test_get_status = qca808x_cable_test_get_status,
2413 .link_change_notify = qca808x_link_change_notify,
2414}, };
2415
2416module_phy_driver(at803x_driver);
2417
2418static struct mdio_device_id __maybe_unused atheros_tbl[] = {
2419 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
2420 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
2421 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
2422 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
2423 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
2424 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
2425 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
2426 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
2427 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
2428 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
2429 { }
2430};
2431
2432MODULE_DEVICE_TABLE(mdio, atheros_tbl);