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1// SPDX-License-Identifier: GPL-2.0-only
2/*******************************************************************************
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
5 developing this code.
6
7 This only implements the mac core functions for this chip.
8
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
10
11
12 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
13*******************************************************************************/
14
15#include <linux/crc32.h>
16#include <linux/slab.h>
17#include <linux/ethtool.h>
18#include <linux/io.h>
19#include "stmmac.h"
20#include "stmmac_pcs.h"
21#include "stmmac_ptp.h"
22#include "dwmac1000.h"
23
24static void dwmac1000_core_init(struct mac_device_info *hw,
25 struct net_device *dev)
26{
27 void __iomem *ioaddr = hw->pcsr;
28 u32 value = readl(ioaddr + GMAC_CONTROL);
29 int mtu = dev->mtu;
30
31 /* Configure GMAC core */
32 value |= GMAC_CORE_INIT;
33
34 if (mtu > 1500)
35 value |= GMAC_CONTROL_2K;
36 if (mtu > 2000)
37 value |= GMAC_CONTROL_JE;
38
39 if (hw->ps) {
40 value |= GMAC_CONTROL_TE;
41
42 value &= ~hw->link.speed_mask;
43 switch (hw->ps) {
44 case SPEED_1000:
45 value |= hw->link.speed1000;
46 break;
47 case SPEED_100:
48 value |= hw->link.speed100;
49 break;
50 case SPEED_10:
51 value |= hw->link.speed10;
52 break;
53 }
54 }
55
56 writel(value, ioaddr + GMAC_CONTROL);
57
58 /* Mask GMAC interrupts */
59 value = GMAC_INT_DEFAULT_MASK;
60
61 if (hw->pcs)
62 value &= ~GMAC_INT_DISABLE_PCS;
63
64 writel(value, ioaddr + GMAC_INT_MASK);
65
66#ifdef STMMAC_VLAN_TAG_USED
67 /* Tag detection without filtering */
68 writel(0x0, ioaddr + GMAC_VLAN_TAG);
69#endif
70}
71
72static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
73{
74 void __iomem *ioaddr = hw->pcsr;
75 u32 value = readl(ioaddr + GMAC_CONTROL);
76
77 if (hw->rx_csum)
78 value |= GMAC_CONTROL_IPC;
79 else
80 value &= ~GMAC_CONTROL_IPC;
81
82 writel(value, ioaddr + GMAC_CONTROL);
83
84 value = readl(ioaddr + GMAC_CONTROL);
85
86 return !!(value & GMAC_CONTROL_IPC);
87}
88
89static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
90{
91 void __iomem *ioaddr = hw->pcsr;
92 int i;
93
94 for (i = 0; i < 55; i++)
95 reg_space[i] = readl(ioaddr + i * 4);
96}
97
98static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
99 const unsigned char *addr,
100 unsigned int reg_n)
101{
102 void __iomem *ioaddr = hw->pcsr;
103 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
104 GMAC_ADDR_LOW(reg_n));
105}
106
107static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
108 unsigned char *addr,
109 unsigned int reg_n)
110{
111 void __iomem *ioaddr = hw->pcsr;
112 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
113 GMAC_ADDR_LOW(reg_n));
114}
115
116static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
117 int mcbitslog2)
118{
119 int numhashregs, regs;
120
121 switch (mcbitslog2) {
122 case 6:
123 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
124 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
125 return;
126 case 7:
127 numhashregs = 4;
128 break;
129 case 8:
130 numhashregs = 8;
131 break;
132 default:
133 pr_debug("STMMAC: err in setting multicast filter\n");
134 return;
135 }
136 for (regs = 0; regs < numhashregs; regs++)
137 writel(mcfilterbits[regs],
138 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
139}
140
141static void dwmac1000_set_filter(struct mac_device_info *hw,
142 struct net_device *dev)
143{
144 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
145 unsigned int value = 0;
146 unsigned int perfect_addr_number = hw->unicast_filter_entries;
147 u32 mc_filter[8];
148 int mcbitslog2 = hw->mcast_bits_log2;
149
150 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
151 netdev_mc_count(dev), netdev_uc_count(dev));
152
153 memset(mc_filter, 0, sizeof(mc_filter));
154
155 if (dev->flags & IFF_PROMISC) {
156 value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
157 } else if (dev->flags & IFF_ALLMULTI) {
158 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
159 } else if (!netdev_mc_empty(dev) && (mcbitslog2 == 0)) {
160 /* Fall back to all multicast if we've no filter */
161 value = GMAC_FRAME_FILTER_PM;
162 } else if (!netdev_mc_empty(dev)) {
163 struct netdev_hw_addr *ha;
164
165 /* Hash filter for multicast */
166 value = GMAC_FRAME_FILTER_HMC;
167
168 netdev_for_each_mc_addr(ha, dev) {
169 /* The upper n bits of the calculated CRC are used to
170 * index the contents of the hash table. The number of
171 * bits used depends on the hardware configuration
172 * selected at core configuration time.
173 */
174 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
175 ETH_ALEN)) >>
176 (32 - mcbitslog2);
177 /* The most significant bit determines the register to
178 * use (H/L) while the other 5 bits determine the bit
179 * within the register.
180 */
181 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
182 }
183 }
184
185 value |= GMAC_FRAME_FILTER_HPF;
186 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
187
188 /* Handle multiple unicast addresses (perfect filtering) */
189 if (netdev_uc_count(dev) > perfect_addr_number)
190 /* Switch to promiscuous mode if more than unicast
191 * addresses are requested than supported by hardware.
192 */
193 value |= GMAC_FRAME_FILTER_PR;
194 else {
195 int reg = 1;
196 struct netdev_hw_addr *ha;
197
198 netdev_for_each_uc_addr(ha, dev) {
199 stmmac_set_mac_addr(ioaddr, ha->addr,
200 GMAC_ADDR_HIGH(reg),
201 GMAC_ADDR_LOW(reg));
202 reg++;
203 }
204
205 while (reg < perfect_addr_number) {
206 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
207 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
208 reg++;
209 }
210 }
211
212#ifdef FRAME_FILTER_DEBUG
213 /* Enable Receive all mode (to debug filtering_fail errors) */
214 value |= GMAC_FRAME_FILTER_RA;
215#endif
216 writel(value, ioaddr + GMAC_FRAME_FILTER);
217}
218
219
220static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
221 unsigned int fc, unsigned int pause_time,
222 u32 tx_cnt)
223{
224 void __iomem *ioaddr = hw->pcsr;
225 /* Set flow such that DZPQ in Mac Register 6 is 0,
226 * and unicast pause detect is enabled.
227 */
228 unsigned int flow = GMAC_FLOW_CTRL_UP;
229
230 pr_debug("GMAC Flow-Control:\n");
231 if (fc & FLOW_RX) {
232 pr_debug("\tReceive Flow-Control ON\n");
233 flow |= GMAC_FLOW_CTRL_RFE;
234 }
235 if (fc & FLOW_TX) {
236 pr_debug("\tTransmit Flow-Control ON\n");
237 flow |= GMAC_FLOW_CTRL_TFE;
238 }
239
240 if (duplex) {
241 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
242 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
243 }
244
245 writel(flow, ioaddr + GMAC_FLOW_CTRL);
246}
247
248static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
249{
250 void __iomem *ioaddr = hw->pcsr;
251 unsigned int pmt = 0;
252
253 if (mode & WAKE_MAGIC) {
254 pr_debug("GMAC: WOL Magic frame\n");
255 pmt |= power_down | magic_pkt_en;
256 }
257 if (mode & WAKE_UCAST) {
258 pr_debug("GMAC: WOL on global unicast\n");
259 pmt |= power_down | global_unicast | wake_up_frame_en;
260 }
261
262 writel(pmt, ioaddr + GMAC_PMT);
263}
264
265/* RGMII or SMII interface */
266static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
267{
268 u32 status;
269
270 status = readl(ioaddr + GMAC_RGSMIIIS);
271 x->irq_rgmii_n++;
272
273 /* Check the link status */
274 if (status & GMAC_RGSMIIIS_LNKSTS) {
275 int speed_value;
276
277 x->pcs_link = 1;
278
279 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
280 GMAC_RGSMIIIS_SPEED_SHIFT);
281 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
282 x->pcs_speed = SPEED_1000;
283 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
284 x->pcs_speed = SPEED_100;
285 else
286 x->pcs_speed = SPEED_10;
287
288 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
289
290 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
291 x->pcs_duplex ? "Full" : "Half");
292 } else {
293 x->pcs_link = 0;
294 pr_info("Link is Down\n");
295 }
296}
297
298static int dwmac1000_irq_status(struct mac_device_info *hw,
299 struct stmmac_extra_stats *x)
300{
301 void __iomem *ioaddr = hw->pcsr;
302 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
303 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
304 int ret = 0;
305
306 /* Discard masked bits */
307 intr_status &= ~intr_mask;
308
309 /* Not used events (e.g. MMC interrupts) are not handled. */
310 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
311 x->mmc_tx_irq_n++;
312 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
313 x->mmc_rx_irq_n++;
314 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
315 x->mmc_rx_csum_offload_irq_n++;
316 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
317 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
318 readl(ioaddr + GMAC_PMT);
319 x->irq_receive_pmt_irq_n++;
320 }
321
322 /* MAC tx/rx EEE LPI entry/exit interrupts */
323 if (intr_status & GMAC_INT_STATUS_LPIIS) {
324 /* Clean LPI interrupt by reading the Reg 12 */
325 ret = readl(ioaddr + LPI_CTRL_STATUS);
326
327 if (ret & LPI_CTRL_STATUS_TLPIEN)
328 x->irq_tx_path_in_lpi_mode_n++;
329 if (ret & LPI_CTRL_STATUS_TLPIEX)
330 x->irq_tx_path_exit_lpi_mode_n++;
331 if (ret & LPI_CTRL_STATUS_RLPIEN)
332 x->irq_rx_path_in_lpi_mode_n++;
333 if (ret & LPI_CTRL_STATUS_RLPIEX)
334 x->irq_rx_path_exit_lpi_mode_n++;
335 }
336
337 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
338
339 if (intr_status & PCS_RGSMIIIS_IRQ)
340 dwmac1000_rgsmii(ioaddr, x);
341
342 return ret;
343}
344
345static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
346 bool en_tx_lpi_clockgating)
347{
348 void __iomem *ioaddr = hw->pcsr;
349 u32 value;
350
351 /*TODO - en_tx_lpi_clockgating treatment */
352
353 /* Enable the link status receive on RGMII, SGMII ore SMII
354 * receive path and instruct the transmit to enter in LPI
355 * state.
356 */
357 value = readl(ioaddr + LPI_CTRL_STATUS);
358 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
359 writel(value, ioaddr + LPI_CTRL_STATUS);
360}
361
362static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
363{
364 void __iomem *ioaddr = hw->pcsr;
365 u32 value;
366
367 value = readl(ioaddr + LPI_CTRL_STATUS);
368 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
369 writel(value, ioaddr + LPI_CTRL_STATUS);
370}
371
372static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
373{
374 void __iomem *ioaddr = hw->pcsr;
375 u32 value;
376
377 value = readl(ioaddr + LPI_CTRL_STATUS);
378
379 if (link)
380 value |= LPI_CTRL_STATUS_PLS;
381 else
382 value &= ~LPI_CTRL_STATUS_PLS;
383
384 writel(value, ioaddr + LPI_CTRL_STATUS);
385}
386
387static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
388{
389 void __iomem *ioaddr = hw->pcsr;
390 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
391
392 /* Program the timers in the LPI timer control register:
393 * LS: minimum time (ms) for which the link
394 * status from PHY should be ok before transmitting
395 * the LPI pattern.
396 * TW: minimum time (us) for which the core waits
397 * after it has stopped transmitting the LPI pattern.
398 */
399 writel(value, ioaddr + LPI_TIMER_CTRL);
400}
401
402static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
403 bool loopback)
404{
405 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
406}
407
408static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
409{
410 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
411}
412
413static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr,
414 struct stmmac_extra_stats *x,
415 u32 rx_queues, u32 tx_queues)
416{
417 u32 value = readl(ioaddr + GMAC_DEBUG);
418
419 if (value & GMAC_DEBUG_TXSTSFSTS)
420 x->mtl_tx_status_fifo_full++;
421 if (value & GMAC_DEBUG_TXFSTS)
422 x->mtl_tx_fifo_not_empty++;
423 if (value & GMAC_DEBUG_TWCSTS)
424 x->mmtl_fifo_ctrl++;
425 if (value & GMAC_DEBUG_TRCSTS_MASK) {
426 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
427 >> GMAC_DEBUG_TRCSTS_SHIFT;
428 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
429 x->mtl_tx_fifo_read_ctrl_write++;
430 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
431 x->mtl_tx_fifo_read_ctrl_wait++;
432 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
433 x->mtl_tx_fifo_read_ctrl_read++;
434 else
435 x->mtl_tx_fifo_read_ctrl_idle++;
436 }
437 if (value & GMAC_DEBUG_TXPAUSED)
438 x->mac_tx_in_pause++;
439 if (value & GMAC_DEBUG_TFCSTS_MASK) {
440 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
441 >> GMAC_DEBUG_TFCSTS_SHIFT;
442
443 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
444 x->mac_tx_frame_ctrl_xfer++;
445 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
446 x->mac_tx_frame_ctrl_pause++;
447 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
448 x->mac_tx_frame_ctrl_wait++;
449 else
450 x->mac_tx_frame_ctrl_idle++;
451 }
452 if (value & GMAC_DEBUG_TPESTS)
453 x->mac_gmii_tx_proto_engine++;
454 if (value & GMAC_DEBUG_RXFSTS_MASK) {
455 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
456 >> GMAC_DEBUG_RRCSTS_SHIFT;
457
458 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
459 x->mtl_rx_fifo_fill_level_full++;
460 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
461 x->mtl_rx_fifo_fill_above_thresh++;
462 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
463 x->mtl_rx_fifo_fill_below_thresh++;
464 else
465 x->mtl_rx_fifo_fill_level_empty++;
466 }
467 if (value & GMAC_DEBUG_RRCSTS_MASK) {
468 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
469 GMAC_DEBUG_RRCSTS_SHIFT;
470
471 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
472 x->mtl_rx_fifo_read_ctrl_flush++;
473 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
474 x->mtl_rx_fifo_read_ctrl_read_data++;
475 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
476 x->mtl_rx_fifo_read_ctrl_status++;
477 else
478 x->mtl_rx_fifo_read_ctrl_idle++;
479 }
480 if (value & GMAC_DEBUG_RWCSTS)
481 x->mtl_rx_fifo_ctrl_active++;
482 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
483 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
484 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
485 if (value & GMAC_DEBUG_RPESTS)
486 x->mac_gmii_rx_proto_engine++;
487}
488
489static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
490{
491 u32 value = readl(ioaddr + GMAC_CONTROL);
492
493 if (enable)
494 value |= GMAC_CONTROL_LM;
495 else
496 value &= ~GMAC_CONTROL_LM;
497
498 writel(value, ioaddr + GMAC_CONTROL);
499}
500
501const struct stmmac_ops dwmac1000_ops = {
502 .core_init = dwmac1000_core_init,
503 .set_mac = stmmac_set_mac,
504 .rx_ipc = dwmac1000_rx_ipc_enable,
505 .dump_regs = dwmac1000_dump_regs,
506 .host_irq_status = dwmac1000_irq_status,
507 .set_filter = dwmac1000_set_filter,
508 .flow_ctrl = dwmac1000_flow_ctrl,
509 .pmt = dwmac1000_pmt,
510 .set_umac_addr = dwmac1000_set_umac_addr,
511 .get_umac_addr = dwmac1000_get_umac_addr,
512 .set_eee_mode = dwmac1000_set_eee_mode,
513 .reset_eee_mode = dwmac1000_reset_eee_mode,
514 .set_eee_timer = dwmac1000_set_eee_timer,
515 .set_eee_pls = dwmac1000_set_eee_pls,
516 .debug = dwmac1000_debug,
517 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
518 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
519 .set_mac_loopback = dwmac1000_set_mac_loopback,
520};
521
522int dwmac1000_setup(struct stmmac_priv *priv)
523{
524 struct mac_device_info *mac = priv->hw;
525
526 dev_info(priv->device, "\tDWMAC1000\n");
527
528 priv->dev->priv_flags |= IFF_UNICAST_FLT;
529 mac->pcsr = priv->ioaddr;
530 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
531 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
532 mac->mcast_bits_log2 = 0;
533
534 if (mac->multicast_filter_bins)
535 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
536
537 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
538 MAC_10 | MAC_100 | MAC_1000;
539 mac->link.duplex = GMAC_CONTROL_DM;
540 mac->link.speed10 = GMAC_CONTROL_PS;
541 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
542 mac->link.speed1000 = 0;
543 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
544 mac->mii.addr = GMAC_MII_ADDR;
545 mac->mii.data = GMAC_MII_DATA;
546 mac->mii.addr_shift = 11;
547 mac->mii.addr_mask = 0x0000F800;
548 mac->mii.reg_shift = 6;
549 mac->mii.reg_mask = 0x000007C0;
550 mac->mii.clk_csr_shift = 2;
551 mac->mii.clk_csr_mask = GENMASK(5, 2);
552
553 return 0;
554}
555
556/* DWMAC 1000 HW Timestaming ops */
557
558void dwmac1000_get_ptptime(void __iomem *ptpaddr, u64 *ptp_time)
559{
560 u64 ns;
561
562 ns = readl(ptpaddr + GMAC_PTP_ATNR);
563 ns += readl(ptpaddr + GMAC_PTP_ATSR) * NSEC_PER_SEC;
564
565 *ptp_time = ns;
566}
567
568void dwmac1000_timestamp_interrupt(struct stmmac_priv *priv)
569{
570 struct ptp_clock_event event;
571 u32 ts_status, num_snapshot;
572 unsigned long flags;
573 u64 ptp_time;
574 int i;
575
576 /* Clears the timestamp interrupt */
577 ts_status = readl(priv->ptpaddr + GMAC3_X_TIMESTAMP_STATUS);
578
579 if (!(priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN))
580 return;
581
582 num_snapshot = (ts_status & GMAC3_X_ATSNS) >> GMAC3_X_ATSNS_SHIFT;
583
584 for (i = 0; i < num_snapshot; i++) {
585 read_lock_irqsave(&priv->ptp_lock, flags);
586 stmmac_get_ptptime(priv, priv->ptpaddr, &ptp_time);
587 read_unlock_irqrestore(&priv->ptp_lock, flags);
588
589 event.type = PTP_CLOCK_EXTTS;
590 event.index = 0;
591 event.timestamp = ptp_time;
592 ptp_clock_event(priv->ptp_clock, &event);
593 }
594}
595
596/* DWMAC 1000 ptp_clock_info ops */
597
598static void dwmac1000_timestamp_interrupt_cfg(struct stmmac_priv *priv, bool en)
599{
600 void __iomem *ioaddr = priv->ioaddr;
601
602 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
603
604 if (en)
605 intr_mask &= ~GMAC_INT_DISABLE_TIMESTAMP;
606 else
607 intr_mask |= GMAC_INT_DISABLE_TIMESTAMP;
608
609 writel(intr_mask, ioaddr + GMAC_INT_MASK);
610}
611
612int dwmac1000_ptp_enable(struct ptp_clock_info *ptp,
613 struct ptp_clock_request *rq, int on)
614{
615 struct stmmac_priv *priv =
616 container_of(ptp, struct stmmac_priv, ptp_clock_ops);
617 void __iomem *ptpaddr = priv->ptpaddr;
618 int ret = -EOPNOTSUPP;
619 u32 tcr_val;
620
621 switch (rq->type) {
622 case PTP_CLK_REQ_EXTTS:
623 mutex_lock(&priv->aux_ts_lock);
624 tcr_val = readl(ptpaddr + PTP_TCR);
625
626 if (on) {
627 tcr_val |= GMAC_PTP_TCR_ATSEN0;
628 tcr_val |= GMAC_PTP_TCR_ATSFC;
629 priv->plat->flags |= STMMAC_FLAG_EXT_SNAPSHOT_EN;
630 } else {
631 tcr_val &= ~GMAC_PTP_TCR_ATSEN0;
632 priv->plat->flags &= ~STMMAC_FLAG_EXT_SNAPSHOT_EN;
633 }
634
635 netdev_dbg(priv->dev, "Auxiliary Snapshot %s.\n",
636 on ? "enabled" : "disabled");
637 writel(tcr_val, ptpaddr + PTP_TCR);
638
639 /* wait for auxts fifo clear to finish */
640 ret = readl_poll_timeout(ptpaddr + PTP_TCR, tcr_val,
641 !(tcr_val & GMAC_PTP_TCR_ATSFC),
642 10, 10000);
643
644 mutex_unlock(&priv->aux_ts_lock);
645
646 dwmac1000_timestamp_interrupt_cfg(priv, on);
647 break;
648
649 default:
650 break;
651 }
652
653 return ret;
654}
1// SPDX-License-Identifier: GPL-2.0-only
2/*******************************************************************************
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
5 developing this code.
6
7 This only implements the mac core functions for this chip.
8
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
10
11
12 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
13*******************************************************************************/
14
15#include <linux/crc32.h>
16#include <linux/slab.h>
17#include <linux/ethtool.h>
18#include <asm/io.h>
19#include "stmmac.h"
20#include "stmmac_pcs.h"
21#include "dwmac1000.h"
22
23static void dwmac1000_core_init(struct mac_device_info *hw,
24 struct net_device *dev)
25{
26 void __iomem *ioaddr = hw->pcsr;
27 u32 value = readl(ioaddr + GMAC_CONTROL);
28 int mtu = dev->mtu;
29
30 /* Configure GMAC core */
31 value |= GMAC_CORE_INIT;
32
33 if (mtu > 1500)
34 value |= GMAC_CONTROL_2K;
35 if (mtu > 2000)
36 value |= GMAC_CONTROL_JE;
37
38 if (hw->ps) {
39 value |= GMAC_CONTROL_TE;
40
41 value &= ~hw->link.speed_mask;
42 switch (hw->ps) {
43 case SPEED_1000:
44 value |= hw->link.speed1000;
45 break;
46 case SPEED_100:
47 value |= hw->link.speed100;
48 break;
49 case SPEED_10:
50 value |= hw->link.speed10;
51 break;
52 }
53 }
54
55 writel(value, ioaddr + GMAC_CONTROL);
56
57 /* Mask GMAC interrupts */
58 value = GMAC_INT_DEFAULT_MASK;
59
60 if (hw->pcs)
61 value &= ~GMAC_INT_DISABLE_PCS;
62
63 writel(value, ioaddr + GMAC_INT_MASK);
64
65#ifdef STMMAC_VLAN_TAG_USED
66 /* Tag detection without filtering */
67 writel(0x0, ioaddr + GMAC_VLAN_TAG);
68#endif
69}
70
71static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
72{
73 void __iomem *ioaddr = hw->pcsr;
74 u32 value = readl(ioaddr + GMAC_CONTROL);
75
76 if (hw->rx_csum)
77 value |= GMAC_CONTROL_IPC;
78 else
79 value &= ~GMAC_CONTROL_IPC;
80
81 writel(value, ioaddr + GMAC_CONTROL);
82
83 value = readl(ioaddr + GMAC_CONTROL);
84
85 return !!(value & GMAC_CONTROL_IPC);
86}
87
88static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
89{
90 void __iomem *ioaddr = hw->pcsr;
91 int i;
92
93 for (i = 0; i < 55; i++)
94 reg_space[i] = readl(ioaddr + i * 4);
95}
96
97static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
98 const unsigned char *addr,
99 unsigned int reg_n)
100{
101 void __iomem *ioaddr = hw->pcsr;
102 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
103 GMAC_ADDR_LOW(reg_n));
104}
105
106static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
107 unsigned char *addr,
108 unsigned int reg_n)
109{
110 void __iomem *ioaddr = hw->pcsr;
111 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
112 GMAC_ADDR_LOW(reg_n));
113}
114
115static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
116 int mcbitslog2)
117{
118 int numhashregs, regs;
119
120 switch (mcbitslog2) {
121 case 6:
122 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
123 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
124 return;
125 case 7:
126 numhashregs = 4;
127 break;
128 case 8:
129 numhashregs = 8;
130 break;
131 default:
132 pr_debug("STMMAC: err in setting multicast filter\n");
133 return;
134 }
135 for (regs = 0; regs < numhashregs; regs++)
136 writel(mcfilterbits[regs],
137 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
138}
139
140static void dwmac1000_set_filter(struct mac_device_info *hw,
141 struct net_device *dev)
142{
143 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
144 unsigned int value = 0;
145 unsigned int perfect_addr_number = hw->unicast_filter_entries;
146 u32 mc_filter[8];
147 int mcbitslog2 = hw->mcast_bits_log2;
148
149 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
150 netdev_mc_count(dev), netdev_uc_count(dev));
151
152 memset(mc_filter, 0, sizeof(mc_filter));
153
154 if (dev->flags & IFF_PROMISC) {
155 value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
156 } else if (dev->flags & IFF_ALLMULTI) {
157 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
158 } else if (!netdev_mc_empty(dev) && (mcbitslog2 == 0)) {
159 /* Fall back to all multicast if we've no filter */
160 value = GMAC_FRAME_FILTER_PM;
161 } else if (!netdev_mc_empty(dev)) {
162 struct netdev_hw_addr *ha;
163
164 /* Hash filter for multicast */
165 value = GMAC_FRAME_FILTER_HMC;
166
167 netdev_for_each_mc_addr(ha, dev) {
168 /* The upper n bits of the calculated CRC are used to
169 * index the contents of the hash table. The number of
170 * bits used depends on the hardware configuration
171 * selected at core configuration time.
172 */
173 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
174 ETH_ALEN)) >>
175 (32 - mcbitslog2);
176 /* The most significant bit determines the register to
177 * use (H/L) while the other 5 bits determine the bit
178 * within the register.
179 */
180 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
181 }
182 }
183
184 value |= GMAC_FRAME_FILTER_HPF;
185 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
186
187 /* Handle multiple unicast addresses (perfect filtering) */
188 if (netdev_uc_count(dev) > perfect_addr_number)
189 /* Switch to promiscuous mode if more than unicast
190 * addresses are requested than supported by hardware.
191 */
192 value |= GMAC_FRAME_FILTER_PR;
193 else {
194 int reg = 1;
195 struct netdev_hw_addr *ha;
196
197 netdev_for_each_uc_addr(ha, dev) {
198 stmmac_set_mac_addr(ioaddr, ha->addr,
199 GMAC_ADDR_HIGH(reg),
200 GMAC_ADDR_LOW(reg));
201 reg++;
202 }
203
204 while (reg < perfect_addr_number) {
205 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
206 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
207 reg++;
208 }
209 }
210
211#ifdef FRAME_FILTER_DEBUG
212 /* Enable Receive all mode (to debug filtering_fail errors) */
213 value |= GMAC_FRAME_FILTER_RA;
214#endif
215 writel(value, ioaddr + GMAC_FRAME_FILTER);
216}
217
218
219static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
220 unsigned int fc, unsigned int pause_time,
221 u32 tx_cnt)
222{
223 void __iomem *ioaddr = hw->pcsr;
224 /* Set flow such that DZPQ in Mac Register 6 is 0,
225 * and unicast pause detect is enabled.
226 */
227 unsigned int flow = GMAC_FLOW_CTRL_UP;
228
229 pr_debug("GMAC Flow-Control:\n");
230 if (fc & FLOW_RX) {
231 pr_debug("\tReceive Flow-Control ON\n");
232 flow |= GMAC_FLOW_CTRL_RFE;
233 }
234 if (fc & FLOW_TX) {
235 pr_debug("\tTransmit Flow-Control ON\n");
236 flow |= GMAC_FLOW_CTRL_TFE;
237 }
238
239 if (duplex) {
240 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
241 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
242 }
243
244 writel(flow, ioaddr + GMAC_FLOW_CTRL);
245}
246
247static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
248{
249 void __iomem *ioaddr = hw->pcsr;
250 unsigned int pmt = 0;
251
252 if (mode & WAKE_MAGIC) {
253 pr_debug("GMAC: WOL Magic frame\n");
254 pmt |= power_down | magic_pkt_en;
255 }
256 if (mode & WAKE_UCAST) {
257 pr_debug("GMAC: WOL on global unicast\n");
258 pmt |= power_down | global_unicast | wake_up_frame_en;
259 }
260
261 writel(pmt, ioaddr + GMAC_PMT);
262}
263
264/* RGMII or SMII interface */
265static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
266{
267 u32 status;
268
269 status = readl(ioaddr + GMAC_RGSMIIIS);
270 x->irq_rgmii_n++;
271
272 /* Check the link status */
273 if (status & GMAC_RGSMIIIS_LNKSTS) {
274 int speed_value;
275
276 x->pcs_link = 1;
277
278 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
279 GMAC_RGSMIIIS_SPEED_SHIFT);
280 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
281 x->pcs_speed = SPEED_1000;
282 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
283 x->pcs_speed = SPEED_100;
284 else
285 x->pcs_speed = SPEED_10;
286
287 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
288
289 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
290 x->pcs_duplex ? "Full" : "Half");
291 } else {
292 x->pcs_link = 0;
293 pr_info("Link is Down\n");
294 }
295}
296
297static int dwmac1000_irq_status(struct mac_device_info *hw,
298 struct stmmac_extra_stats *x)
299{
300 void __iomem *ioaddr = hw->pcsr;
301 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
302 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
303 int ret = 0;
304
305 /* Discard masked bits */
306 intr_status &= ~intr_mask;
307
308 /* Not used events (e.g. MMC interrupts) are not handled. */
309 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
310 x->mmc_tx_irq_n++;
311 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
312 x->mmc_rx_irq_n++;
313 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
314 x->mmc_rx_csum_offload_irq_n++;
315 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
316 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
317 readl(ioaddr + GMAC_PMT);
318 x->irq_receive_pmt_irq_n++;
319 }
320
321 /* MAC tx/rx EEE LPI entry/exit interrupts */
322 if (intr_status & GMAC_INT_STATUS_LPIIS) {
323 /* Clean LPI interrupt by reading the Reg 12 */
324 ret = readl(ioaddr + LPI_CTRL_STATUS);
325
326 if (ret & LPI_CTRL_STATUS_TLPIEN)
327 x->irq_tx_path_in_lpi_mode_n++;
328 if (ret & LPI_CTRL_STATUS_TLPIEX)
329 x->irq_tx_path_exit_lpi_mode_n++;
330 if (ret & LPI_CTRL_STATUS_RLPIEN)
331 x->irq_rx_path_in_lpi_mode_n++;
332 if (ret & LPI_CTRL_STATUS_RLPIEX)
333 x->irq_rx_path_exit_lpi_mode_n++;
334 }
335
336 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
337
338 if (intr_status & PCS_RGSMIIIS_IRQ)
339 dwmac1000_rgsmii(ioaddr, x);
340
341 return ret;
342}
343
344static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
345 bool en_tx_lpi_clockgating)
346{
347 void __iomem *ioaddr = hw->pcsr;
348 u32 value;
349
350 /*TODO - en_tx_lpi_clockgating treatment */
351
352 /* Enable the link status receive on RGMII, SGMII ore SMII
353 * receive path and instruct the transmit to enter in LPI
354 * state.
355 */
356 value = readl(ioaddr + LPI_CTRL_STATUS);
357 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
358 writel(value, ioaddr + LPI_CTRL_STATUS);
359}
360
361static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
362{
363 void __iomem *ioaddr = hw->pcsr;
364 u32 value;
365
366 value = readl(ioaddr + LPI_CTRL_STATUS);
367 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
368 writel(value, ioaddr + LPI_CTRL_STATUS);
369}
370
371static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
372{
373 void __iomem *ioaddr = hw->pcsr;
374 u32 value;
375
376 value = readl(ioaddr + LPI_CTRL_STATUS);
377
378 if (link)
379 value |= LPI_CTRL_STATUS_PLS;
380 else
381 value &= ~LPI_CTRL_STATUS_PLS;
382
383 writel(value, ioaddr + LPI_CTRL_STATUS);
384}
385
386static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
387{
388 void __iomem *ioaddr = hw->pcsr;
389 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
390
391 /* Program the timers in the LPI timer control register:
392 * LS: minimum time (ms) for which the link
393 * status from PHY should be ok before transmitting
394 * the LPI pattern.
395 * TW: minimum time (us) for which the core waits
396 * after it has stopped transmitting the LPI pattern.
397 */
398 writel(value, ioaddr + LPI_TIMER_CTRL);
399}
400
401static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
402 bool loopback)
403{
404 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
405}
406
407static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
408{
409 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
410}
411
412static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
413{
414 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
415}
416
417static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr,
418 struct stmmac_extra_stats *x,
419 u32 rx_queues, u32 tx_queues)
420{
421 u32 value = readl(ioaddr + GMAC_DEBUG);
422
423 if (value & GMAC_DEBUG_TXSTSFSTS)
424 x->mtl_tx_status_fifo_full++;
425 if (value & GMAC_DEBUG_TXFSTS)
426 x->mtl_tx_fifo_not_empty++;
427 if (value & GMAC_DEBUG_TWCSTS)
428 x->mmtl_fifo_ctrl++;
429 if (value & GMAC_DEBUG_TRCSTS_MASK) {
430 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
431 >> GMAC_DEBUG_TRCSTS_SHIFT;
432 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
433 x->mtl_tx_fifo_read_ctrl_write++;
434 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
435 x->mtl_tx_fifo_read_ctrl_wait++;
436 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
437 x->mtl_tx_fifo_read_ctrl_read++;
438 else
439 x->mtl_tx_fifo_read_ctrl_idle++;
440 }
441 if (value & GMAC_DEBUG_TXPAUSED)
442 x->mac_tx_in_pause++;
443 if (value & GMAC_DEBUG_TFCSTS_MASK) {
444 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
445 >> GMAC_DEBUG_TFCSTS_SHIFT;
446
447 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
448 x->mac_tx_frame_ctrl_xfer++;
449 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
450 x->mac_tx_frame_ctrl_pause++;
451 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
452 x->mac_tx_frame_ctrl_wait++;
453 else
454 x->mac_tx_frame_ctrl_idle++;
455 }
456 if (value & GMAC_DEBUG_TPESTS)
457 x->mac_gmii_tx_proto_engine++;
458 if (value & GMAC_DEBUG_RXFSTS_MASK) {
459 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
460 >> GMAC_DEBUG_RRCSTS_SHIFT;
461
462 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
463 x->mtl_rx_fifo_fill_level_full++;
464 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
465 x->mtl_rx_fifo_fill_above_thresh++;
466 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
467 x->mtl_rx_fifo_fill_below_thresh++;
468 else
469 x->mtl_rx_fifo_fill_level_empty++;
470 }
471 if (value & GMAC_DEBUG_RRCSTS_MASK) {
472 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
473 GMAC_DEBUG_RRCSTS_SHIFT;
474
475 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
476 x->mtl_rx_fifo_read_ctrl_flush++;
477 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
478 x->mtl_rx_fifo_read_ctrl_read_data++;
479 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
480 x->mtl_rx_fifo_read_ctrl_status++;
481 else
482 x->mtl_rx_fifo_read_ctrl_idle++;
483 }
484 if (value & GMAC_DEBUG_RWCSTS)
485 x->mtl_rx_fifo_ctrl_active++;
486 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
487 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
488 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
489 if (value & GMAC_DEBUG_RPESTS)
490 x->mac_gmii_rx_proto_engine++;
491}
492
493static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
494{
495 u32 value = readl(ioaddr + GMAC_CONTROL);
496
497 if (enable)
498 value |= GMAC_CONTROL_LM;
499 else
500 value &= ~GMAC_CONTROL_LM;
501
502 writel(value, ioaddr + GMAC_CONTROL);
503}
504
505const struct stmmac_ops dwmac1000_ops = {
506 .core_init = dwmac1000_core_init,
507 .set_mac = stmmac_set_mac,
508 .rx_ipc = dwmac1000_rx_ipc_enable,
509 .dump_regs = dwmac1000_dump_regs,
510 .host_irq_status = dwmac1000_irq_status,
511 .set_filter = dwmac1000_set_filter,
512 .flow_ctrl = dwmac1000_flow_ctrl,
513 .pmt = dwmac1000_pmt,
514 .set_umac_addr = dwmac1000_set_umac_addr,
515 .get_umac_addr = dwmac1000_get_umac_addr,
516 .set_eee_mode = dwmac1000_set_eee_mode,
517 .reset_eee_mode = dwmac1000_reset_eee_mode,
518 .set_eee_timer = dwmac1000_set_eee_timer,
519 .set_eee_pls = dwmac1000_set_eee_pls,
520 .debug = dwmac1000_debug,
521 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
522 .pcs_rane = dwmac1000_rane,
523 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
524 .set_mac_loopback = dwmac1000_set_mac_loopback,
525};
526
527int dwmac1000_setup(struct stmmac_priv *priv)
528{
529 struct mac_device_info *mac = priv->hw;
530
531 dev_info(priv->device, "\tDWMAC1000\n");
532
533 priv->dev->priv_flags |= IFF_UNICAST_FLT;
534 mac->pcsr = priv->ioaddr;
535 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
536 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
537 mac->mcast_bits_log2 = 0;
538
539 if (mac->multicast_filter_bins)
540 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
541
542 mac->link.duplex = GMAC_CONTROL_DM;
543 mac->link.speed10 = GMAC_CONTROL_PS;
544 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
545 mac->link.speed1000 = 0;
546 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
547 mac->mii.addr = GMAC_MII_ADDR;
548 mac->mii.data = GMAC_MII_DATA;
549 mac->mii.addr_shift = 11;
550 mac->mii.addr_mask = 0x0000F800;
551 mac->mii.reg_shift = 6;
552 mac->mii.reg_mask = 0x000007C0;
553 mac->mii.clk_csr_shift = 2;
554 mac->mii.clk_csr_mask = GENMASK(5, 2);
555
556 return 0;
557}