Loading...
1// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2/*
3 * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
4 * Copyright (c) 2014, I2SE GmbH
5 */
6
7/* This module implements the Qualcomm Atheros SPI protocol for
8 * kernel-based SPI device; it is essentially an Ethernet-to-SPI
9 * serial converter;
10 */
11
12#include <linux/errno.h>
13#include <linux/etherdevice.h>
14#include <linux/if_arp.h>
15#include <linux/if_ether.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/jiffies.h>
19#include <linux/kernel.h>
20#include <linux/kthread.h>
21#include <linux/module.h>
22#include <linux/moduleparam.h>
23#include <linux/netdevice.h>
24#include <linux/of.h>
25#include <linux/of_net.h>
26#include <linux/sched.h>
27#include <linux/skbuff.h>
28#include <linux/spi/spi.h>
29#include <linux/types.h>
30
31#include "qca_7k.h"
32#include "qca_7k_common.h"
33#include "qca_debug.h"
34#include "qca_spi.h"
35
36#define MAX_DMA_BURST_LEN 5000
37
38#define SPI_INTR 0
39#define SPI_RESET 1
40
41/* Modules parameters */
42#define QCASPI_CLK_SPEED_MIN 1000000
43#define QCASPI_CLK_SPEED_MAX 16000000
44#define QCASPI_CLK_SPEED 8000000
45static int qcaspi_clkspeed;
46module_param(qcaspi_clkspeed, int, 0);
47MODULE_PARM_DESC(qcaspi_clkspeed, "SPI bus clock speed (Hz). Use 1000000-16000000.");
48
49#define QCASPI_BURST_LEN_MIN 1
50#define QCASPI_BURST_LEN_MAX MAX_DMA_BURST_LEN
51static int qcaspi_burst_len = MAX_DMA_BURST_LEN;
52module_param(qcaspi_burst_len, int, 0);
53MODULE_PARM_DESC(qcaspi_burst_len, "Number of data bytes per burst. Use 1-5000.");
54
55#define QCASPI_PLUGGABLE_MIN 0
56#define QCASPI_PLUGGABLE_MAX 1
57static int qcaspi_pluggable = QCASPI_PLUGGABLE_MAX;
58module_param(qcaspi_pluggable, int, 0);
59MODULE_PARM_DESC(qcaspi_pluggable, "Pluggable SPI connection (yes/no).");
60
61#define QCASPI_WRITE_VERIFY_MIN 0
62#define QCASPI_WRITE_VERIFY_MAX 3
63static int wr_verify = QCASPI_WRITE_VERIFY_MIN;
64module_param(wr_verify, int, 0);
65MODULE_PARM_DESC(wr_verify, "SPI register write verify trails. Use 0-3.");
66
67#define QCASPI_TX_TIMEOUT (1 * HZ)
68#define QCASPI_QCA7K_REBOOT_TIME_MS 1000
69
70static void
71start_spi_intr_handling(struct qcaspi *qca, u16 *intr_cause)
72{
73 *intr_cause = 0;
74
75 qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0, wr_verify);
76 qcaspi_read_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
77 netdev_dbg(qca->net_dev, "interrupts: 0x%04x\n", *intr_cause);
78}
79
80static void
81end_spi_intr_handling(struct qcaspi *qca, u16 intr_cause)
82{
83 u16 intr_enable = (SPI_INT_CPU_ON |
84 SPI_INT_PKT_AVLBL |
85 SPI_INT_RDBUF_ERR |
86 SPI_INT_WRBUF_ERR);
87
88 qcaspi_write_register(qca, SPI_REG_INTR_CAUSE, intr_cause, 0);
89 qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, intr_enable, wr_verify);
90 netdev_dbg(qca->net_dev, "acking int: 0x%04x\n", intr_cause);
91}
92
93static u32
94qcaspi_write_burst(struct qcaspi *qca, u8 *src, u32 len)
95{
96 __be16 cmd;
97 struct spi_message msg;
98 struct spi_transfer transfer[2];
99 int ret;
100
101 memset(&transfer, 0, sizeof(transfer));
102 spi_message_init(&msg);
103
104 cmd = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
105 transfer[0].tx_buf = &cmd;
106 transfer[0].len = QCASPI_CMD_LEN;
107 transfer[1].tx_buf = src;
108 transfer[1].len = len;
109
110 spi_message_add_tail(&transfer[0], &msg);
111 spi_message_add_tail(&transfer[1], &msg);
112 ret = spi_sync(qca->spi_dev, &msg);
113
114 if (ret || (msg.actual_length != QCASPI_CMD_LEN + len)) {
115 qcaspi_spi_error(qca);
116 return 0;
117 }
118
119 return len;
120}
121
122static u32
123qcaspi_write_legacy(struct qcaspi *qca, u8 *src, u32 len)
124{
125 struct spi_message msg;
126 struct spi_transfer transfer;
127 int ret;
128
129 memset(&transfer, 0, sizeof(transfer));
130 spi_message_init(&msg);
131
132 transfer.tx_buf = src;
133 transfer.len = len;
134
135 spi_message_add_tail(&transfer, &msg);
136 ret = spi_sync(qca->spi_dev, &msg);
137
138 if (ret || (msg.actual_length != len)) {
139 qcaspi_spi_error(qca);
140 return 0;
141 }
142
143 return len;
144}
145
146static u32
147qcaspi_read_burst(struct qcaspi *qca, u8 *dst, u32 len)
148{
149 struct spi_message msg;
150 __be16 cmd;
151 struct spi_transfer transfer[2];
152 int ret;
153
154 memset(&transfer, 0, sizeof(transfer));
155 spi_message_init(&msg);
156
157 cmd = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
158 transfer[0].tx_buf = &cmd;
159 transfer[0].len = QCASPI_CMD_LEN;
160 transfer[1].rx_buf = dst;
161 transfer[1].len = len;
162
163 spi_message_add_tail(&transfer[0], &msg);
164 spi_message_add_tail(&transfer[1], &msg);
165 ret = spi_sync(qca->spi_dev, &msg);
166
167 if (ret || (msg.actual_length != QCASPI_CMD_LEN + len)) {
168 qcaspi_spi_error(qca);
169 return 0;
170 }
171
172 return len;
173}
174
175static u32
176qcaspi_read_legacy(struct qcaspi *qca, u8 *dst, u32 len)
177{
178 struct spi_message msg;
179 struct spi_transfer transfer;
180 int ret;
181
182 memset(&transfer, 0, sizeof(transfer));
183 spi_message_init(&msg);
184
185 transfer.rx_buf = dst;
186 transfer.len = len;
187
188 spi_message_add_tail(&transfer, &msg);
189 ret = spi_sync(qca->spi_dev, &msg);
190
191 if (ret || (msg.actual_length != len)) {
192 qcaspi_spi_error(qca);
193 return 0;
194 }
195
196 return len;
197}
198
199static int
200qcaspi_tx_cmd(struct qcaspi *qca, u16 cmd)
201{
202 __be16 tx_data;
203 struct spi_message msg;
204 struct spi_transfer transfer;
205 int ret;
206
207 memset(&transfer, 0, sizeof(transfer));
208
209 spi_message_init(&msg);
210
211 tx_data = cpu_to_be16(cmd);
212 transfer.len = sizeof(cmd);
213 transfer.tx_buf = &tx_data;
214 spi_message_add_tail(&transfer, &msg);
215
216 ret = spi_sync(qca->spi_dev, &msg);
217
218 if (!ret)
219 ret = msg.status;
220
221 if (ret)
222 qcaspi_spi_error(qca);
223
224 return ret;
225}
226
227static int
228qcaspi_tx_frame(struct qcaspi *qca, struct sk_buff *skb)
229{
230 u32 count;
231 u32 written;
232 u32 offset;
233 u32 len;
234
235 len = skb->len;
236
237 qcaspi_write_register(qca, SPI_REG_BFR_SIZE, len, wr_verify);
238 if (qca->legacy_mode)
239 qcaspi_tx_cmd(qca, QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
240
241 offset = 0;
242 while (len) {
243 count = len;
244 if (count > qca->burst_len)
245 count = qca->burst_len;
246
247 if (qca->legacy_mode) {
248 written = qcaspi_write_legacy(qca,
249 skb->data + offset,
250 count);
251 } else {
252 written = qcaspi_write_burst(qca,
253 skb->data + offset,
254 count);
255 }
256
257 if (written != count)
258 return -1;
259
260 offset += count;
261 len -= count;
262 }
263
264 return 0;
265}
266
267static int
268qcaspi_transmit(struct qcaspi *qca)
269{
270 struct net_device_stats *n_stats = &qca->net_dev->stats;
271 u16 available = 0;
272 u32 pkt_len;
273 u16 new_head;
274 u16 packets = 0;
275
276 if (qca->txr.skb[qca->txr.head] == NULL)
277 return 0;
278
279 qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, &available);
280
281 if (available > QCASPI_HW_BUF_LEN) {
282 /* This could only happen by interferences on the SPI line.
283 * So retry later ...
284 */
285 qca->stats.buf_avail_err++;
286 return -1;
287 }
288
289 while (qca->txr.skb[qca->txr.head]) {
290 pkt_len = qca->txr.skb[qca->txr.head]->len + QCASPI_HW_PKT_LEN;
291
292 if (available < pkt_len) {
293 if (packets == 0)
294 qca->stats.write_buf_miss++;
295 break;
296 }
297
298 if (qcaspi_tx_frame(qca, qca->txr.skb[qca->txr.head]) == -1) {
299 qca->stats.write_err++;
300 return -1;
301 }
302
303 packets++;
304 n_stats->tx_packets++;
305 n_stats->tx_bytes += qca->txr.skb[qca->txr.head]->len;
306 available -= pkt_len;
307
308 /* remove the skb from the queue */
309 /* XXX After inconsistent lock states netif_tx_lock()
310 * has been replaced by netif_tx_lock_bh() and so on.
311 */
312 netif_tx_lock_bh(qca->net_dev);
313 dev_kfree_skb(qca->txr.skb[qca->txr.head]);
314 qca->txr.skb[qca->txr.head] = NULL;
315 qca->txr.size -= pkt_len;
316 new_head = qca->txr.head + 1;
317 if (new_head >= qca->txr.count)
318 new_head = 0;
319 qca->txr.head = new_head;
320 if (netif_queue_stopped(qca->net_dev))
321 netif_wake_queue(qca->net_dev);
322 netif_tx_unlock_bh(qca->net_dev);
323 }
324
325 return 0;
326}
327
328static int
329qcaspi_receive(struct qcaspi *qca)
330{
331 struct net_device *net_dev = qca->net_dev;
332 struct net_device_stats *n_stats = &net_dev->stats;
333 u16 available = 0;
334 u32 bytes_read;
335 u8 *cp;
336
337 /* Allocate rx SKB if we don't have one available. */
338 if (!qca->rx_skb) {
339 qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
340 net_dev->mtu +
341 VLAN_ETH_HLEN);
342 if (!qca->rx_skb) {
343 netdev_dbg(net_dev, "out of RX resources\n");
344 qca->stats.out_of_mem++;
345 return -1;
346 }
347 }
348
349 /* Read the packet size. */
350 qcaspi_read_register(qca, SPI_REG_RDBUF_BYTE_AVA, &available);
351
352 netdev_dbg(net_dev, "qcaspi_receive: SPI_REG_RDBUF_BYTE_AVA: Value: %04x\n",
353 available);
354
355 if (available > QCASPI_HW_BUF_LEN + QCASPI_HW_PKT_LEN) {
356 /* This could only happen by interferences on the SPI line.
357 * So retry later ...
358 */
359 qca->stats.buf_avail_err++;
360 return -1;
361 } else if (available == 0) {
362 netdev_dbg(net_dev, "qcaspi_receive called without any data being available!\n");
363 return -1;
364 }
365
366 qcaspi_write_register(qca, SPI_REG_BFR_SIZE, available, wr_verify);
367
368 if (qca->legacy_mode)
369 qcaspi_tx_cmd(qca, QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
370
371 while (available) {
372 u32 count = available;
373
374 if (count > qca->burst_len)
375 count = qca->burst_len;
376
377 if (qca->legacy_mode) {
378 bytes_read = qcaspi_read_legacy(qca, qca->rx_buffer,
379 count);
380 } else {
381 bytes_read = qcaspi_read_burst(qca, qca->rx_buffer,
382 count);
383 }
384
385 netdev_dbg(net_dev, "available: %d, byte read: %d\n",
386 available, bytes_read);
387
388 if (bytes_read) {
389 available -= bytes_read;
390 } else {
391 qca->stats.read_err++;
392 return -1;
393 }
394
395 cp = qca->rx_buffer;
396
397 while ((bytes_read--) && (qca->rx_skb)) {
398 s32 retcode;
399
400 retcode = qcafrm_fsm_decode(&qca->frm_handle,
401 qca->rx_skb->data,
402 skb_tailroom(qca->rx_skb),
403 *cp);
404 cp++;
405 switch (retcode) {
406 case QCAFRM_GATHER:
407 case QCAFRM_NOHEAD:
408 break;
409 case QCAFRM_NOTAIL:
410 netdev_dbg(net_dev, "no RX tail\n");
411 n_stats->rx_errors++;
412 n_stats->rx_dropped++;
413 break;
414 case QCAFRM_INVLEN:
415 netdev_dbg(net_dev, "invalid RX length\n");
416 n_stats->rx_errors++;
417 n_stats->rx_dropped++;
418 break;
419 default:
420 qca->rx_skb->dev = qca->net_dev;
421 n_stats->rx_packets++;
422 n_stats->rx_bytes += retcode;
423 skb_put(qca->rx_skb, retcode);
424 qca->rx_skb->protocol = eth_type_trans(
425 qca->rx_skb, qca->rx_skb->dev);
426 skb_checksum_none_assert(qca->rx_skb);
427 netif_rx(qca->rx_skb);
428 qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
429 net_dev->mtu + VLAN_ETH_HLEN);
430 if (!qca->rx_skb) {
431 netdev_dbg(net_dev, "out of RX resources\n");
432 n_stats->rx_errors++;
433 qca->stats.out_of_mem++;
434 break;
435 }
436 }
437 }
438 }
439
440 return 0;
441}
442
443/* Check that tx ring stores only so much bytes
444 * that fit into the internal QCA buffer.
445 */
446
447static int
448qcaspi_tx_ring_has_space(struct tx_ring *txr)
449{
450 if (txr->skb[txr->tail])
451 return 0;
452
453 return (txr->size + QCAFRM_MAX_LEN < QCASPI_HW_BUF_LEN) ? 1 : 0;
454}
455
456/* Flush the tx ring. This function is only safe to
457 * call from the qcaspi_spi_thread.
458 */
459
460static void
461qcaspi_flush_tx_ring(struct qcaspi *qca)
462{
463 int i;
464
465 /* XXX After inconsistent lock states netif_tx_lock()
466 * has been replaced by netif_tx_lock_bh() and so on.
467 */
468 netif_tx_lock_bh(qca->net_dev);
469 for (i = 0; i < QCASPI_TX_RING_MAX_LEN; i++) {
470 if (qca->txr.skb[i]) {
471 dev_kfree_skb(qca->txr.skb[i]);
472 qca->txr.skb[i] = NULL;
473 qca->net_dev->stats.tx_dropped++;
474 }
475 }
476 qca->txr.tail = 0;
477 qca->txr.head = 0;
478 qca->txr.size = 0;
479 netif_tx_unlock_bh(qca->net_dev);
480}
481
482static void
483qcaspi_qca7k_sync(struct qcaspi *qca, int event)
484{
485 u16 signature = 0;
486 u16 spi_config;
487 u16 wrbuf_space = 0;
488
489 if (event == QCASPI_EVENT_CPUON) {
490 /* Read signature twice, if not valid
491 * go back to unknown state.
492 */
493 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
494 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
495 if (signature != QCASPI_GOOD_SIGNATURE) {
496 if (qca->sync == QCASPI_SYNC_READY)
497 qca->stats.bad_signature++;
498
499 set_bit(SPI_RESET, &qca->flags);
500 netdev_dbg(qca->net_dev, "sync: got CPU on, but signature was invalid, restart\n");
501 return;
502 } else {
503 /* ensure that the WRBUF is empty */
504 qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA,
505 &wrbuf_space);
506 if (wrbuf_space != QCASPI_HW_BUF_LEN) {
507 netdev_dbg(qca->net_dev, "sync: got CPU on, but wrbuf not empty. reset!\n");
508 qca->sync = QCASPI_SYNC_UNKNOWN;
509 qca->stats.buf_avail_err++;
510 } else {
511 netdev_dbg(qca->net_dev, "sync: got CPU on, now in sync\n");
512 qca->sync = QCASPI_SYNC_READY;
513 return;
514 }
515 }
516 } else {
517 /* Handle reset only on QCASPI_EVENT_UPDATE */
518 if (test_and_clear_bit(SPI_RESET, &qca->flags))
519 qca->sync = QCASPI_SYNC_UNKNOWN;
520 }
521
522 switch (qca->sync) {
523 case QCASPI_SYNC_READY:
524 /* Check signature twice, if not valid go to unknown state. */
525 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
526 if (signature != QCASPI_GOOD_SIGNATURE)
527 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
528
529 if (signature != QCASPI_GOOD_SIGNATURE) {
530 set_bit(SPI_RESET, &qca->flags);
531 qca->stats.bad_signature++;
532 netdev_dbg(qca->net_dev, "sync: bad signature, restart\n");
533 /* don't reset right away */
534 return;
535 }
536 break;
537 case QCASPI_SYNC_UNKNOWN:
538 /* Read signature, if not valid stay in unknown state */
539 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
540 if (signature != QCASPI_GOOD_SIGNATURE) {
541 netdev_dbg(qca->net_dev, "sync: could not read signature to reset device, retry.\n");
542 return;
543 }
544
545 /* TODO: use GPIO to reset QCA7000 in legacy mode*/
546 netdev_dbg(qca->net_dev, "sync: resetting device.\n");
547 qcaspi_read_register(qca, SPI_REG_SPI_CONFIG, &spi_config);
548 spi_config |= QCASPI_SLAVE_RESET_BIT;
549 qcaspi_write_register(qca, SPI_REG_SPI_CONFIG, spi_config, 0);
550
551 qca->sync = QCASPI_SYNC_RESET;
552 qca->stats.trig_reset++;
553 qca->reset_count = 0;
554 break;
555 case QCASPI_SYNC_RESET:
556 qca->reset_count++;
557 netdev_dbg(qca->net_dev, "sync: waiting for CPU on, count %u.\n",
558 qca->reset_count);
559 if (qca->reset_count >= QCASPI_RESET_TIMEOUT) {
560 /* reset did not seem to take place, try again */
561 set_bit(SPI_RESET, &qca->flags);
562 qca->stats.reset_timeout++;
563 netdev_dbg(qca->net_dev, "sync: reset timeout, restarting process.\n");
564 }
565 break;
566 }
567}
568
569static int
570qcaspi_spi_thread(void *data)
571{
572 struct qcaspi *qca = data;
573 u16 intr_cause = 0;
574
575 netdev_info(qca->net_dev, "SPI thread created\n");
576 while (!kthread_should_stop()) {
577 set_current_state(TASK_INTERRUPTIBLE);
578 if (kthread_should_park()) {
579 netif_tx_disable(qca->net_dev);
580 netif_carrier_off(qca->net_dev);
581 qcaspi_flush_tx_ring(qca);
582 kthread_parkme();
583 if (qca->sync == QCASPI_SYNC_READY) {
584 netif_carrier_on(qca->net_dev);
585 netif_wake_queue(qca->net_dev);
586 }
587 continue;
588 }
589
590 if (!qca->flags &&
591 !qca->txr.skb[qca->txr.head])
592 schedule();
593
594 set_current_state(TASK_RUNNING);
595
596 netdev_dbg(qca->net_dev, "have work to do. int: %lu, tx_skb: %p\n",
597 qca->flags,
598 qca->txr.skb[qca->txr.head]);
599
600 qcaspi_qca7k_sync(qca, QCASPI_EVENT_UPDATE);
601
602 if (qca->sync != QCASPI_SYNC_READY) {
603 netdev_dbg(qca->net_dev, "sync: not ready %u, turn off carrier and flush\n",
604 (unsigned int)qca->sync);
605 netif_stop_queue(qca->net_dev);
606 netif_carrier_off(qca->net_dev);
607 qcaspi_flush_tx_ring(qca);
608 msleep(QCASPI_QCA7K_REBOOT_TIME_MS);
609 }
610
611 if (test_and_clear_bit(SPI_INTR, &qca->flags)) {
612 start_spi_intr_handling(qca, &intr_cause);
613
614 if (intr_cause & SPI_INT_CPU_ON) {
615 qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON);
616
617 /* Frame decoding in progress */
618 if (qca->frm_handle.state != qca->frm_handle.init)
619 qca->net_dev->stats.rx_dropped++;
620
621 qcafrm_fsm_init_spi(&qca->frm_handle);
622 qca->stats.device_reset++;
623
624 /* not synced. */
625 if (qca->sync != QCASPI_SYNC_READY)
626 continue;
627
628 netif_wake_queue(qca->net_dev);
629 netif_carrier_on(qca->net_dev);
630 }
631
632 if (intr_cause & SPI_INT_RDBUF_ERR) {
633 /* restart sync */
634 netdev_dbg(qca->net_dev, "===> rdbuf error!\n");
635 qca->stats.read_buf_err++;
636 set_bit(SPI_RESET, &qca->flags);
637 continue;
638 }
639
640 if (intr_cause & SPI_INT_WRBUF_ERR) {
641 /* restart sync */
642 netdev_dbg(qca->net_dev, "===> wrbuf error!\n");
643 qca->stats.write_buf_err++;
644 set_bit(SPI_RESET, &qca->flags);
645 continue;
646 }
647
648 /* can only handle other interrupts
649 * if sync has occurred
650 */
651 if (qca->sync == QCASPI_SYNC_READY) {
652 if (intr_cause & SPI_INT_PKT_AVLBL)
653 qcaspi_receive(qca);
654 }
655
656 end_spi_intr_handling(qca, intr_cause);
657 }
658
659 if (qca->sync == QCASPI_SYNC_READY)
660 qcaspi_transmit(qca);
661 }
662 set_current_state(TASK_RUNNING);
663 netdev_info(qca->net_dev, "SPI thread exit\n");
664
665 return 0;
666}
667
668static irqreturn_t
669qcaspi_intr_handler(int irq, void *data)
670{
671 struct qcaspi *qca = data;
672
673 set_bit(SPI_INTR, &qca->flags);
674 if (qca->spi_thread)
675 wake_up_process(qca->spi_thread);
676
677 return IRQ_HANDLED;
678}
679
680static int
681qcaspi_netdev_open(struct net_device *dev)
682{
683 struct qcaspi *qca = netdev_priv(dev);
684 struct task_struct *thread;
685
686 if (!qca)
687 return -EINVAL;
688
689 set_bit(SPI_INTR, &qca->flags);
690 qca->sync = QCASPI_SYNC_UNKNOWN;
691 qcafrm_fsm_init_spi(&qca->frm_handle);
692
693 thread = kthread_run((void *)qcaspi_spi_thread,
694 qca, "%s", dev->name);
695
696 if (IS_ERR(thread)) {
697 netdev_err(dev, "%s: unable to start kernel thread.\n",
698 QCASPI_DRV_NAME);
699 return PTR_ERR(thread);
700 }
701
702 qca->spi_thread = thread;
703
704 enable_irq(qca->spi_dev->irq);
705
706 /* SPI thread takes care of TX queue */
707
708 return 0;
709}
710
711static int
712qcaspi_netdev_close(struct net_device *dev)
713{
714 struct qcaspi *qca = netdev_priv(dev);
715
716 netif_stop_queue(dev);
717
718 qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0, wr_verify);
719 disable_irq(qca->spi_dev->irq);
720
721 if (qca->spi_thread) {
722 kthread_stop(qca->spi_thread);
723 qca->spi_thread = NULL;
724 }
725 qcaspi_flush_tx_ring(qca);
726
727 return 0;
728}
729
730static netdev_tx_t
731qcaspi_netdev_xmit(struct sk_buff *skb, struct net_device *dev)
732{
733 u32 frame_len;
734 u8 *ptmp;
735 struct qcaspi *qca = netdev_priv(dev);
736 u16 new_tail;
737 struct sk_buff *tskb;
738 u8 pad_len = 0;
739
740 if (skb->len < QCAFRM_MIN_LEN)
741 pad_len = QCAFRM_MIN_LEN - skb->len;
742
743 if (qca->txr.skb[qca->txr.tail]) {
744 netdev_warn(qca->net_dev, "queue was unexpectedly full!\n");
745 netif_stop_queue(qca->net_dev);
746 qca->stats.ring_full++;
747 return NETDEV_TX_BUSY;
748 }
749
750 if ((skb_headroom(skb) < QCAFRM_HEADER_LEN) ||
751 (skb_tailroom(skb) < QCAFRM_FOOTER_LEN + pad_len)) {
752 tskb = skb_copy_expand(skb, QCAFRM_HEADER_LEN,
753 QCAFRM_FOOTER_LEN + pad_len, GFP_ATOMIC);
754 if (!tskb) {
755 qca->stats.out_of_mem++;
756 return NETDEV_TX_BUSY;
757 }
758 dev_kfree_skb(skb);
759 skb = tskb;
760 }
761
762 frame_len = skb->len + pad_len;
763
764 ptmp = skb_push(skb, QCAFRM_HEADER_LEN);
765 qcafrm_create_header(ptmp, frame_len);
766
767 if (pad_len) {
768 ptmp = skb_put_zero(skb, pad_len);
769 }
770
771 ptmp = skb_put(skb, QCAFRM_FOOTER_LEN);
772 qcafrm_create_footer(ptmp);
773
774 netdev_dbg(qca->net_dev, "Tx-ing packet: Size: 0x%08x\n",
775 skb->len);
776
777 qca->txr.size += skb->len + QCASPI_HW_PKT_LEN;
778
779 new_tail = qca->txr.tail + 1;
780 if (new_tail >= qca->txr.count)
781 new_tail = 0;
782
783 qca->txr.skb[qca->txr.tail] = skb;
784 qca->txr.tail = new_tail;
785
786 if (!qcaspi_tx_ring_has_space(&qca->txr)) {
787 netif_stop_queue(qca->net_dev);
788 qca->stats.ring_full++;
789 }
790
791 netif_trans_update(dev);
792
793 if (qca->spi_thread)
794 wake_up_process(qca->spi_thread);
795
796 return NETDEV_TX_OK;
797}
798
799static void
800qcaspi_netdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
801{
802 struct qcaspi *qca = netdev_priv(dev);
803
804 netdev_info(qca->net_dev, "Transmit timeout at %ld, latency %ld\n",
805 jiffies, jiffies - dev_trans_start(dev));
806 qca->net_dev->stats.tx_errors++;
807 /* Trigger tx queue flush and QCA7000 reset */
808 set_bit(SPI_RESET, &qca->flags);
809
810 if (qca->spi_thread)
811 wake_up_process(qca->spi_thread);
812}
813
814static int
815qcaspi_netdev_init(struct net_device *dev)
816{
817 struct qcaspi *qca = netdev_priv(dev);
818
819 dev->mtu = QCAFRM_MAX_MTU;
820 dev->type = ARPHRD_ETHER;
821 qca->burst_len = qcaspi_burst_len;
822 qca->spi_thread = NULL;
823 qca->buffer_size = (QCAFRM_MAX_MTU + VLAN_ETH_HLEN + QCAFRM_HEADER_LEN +
824 QCAFRM_FOOTER_LEN + QCASPI_HW_PKT_LEN) * QCASPI_RX_MAX_FRAMES;
825
826 memset(&qca->stats, 0, sizeof(struct qcaspi_stats));
827
828 qca->rx_buffer = kmalloc(qca->buffer_size, GFP_KERNEL);
829 if (!qca->rx_buffer)
830 return -ENOBUFS;
831
832 qca->rx_skb = netdev_alloc_skb_ip_align(dev, qca->net_dev->mtu +
833 VLAN_ETH_HLEN);
834 if (!qca->rx_skb) {
835 kfree(qca->rx_buffer);
836 netdev_info(qca->net_dev, "Failed to allocate RX sk_buff.\n");
837 return -ENOBUFS;
838 }
839
840 return 0;
841}
842
843static void
844qcaspi_netdev_uninit(struct net_device *dev)
845{
846 struct qcaspi *qca = netdev_priv(dev);
847
848 kfree(qca->rx_buffer);
849 qca->buffer_size = 0;
850 dev_kfree_skb(qca->rx_skb);
851}
852
853static const struct net_device_ops qcaspi_netdev_ops = {
854 .ndo_init = qcaspi_netdev_init,
855 .ndo_uninit = qcaspi_netdev_uninit,
856 .ndo_open = qcaspi_netdev_open,
857 .ndo_stop = qcaspi_netdev_close,
858 .ndo_start_xmit = qcaspi_netdev_xmit,
859 .ndo_set_mac_address = eth_mac_addr,
860 .ndo_tx_timeout = qcaspi_netdev_tx_timeout,
861 .ndo_validate_addr = eth_validate_addr,
862};
863
864static void
865qcaspi_netdev_setup(struct net_device *dev)
866{
867 struct qcaspi *qca = NULL;
868
869 dev->netdev_ops = &qcaspi_netdev_ops;
870 qcaspi_set_ethtool_ops(dev);
871 dev->watchdog_timeo = QCASPI_TX_TIMEOUT;
872 dev->priv_flags &= ~IFF_TX_SKB_SHARING;
873 dev->needed_tailroom = ALIGN(QCAFRM_FOOTER_LEN + QCAFRM_MIN_LEN, 4);
874 dev->needed_headroom = ALIGN(QCAFRM_HEADER_LEN, 4);
875 dev->tx_queue_len = 100;
876
877 /* MTU range: 46 - 1500 */
878 dev->min_mtu = QCAFRM_MIN_MTU;
879 dev->max_mtu = QCAFRM_MAX_MTU;
880
881 qca = netdev_priv(dev);
882 memset(qca, 0, sizeof(struct qcaspi));
883
884 memset(&qca->txr, 0, sizeof(qca->txr));
885 qca->txr.count = QCASPI_TX_RING_MAX_LEN;
886}
887
888static const struct of_device_id qca_spi_of_match[] = {
889 { .compatible = "qca,qca7000" },
890 { /* sentinel */ }
891};
892MODULE_DEVICE_TABLE(of, qca_spi_of_match);
893
894static int
895qca_spi_probe(struct spi_device *spi)
896{
897 struct qcaspi *qca = NULL;
898 struct net_device *qcaspi_devs = NULL;
899 u8 legacy_mode = 0;
900 u16 signature;
901 int ret;
902
903 if (!spi->dev.of_node) {
904 dev_err(&spi->dev, "Missing device tree\n");
905 return -EINVAL;
906 }
907
908 legacy_mode = of_property_read_bool(spi->dev.of_node,
909 "qca,legacy-mode");
910
911 if (qcaspi_clkspeed)
912 spi->max_speed_hz = qcaspi_clkspeed;
913 else if (!spi->max_speed_hz)
914 spi->max_speed_hz = QCASPI_CLK_SPEED;
915
916 if (spi->max_speed_hz < QCASPI_CLK_SPEED_MIN ||
917 spi->max_speed_hz > QCASPI_CLK_SPEED_MAX) {
918 dev_err(&spi->dev, "Invalid clkspeed: %u\n",
919 spi->max_speed_hz);
920 return -EINVAL;
921 }
922
923 if ((qcaspi_burst_len < QCASPI_BURST_LEN_MIN) ||
924 (qcaspi_burst_len > QCASPI_BURST_LEN_MAX)) {
925 dev_err(&spi->dev, "Invalid burst len: %d\n",
926 qcaspi_burst_len);
927 return -EINVAL;
928 }
929
930 if ((qcaspi_pluggable < QCASPI_PLUGGABLE_MIN) ||
931 (qcaspi_pluggable > QCASPI_PLUGGABLE_MAX)) {
932 dev_err(&spi->dev, "Invalid pluggable: %d\n",
933 qcaspi_pluggable);
934 return -EINVAL;
935 }
936
937 if (wr_verify < QCASPI_WRITE_VERIFY_MIN ||
938 wr_verify > QCASPI_WRITE_VERIFY_MAX) {
939 dev_err(&spi->dev, "Invalid write verify: %d\n",
940 wr_verify);
941 return -EINVAL;
942 }
943
944 dev_info(&spi->dev, "ver=%s, clkspeed=%u, burst_len=%d, pluggable=%d\n",
945 QCASPI_DRV_VERSION,
946 spi->max_speed_hz,
947 qcaspi_burst_len,
948 qcaspi_pluggable);
949
950 spi->mode = SPI_MODE_3;
951 if (spi_setup(spi) < 0) {
952 dev_err(&spi->dev, "Unable to setup SPI device\n");
953 return -EFAULT;
954 }
955
956 qcaspi_devs = alloc_etherdev(sizeof(struct qcaspi));
957 if (!qcaspi_devs)
958 return -ENOMEM;
959
960 qcaspi_netdev_setup(qcaspi_devs);
961 SET_NETDEV_DEV(qcaspi_devs, &spi->dev);
962
963 qca = netdev_priv(qcaspi_devs);
964 if (!qca) {
965 free_netdev(qcaspi_devs);
966 dev_err(&spi->dev, "Fail to retrieve private structure\n");
967 return -ENOMEM;
968 }
969 qca->net_dev = qcaspi_devs;
970 qca->spi_dev = spi;
971 qca->legacy_mode = legacy_mode;
972
973 spi_set_drvdata(spi, qcaspi_devs);
974
975 ret = devm_request_irq(&spi->dev, spi->irq, qcaspi_intr_handler,
976 IRQF_NO_AUTOEN, qca->net_dev->name, qca);
977 if (ret) {
978 dev_err(&spi->dev, "Unable to get IRQ %d (irqval=%d).\n",
979 spi->irq, ret);
980 free_netdev(qcaspi_devs);
981 return ret;
982 }
983
984 ret = of_get_ethdev_address(spi->dev.of_node, qca->net_dev);
985 if (ret) {
986 eth_hw_addr_random(qca->net_dev);
987 dev_info(&spi->dev, "Using random MAC address: %pM\n",
988 qca->net_dev->dev_addr);
989 }
990
991 netif_carrier_off(qca->net_dev);
992
993 if (!qcaspi_pluggable) {
994 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
995 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
996
997 if (signature != QCASPI_GOOD_SIGNATURE) {
998 dev_err(&spi->dev, "Invalid signature (expected 0x%04x, read 0x%04x)\n",
999 QCASPI_GOOD_SIGNATURE, signature);
1000 free_netdev(qcaspi_devs);
1001 return -EFAULT;
1002 }
1003 }
1004
1005 if (register_netdev(qcaspi_devs)) {
1006 dev_err(&spi->dev, "Unable to register net device %s\n",
1007 qcaspi_devs->name);
1008 free_netdev(qcaspi_devs);
1009 return -EFAULT;
1010 }
1011
1012 qcaspi_init_device_debugfs(qca);
1013
1014 return 0;
1015}
1016
1017static void
1018qca_spi_remove(struct spi_device *spi)
1019{
1020 struct net_device *qcaspi_devs = spi_get_drvdata(spi);
1021 struct qcaspi *qca = netdev_priv(qcaspi_devs);
1022
1023 qcaspi_remove_device_debugfs(qca);
1024
1025 unregister_netdev(qcaspi_devs);
1026 free_netdev(qcaspi_devs);
1027}
1028
1029static const struct spi_device_id qca_spi_id[] = {
1030 { "qca7000", 0 },
1031 { /* sentinel */ }
1032};
1033MODULE_DEVICE_TABLE(spi, qca_spi_id);
1034
1035static struct spi_driver qca_spi_driver = {
1036 .driver = {
1037 .name = QCASPI_DRV_NAME,
1038 .of_match_table = qca_spi_of_match,
1039 },
1040 .id_table = qca_spi_id,
1041 .probe = qca_spi_probe,
1042 .remove = qca_spi_remove,
1043};
1044module_spi_driver(qca_spi_driver);
1045
1046MODULE_DESCRIPTION("Qualcomm Atheros QCA7000 SPI Driver");
1047MODULE_AUTHOR("Qualcomm Atheros Communications");
1048MODULE_AUTHOR("Stefan Wahren <wahrenst@gmx.net>");
1049MODULE_LICENSE("Dual BSD/GPL");
1050MODULE_VERSION(QCASPI_DRV_VERSION);
1/*
2 * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
3 * Copyright (c) 2014, I2SE GmbH
4 *
5 * Permission to use, copy, modify, and/or distribute this software
6 * for any purpose with or without fee is hereby granted, provided
7 * that the above copyright notice and this permission notice appear
8 * in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
13 * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
14 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
15 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
16 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20/* This module implements the Qualcomm Atheros SPI protocol for
21 * kernel-based SPI device; it is essentially an Ethernet-to-SPI
22 * serial converter;
23 */
24
25#include <linux/errno.h>
26#include <linux/etherdevice.h>
27#include <linux/if_arp.h>
28#include <linux/if_ether.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/jiffies.h>
32#include <linux/kernel.h>
33#include <linux/kthread.h>
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/netdevice.h>
37#include <linux/of.h>
38#include <linux/of_net.h>
39#include <linux/sched.h>
40#include <linux/skbuff.h>
41#include <linux/spi/spi.h>
42#include <linux/types.h>
43
44#include "qca_7k.h"
45#include "qca_7k_common.h"
46#include "qca_debug.h"
47#include "qca_spi.h"
48
49#define MAX_DMA_BURST_LEN 5000
50
51/* Modules parameters */
52#define QCASPI_CLK_SPEED_MIN 1000000
53#define QCASPI_CLK_SPEED_MAX 16000000
54#define QCASPI_CLK_SPEED 8000000
55static int qcaspi_clkspeed;
56module_param(qcaspi_clkspeed, int, 0);
57MODULE_PARM_DESC(qcaspi_clkspeed, "SPI bus clock speed (Hz). Use 1000000-16000000.");
58
59#define QCASPI_BURST_LEN_MIN 1
60#define QCASPI_BURST_LEN_MAX MAX_DMA_BURST_LEN
61static int qcaspi_burst_len = MAX_DMA_BURST_LEN;
62module_param(qcaspi_burst_len, int, 0);
63MODULE_PARM_DESC(qcaspi_burst_len, "Number of data bytes per burst. Use 1-5000.");
64
65#define QCASPI_PLUGGABLE_MIN 0
66#define QCASPI_PLUGGABLE_MAX 1
67static int qcaspi_pluggable = QCASPI_PLUGGABLE_MIN;
68module_param(qcaspi_pluggable, int, 0);
69MODULE_PARM_DESC(qcaspi_pluggable, "Pluggable SPI connection (yes/no).");
70
71#define QCASPI_WRITE_VERIFY_MIN 0
72#define QCASPI_WRITE_VERIFY_MAX 3
73static int wr_verify = QCASPI_WRITE_VERIFY_MIN;
74module_param(wr_verify, int, 0);
75MODULE_PARM_DESC(wr_verify, "SPI register write verify trails. Use 0-3.");
76
77#define QCASPI_TX_TIMEOUT (1 * HZ)
78#define QCASPI_QCA7K_REBOOT_TIME_MS 1000
79
80static void
81start_spi_intr_handling(struct qcaspi *qca, u16 *intr_cause)
82{
83 *intr_cause = 0;
84
85 qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0, wr_verify);
86 qcaspi_read_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
87 netdev_dbg(qca->net_dev, "interrupts: 0x%04x\n", *intr_cause);
88}
89
90static void
91end_spi_intr_handling(struct qcaspi *qca, u16 intr_cause)
92{
93 u16 intr_enable = (SPI_INT_CPU_ON |
94 SPI_INT_PKT_AVLBL |
95 SPI_INT_RDBUF_ERR |
96 SPI_INT_WRBUF_ERR);
97
98 qcaspi_write_register(qca, SPI_REG_INTR_CAUSE, intr_cause, 0);
99 qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, intr_enable, wr_verify);
100 netdev_dbg(qca->net_dev, "acking int: 0x%04x\n", intr_cause);
101}
102
103static u32
104qcaspi_write_burst(struct qcaspi *qca, u8 *src, u32 len)
105{
106 __be16 cmd;
107 struct spi_message msg;
108 struct spi_transfer transfer[2];
109 int ret;
110
111 memset(&transfer, 0, sizeof(transfer));
112 spi_message_init(&msg);
113
114 cmd = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
115 transfer[0].tx_buf = &cmd;
116 transfer[0].len = QCASPI_CMD_LEN;
117 transfer[1].tx_buf = src;
118 transfer[1].len = len;
119
120 spi_message_add_tail(&transfer[0], &msg);
121 spi_message_add_tail(&transfer[1], &msg);
122 ret = spi_sync(qca->spi_dev, &msg);
123
124 if (ret || (msg.actual_length != QCASPI_CMD_LEN + len)) {
125 qcaspi_spi_error(qca);
126 return 0;
127 }
128
129 return len;
130}
131
132static u32
133qcaspi_write_legacy(struct qcaspi *qca, u8 *src, u32 len)
134{
135 struct spi_message msg;
136 struct spi_transfer transfer;
137 int ret;
138
139 memset(&transfer, 0, sizeof(transfer));
140 spi_message_init(&msg);
141
142 transfer.tx_buf = src;
143 transfer.len = len;
144
145 spi_message_add_tail(&transfer, &msg);
146 ret = spi_sync(qca->spi_dev, &msg);
147
148 if (ret || (msg.actual_length != len)) {
149 qcaspi_spi_error(qca);
150 return 0;
151 }
152
153 return len;
154}
155
156static u32
157qcaspi_read_burst(struct qcaspi *qca, u8 *dst, u32 len)
158{
159 struct spi_message msg;
160 __be16 cmd;
161 struct spi_transfer transfer[2];
162 int ret;
163
164 memset(&transfer, 0, sizeof(transfer));
165 spi_message_init(&msg);
166
167 cmd = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
168 transfer[0].tx_buf = &cmd;
169 transfer[0].len = QCASPI_CMD_LEN;
170 transfer[1].rx_buf = dst;
171 transfer[1].len = len;
172
173 spi_message_add_tail(&transfer[0], &msg);
174 spi_message_add_tail(&transfer[1], &msg);
175 ret = spi_sync(qca->spi_dev, &msg);
176
177 if (ret || (msg.actual_length != QCASPI_CMD_LEN + len)) {
178 qcaspi_spi_error(qca);
179 return 0;
180 }
181
182 return len;
183}
184
185static u32
186qcaspi_read_legacy(struct qcaspi *qca, u8 *dst, u32 len)
187{
188 struct spi_message msg;
189 struct spi_transfer transfer;
190 int ret;
191
192 memset(&transfer, 0, sizeof(transfer));
193 spi_message_init(&msg);
194
195 transfer.rx_buf = dst;
196 transfer.len = len;
197
198 spi_message_add_tail(&transfer, &msg);
199 ret = spi_sync(qca->spi_dev, &msg);
200
201 if (ret || (msg.actual_length != len)) {
202 qcaspi_spi_error(qca);
203 return 0;
204 }
205
206 return len;
207}
208
209static int
210qcaspi_tx_cmd(struct qcaspi *qca, u16 cmd)
211{
212 __be16 tx_data;
213 struct spi_message msg;
214 struct spi_transfer transfer;
215 int ret;
216
217 memset(&transfer, 0, sizeof(transfer));
218
219 spi_message_init(&msg);
220
221 tx_data = cpu_to_be16(cmd);
222 transfer.len = sizeof(cmd);
223 transfer.tx_buf = &tx_data;
224 spi_message_add_tail(&transfer, &msg);
225
226 ret = spi_sync(qca->spi_dev, &msg);
227
228 if (!ret)
229 ret = msg.status;
230
231 if (ret)
232 qcaspi_spi_error(qca);
233
234 return ret;
235}
236
237static int
238qcaspi_tx_frame(struct qcaspi *qca, struct sk_buff *skb)
239{
240 u32 count;
241 u32 written;
242 u32 offset;
243 u32 len;
244
245 len = skb->len;
246
247 qcaspi_write_register(qca, SPI_REG_BFR_SIZE, len, wr_verify);
248 if (qca->legacy_mode)
249 qcaspi_tx_cmd(qca, QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
250
251 offset = 0;
252 while (len) {
253 count = len;
254 if (count > qca->burst_len)
255 count = qca->burst_len;
256
257 if (qca->legacy_mode) {
258 written = qcaspi_write_legacy(qca,
259 skb->data + offset,
260 count);
261 } else {
262 written = qcaspi_write_burst(qca,
263 skb->data + offset,
264 count);
265 }
266
267 if (written != count)
268 return -1;
269
270 offset += count;
271 len -= count;
272 }
273
274 return 0;
275}
276
277static int
278qcaspi_transmit(struct qcaspi *qca)
279{
280 struct net_device_stats *n_stats = &qca->net_dev->stats;
281 u16 available = 0;
282 u32 pkt_len;
283 u16 new_head;
284 u16 packets = 0;
285
286 if (qca->txr.skb[qca->txr.head] == NULL)
287 return 0;
288
289 qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, &available);
290
291 if (available > QCASPI_HW_BUF_LEN) {
292 /* This could only happen by interferences on the SPI line.
293 * So retry later ...
294 */
295 qca->stats.buf_avail_err++;
296 return -1;
297 }
298
299 while (qca->txr.skb[qca->txr.head]) {
300 pkt_len = qca->txr.skb[qca->txr.head]->len + QCASPI_HW_PKT_LEN;
301
302 if (available < pkt_len) {
303 if (packets == 0)
304 qca->stats.write_buf_miss++;
305 break;
306 }
307
308 if (qcaspi_tx_frame(qca, qca->txr.skb[qca->txr.head]) == -1) {
309 qca->stats.write_err++;
310 return -1;
311 }
312
313 packets++;
314 n_stats->tx_packets++;
315 n_stats->tx_bytes += qca->txr.skb[qca->txr.head]->len;
316 available -= pkt_len;
317
318 /* remove the skb from the queue */
319 /* XXX After inconsistent lock states netif_tx_lock()
320 * has been replaced by netif_tx_lock_bh() and so on.
321 */
322 netif_tx_lock_bh(qca->net_dev);
323 dev_kfree_skb(qca->txr.skb[qca->txr.head]);
324 qca->txr.skb[qca->txr.head] = NULL;
325 qca->txr.size -= pkt_len;
326 new_head = qca->txr.head + 1;
327 if (new_head >= qca->txr.count)
328 new_head = 0;
329 qca->txr.head = new_head;
330 if (netif_queue_stopped(qca->net_dev))
331 netif_wake_queue(qca->net_dev);
332 netif_tx_unlock_bh(qca->net_dev);
333 }
334
335 return 0;
336}
337
338static int
339qcaspi_receive(struct qcaspi *qca)
340{
341 struct net_device *net_dev = qca->net_dev;
342 struct net_device_stats *n_stats = &net_dev->stats;
343 u16 available = 0;
344 u32 bytes_read;
345 u8 *cp;
346
347 /* Allocate rx SKB if we don't have one available. */
348 if (!qca->rx_skb) {
349 qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
350 net_dev->mtu +
351 VLAN_ETH_HLEN);
352 if (!qca->rx_skb) {
353 netdev_dbg(net_dev, "out of RX resources\n");
354 qca->stats.out_of_mem++;
355 return -1;
356 }
357 }
358
359 /* Read the packet size. */
360 qcaspi_read_register(qca, SPI_REG_RDBUF_BYTE_AVA, &available);
361
362 netdev_dbg(net_dev, "qcaspi_receive: SPI_REG_RDBUF_BYTE_AVA: Value: %08x\n",
363 available);
364
365 if (available > QCASPI_HW_BUF_LEN + QCASPI_HW_PKT_LEN) {
366 /* This could only happen by interferences on the SPI line.
367 * So retry later ...
368 */
369 qca->stats.buf_avail_err++;
370 return -1;
371 } else if (available == 0) {
372 netdev_dbg(net_dev, "qcaspi_receive called without any data being available!\n");
373 return -1;
374 }
375
376 qcaspi_write_register(qca, SPI_REG_BFR_SIZE, available, wr_verify);
377
378 if (qca->legacy_mode)
379 qcaspi_tx_cmd(qca, QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
380
381 while (available) {
382 u32 count = available;
383
384 if (count > qca->burst_len)
385 count = qca->burst_len;
386
387 if (qca->legacy_mode) {
388 bytes_read = qcaspi_read_legacy(qca, qca->rx_buffer,
389 count);
390 } else {
391 bytes_read = qcaspi_read_burst(qca, qca->rx_buffer,
392 count);
393 }
394
395 netdev_dbg(net_dev, "available: %d, byte read: %d\n",
396 available, bytes_read);
397
398 if (bytes_read) {
399 available -= bytes_read;
400 } else {
401 qca->stats.read_err++;
402 return -1;
403 }
404
405 cp = qca->rx_buffer;
406
407 while ((bytes_read--) && (qca->rx_skb)) {
408 s32 retcode;
409
410 retcode = qcafrm_fsm_decode(&qca->frm_handle,
411 qca->rx_skb->data,
412 skb_tailroom(qca->rx_skb),
413 *cp);
414 cp++;
415 switch (retcode) {
416 case QCAFRM_GATHER:
417 case QCAFRM_NOHEAD:
418 break;
419 case QCAFRM_NOTAIL:
420 netdev_dbg(net_dev, "no RX tail\n");
421 n_stats->rx_errors++;
422 n_stats->rx_dropped++;
423 break;
424 case QCAFRM_INVLEN:
425 netdev_dbg(net_dev, "invalid RX length\n");
426 n_stats->rx_errors++;
427 n_stats->rx_dropped++;
428 break;
429 default:
430 qca->rx_skb->dev = qca->net_dev;
431 n_stats->rx_packets++;
432 n_stats->rx_bytes += retcode;
433 skb_put(qca->rx_skb, retcode);
434 qca->rx_skb->protocol = eth_type_trans(
435 qca->rx_skb, qca->rx_skb->dev);
436 skb_checksum_none_assert(qca->rx_skb);
437 netif_rx(qca->rx_skb);
438 qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
439 net_dev->mtu + VLAN_ETH_HLEN);
440 if (!qca->rx_skb) {
441 netdev_dbg(net_dev, "out of RX resources\n");
442 n_stats->rx_errors++;
443 qca->stats.out_of_mem++;
444 break;
445 }
446 }
447 }
448 }
449
450 return 0;
451}
452
453/* Check that tx ring stores only so much bytes
454 * that fit into the internal QCA buffer.
455 */
456
457static int
458qcaspi_tx_ring_has_space(struct tx_ring *txr)
459{
460 if (txr->skb[txr->tail])
461 return 0;
462
463 return (txr->size + QCAFRM_MAX_LEN < QCASPI_HW_BUF_LEN) ? 1 : 0;
464}
465
466/* Flush the tx ring. This function is only safe to
467 * call from the qcaspi_spi_thread.
468 */
469
470static void
471qcaspi_flush_tx_ring(struct qcaspi *qca)
472{
473 int i;
474
475 /* XXX After inconsistent lock states netif_tx_lock()
476 * has been replaced by netif_tx_lock_bh() and so on.
477 */
478 netif_tx_lock_bh(qca->net_dev);
479 for (i = 0; i < TX_RING_MAX_LEN; i++) {
480 if (qca->txr.skb[i]) {
481 dev_kfree_skb(qca->txr.skb[i]);
482 qca->txr.skb[i] = NULL;
483 qca->net_dev->stats.tx_dropped++;
484 }
485 }
486 qca->txr.tail = 0;
487 qca->txr.head = 0;
488 qca->txr.size = 0;
489 netif_tx_unlock_bh(qca->net_dev);
490}
491
492static void
493qcaspi_qca7k_sync(struct qcaspi *qca, int event)
494{
495 u16 signature = 0;
496 u16 spi_config;
497 u16 wrbuf_space = 0;
498
499 if (event == QCASPI_EVENT_CPUON) {
500 /* Read signature twice, if not valid
501 * go back to unknown state.
502 */
503 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
504 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
505 if (signature != QCASPI_GOOD_SIGNATURE) {
506 if (qca->sync == QCASPI_SYNC_READY)
507 qca->stats.bad_signature++;
508
509 qca->sync = QCASPI_SYNC_UNKNOWN;
510 netdev_dbg(qca->net_dev, "sync: got CPU on, but signature was invalid, restart\n");
511 return;
512 } else {
513 /* ensure that the WRBUF is empty */
514 qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA,
515 &wrbuf_space);
516 if (wrbuf_space != QCASPI_HW_BUF_LEN) {
517 netdev_dbg(qca->net_dev, "sync: got CPU on, but wrbuf not empty. reset!\n");
518 qca->sync = QCASPI_SYNC_UNKNOWN;
519 } else {
520 netdev_dbg(qca->net_dev, "sync: got CPU on, now in sync\n");
521 qca->sync = QCASPI_SYNC_READY;
522 return;
523 }
524 }
525 }
526
527 switch (qca->sync) {
528 case QCASPI_SYNC_READY:
529 /* Check signature twice, if not valid go to unknown state. */
530 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
531 if (signature != QCASPI_GOOD_SIGNATURE)
532 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
533
534 if (signature != QCASPI_GOOD_SIGNATURE) {
535 qca->sync = QCASPI_SYNC_UNKNOWN;
536 qca->stats.bad_signature++;
537 netdev_dbg(qca->net_dev, "sync: bad signature, restart\n");
538 /* don't reset right away */
539 return;
540 }
541 break;
542 case QCASPI_SYNC_UNKNOWN:
543 /* Read signature, if not valid stay in unknown state */
544 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
545 if (signature != QCASPI_GOOD_SIGNATURE) {
546 netdev_dbg(qca->net_dev, "sync: could not read signature to reset device, retry.\n");
547 return;
548 }
549
550 /* TODO: use GPIO to reset QCA7000 in legacy mode*/
551 netdev_dbg(qca->net_dev, "sync: resetting device.\n");
552 qcaspi_read_register(qca, SPI_REG_SPI_CONFIG, &spi_config);
553 spi_config |= QCASPI_SLAVE_RESET_BIT;
554 qcaspi_write_register(qca, SPI_REG_SPI_CONFIG, spi_config, 0);
555
556 qca->sync = QCASPI_SYNC_RESET;
557 qca->stats.trig_reset++;
558 qca->reset_count = 0;
559 break;
560 case QCASPI_SYNC_RESET:
561 qca->reset_count++;
562 netdev_dbg(qca->net_dev, "sync: waiting for CPU on, count %u.\n",
563 qca->reset_count);
564 if (qca->reset_count >= QCASPI_RESET_TIMEOUT) {
565 /* reset did not seem to take place, try again */
566 qca->sync = QCASPI_SYNC_UNKNOWN;
567 qca->stats.reset_timeout++;
568 netdev_dbg(qca->net_dev, "sync: reset timeout, restarting process.\n");
569 }
570 break;
571 }
572}
573
574static int
575qcaspi_spi_thread(void *data)
576{
577 struct qcaspi *qca = data;
578 u16 intr_cause = 0;
579
580 netdev_info(qca->net_dev, "SPI thread created\n");
581 while (!kthread_should_stop()) {
582 set_current_state(TASK_INTERRUPTIBLE);
583 if (kthread_should_park()) {
584 netif_tx_disable(qca->net_dev);
585 netif_carrier_off(qca->net_dev);
586 qcaspi_flush_tx_ring(qca);
587 kthread_parkme();
588 if (qca->sync == QCASPI_SYNC_READY) {
589 netif_carrier_on(qca->net_dev);
590 netif_wake_queue(qca->net_dev);
591 }
592 continue;
593 }
594
595 if ((qca->intr_req == qca->intr_svc) &&
596 !qca->txr.skb[qca->txr.head])
597 schedule();
598
599 set_current_state(TASK_RUNNING);
600
601 netdev_dbg(qca->net_dev, "have work to do. int: %d, tx_skb: %p\n",
602 qca->intr_req - qca->intr_svc,
603 qca->txr.skb[qca->txr.head]);
604
605 qcaspi_qca7k_sync(qca, QCASPI_EVENT_UPDATE);
606
607 if (qca->sync != QCASPI_SYNC_READY) {
608 netdev_dbg(qca->net_dev, "sync: not ready %u, turn off carrier and flush\n",
609 (unsigned int)qca->sync);
610 netif_stop_queue(qca->net_dev);
611 netif_carrier_off(qca->net_dev);
612 qcaspi_flush_tx_ring(qca);
613 msleep(QCASPI_QCA7K_REBOOT_TIME_MS);
614 }
615
616 if (qca->intr_svc != qca->intr_req) {
617 qca->intr_svc = qca->intr_req;
618 start_spi_intr_handling(qca, &intr_cause);
619
620 if (intr_cause & SPI_INT_CPU_ON) {
621 qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON);
622
623 /* Frame decoding in progress */
624 if (qca->frm_handle.state != qca->frm_handle.init)
625 qca->net_dev->stats.rx_dropped++;
626
627 qcafrm_fsm_init_spi(&qca->frm_handle);
628 qca->stats.device_reset++;
629
630 /* not synced. */
631 if (qca->sync != QCASPI_SYNC_READY)
632 continue;
633
634 netif_wake_queue(qca->net_dev);
635 netif_carrier_on(qca->net_dev);
636 }
637
638 if (intr_cause & SPI_INT_RDBUF_ERR) {
639 /* restart sync */
640 netdev_dbg(qca->net_dev, "===> rdbuf error!\n");
641 qca->stats.read_buf_err++;
642 qca->sync = QCASPI_SYNC_UNKNOWN;
643 continue;
644 }
645
646 if (intr_cause & SPI_INT_WRBUF_ERR) {
647 /* restart sync */
648 netdev_dbg(qca->net_dev, "===> wrbuf error!\n");
649 qca->stats.write_buf_err++;
650 qca->sync = QCASPI_SYNC_UNKNOWN;
651 continue;
652 }
653
654 /* can only handle other interrupts
655 * if sync has occurred
656 */
657 if (qca->sync == QCASPI_SYNC_READY) {
658 if (intr_cause & SPI_INT_PKT_AVLBL)
659 qcaspi_receive(qca);
660 }
661
662 end_spi_intr_handling(qca, intr_cause);
663 }
664
665 if (qca->sync == QCASPI_SYNC_READY)
666 qcaspi_transmit(qca);
667 }
668 set_current_state(TASK_RUNNING);
669 netdev_info(qca->net_dev, "SPI thread exit\n");
670
671 return 0;
672}
673
674static irqreturn_t
675qcaspi_intr_handler(int irq, void *data)
676{
677 struct qcaspi *qca = data;
678
679 qca->intr_req++;
680 if (qca->spi_thread)
681 wake_up_process(qca->spi_thread);
682
683 return IRQ_HANDLED;
684}
685
686static int
687qcaspi_netdev_open(struct net_device *dev)
688{
689 struct qcaspi *qca = netdev_priv(dev);
690 int ret = 0;
691
692 if (!qca)
693 return -EINVAL;
694
695 qca->intr_req = 1;
696 qca->intr_svc = 0;
697 qca->sync = QCASPI_SYNC_UNKNOWN;
698 qcafrm_fsm_init_spi(&qca->frm_handle);
699
700 qca->spi_thread = kthread_run((void *)qcaspi_spi_thread,
701 qca, "%s", dev->name);
702
703 if (IS_ERR(qca->spi_thread)) {
704 netdev_err(dev, "%s: unable to start kernel thread.\n",
705 QCASPI_DRV_NAME);
706 return PTR_ERR(qca->spi_thread);
707 }
708
709 ret = request_irq(qca->spi_dev->irq, qcaspi_intr_handler, 0,
710 dev->name, qca);
711 if (ret) {
712 netdev_err(dev, "%s: unable to get IRQ %d (irqval=%d).\n",
713 QCASPI_DRV_NAME, qca->spi_dev->irq, ret);
714 kthread_stop(qca->spi_thread);
715 return ret;
716 }
717
718 /* SPI thread takes care of TX queue */
719
720 return 0;
721}
722
723static int
724qcaspi_netdev_close(struct net_device *dev)
725{
726 struct qcaspi *qca = netdev_priv(dev);
727
728 netif_stop_queue(dev);
729
730 qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0, wr_verify);
731 free_irq(qca->spi_dev->irq, qca);
732
733 kthread_stop(qca->spi_thread);
734 qca->spi_thread = NULL;
735 qcaspi_flush_tx_ring(qca);
736
737 return 0;
738}
739
740static netdev_tx_t
741qcaspi_netdev_xmit(struct sk_buff *skb, struct net_device *dev)
742{
743 u32 frame_len;
744 u8 *ptmp;
745 struct qcaspi *qca = netdev_priv(dev);
746 u16 new_tail;
747 struct sk_buff *tskb;
748 u8 pad_len = 0;
749
750 if (skb->len < QCAFRM_MIN_LEN)
751 pad_len = QCAFRM_MIN_LEN - skb->len;
752
753 if (qca->txr.skb[qca->txr.tail]) {
754 netdev_warn(qca->net_dev, "queue was unexpectedly full!\n");
755 netif_stop_queue(qca->net_dev);
756 qca->stats.ring_full++;
757 return NETDEV_TX_BUSY;
758 }
759
760 if ((skb_headroom(skb) < QCAFRM_HEADER_LEN) ||
761 (skb_tailroom(skb) < QCAFRM_FOOTER_LEN + pad_len)) {
762 tskb = skb_copy_expand(skb, QCAFRM_HEADER_LEN,
763 QCAFRM_FOOTER_LEN + pad_len, GFP_ATOMIC);
764 if (!tskb) {
765 qca->stats.out_of_mem++;
766 return NETDEV_TX_BUSY;
767 }
768 dev_kfree_skb(skb);
769 skb = tskb;
770 }
771
772 frame_len = skb->len + pad_len;
773
774 ptmp = skb_push(skb, QCAFRM_HEADER_LEN);
775 qcafrm_create_header(ptmp, frame_len);
776
777 if (pad_len) {
778 ptmp = skb_put_zero(skb, pad_len);
779 }
780
781 ptmp = skb_put(skb, QCAFRM_FOOTER_LEN);
782 qcafrm_create_footer(ptmp);
783
784 netdev_dbg(qca->net_dev, "Tx-ing packet: Size: 0x%08x\n",
785 skb->len);
786
787 qca->txr.size += skb->len + QCASPI_HW_PKT_LEN;
788
789 new_tail = qca->txr.tail + 1;
790 if (new_tail >= qca->txr.count)
791 new_tail = 0;
792
793 qca->txr.skb[qca->txr.tail] = skb;
794 qca->txr.tail = new_tail;
795
796 if (!qcaspi_tx_ring_has_space(&qca->txr)) {
797 netif_stop_queue(qca->net_dev);
798 qca->stats.ring_full++;
799 }
800
801 netif_trans_update(dev);
802
803 if (qca->spi_thread)
804 wake_up_process(qca->spi_thread);
805
806 return NETDEV_TX_OK;
807}
808
809static void
810qcaspi_netdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
811{
812 struct qcaspi *qca = netdev_priv(dev);
813
814 netdev_info(qca->net_dev, "Transmit timeout at %ld, latency %ld\n",
815 jiffies, jiffies - dev_trans_start(dev));
816 qca->net_dev->stats.tx_errors++;
817 /* Trigger tx queue flush and QCA7000 reset */
818 qca->sync = QCASPI_SYNC_UNKNOWN;
819
820 if (qca->spi_thread)
821 wake_up_process(qca->spi_thread);
822}
823
824static int
825qcaspi_netdev_init(struct net_device *dev)
826{
827 struct qcaspi *qca = netdev_priv(dev);
828
829 dev->mtu = QCAFRM_MAX_MTU;
830 dev->type = ARPHRD_ETHER;
831 qca->clkspeed = qcaspi_clkspeed;
832 qca->burst_len = qcaspi_burst_len;
833 qca->spi_thread = NULL;
834 qca->buffer_size = (dev->mtu + VLAN_ETH_HLEN + QCAFRM_HEADER_LEN +
835 QCAFRM_FOOTER_LEN + 4) * 4;
836
837 memset(&qca->stats, 0, sizeof(struct qcaspi_stats));
838
839 qca->rx_buffer = kmalloc(qca->buffer_size, GFP_KERNEL);
840 if (!qca->rx_buffer)
841 return -ENOBUFS;
842
843 qca->rx_skb = netdev_alloc_skb_ip_align(dev, qca->net_dev->mtu +
844 VLAN_ETH_HLEN);
845 if (!qca->rx_skb) {
846 kfree(qca->rx_buffer);
847 netdev_info(qca->net_dev, "Failed to allocate RX sk_buff.\n");
848 return -ENOBUFS;
849 }
850
851 return 0;
852}
853
854static void
855qcaspi_netdev_uninit(struct net_device *dev)
856{
857 struct qcaspi *qca = netdev_priv(dev);
858
859 kfree(qca->rx_buffer);
860 qca->buffer_size = 0;
861 dev_kfree_skb(qca->rx_skb);
862}
863
864static const struct net_device_ops qcaspi_netdev_ops = {
865 .ndo_init = qcaspi_netdev_init,
866 .ndo_uninit = qcaspi_netdev_uninit,
867 .ndo_open = qcaspi_netdev_open,
868 .ndo_stop = qcaspi_netdev_close,
869 .ndo_start_xmit = qcaspi_netdev_xmit,
870 .ndo_set_mac_address = eth_mac_addr,
871 .ndo_tx_timeout = qcaspi_netdev_tx_timeout,
872 .ndo_validate_addr = eth_validate_addr,
873};
874
875static void
876qcaspi_netdev_setup(struct net_device *dev)
877{
878 struct qcaspi *qca = NULL;
879
880 dev->netdev_ops = &qcaspi_netdev_ops;
881 qcaspi_set_ethtool_ops(dev);
882 dev->watchdog_timeo = QCASPI_TX_TIMEOUT;
883 dev->priv_flags &= ~IFF_TX_SKB_SHARING;
884 dev->tx_queue_len = 100;
885
886 /* MTU range: 46 - 1500 */
887 dev->min_mtu = QCAFRM_MIN_MTU;
888 dev->max_mtu = QCAFRM_MAX_MTU;
889
890 qca = netdev_priv(dev);
891 memset(qca, 0, sizeof(struct qcaspi));
892
893 memset(&qca->txr, 0, sizeof(qca->txr));
894 qca->txr.count = TX_RING_MAX_LEN;
895}
896
897static const struct of_device_id qca_spi_of_match[] = {
898 { .compatible = "qca,qca7000" },
899 { /* sentinel */ }
900};
901MODULE_DEVICE_TABLE(of, qca_spi_of_match);
902
903static int
904qca_spi_probe(struct spi_device *spi)
905{
906 struct qcaspi *qca = NULL;
907 struct net_device *qcaspi_devs = NULL;
908 u8 legacy_mode = 0;
909 u16 signature;
910 int ret;
911
912 if (!spi->dev.of_node) {
913 dev_err(&spi->dev, "Missing device tree\n");
914 return -EINVAL;
915 }
916
917 legacy_mode = of_property_read_bool(spi->dev.of_node,
918 "qca,legacy-mode");
919
920 if (qcaspi_clkspeed == 0) {
921 if (spi->max_speed_hz)
922 qcaspi_clkspeed = spi->max_speed_hz;
923 else
924 qcaspi_clkspeed = QCASPI_CLK_SPEED;
925 }
926
927 if ((qcaspi_clkspeed < QCASPI_CLK_SPEED_MIN) ||
928 (qcaspi_clkspeed > QCASPI_CLK_SPEED_MAX)) {
929 dev_err(&spi->dev, "Invalid clkspeed: %d\n",
930 qcaspi_clkspeed);
931 return -EINVAL;
932 }
933
934 if ((qcaspi_burst_len < QCASPI_BURST_LEN_MIN) ||
935 (qcaspi_burst_len > QCASPI_BURST_LEN_MAX)) {
936 dev_err(&spi->dev, "Invalid burst len: %d\n",
937 qcaspi_burst_len);
938 return -EINVAL;
939 }
940
941 if ((qcaspi_pluggable < QCASPI_PLUGGABLE_MIN) ||
942 (qcaspi_pluggable > QCASPI_PLUGGABLE_MAX)) {
943 dev_err(&spi->dev, "Invalid pluggable: %d\n",
944 qcaspi_pluggable);
945 return -EINVAL;
946 }
947
948 if (wr_verify < QCASPI_WRITE_VERIFY_MIN ||
949 wr_verify > QCASPI_WRITE_VERIFY_MAX) {
950 dev_err(&spi->dev, "Invalid write verify: %d\n",
951 wr_verify);
952 return -EINVAL;
953 }
954
955 dev_info(&spi->dev, "ver=%s, clkspeed=%d, burst_len=%d, pluggable=%d\n",
956 QCASPI_DRV_VERSION,
957 qcaspi_clkspeed,
958 qcaspi_burst_len,
959 qcaspi_pluggable);
960
961 spi->mode = SPI_MODE_3;
962 spi->max_speed_hz = qcaspi_clkspeed;
963 if (spi_setup(spi) < 0) {
964 dev_err(&spi->dev, "Unable to setup SPI device\n");
965 return -EFAULT;
966 }
967
968 qcaspi_devs = alloc_etherdev(sizeof(struct qcaspi));
969 if (!qcaspi_devs)
970 return -ENOMEM;
971
972 qcaspi_netdev_setup(qcaspi_devs);
973 SET_NETDEV_DEV(qcaspi_devs, &spi->dev);
974
975 qca = netdev_priv(qcaspi_devs);
976 if (!qca) {
977 free_netdev(qcaspi_devs);
978 dev_err(&spi->dev, "Fail to retrieve private structure\n");
979 return -ENOMEM;
980 }
981 qca->net_dev = qcaspi_devs;
982 qca->spi_dev = spi;
983 qca->legacy_mode = legacy_mode;
984
985 spi_set_drvdata(spi, qcaspi_devs);
986
987 ret = of_get_ethdev_address(spi->dev.of_node, qca->net_dev);
988 if (ret) {
989 eth_hw_addr_random(qca->net_dev);
990 dev_info(&spi->dev, "Using random MAC address: %pM\n",
991 qca->net_dev->dev_addr);
992 }
993
994 netif_carrier_off(qca->net_dev);
995
996 if (!qcaspi_pluggable) {
997 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
998 qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
999
1000 if (signature != QCASPI_GOOD_SIGNATURE) {
1001 dev_err(&spi->dev, "Invalid signature (0x%04X)\n",
1002 signature);
1003 free_netdev(qcaspi_devs);
1004 return -EFAULT;
1005 }
1006 }
1007
1008 if (register_netdev(qcaspi_devs)) {
1009 dev_err(&spi->dev, "Unable to register net device %s\n",
1010 qcaspi_devs->name);
1011 free_netdev(qcaspi_devs);
1012 return -EFAULT;
1013 }
1014
1015 qcaspi_init_device_debugfs(qca);
1016
1017 return 0;
1018}
1019
1020static void
1021qca_spi_remove(struct spi_device *spi)
1022{
1023 struct net_device *qcaspi_devs = spi_get_drvdata(spi);
1024 struct qcaspi *qca = netdev_priv(qcaspi_devs);
1025
1026 qcaspi_remove_device_debugfs(qca);
1027
1028 unregister_netdev(qcaspi_devs);
1029 free_netdev(qcaspi_devs);
1030}
1031
1032static const struct spi_device_id qca_spi_id[] = {
1033 { "qca7000", 0 },
1034 { /* sentinel */ }
1035};
1036MODULE_DEVICE_TABLE(spi, qca_spi_id);
1037
1038static struct spi_driver qca_spi_driver = {
1039 .driver = {
1040 .name = QCASPI_DRV_NAME,
1041 .of_match_table = qca_spi_of_match,
1042 },
1043 .id_table = qca_spi_id,
1044 .probe = qca_spi_probe,
1045 .remove = qca_spi_remove,
1046};
1047module_spi_driver(qca_spi_driver);
1048
1049MODULE_DESCRIPTION("Qualcomm Atheros QCA7000 SPI Driver");
1050MODULE_AUTHOR("Qualcomm Atheros Communications");
1051MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>");
1052MODULE_LICENSE("Dual BSD/GPL");
1053MODULE_VERSION(QCASPI_DRV_VERSION);