1/* SPDX-License-Identifier: GPL-2.0+ */
  2/* Microchip Sparx5 Switch driver
  3 *
  4 * Copyright (c) 2024 Microchip Technology Inc.
  5 */
  6
  7/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200.
  8 * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
  9 */
 10
 11#ifndef _SPARX5_REGS_H_
 12#define _SPARX5_REGS_H_
 13
 14/* These enumerated values are used to index the platform specific structs
 15 * containing the addresses, counts, size and positions, of register groups,
 16 * registers and fields.
 17 */
 18
 19enum sparx5_tsize_enum {
 20	TC_DEV10G,
 21	TC_DEV2G5,
 22	TC_DEV5G,
 23	TC_PCS10G_BR,
 24	TC_PCS5G_BR,
 25	TSIZE_LAST,
 26};
 27
 28enum sparx5_raddr_enum {
 29	RA_CPU_PROC_CTRL,
 30	RA_GCB_SOFT_RST,
 31	RA_GCB_HW_SGPIO_TO_SD_MAP_CFG,
 32	RADDR_LAST,
 33};
 34
 35enum sparx5_rcnt_enum {
 36	RC_ANA_AC_OWN_UPSID,
 37	RC_ANA_ACL_VCAP_S2_CFG,
 38	RC_ANA_ACL_OWN_UPSID,
 39	RC_ANA_CL_OWN_UPSID,
 40	RC_ANA_L2_OWN_UPSID,
 41	RC_ASM_PORT_CFG,
 42	RC_DSM_BUF_CFG,
 43	RC_DSM_DEV_TX_STOP_WM_CFG,
 44	RC_DSM_RX_PAUSE_CFG,
 45	RC_DSM_MAC_CFG,
 46	RC_DSM_MAC_ADDR_BASE_HIGH_CFG,
 47	RC_DSM_MAC_ADDR_BASE_LOW_CFG,
 48	RC_DSM_TAXI_CAL_CFG,
 49	RC_GCB_HW_SGPIO_TO_SD_MAP_CFG,
 50	RC_HSCH_PORT_MODE,
 51	RC_QFWD_SWITCH_PORT_MODE,
 52	RC_QSYS_PAUSE_CFG,
 53	RC_QSYS_ATOP,
 54	RC_QSYS_FWD_PRESSURE,
 55	RC_QSYS_CAL_AUTO,
 56	RC_REW_OWN_UPSID,
 57	RC_REW_RTAG_ETAG_CTRL,
 58	RCNT_LAST,
 59};
 60
 61enum sparx5_gaddr_enum {
 62	GA_ANA_AC_RAM_CTRL,
 63	GA_ANA_AC_PS_COMMON,
 64	GA_ANA_AC_MIRROR_PROBE,
 65	GA_ANA_AC_SRC,
 66	GA_ANA_AC_PGID,
 67	GA_ANA_AC_TSN_SF,
 68	GA_ANA_AC_TSN_SF_CFG,
 69	GA_ANA_AC_TSN_SF_STATUS,
 70	GA_ANA_AC_SG_ACCESS,
 71	GA_ANA_AC_SG_CONFIG,
 72	GA_ANA_AC_SG_STATUS,
 73	GA_ANA_AC_SG_STATUS_STICKY,
 74	GA_ANA_AC_STAT_GLOBAL_CFG_PORT,
 75	GA_ANA_AC_STAT_CNT_CFG_PORT,
 76	GA_ANA_AC_STAT_GLOBAL_CFG_ACL,
 77	GA_ANA_ACL_COMMON,
 78	GA_ANA_ACL_KEY_SEL,
 79	GA_ANA_ACL_CNT_B,
 80	GA_ANA_ACL_STICKY,
 81	GA_ANA_AC_POL_POL_ALL_CFG,
 82	GA_ANA_AC_POL_COMMON_BDLB,
 83	GA_ANA_AC_POL_COMMON_BUM_SLB,
 84	GA_ANA_AC_SDLB_LBGRP_TBL,
 85	GA_ANA_CL_PORT,
 86	GA_ANA_CL_COMMON,
 87	GA_ANA_L2_COMMON,
 88	GA_ANA_L3_COMMON,
 89	GA_ANA_L3_VLAN_ARP_L3MC_STICKY,
 90	GA_ASM_CFG,
 91	GA_ASM_PFC_TIMER_CFG,
 92	GA_ASM_LBK_WM_CFG,
 93	GA_ASM_LBK_MISC_CFG,
 94	GA_ASM_RAM_CTRL,
 95	GA_EACL_ES2_KEY_SELECT_PROFILE,
 96	GA_EACL_CNT_TBL,
 97	GA_EACL_POL_CFG,
 98	GA_EACL_ES2_STICKY,
 99	GA_EACL_RAM_CTRL,
100	GA_GCB_SIO_CTRL,
101	GA_HSCH_HSCH_DWRR,
102	GA_HSCH_HSCH_MISC,
103	GA_HSCH_HSCH_LEAK_LISTS,
104	GA_HSCH_SYSTEM,
105	GA_HSCH_MMGT,
106	GA_HSCH_TAS_CONFIG,
107	GA_PTP_PTP_CFG,
108	GA_PTP_PTP_TOD_DOMAINS,
109	GA_PTP_PHASE_DETECTOR_CTRL,
110	GA_QSYS_CALCFG,
111	GA_QSYS_RAM_CTRL,
112	GA_REW_COMMON,
113	GA_REW_PORT,
114	GA_REW_VOE_PORT_LM_CNT,
115	GA_REW_RAM_CTRL,
116	GA_VOP_RAM_CTRL,
117	GA_XQS_SYSTEM,
118	GA_XQS_QLIMIT_SHR,
119	GADDR_LAST,
120};
121
122enum sparx5_gcnt_enum {
123	GC_ANA_AC_SRC,
124	GC_ANA_AC_PGID,
125	GC_ANA_AC_TSN_SF_CFG,
126	GC_ANA_AC_STAT_CNT_CFG_PORT,
127	GC_ANA_ACL_KEY_SEL,
128	GC_ANA_ACL_CNT_A,
129	GC_ANA_ACL_CNT_B,
130	GC_ANA_AC_SDLB_LBGRP_TBL,
131	GC_ANA_AC_SDLB_LBSET_TBL,
132	GC_ANA_CL_PORT,
133	GC_ANA_L2_ISDX_LIMIT,
134	GC_ANA_L2_ISDX,
135	GC_ANA_L3_VLAN,
136	GC_ASM_DEV_STATISTICS,
137	GC_EACL_ES2_KEY_SELECT_PROFILE,
138	GC_EACL_CNT_TBL,
139	GC_GCB_SIO_CTRL,
140	GC_HSCH_HSCH_CFG,
141	GC_HSCH_HSCH_DWRR,
142	GC_PTP_PTP_PINS,
143	GC_PTP_PHASE_DETECTOR_CTRL,
144	GC_REW_PORT,
145	GC_REW_VOE_PORT_LM_CNT,
146	GCNT_LAST,
147};
148
149enum sparx5_gsize_enum {
150	GW_ANA_AC_SRC,
151	GW_ANA_L2_COMMON,
152	GW_ASM_CFG,
153	GW_CPU_CPU_REGS,
154	GW_DEV2G5_PHASE_DETECTOR_CTRL,
155	GW_FDMA_FDMA,
156	GW_GCB_CHIP_REGS,
157	GW_HSCH_TAS_CONFIG,
158	GW_PTP_PHASE_DETECTOR_CTRL,
159	GW_QSYS_PAUSE_CFG,
160	GSIZE_LAST,
161};
162
163enum sparx5_fpos_enum {
164	FP_CPU_PROC_CTRL_AARCH64_MODE_ENA,
165	FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS,
166	FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS,
167	FP_CPU_PROC_CTRL_BE_EXCEP_MODE,
168	FP_CPU_PROC_CTRL_VINITHI,
169	FP_CPU_PROC_CTRL_CFGTE,
170	FP_CPU_PROC_CTRL_CP15S_DISABLE,
171	FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE,
172	FP_CPU_PROC_CTRL_L2_FLUSH_REQ,
173	FP_DEV2G5_PHAD_CTRL_PHAD_ENA,
174	FP_DEV2G5_PHAD_CTRL_PHAD_FAILED,
175	FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE,
176	FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY,
177	FP_FDMA_CH_CFG_CH_INJ_PORT,
178	FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION,
179	FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC,
180	FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL,
181	FP_PTP_PHAD_CTRL_PHAD_ENA,
182	FP_PTP_PHAD_CTRL_PHAD_FAILED,
183	FPOS_LAST,
184};
185
186enum sparx5_fsize_enum {
187	FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK,
188	FW_ANA_AC_SRC_CFG_PORT_MASK,
189	FW_ANA_AC_PGID_CFG_PORT_MASK,
190	FW_ANA_AC_TSN_SF_PORT_NUM,
191	FW_ANA_AC_TSN_SF_CFG_TSN_SGID,
192	FW_ANA_AC_TSN_SF_STATUS_TSN_SFID,
193	FW_ANA_AC_SG_ACCESS_CTRL_SGID,
194	FW_ANA_AC_PORT_SGE_CFG_MASK,
195	FW_ANA_AC_SDLB_XLB_START_LBSET_START,
196	FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT,
197	FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT,
198	FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT,
199	FW_ANA_AC_SDLB_XLB_NEXT_LBGRP,
200	FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR,
201	FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA,
202	FW_ANA_L2_DLB_CFG_DLB_IDX,
203	FW_ANA_L2_TSN_CFG_TSN_SFID,
204	FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK,
205	FW_FDMA_CH_CFG_CH_DCB_DB_CNT,
206	FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL,
207	FW_HSCH_SE_CFG_SE_DWRR_CNT,
208	FW_HSCH_SE_CONNECT_SE_LEAK_LINK,
209	FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT,
210	FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX,
211	FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST,
212	FW_HSCH_FLUSH_CTRL_FLUSH_PORT,
213	FW_HSCH_FLUSH_CTRL_FLUSH_HIER,
214	FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW,
215	FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX,
216	FW_LRN_AUTOAGE_CFG_2_NEXT_ROW,
217	FW_PTP_PTP_PIN_INTR_INTR_PTP,
218	FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA,
219	FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT,
220	FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT,
221	FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL,
222	FW_QRES_RES_CFG_WM_HIGH,
223	FW_QRES_RES_STAT_MAXUSE,
224	FW_QRES_RES_STAT_CUR_INUSE,
225	FW_QSYS_PAUSE_CFG_PAUSE_START,
226	FW_QSYS_PAUSE_CFG_PAUSE_STOP,
227	FW_QSYS_ATOP_ATOP,
228	FW_QSYS_ATOP_TOT_CFG_ATOP_TOT,
229	FW_REW_RTAG_ETAG_CTRL_IPE_TBL,
230	FW_XQS_STAT_CFG_STAT_VIEW,
231	FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP,
232	FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP,
233	FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP,
234	FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM,
235	FSIZE_LAST,
236};
237
238extern const unsigned int sparx5_tsize[TSIZE_LAST];
239extern const unsigned int sparx5_raddr[RADDR_LAST];
240extern const unsigned int sparx5_rcnt[RCNT_LAST];
241extern const unsigned int sparx5_gaddr[GADDR_LAST];
242extern const unsigned int sparx5_gcnt[GCNT_LAST];
243extern const unsigned int sparx5_gsize[GSIZE_LAST];
244extern const unsigned int sparx5_fpos[FPOS_LAST];
245extern const unsigned int sparx5_fsize[FSIZE_LAST];
246
247#endif /* _SPARX5_REGS_H_ */