1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Microchip ENC28J60 ethernet driver (MAC + PHY)
   4 *
   5 * Copyright (C) 2007 Eurek srl
   6 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
   7 * based on enc28j60.c written by David Anders for 2.4 kernel version
   8 *
   9 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/kernel.h>
  14#include <linux/types.h>
  15#include <linux/fcntl.h>
  16#include <linux/interrupt.h>
  17#include <linux/property.h>
  18#include <linux/string.h>
  19#include <linux/errno.h>
  20#include <linux/netdevice.h>
  21#include <linux/etherdevice.h>
  22#include <linux/ethtool.h>
  23#include <linux/tcp.h>
  24#include <linux/skbuff.h>
  25#include <linux/delay.h>
  26#include <linux/spi/spi.h>
  27
  28#include "enc28j60_hw.h"
  29
  30#define DRV_NAME	"enc28j60"
  31#define DRV_VERSION	"1.02"
  32
  33#define SPI_OPLEN	1
  34
  35#define ENC28J60_MSG_DEFAULT	\
  36	(NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
  37
  38/* Buffer size required for the largest SPI transfer (i.e., reading a
  39 * frame).
  40 */
  41#define SPI_TRANSFER_BUF_LEN	(4 + MAX_FRAMELEN)
  42
  43#define TX_TIMEOUT		(4 * HZ)
  44
  45/* Max TX retries in case of collision as suggested by errata datasheet */
  46#define MAX_TX_RETRYCOUNT	16
  47
  48enum {
  49	RXFILTER_NORMAL,
  50	RXFILTER_MULTI,
  51	RXFILTER_PROMISC
  52};
  53
  54/* Driver local data */
  55struct enc28j60_net {
  56	struct net_device *netdev;
  57	struct spi_device *spi;
  58	struct mutex lock;
  59	struct sk_buff *tx_skb;
  60	struct work_struct tx_work;
  61	struct work_struct setrx_work;
  62	struct work_struct restart_work;
  63	u8 bank;		/* current register bank selected */
  64	u16 next_pk_ptr;	/* next packet pointer within FIFO */
  65	u16 max_pk_counter;	/* statistics: max packet counter */
  66	u16 tx_retry_count;
  67	bool hw_enable;
  68	bool full_duplex;
  69	int rxfilter;
  70	u32 msg_enable;
  71	u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
  72};
  73
  74/* use ethtool to change the level for any given device */
  75static struct {
  76	u32 msg_enable;
  77} debug = { -1 };
  78
  79/*
  80 * SPI read buffer
  81 * Wait for the SPI transfer and copy received data to destination.
  82 */
  83static int
  84spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
  85{
  86	struct device *dev = &priv->spi->dev;
  87	u8 *rx_buf = priv->spi_transfer_buf + 4;
  88	u8 *tx_buf = priv->spi_transfer_buf;
  89	struct spi_transfer tx = {
  90		.tx_buf = tx_buf,
  91		.len = SPI_OPLEN,
  92	};
  93	struct spi_transfer rx = {
  94		.rx_buf = rx_buf,
  95		.len = len,
  96	};
  97	struct spi_message msg;
  98	int ret;
  99
 100	tx_buf[0] = ENC28J60_READ_BUF_MEM;
 101
 102	spi_message_init(&msg);
 103	spi_message_add_tail(&tx, &msg);
 104	spi_message_add_tail(&rx, &msg);
 105
 106	ret = spi_sync(priv->spi, &msg);
 107	if (ret == 0) {
 108		memcpy(data, rx_buf, len);
 109		ret = msg.status;
 110	}
 111	if (ret && netif_msg_drv(priv))
 112		dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
 113			   __func__, ret);
 114
 115	return ret;
 116}
 117
 118/*
 119 * SPI write buffer
 120 */
 121static int spi_write_buf(struct enc28j60_net *priv, int len, const u8 *data)
 122{
 123	struct device *dev = &priv->spi->dev;
 124	int ret;
 125
 126	if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
 127		ret = -EINVAL;
 128	else {
 129		priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
 130		memcpy(&priv->spi_transfer_buf[1], data, len);
 131		ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
 132		if (ret && netif_msg_drv(priv))
 133			dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
 134				   __func__, ret);
 135	}
 136	return ret;
 137}
 138
 139/*
 140 * basic SPI read operation
 141 */
 142static u8 spi_read_op(struct enc28j60_net *priv, u8 op, u8 addr)
 143{
 144	struct device *dev = &priv->spi->dev;
 145	u8 tx_buf[2];
 146	u8 rx_buf[4];
 147	u8 val = 0;
 148	int ret;
 149	int slen = SPI_OPLEN;
 150
 151	/* do dummy read if needed */
 152	if (addr & SPRD_MASK)
 153		slen++;
 154
 155	tx_buf[0] = op | (addr & ADDR_MASK);
 156	ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
 157	if (ret)
 158		dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
 159			   __func__, ret);
 160	else
 161		val = rx_buf[slen - 1];
 162
 163	return val;
 164}
 165
 166/*
 167 * basic SPI write operation
 168 */
 169static int spi_write_op(struct enc28j60_net *priv, u8 op, u8 addr, u8 val)
 170{
 171	struct device *dev = &priv->spi->dev;
 172	int ret;
 173
 174	priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
 175	priv->spi_transfer_buf[1] = val;
 176	ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
 177	if (ret && netif_msg_drv(priv))
 178		dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
 179			   __func__, ret);
 180	return ret;
 181}
 182
 183static void enc28j60_soft_reset(struct enc28j60_net *priv)
 184{
 185	spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
 186	/* Errata workaround #1, CLKRDY check is unreliable,
 187	 * delay at least 1 ms instead */
 188	udelay(2000);
 189}
 190
 191/*
 192 * select the current register bank if necessary
 193 */
 194static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
 195{
 196	u8 b = (addr & BANK_MASK) >> 5;
 197
 198	/* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
 199	 * are present in all banks, no need to switch bank.
 200	 */
 201	if (addr >= EIE && addr <= ECON1)
 202		return;
 203
 204	/* Clear or set each bank selection bit as needed */
 205	if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
 206		if (b & ECON1_BSEL0)
 207			spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
 208					ECON1_BSEL0);
 209		else
 210			spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
 211					ECON1_BSEL0);
 212	}
 213	if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
 214		if (b & ECON1_BSEL1)
 215			spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
 216					ECON1_BSEL1);
 217		else
 218			spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
 219					ECON1_BSEL1);
 220	}
 221	priv->bank = b;
 222}
 223
 224/*
 225 * Register access routines through the SPI bus.
 226 * Every register access comes in two flavours:
 227 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
 228 *   atomically more than one register
 229 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
 230 *
 231 * Some registers can be accessed through the bit field clear and
 232 * bit field set to avoid a read modify write cycle.
 233 */
 234
 235/*
 236 * Register bit field Set
 237 */
 238static void nolock_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
 239{
 240	enc28j60_set_bank(priv, addr);
 241	spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
 242}
 243
 244static void locked_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
 245{
 246	mutex_lock(&priv->lock);
 247	nolock_reg_bfset(priv, addr, mask);
 248	mutex_unlock(&priv->lock);
 249}
 250
 251/*
 252 * Register bit field Clear
 253 */
 254static void nolock_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
 255{
 256	enc28j60_set_bank(priv, addr);
 257	spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
 258}
 259
 260static void locked_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
 261{
 262	mutex_lock(&priv->lock);
 263	nolock_reg_bfclr(priv, addr, mask);
 264	mutex_unlock(&priv->lock);
 265}
 266
 267/*
 268 * Register byte read
 269 */
 270static int nolock_regb_read(struct enc28j60_net *priv, u8 address)
 271{
 272	enc28j60_set_bank(priv, address);
 273	return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
 274}
 275
 276static int locked_regb_read(struct enc28j60_net *priv, u8 address)
 277{
 278	int ret;
 279
 280	mutex_lock(&priv->lock);
 281	ret = nolock_regb_read(priv, address);
 282	mutex_unlock(&priv->lock);
 283
 284	return ret;
 285}
 286
 287/*
 288 * Register word read
 289 */
 290static int nolock_regw_read(struct enc28j60_net *priv, u8 address)
 291{
 292	int rl, rh;
 293
 294	enc28j60_set_bank(priv, address);
 295	rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
 296	rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
 297
 298	return (rh << 8) | rl;
 299}
 300
 301static int locked_regw_read(struct enc28j60_net *priv, u8 address)
 302{
 303	int ret;
 304
 305	mutex_lock(&priv->lock);
 306	ret = nolock_regw_read(priv, address);
 307	mutex_unlock(&priv->lock);
 308
 309	return ret;
 310}
 311
 312/*
 313 * Register byte write
 314 */
 315static void nolock_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
 316{
 317	enc28j60_set_bank(priv, address);
 318	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
 319}
 320
 321static void locked_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
 322{
 323	mutex_lock(&priv->lock);
 324	nolock_regb_write(priv, address, data);
 325	mutex_unlock(&priv->lock);
 326}
 327
 328/*
 329 * Register word write
 330 */
 331static void nolock_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
 332{
 333	enc28j60_set_bank(priv, address);
 334	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
 335	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
 336		     (u8) (data >> 8));
 337}
 338
 339static void locked_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
 340{
 341	mutex_lock(&priv->lock);
 342	nolock_regw_write(priv, address, data);
 343	mutex_unlock(&priv->lock);
 344}
 345
 346/*
 347 * Buffer memory read
 348 * Select the starting address and execute a SPI buffer read.
 349 */
 350static void enc28j60_mem_read(struct enc28j60_net *priv, u16 addr, int len,
 351			      u8 *data)
 352{
 353	mutex_lock(&priv->lock);
 354	nolock_regw_write(priv, ERDPTL, addr);
 355#ifdef CONFIG_ENC28J60_WRITEVERIFY
 356	if (netif_msg_drv(priv)) {
 357		struct device *dev = &priv->spi->dev;
 358		u16 reg;
 359
 360		reg = nolock_regw_read(priv, ERDPTL);
 361		if (reg != addr)
 362			dev_printk(KERN_DEBUG, dev,
 363				   "%s() error writing ERDPT (0x%04x - 0x%04x)\n",
 364				   __func__, reg, addr);
 365	}
 366#endif
 367	spi_read_buf(priv, len, data);
 368	mutex_unlock(&priv->lock);
 369}
 370
 371/*
 372 * Write packet to enc28j60 TX buffer memory
 373 */
 374static void
 375enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
 376{
 377	struct device *dev = &priv->spi->dev;
 378
 379	mutex_lock(&priv->lock);
 380	/* Set the write pointer to start of transmit buffer area */
 381	nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
 382#ifdef CONFIG_ENC28J60_WRITEVERIFY
 383	if (netif_msg_drv(priv)) {
 384		u16 reg;
 385		reg = nolock_regw_read(priv, EWRPTL);
 386		if (reg != TXSTART_INIT)
 387			dev_printk(KERN_DEBUG, dev,
 388				   "%s() ERWPT:0x%04x != 0x%04x\n",
 389				   __func__, reg, TXSTART_INIT);
 390	}
 391#endif
 392	/* Set the TXND pointer to correspond to the packet size given */
 393	nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
 394	/* write per-packet control byte */
 395	spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
 396	if (netif_msg_hw(priv))
 397		dev_printk(KERN_DEBUG, dev,
 398			   "%s() after control byte ERWPT:0x%04x\n",
 399			   __func__, nolock_regw_read(priv, EWRPTL));
 400	/* copy the packet into the transmit buffer */
 401	spi_write_buf(priv, len, data);
 402	if (netif_msg_hw(priv))
 403		dev_printk(KERN_DEBUG, dev,
 404			   "%s() after write packet ERWPT:0x%04x, len=%d\n",
 405			   __func__, nolock_regw_read(priv, EWRPTL), len);
 406	mutex_unlock(&priv->lock);
 407}
 408
 409static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
 410{
 411	struct device *dev = &priv->spi->dev;
 412	unsigned long timeout = jiffies + msecs_to_jiffies(20);
 413
 414	/* 20 msec timeout read */
 415	while ((nolock_regb_read(priv, reg) & mask) != val) {
 416		if (time_after(jiffies, timeout)) {
 417			if (netif_msg_drv(priv))
 418				dev_dbg(dev, "reg %02x ready timeout!\n", reg);
 419			return -ETIMEDOUT;
 420		}
 421		cpu_relax();
 422	}
 423	return 0;
 424}
 425
 426/*
 427 * Wait until the PHY operation is complete.
 428 */
 429static int wait_phy_ready(struct enc28j60_net *priv)
 430{
 431	return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
 432}
 433
 434/*
 435 * PHY register read
 436 * PHY registers are not accessed directly, but through the MII.
 437 */
 438static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
 439{
 440	u16 ret;
 441
 442	mutex_lock(&priv->lock);
 443	/* set the PHY register address */
 444	nolock_regb_write(priv, MIREGADR, address);
 445	/* start the register read operation */
 446	nolock_regb_write(priv, MICMD, MICMD_MIIRD);
 447	/* wait until the PHY read completes */
 448	wait_phy_ready(priv);
 449	/* quit reading */
 450	nolock_regb_write(priv, MICMD, 0x00);
 451	/* return the data */
 452	ret = nolock_regw_read(priv, MIRDL);
 453	mutex_unlock(&priv->lock);
 454
 455	return ret;
 456}
 457
 458static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
 459{
 460	int ret;
 461
 462	mutex_lock(&priv->lock);
 463	/* set the PHY register address */
 464	nolock_regb_write(priv, MIREGADR, address);
 465	/* write the PHY data */
 466	nolock_regw_write(priv, MIWRL, data);
 467	/* wait until the PHY write completes and return */
 468	ret = wait_phy_ready(priv);
 469	mutex_unlock(&priv->lock);
 470
 471	return ret;
 472}
 473
 474/*
 475 * Program the hardware MAC address from dev->dev_addr.
 476 */
 477static int enc28j60_set_hw_macaddr(struct net_device *ndev)
 478{
 479	int ret;
 480	struct enc28j60_net *priv = netdev_priv(ndev);
 481	struct device *dev = &priv->spi->dev;
 482
 483	mutex_lock(&priv->lock);
 484	if (!priv->hw_enable) {
 485		if (netif_msg_drv(priv))
 486			dev_info(dev, "%s: Setting MAC address to %pM\n",
 487				 ndev->name, ndev->dev_addr);
 488		/* NOTE: MAC address in ENC28J60 is byte-backward */
 489		nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
 490		nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
 491		nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
 492		nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
 493		nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
 494		nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
 495		ret = 0;
 496	} else {
 497		if (netif_msg_drv(priv))
 498			dev_printk(KERN_DEBUG, dev,
 499				   "%s() Hardware must be disabled to set Mac address\n",
 500				   __func__);
 501		ret = -EBUSY;
 502	}
 503	mutex_unlock(&priv->lock);
 504	return ret;
 505}
 506
 507/*
 508 * Store the new hardware address in dev->dev_addr, and update the MAC.
 509 */
 510static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
 511{
 512	struct sockaddr *address = addr;
 513
 514	if (netif_running(dev))
 515		return -EBUSY;
 516	if (!is_valid_ether_addr(address->sa_data))
 517		return -EADDRNOTAVAIL;
 518
 519	eth_hw_addr_set(dev, address->sa_data);
 520	return enc28j60_set_hw_macaddr(dev);
 521}
 522
 523/*
 524 * Debug routine to dump useful register contents
 525 */
 526static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
 527{
 528	struct device *dev = &priv->spi->dev;
 529
 530	mutex_lock(&priv->lock);
 531	dev_printk(KERN_DEBUG, dev,
 532		   " %s\n"
 533		   "HwRevID: 0x%02x\n"
 534		   "Cntrl: ECON1 ECON2 ESTAT  EIR  EIE\n"
 535		   "       0x%02x  0x%02x  0x%02x  0x%02x  0x%02x\n"
 536		   "MAC  : MACON1 MACON3 MACON4\n"
 537		   "       0x%02x   0x%02x   0x%02x\n"
 538		   "Rx   : ERXST  ERXND  ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
 539		   "       0x%04x 0x%04x 0x%04x  0x%04x  "
 540		   "0x%02x    0x%02x    0x%04x\n"
 541		   "Tx   : ETXST  ETXND  MACLCON1 MACLCON2 MAPHSUP\n"
 542		   "       0x%04x 0x%04x 0x%02x     0x%02x     0x%02x\n",
 543		   msg, nolock_regb_read(priv, EREVID),
 544		   nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
 545		   nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
 546		   nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
 547		   nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
 548		   nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
 549		   nolock_regw_read(priv, ERXWRPTL),
 550		   nolock_regw_read(priv, ERXRDPTL),
 551		   nolock_regb_read(priv, ERXFCON),
 552		   nolock_regb_read(priv, EPKTCNT),
 553		   nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
 554		   nolock_regw_read(priv, ETXNDL),
 555		   nolock_regb_read(priv, MACLCON1),
 556		   nolock_regb_read(priv, MACLCON2),
 557		   nolock_regb_read(priv, MAPHSUP));
 558	mutex_unlock(&priv->lock);
 559}
 560
 561/*
 562 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
 563 */
 564static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
 565{
 566	u16 erxrdpt;
 567
 568	if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
 569		erxrdpt = end;
 570	else
 571		erxrdpt = next_packet_ptr - 1;
 572
 573	return erxrdpt;
 574}
 575
 576/*
 577 * Calculate wrap around when reading beyond the end of the RX buffer
 578 */
 579static u16 rx_packet_start(u16 ptr)
 580{
 581	if (ptr + RSV_SIZE > RXEND_INIT)
 582		return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
 583	else
 584		return ptr + RSV_SIZE;
 585}
 586
 587static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
 588{
 589	struct device *dev = &priv->spi->dev;
 590	u16 erxrdpt;
 591
 592	if (start > 0x1FFF || end > 0x1FFF || start > end) {
 593		if (netif_msg_drv(priv))
 594			dev_err(dev, "%s(%d, %d) RXFIFO bad parameters!\n",
 595				__func__, start, end);
 596		return;
 597	}
 598	/* set receive buffer start + end */
 599	priv->next_pk_ptr = start;
 600	nolock_regw_write(priv, ERXSTL, start);
 601	erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
 602	nolock_regw_write(priv, ERXRDPTL, erxrdpt);
 603	nolock_regw_write(priv, ERXNDL, end);
 604}
 605
 606static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
 607{
 608	struct device *dev = &priv->spi->dev;
 609
 610	if (start > 0x1FFF || end > 0x1FFF || start > end) {
 611		if (netif_msg_drv(priv))
 612			dev_err(dev, "%s(%d, %d) TXFIFO bad parameters!\n",
 613				__func__, start, end);
 614		return;
 615	}
 616	/* set transmit buffer start + end */
 617	nolock_regw_write(priv, ETXSTL, start);
 618	nolock_regw_write(priv, ETXNDL, end);
 619}
 620
 621/*
 622 * Low power mode shrinks power consumption about 100x, so we'd like
 623 * the chip to be in that mode whenever it's inactive. (However, we
 624 * can't stay in low power mode during suspend with WOL active.)
 625 */
 626static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
 627{
 628	struct device *dev = &priv->spi->dev;
 629
 630	if (netif_msg_drv(priv))
 631		dev_dbg(dev, "%s power...\n", is_low ? "low" : "high");
 632
 633	mutex_lock(&priv->lock);
 634	if (is_low) {
 635		nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 636		poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
 637		poll_ready(priv, ECON1, ECON1_TXRTS, 0);
 638		/* ECON2_VRPS was set during initialization */
 639		nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
 640	} else {
 641		nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
 642		poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
 643		/* caller sets ECON1_RXEN */
 644	}
 645	mutex_unlock(&priv->lock);
 646}
 647
 648static int enc28j60_hw_init(struct enc28j60_net *priv)
 649{
 650	struct device *dev = &priv->spi->dev;
 651	u8 reg;
 652
 653	if (netif_msg_drv(priv))
 654		dev_printk(KERN_DEBUG, dev, "%s() - %s\n", __func__,
 655			   priv->full_duplex ? "FullDuplex" : "HalfDuplex");
 656
 657	mutex_lock(&priv->lock);
 658	/* first reset the chip */
 659	enc28j60_soft_reset(priv);
 660	/* Clear ECON1 */
 661	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
 662	priv->bank = 0;
 663	priv->hw_enable = false;
 664	priv->tx_retry_count = 0;
 665	priv->max_pk_counter = 0;
 666	priv->rxfilter = RXFILTER_NORMAL;
 667	/* enable address auto increment and voltage regulator powersave */
 668	nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
 669
 670	nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
 671	nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
 672	mutex_unlock(&priv->lock);
 673
 674	/*
 675	 * Check the RevID.
 676	 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
 677	 * damaged.
 678	 */
 679	reg = locked_regb_read(priv, EREVID);
 680	if (netif_msg_drv(priv))
 681		dev_info(dev, "chip RevID: 0x%02x\n", reg);
 682	if (reg == 0x00 || reg == 0xff) {
 683		if (netif_msg_drv(priv))
 684			dev_printk(KERN_DEBUG, dev, "%s() Invalid RevId %d\n",
 685				   __func__, reg);
 686		return 0;
 687	}
 688
 689	/* default filter mode: (unicast OR broadcast) AND crc valid */
 690	locked_regb_write(priv, ERXFCON,
 691			    ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
 692
 693	/* enable MAC receive */
 694	locked_regb_write(priv, MACON1,
 695			    MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
 696	/* enable automatic padding and CRC operations */
 697	if (priv->full_duplex) {
 698		locked_regb_write(priv, MACON3,
 699				    MACON3_PADCFG0 | MACON3_TXCRCEN |
 700				    MACON3_FRMLNEN | MACON3_FULDPX);
 701		/* set inter-frame gap (non-back-to-back) */
 702		locked_regb_write(priv, MAIPGL, 0x12);
 703		/* set inter-frame gap (back-to-back) */
 704		locked_regb_write(priv, MABBIPG, 0x15);
 705	} else {
 706		locked_regb_write(priv, MACON3,
 707				    MACON3_PADCFG0 | MACON3_TXCRCEN |
 708				    MACON3_FRMLNEN);
 709		locked_regb_write(priv, MACON4, 1 << 6);	/* DEFER bit */
 710		/* set inter-frame gap (non-back-to-back) */
 711		locked_regw_write(priv, MAIPGL, 0x0C12);
 712		/* set inter-frame gap (back-to-back) */
 713		locked_regb_write(priv, MABBIPG, 0x12);
 714	}
 715	/*
 716	 * MACLCON1 (default)
 717	 * MACLCON2 (default)
 718	 * Set the maximum packet size which the controller will accept.
 719	 */
 720	locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
 721
 722	/* Configure LEDs */
 723	if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
 724		return 0;
 725
 726	if (priv->full_duplex) {
 727		if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
 728			return 0;
 729		if (!enc28j60_phy_write(priv, PHCON2, 0x00))
 730			return 0;
 731	} else {
 732		if (!enc28j60_phy_write(priv, PHCON1, 0x00))
 733			return 0;
 734		if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
 735			return 0;
 736	}
 737	if (netif_msg_hw(priv))
 738		enc28j60_dump_regs(priv, "Hw initialized.");
 739
 740	return 1;
 741}
 742
 743static void enc28j60_hw_enable(struct enc28j60_net *priv)
 744{
 745	struct device *dev = &priv->spi->dev;
 746
 747	/* enable interrupts */
 748	if (netif_msg_hw(priv))
 749		dev_printk(KERN_DEBUG, dev, "%s() enabling interrupts.\n",
 750			   __func__);
 751
 752	enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
 753
 754	mutex_lock(&priv->lock);
 755	nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
 756			 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
 757	nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
 758			  EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
 759
 760	/* enable receive logic */
 761	nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
 762	priv->hw_enable = true;
 763	mutex_unlock(&priv->lock);
 764}
 765
 766static void enc28j60_hw_disable(struct enc28j60_net *priv)
 767{
 768	mutex_lock(&priv->lock);
 769	/* disable interrupts and packet reception */
 770	nolock_regb_write(priv, EIE, 0x00);
 771	nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 772	priv->hw_enable = false;
 773	mutex_unlock(&priv->lock);
 774}
 775
 776static int
 777enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
 778{
 779	struct enc28j60_net *priv = netdev_priv(ndev);
 780	int ret = 0;
 781
 782	if (!priv->hw_enable) {
 783		/* link is in low power mode now; duplex setting
 784		 * will take effect on next enc28j60_hw_init().
 785		 */
 786		if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
 787			priv->full_duplex = (duplex == DUPLEX_FULL);
 788		else {
 789			if (netif_msg_link(priv))
 790				netdev_warn(ndev, "unsupported link setting\n");
 791			ret = -EOPNOTSUPP;
 792		}
 793	} else {
 794		if (netif_msg_link(priv))
 795			netdev_warn(ndev, "Warning: hw must be disabled to set link mode\n");
 796		ret = -EBUSY;
 797	}
 798	return ret;
 799}
 800
 801/*
 802 * Read the Transmit Status Vector
 803 */
 804static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
 805{
 806	struct device *dev = &priv->spi->dev;
 807	int endptr;
 808
 809	endptr = locked_regw_read(priv, ETXNDL);
 810	if (netif_msg_hw(priv))
 811		dev_printk(KERN_DEBUG, dev, "reading TSV at addr:0x%04x\n",
 812			   endptr + 1);
 813	enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
 814}
 815
 816static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
 817			      u8 tsv[TSV_SIZE])
 818{
 819	struct device *dev = &priv->spi->dev;
 820	u16 tmp1, tmp2;
 821
 822	dev_printk(KERN_DEBUG, dev, "%s - TSV:\n", msg);
 823	tmp1 = tsv[1];
 824	tmp1 <<= 8;
 825	tmp1 |= tsv[0];
 826
 827	tmp2 = tsv[5];
 828	tmp2 <<= 8;
 829	tmp2 |= tsv[4];
 830
 831	dev_printk(KERN_DEBUG, dev,
 832		   "ByteCount: %d, CollisionCount: %d, TotByteOnWire: %d\n",
 833		   tmp1, tsv[2] & 0x0f, tmp2);
 834	dev_printk(KERN_DEBUG, dev,
 835		   "TxDone: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
 836		   TSV_GETBIT(tsv, TSV_TXDONE),
 837		   TSV_GETBIT(tsv, TSV_TXCRCERROR),
 838		   TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
 839		   TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
 840	dev_printk(KERN_DEBUG, dev,
 841		   "Multicast: %d, Broadcast: %d, PacketDefer: %d, ExDefer: %d\n",
 842		   TSV_GETBIT(tsv, TSV_TXMULTICAST),
 843		   TSV_GETBIT(tsv, TSV_TXBROADCAST),
 844		   TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
 845		   TSV_GETBIT(tsv, TSV_TXEXDEFER));
 846	dev_printk(KERN_DEBUG, dev,
 847		   "ExCollision: %d, LateCollision: %d, Giant: %d, Underrun: %d\n",
 848		   TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
 849		   TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
 850		   TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
 851	dev_printk(KERN_DEBUG, dev,
 852		   "ControlFrame: %d, PauseFrame: %d, BackPressApp: %d, VLanTagFrame: %d\n",
 853		   TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
 854		   TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
 855		   TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
 856		   TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
 857}
 858
 859/*
 860 * Receive Status vector
 861 */
 862static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
 863			      u16 pk_ptr, int len, u16 sts)
 864{
 865	struct device *dev = &priv->spi->dev;
 866
 867	dev_printk(KERN_DEBUG, dev, "%s - NextPk: 0x%04x - RSV:\n", msg, pk_ptr);
 868	dev_printk(KERN_DEBUG, dev, "ByteCount: %d, DribbleNibble: %d\n",
 869		   len, RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
 870	dev_printk(KERN_DEBUG, dev,
 871		   "RxOK: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
 872		   RSV_GETBIT(sts, RSV_RXOK),
 873		   RSV_GETBIT(sts, RSV_CRCERROR),
 874		   RSV_GETBIT(sts, RSV_LENCHECKERR),
 875		   RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
 876	dev_printk(KERN_DEBUG, dev,
 877		   "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
 878		   RSV_GETBIT(sts, RSV_RXMULTICAST),
 879		   RSV_GETBIT(sts, RSV_RXBROADCAST),
 880		   RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
 881		   RSV_GETBIT(sts, RSV_CARRIEREV));
 882	dev_printk(KERN_DEBUG, dev,
 883		   "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
 884		   RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
 885		   RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
 886		   RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
 887		   RSV_GETBIT(sts, RSV_RXTYPEVLAN));
 888}
 889
 890static void dump_packet(const char *msg, int len, const char *data)
 891{
 892	printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
 893	print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
 894			data, len, true);
 895}
 896
 897/*
 898 * Hardware receive function.
 899 * Read the buffer memory, update the FIFO pointer to free the buffer,
 900 * check the status vector and decrement the packet counter.
 901 */
 902static void enc28j60_hw_rx(struct net_device *ndev)
 903{
 904	struct enc28j60_net *priv = netdev_priv(ndev);
 905	struct device *dev = &priv->spi->dev;
 906	struct sk_buff *skb = NULL;
 907	u16 erxrdpt, next_packet, rxstat;
 908	u8 rsv[RSV_SIZE];
 909	int len;
 910
 911	if (netif_msg_rx_status(priv))
 912		netdev_printk(KERN_DEBUG, ndev, "RX pk_addr:0x%04x\n",
 913			      priv->next_pk_ptr);
 914
 915	if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
 916		if (netif_msg_rx_err(priv))
 917			netdev_err(ndev, "%s() Invalid packet address!! 0x%04x\n",
 918				   __func__, priv->next_pk_ptr);
 919		/* packet address corrupted: reset RX logic */
 920		mutex_lock(&priv->lock);
 921		nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 922		nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
 923		nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
 924		nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
 925		nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
 926		nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
 927		mutex_unlock(&priv->lock);
 928		ndev->stats.rx_errors++;
 929		return;
 930	}
 931	/* Read next packet pointer and rx status vector */
 932	enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
 933
 934	next_packet = rsv[1];
 935	next_packet <<= 8;
 936	next_packet |= rsv[0];
 937
 938	len = rsv[3];
 939	len <<= 8;
 940	len |= rsv[2];
 941
 942	rxstat = rsv[5];
 943	rxstat <<= 8;
 944	rxstat |= rsv[4];
 945
 946	if (netif_msg_rx_status(priv))
 947		enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
 948
 949	if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
 950		if (netif_msg_rx_err(priv))
 951			netdev_err(ndev, "Rx Error (%04x)\n", rxstat);
 952		ndev->stats.rx_errors++;
 953		if (RSV_GETBIT(rxstat, RSV_CRCERROR))
 954			ndev->stats.rx_crc_errors++;
 955		if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
 956			ndev->stats.rx_frame_errors++;
 957		if (len > MAX_FRAMELEN)
 958			ndev->stats.rx_over_errors++;
 959	} else {
 960		skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN);
 961		if (!skb) {
 962			if (netif_msg_rx_err(priv))
 963				netdev_err(ndev, "out of memory for Rx'd frame\n");
 964			ndev->stats.rx_dropped++;
 965		} else {
 966			skb_reserve(skb, NET_IP_ALIGN);
 967			/* copy the packet from the receive buffer */
 968			enc28j60_mem_read(priv,
 969				rx_packet_start(priv->next_pk_ptr),
 970				len, skb_put(skb, len));
 971			if (netif_msg_pktdata(priv))
 972				dump_packet(__func__, skb->len, skb->data);
 973			skb->protocol = eth_type_trans(skb, ndev);
 974			/* update statistics */
 975			ndev->stats.rx_packets++;
 976			ndev->stats.rx_bytes += len;
 977			netif_rx(skb);
 978		}
 979	}
 980	/*
 981	 * Move the RX read pointer to the start of the next
 982	 * received packet.
 983	 * This frees the memory we just read out.
 984	 */
 985	erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
 986	if (netif_msg_hw(priv))
 987		dev_printk(KERN_DEBUG, dev, "%s() ERXRDPT:0x%04x\n",
 988			   __func__, erxrdpt);
 989
 990	mutex_lock(&priv->lock);
 991	nolock_regw_write(priv, ERXRDPTL, erxrdpt);
 992#ifdef CONFIG_ENC28J60_WRITEVERIFY
 993	if (netif_msg_drv(priv)) {
 994		u16 reg;
 995		reg = nolock_regw_read(priv, ERXRDPTL);
 996		if (reg != erxrdpt)
 997			dev_printk(KERN_DEBUG, dev,
 998				   "%s() ERXRDPT verify error (0x%04x - 0x%04x)\n",
 999				   __func__, reg, erxrdpt);
1000	}
1001#endif
1002	priv->next_pk_ptr = next_packet;
1003	/* we are done with this packet, decrement the packet counter */
1004	nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1005	mutex_unlock(&priv->lock);
1006}
1007
1008/*
1009 * Calculate free space in RxFIFO
1010 */
1011static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1012{
1013	struct net_device *ndev = priv->netdev;
1014	int epkcnt, erxst, erxnd, erxwr, erxrd;
1015	int free_space;
1016
1017	mutex_lock(&priv->lock);
1018	epkcnt = nolock_regb_read(priv, EPKTCNT);
1019	if (epkcnt >= 255)
1020		free_space = -1;
1021	else {
1022		erxst = nolock_regw_read(priv, ERXSTL);
1023		erxnd = nolock_regw_read(priv, ERXNDL);
1024		erxwr = nolock_regw_read(priv, ERXWRPTL);
1025		erxrd = nolock_regw_read(priv, ERXRDPTL);
1026
1027		if (erxwr > erxrd)
1028			free_space = (erxnd - erxst) - (erxwr - erxrd);
1029		else if (erxwr == erxrd)
1030			free_space = (erxnd - erxst);
1031		else
1032			free_space = erxrd - erxwr - 1;
1033	}
1034	mutex_unlock(&priv->lock);
1035	if (netif_msg_rx_status(priv))
1036		netdev_printk(KERN_DEBUG, ndev, "%s() free_space = %d\n",
1037			      __func__, free_space);
1038	return free_space;
1039}
1040
1041/*
1042 * Access the PHY to determine link status
1043 */
1044static void enc28j60_check_link_status(struct net_device *ndev)
1045{
1046	struct enc28j60_net *priv = netdev_priv(ndev);
1047	struct device *dev = &priv->spi->dev;
1048	u16 reg;
1049	int duplex;
1050
1051	reg = enc28j60_phy_read(priv, PHSTAT2);
1052	if (netif_msg_hw(priv))
1053		dev_printk(KERN_DEBUG, dev,
1054			   "%s() PHSTAT1: %04x, PHSTAT2: %04x\n", __func__,
1055			   enc28j60_phy_read(priv, PHSTAT1), reg);
1056	duplex = reg & PHSTAT2_DPXSTAT;
1057
1058	if (reg & PHSTAT2_LSTAT) {
1059		netif_carrier_on(ndev);
1060		if (netif_msg_ifup(priv))
1061			netdev_info(ndev, "link up - %s\n",
1062				    duplex ? "Full duplex" : "Half duplex");
1063	} else {
1064		if (netif_msg_ifdown(priv))
1065			netdev_info(ndev, "link down\n");
1066		netif_carrier_off(ndev);
1067	}
1068}
1069
1070static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1071{
1072	struct enc28j60_net *priv = netdev_priv(ndev);
1073
1074	if (err)
1075		ndev->stats.tx_errors++;
1076	else
1077		ndev->stats.tx_packets++;
1078
1079	if (priv->tx_skb) {
1080		if (!err)
1081			ndev->stats.tx_bytes += priv->tx_skb->len;
1082		dev_kfree_skb(priv->tx_skb);
1083		priv->tx_skb = NULL;
1084	}
1085	locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1086	netif_wake_queue(ndev);
1087}
1088
1089/*
1090 * RX handler
1091 * Ignore PKTIF because is unreliable! (Look at the errata datasheet)
1092 * Check EPKTCNT is the suggested workaround.
1093 * We don't need to clear interrupt flag, automatically done when
1094 * enc28j60_hw_rx() decrements the packet counter.
1095 * Returns how many packet processed.
1096 */
1097static int enc28j60_rx_interrupt(struct net_device *ndev)
1098{
1099	struct enc28j60_net *priv = netdev_priv(ndev);
1100	int pk_counter, ret;
1101
1102	pk_counter = locked_regb_read(priv, EPKTCNT);
1103	if (pk_counter && netif_msg_intr(priv))
1104		netdev_printk(KERN_DEBUG, ndev, "intRX, pk_cnt: %d\n",
1105			      pk_counter);
1106	if (pk_counter > priv->max_pk_counter) {
1107		/* update statistics */
1108		priv->max_pk_counter = pk_counter;
1109		if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1110			netdev_printk(KERN_DEBUG, ndev, "RX max_pk_cnt: %d\n",
1111				      priv->max_pk_counter);
1112	}
1113	ret = pk_counter;
1114	while (pk_counter-- > 0)
1115		enc28j60_hw_rx(ndev);
1116
1117	return ret;
1118}
1119
1120static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1121{
1122	struct enc28j60_net *priv = dev_id;
1123	struct net_device *ndev = priv->netdev;
1124	int intflags, loop;
1125
1126	/* disable further interrupts */
1127	locked_reg_bfclr(priv, EIE, EIE_INTIE);
1128
1129	do {
1130		loop = 0;
1131		intflags = locked_regb_read(priv, EIR);
1132		/* DMA interrupt handler (not currently used) */
1133		if ((intflags & EIR_DMAIF) != 0) {
1134			loop++;
1135			if (netif_msg_intr(priv))
1136				netdev_printk(KERN_DEBUG, ndev, "intDMA(%d)\n",
1137					      loop);
1138			locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1139		}
1140		/* LINK changed handler */
1141		if ((intflags & EIR_LINKIF) != 0) {
1142			loop++;
1143			if (netif_msg_intr(priv))
1144				netdev_printk(KERN_DEBUG, ndev, "intLINK(%d)\n",
1145					      loop);
1146			enc28j60_check_link_status(ndev);
1147			/* read PHIR to clear the flag */
1148			enc28j60_phy_read(priv, PHIR);
1149		}
1150		/* TX complete handler */
1151		if (((intflags & EIR_TXIF) != 0) &&
1152		    ((intflags & EIR_TXERIF) == 0)) {
1153			bool err = false;
1154			loop++;
1155			if (netif_msg_intr(priv))
1156				netdev_printk(KERN_DEBUG, ndev, "intTX(%d)\n",
1157					      loop);
1158			priv->tx_retry_count = 0;
1159			if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1160				if (netif_msg_tx_err(priv))
1161					netdev_err(ndev, "Tx Error (aborted)\n");
1162				err = true;
1163			}
1164			if (netif_msg_tx_done(priv)) {
1165				u8 tsv[TSV_SIZE];
1166				enc28j60_read_tsv(priv, tsv);
1167				enc28j60_dump_tsv(priv, "Tx Done", tsv);
1168			}
1169			enc28j60_tx_clear(ndev, err);
1170			locked_reg_bfclr(priv, EIR, EIR_TXIF);
1171		}
1172		/* TX Error handler */
1173		if ((intflags & EIR_TXERIF) != 0) {
1174			u8 tsv[TSV_SIZE];
1175
1176			loop++;
1177			if (netif_msg_intr(priv))
1178				netdev_printk(KERN_DEBUG, ndev, "intTXErr(%d)\n",
1179					      loop);
1180			locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1181			enc28j60_read_tsv(priv, tsv);
1182			if (netif_msg_tx_err(priv))
1183				enc28j60_dump_tsv(priv, "Tx Error", tsv);
1184			/* Reset TX logic */
1185			mutex_lock(&priv->lock);
1186			nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1187			nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1188			nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1189			mutex_unlock(&priv->lock);
1190			/* Transmit Late collision check for retransmit */
1191			if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1192				if (netif_msg_tx_err(priv))
1193					netdev_printk(KERN_DEBUG, ndev,
1194						      "LateCollision TXErr (%d)\n",
1195						      priv->tx_retry_count);
1196				if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1197					locked_reg_bfset(priv, ECON1,
1198							   ECON1_TXRTS);
1199				else
1200					enc28j60_tx_clear(ndev, true);
1201			} else
1202				enc28j60_tx_clear(ndev, true);
1203			locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF);
1204		}
1205		/* RX Error handler */
1206		if ((intflags & EIR_RXERIF) != 0) {
1207			loop++;
1208			if (netif_msg_intr(priv))
1209				netdev_printk(KERN_DEBUG, ndev, "intRXErr(%d)\n",
1210					      loop);
1211			/* Check free FIFO space to flag RX overrun */
1212			if (enc28j60_get_free_rxfifo(priv) <= 0) {
1213				if (netif_msg_rx_err(priv))
1214					netdev_printk(KERN_DEBUG, ndev, "RX Overrun\n");
1215				ndev->stats.rx_dropped++;
1216			}
1217			locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1218		}
1219		/* RX handler */
1220		if (enc28j60_rx_interrupt(ndev))
1221			loop++;
1222	} while (loop);
1223
1224	/* re-enable interrupts */
1225	locked_reg_bfset(priv, EIE, EIE_INTIE);
1226
1227	return IRQ_HANDLED;
1228}
1229
1230/*
1231 * Hardware transmit function.
1232 * Fill the buffer memory and send the contents of the transmit buffer
1233 * onto the network
1234 */
1235static void enc28j60_hw_tx(struct enc28j60_net *priv)
1236{
1237	struct net_device *ndev = priv->netdev;
1238
1239	BUG_ON(!priv->tx_skb);
1240
1241	if (netif_msg_tx_queued(priv))
1242		netdev_printk(KERN_DEBUG, ndev, "Tx Packet Len:%d\n",
1243			      priv->tx_skb->len);
1244
1245	if (netif_msg_pktdata(priv))
1246		dump_packet(__func__,
1247			    priv->tx_skb->len, priv->tx_skb->data);
1248	enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1249
1250#ifdef CONFIG_ENC28J60_WRITEVERIFY
1251	/* readback and verify written data */
1252	if (netif_msg_drv(priv)) {
1253		struct device *dev = &priv->spi->dev;
1254		int test_len, k;
1255		u8 test_buf[64]; /* limit the test to the first 64 bytes */
1256		int okflag;
1257
1258		test_len = priv->tx_skb->len;
1259		if (test_len > sizeof(test_buf))
1260			test_len = sizeof(test_buf);
1261
1262		/* + 1 to skip control byte */
1263		enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1264		okflag = 1;
1265		for (k = 0; k < test_len; k++) {
1266			if (priv->tx_skb->data[k] != test_buf[k]) {
1267				dev_printk(KERN_DEBUG, dev,
1268					   "Error, %d location differ: 0x%02x-0x%02x\n",
1269					   k, priv->tx_skb->data[k], test_buf[k]);
1270				okflag = 0;
1271			}
1272		}
1273		if (!okflag)
1274			dev_printk(KERN_DEBUG, dev, "Tx write buffer, verify ERROR!\n");
1275	}
1276#endif
1277	/* set TX request flag */
1278	locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1279}
1280
1281static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1282					struct net_device *dev)
1283{
1284	struct enc28j60_net *priv = netdev_priv(dev);
1285
1286	/* If some error occurs while trying to transmit this
1287	 * packet, you should return '1' from this function.
1288	 * In such a case you _may not_ do anything to the
1289	 * SKB, it is still owned by the network queueing
1290	 * layer when an error is returned. This means you
1291	 * may not modify any SKB fields, you may not free
1292	 * the SKB, etc.
1293	 */
1294	netif_stop_queue(dev);
1295
1296	/* Remember the skb for deferred processing */
1297	priv->tx_skb = skb;
1298	schedule_work(&priv->tx_work);
1299
1300	return NETDEV_TX_OK;
1301}
1302
1303static void enc28j60_tx_work_handler(struct work_struct *work)
1304{
1305	struct enc28j60_net *priv =
1306		container_of(work, struct enc28j60_net, tx_work);
1307
1308	/* actual delivery of data */
1309	enc28j60_hw_tx(priv);
1310}
1311
1312static void enc28j60_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1313{
1314	struct enc28j60_net *priv = netdev_priv(ndev);
1315
1316	if (netif_msg_timer(priv))
1317		netdev_err(ndev, "tx timeout\n");
1318
1319	ndev->stats.tx_errors++;
1320	/* can't restart safely under softirq */
1321	schedule_work(&priv->restart_work);
1322}
1323
1324/*
1325 * Open/initialize the board. This is called (in the current kernel)
1326 * sometime after booting when the 'ifconfig' program is run.
1327 *
1328 * This routine should set everything up anew at each open, even
1329 * registers that "should" only need to be set once at boot, so that
1330 * there is non-reboot way to recover if something goes wrong.
1331 */
1332static int enc28j60_net_open(struct net_device *dev)
1333{
1334	struct enc28j60_net *priv = netdev_priv(dev);
1335
1336	if (!is_valid_ether_addr(dev->dev_addr)) {
1337		if (netif_msg_ifup(priv))
1338			netdev_err(dev, "invalid MAC address %pM\n", dev->dev_addr);
1339		return -EADDRNOTAVAIL;
1340	}
1341	/* Reset the hardware here (and take it out of low power mode) */
1342	enc28j60_lowpower(priv, false);
1343	enc28j60_hw_disable(priv);
1344	if (!enc28j60_hw_init(priv)) {
1345		if (netif_msg_ifup(priv))
1346			netdev_err(dev, "hw_reset() failed\n");
1347		return -EINVAL;
1348	}
1349	/* Update the MAC address (in case user has changed it) */
1350	enc28j60_set_hw_macaddr(dev);
1351	/* Enable interrupts */
1352	enc28j60_hw_enable(priv);
1353	/* check link status */
1354	enc28j60_check_link_status(dev);
1355	/* We are now ready to accept transmit requests from
1356	 * the queueing layer of the networking.
1357	 */
1358	netif_start_queue(dev);
1359
1360	return 0;
1361}
1362
1363/* The inverse routine to net_open(). */
1364static int enc28j60_net_close(struct net_device *dev)
1365{
1366	struct enc28j60_net *priv = netdev_priv(dev);
1367
1368	enc28j60_hw_disable(priv);
1369	enc28j60_lowpower(priv, true);
1370	netif_stop_queue(dev);
1371
1372	return 0;
1373}
1374
1375/*
1376 * Set or clear the multicast filter for this adapter
1377 * num_addrs == -1	Promiscuous mode, receive all packets
1378 * num_addrs == 0	Normal mode, filter out multicast packets
1379 * num_addrs > 0	Multicast mode, receive normal and MC packets
1380 */
1381static void enc28j60_set_multicast_list(struct net_device *dev)
1382{
1383	struct enc28j60_net *priv = netdev_priv(dev);
1384	int oldfilter = priv->rxfilter;
1385
1386	if (dev->flags & IFF_PROMISC) {
1387		if (netif_msg_link(priv))
1388			netdev_info(dev, "promiscuous mode\n");
1389		priv->rxfilter = RXFILTER_PROMISC;
1390	} else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
1391		if (netif_msg_link(priv))
1392			netdev_info(dev, "%smulticast mode\n",
1393				    (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1394		priv->rxfilter = RXFILTER_MULTI;
1395	} else {
1396		if (netif_msg_link(priv))
1397			netdev_info(dev, "normal mode\n");
1398		priv->rxfilter = RXFILTER_NORMAL;
1399	}
1400
1401	if (oldfilter != priv->rxfilter)
1402		schedule_work(&priv->setrx_work);
1403}
1404
1405static void enc28j60_setrx_work_handler(struct work_struct *work)
1406{
1407	struct enc28j60_net *priv =
1408		container_of(work, struct enc28j60_net, setrx_work);
1409	struct device *dev = &priv->spi->dev;
1410
1411	if (priv->rxfilter == RXFILTER_PROMISC) {
1412		if (netif_msg_drv(priv))
1413			dev_printk(KERN_DEBUG, dev, "promiscuous mode\n");
1414		locked_regb_write(priv, ERXFCON, 0x00);
1415	} else if (priv->rxfilter == RXFILTER_MULTI) {
1416		if (netif_msg_drv(priv))
1417			dev_printk(KERN_DEBUG, dev, "multicast mode\n");
1418		locked_regb_write(priv, ERXFCON,
1419					ERXFCON_UCEN | ERXFCON_CRCEN |
1420					ERXFCON_BCEN | ERXFCON_MCEN);
1421	} else {
1422		if (netif_msg_drv(priv))
1423			dev_printk(KERN_DEBUG, dev, "normal mode\n");
1424		locked_regb_write(priv, ERXFCON,
1425					ERXFCON_UCEN | ERXFCON_CRCEN |
1426					ERXFCON_BCEN);
1427	}
1428}
1429
1430static void enc28j60_restart_work_handler(struct work_struct *work)
1431{
1432	struct enc28j60_net *priv =
1433			container_of(work, struct enc28j60_net, restart_work);
1434	struct net_device *ndev = priv->netdev;
1435	int ret;
1436
1437	rtnl_lock();
1438	if (netif_running(ndev)) {
1439		enc28j60_net_close(ndev);
1440		ret = enc28j60_net_open(ndev);
1441		if (unlikely(ret)) {
1442			netdev_info(ndev, "could not restart %d\n", ret);
1443			dev_close(ndev);
1444		}
1445	}
1446	rtnl_unlock();
1447}
1448
1449/* ......................... ETHTOOL SUPPORT ........................... */
1450
1451static void
1452enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1453{
1454	strscpy(info->driver, DRV_NAME, sizeof(info->driver));
1455	strscpy(info->version, DRV_VERSION, sizeof(info->version));
1456	strscpy(info->bus_info,
1457		dev_name(dev->dev.parent), sizeof(info->bus_info));
1458}
1459
1460static int
1461enc28j60_get_link_ksettings(struct net_device *dev,
1462			    struct ethtool_link_ksettings *cmd)
1463{
1464	struct enc28j60_net *priv = netdev_priv(dev);
1465
1466	ethtool_link_ksettings_zero_link_mode(cmd, supported);
1467	ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Half);
1468	ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Full);
1469	ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
1470
1471	cmd->base.speed = SPEED_10;
1472	cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1473	cmd->base.port	= PORT_TP;
1474	cmd->base.autoneg = AUTONEG_DISABLE;
1475
1476	return 0;
1477}
1478
1479static int
1480enc28j60_set_link_ksettings(struct net_device *dev,
1481			    const struct ethtool_link_ksettings *cmd)
1482{
1483	return enc28j60_setlink(dev, cmd->base.autoneg,
1484				cmd->base.speed, cmd->base.duplex);
1485}
1486
1487static u32 enc28j60_get_msglevel(struct net_device *dev)
1488{
1489	struct enc28j60_net *priv = netdev_priv(dev);
1490	return priv->msg_enable;
1491}
1492
1493static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1494{
1495	struct enc28j60_net *priv = netdev_priv(dev);
1496	priv->msg_enable = val;
1497}
1498
1499static const struct ethtool_ops enc28j60_ethtool_ops = {
1500	.get_drvinfo	= enc28j60_get_drvinfo,
1501	.get_msglevel	= enc28j60_get_msglevel,
1502	.set_msglevel	= enc28j60_set_msglevel,
1503	.get_link_ksettings = enc28j60_get_link_ksettings,
1504	.set_link_ksettings = enc28j60_set_link_ksettings,
1505};
1506
1507static int enc28j60_chipset_init(struct net_device *dev)
1508{
1509	struct enc28j60_net *priv = netdev_priv(dev);
1510
1511	return enc28j60_hw_init(priv);
1512}
1513
1514static const struct net_device_ops enc28j60_netdev_ops = {
1515	.ndo_open		= enc28j60_net_open,
1516	.ndo_stop		= enc28j60_net_close,
1517	.ndo_start_xmit		= enc28j60_send_packet,
1518	.ndo_set_rx_mode	= enc28j60_set_multicast_list,
1519	.ndo_set_mac_address	= enc28j60_set_mac_address,
1520	.ndo_tx_timeout		= enc28j60_tx_timeout,
1521	.ndo_validate_addr	= eth_validate_addr,
1522};
1523
1524static int enc28j60_probe(struct spi_device *spi)
1525{
1526	struct net_device *dev;
1527	struct enc28j60_net *priv;
1528	int ret = 0;
1529
1530	if (netif_msg_drv(&debug))
1531		dev_info(&spi->dev, "Ethernet driver %s loaded\n", DRV_VERSION);
1532
1533	dev = alloc_etherdev(sizeof(struct enc28j60_net));
1534	if (!dev) {
1535		ret = -ENOMEM;
1536		goto error_alloc;
1537	}
1538	priv = netdev_priv(dev);
1539
1540	priv->netdev = dev;	/* priv to netdev reference */
1541	priv->spi = spi;	/* priv to spi reference */
1542	priv->msg_enable = netif_msg_init(debug.msg_enable, ENC28J60_MSG_DEFAULT);
1543	mutex_init(&priv->lock);
1544	INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1545	INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1546	INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1547	spi_set_drvdata(spi, priv);	/* spi to priv reference */
1548	SET_NETDEV_DEV(dev, &spi->dev);
1549
1550	if (!enc28j60_chipset_init(dev)) {
1551		if (netif_msg_probe(priv))
1552			dev_info(&spi->dev, "chip not found\n");
1553		ret = -EIO;
1554		goto error_irq;
1555	}
1556
1557	if (device_get_ethdev_address(&spi->dev, dev))
1558		eth_hw_addr_random(dev);
1559	enc28j60_set_hw_macaddr(dev);
1560
1561	/* Board setup must set the relevant edge trigger type;
1562	 * level triggers won't currently work.
1563	 */
1564	ret = request_threaded_irq(spi->irq, NULL, enc28j60_irq, IRQF_ONESHOT,
1565				   DRV_NAME, priv);
1566	if (ret < 0) {
1567		if (netif_msg_probe(priv))
1568			dev_err(&spi->dev, "request irq %d failed (ret = %d)\n",
1569				spi->irq, ret);
1570		goto error_irq;
1571	}
1572
1573	dev->if_port = IF_PORT_10BASET;
1574	dev->irq = spi->irq;
1575	dev->netdev_ops = &enc28j60_netdev_ops;
1576	dev->watchdog_timeo = TX_TIMEOUT;
1577	dev->ethtool_ops = &enc28j60_ethtool_ops;
1578
1579	enc28j60_lowpower(priv, true);
1580
1581	ret = register_netdev(dev);
1582	if (ret) {
1583		if (netif_msg_probe(priv))
1584			dev_err(&spi->dev, "register netdev failed (ret = %d)\n",
1585				ret);
1586		goto error_register;
1587	}
1588
1589	return 0;
1590
1591error_register:
1592	free_irq(spi->irq, priv);
1593error_irq:
1594	free_netdev(dev);
1595error_alloc:
1596	return ret;
1597}
1598
1599static void enc28j60_remove(struct spi_device *spi)
1600{
1601	struct enc28j60_net *priv = spi_get_drvdata(spi);
1602
1603	unregister_netdev(priv->netdev);
1604	free_irq(spi->irq, priv);
1605	free_netdev(priv->netdev);
1606}
1607
1608static const struct of_device_id enc28j60_dt_ids[] = {
1609	{ .compatible = "microchip,enc28j60" },
1610	{ /* sentinel */ }
1611};
1612MODULE_DEVICE_TABLE(of, enc28j60_dt_ids);
1613
1614static struct spi_driver enc28j60_driver = {
1615	.driver = {
1616		.name = DRV_NAME,
1617		.of_match_table = enc28j60_dt_ids,
1618	 },
1619	.probe = enc28j60_probe,
1620	.remove = enc28j60_remove,
1621};
1622module_spi_driver(enc28j60_driver);
1623
1624MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1625MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1626MODULE_LICENSE("GPL");
1627module_param_named(debug, debug.msg_enable, int, 0);
1628MODULE_PARM_DESC(debug, "Debug verbosity level in amount of bits set (0=none, ..., 31=all)");
1629MODULE_ALIAS("spi:" DRV_NAME);