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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2021, Intel Corporation. */
3
4#ifndef _ICE_PTP_HW_H_
5#define _ICE_PTP_HW_H_
6#include <linux/dpll.h>
7
8enum ice_ptp_tmr_cmd {
9 ICE_PTP_INIT_TIME,
10 ICE_PTP_INIT_INCVAL,
11 ICE_PTP_ADJ_TIME,
12 ICE_PTP_ADJ_TIME_AT_TIME,
13 ICE_PTP_READ_TIME,
14 ICE_PTP_NOP,
15};
16
17enum ice_ptp_serdes {
18 ICE_PTP_SERDES_1G,
19 ICE_PTP_SERDES_10G,
20 ICE_PTP_SERDES_25G,
21 ICE_PTP_SERDES_40G,
22 ICE_PTP_SERDES_50G,
23 ICE_PTP_SERDES_100G
24};
25
26enum ice_ptp_link_spd {
27 ICE_PTP_LNK_SPD_1G,
28 ICE_PTP_LNK_SPD_10G,
29 ICE_PTP_LNK_SPD_25G,
30 ICE_PTP_LNK_SPD_25G_RS,
31 ICE_PTP_LNK_SPD_40G,
32 ICE_PTP_LNK_SPD_50G,
33 ICE_PTP_LNK_SPD_50G_RS,
34 ICE_PTP_LNK_SPD_100G_RS,
35 NUM_ICE_PTP_LNK_SPD /* Must be last */
36};
37
38enum ice_ptp_fec_mode {
39 ICE_PTP_FEC_MODE_NONE,
40 ICE_PTP_FEC_MODE_CLAUSE74,
41 ICE_PTP_FEC_MODE_RS_FEC
42};
43
44enum eth56g_res_type {
45 ETH56G_PHY_REG_PTP,
46 ETH56G_PHY_MEM_PTP,
47 ETH56G_PHY_REG_XPCS,
48 ETH56G_PHY_REG_MAC,
49 ETH56G_PHY_REG_GPCS,
50 NUM_ETH56G_PHY_RES
51};
52
53enum ice_eth56g_link_spd {
54 ICE_ETH56G_LNK_SPD_1G,
55 ICE_ETH56G_LNK_SPD_2_5G,
56 ICE_ETH56G_LNK_SPD_10G,
57 ICE_ETH56G_LNK_SPD_25G,
58 ICE_ETH56G_LNK_SPD_40G,
59 ICE_ETH56G_LNK_SPD_50G,
60 ICE_ETH56G_LNK_SPD_50G2,
61 ICE_ETH56G_LNK_SPD_100G,
62 ICE_ETH56G_LNK_SPD_100G2,
63 NUM_ICE_ETH56G_LNK_SPD /* Must be last */
64};
65
66/**
67 * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
68 * @base: base address for each PHY block
69 * @step: step between PHY lanes
70 *
71 * Characteristic information for the various PHY register parameters in the
72 * ETH56G devices
73 */
74struct ice_phy_reg_info_eth56g {
75 u32 base[NUM_ETH56G_PHY_RES];
76 u32 step;
77};
78
79/**
80 * struct ice_time_ref_info_e82x
81 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
82 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
83 * @pps_delay: propagation delay of the PPS output signal
84 *
85 * Characteristic information for the various TIME_REF sources possible in the
86 * E822 devices
87 */
88struct ice_time_ref_info_e82x {
89 u64 pll_freq;
90 u64 nominal_incval;
91 u8 pps_delay;
92};
93
94/**
95 * struct ice_vernier_info_e82x
96 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
97 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
98 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
99 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
100 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
101 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
102 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
103 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
104 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
105 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
106 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
107 *
108 * Table of constants used during as part of the Vernier calibration of the Tx
109 * and Rx timestamps. This includes frequency values used to compute TUs per
110 * PAR/PCS clock cycle, and static delay values measured during hardware
111 * design.
112 *
113 * Note that some values are not used for all link speeds, and the
114 * P_REG_DESK_PAR* registers may represent different clock markers at
115 * different link speeds, either the deskew marker for multi-lane link speeds
116 * or the Reed Solomon gearbox marker for RS-FEC.
117 */
118struct ice_vernier_info_e82x {
119 u32 tx_par_clk;
120 u32 rx_par_clk;
121 u32 tx_pcs_clk;
122 u32 rx_pcs_clk;
123 u32 tx_desk_rsgb_par;
124 u32 rx_desk_rsgb_par;
125 u32 tx_desk_rsgb_pcs;
126 u32 rx_desk_rsgb_pcs;
127 u32 tx_fixed_delay;
128 u32 pmd_adj_divisor;
129 u32 rx_fixed_delay;
130};
131
132#define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT GENMASK(19, 9)
133#define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)
134#define ICE_ETH56G_MAC_CFG_FRAC_W 9
135/**
136 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
137 * @tx_mode: Tx timestamp compensation mode
138 * @tx_mk_dly: Tx timestamp marker start strobe delay
139 * @tx_cw_dly: Tx timestamp codeword start strobe delay
140 * @rx_mode: Rx timestamp compensation mode
141 * @rx_mk_dly: Rx timestamp marker start strobe delay
142 * @rx_cw_dly: Rx timestamp codeword start strobe delay
143 * @blks_per_clk: number of blocks transferred per clock cycle
144 * @blktime: block time, fixed point
145 * @mktime: marker time, fixed point
146 * @tx_offset: total Tx offset, fixed point
147 * @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point
148 *
149 * All fixed point registers except Rx offset are 23 bit unsigned ints with
150 * a 9 bit fractional.
151 * Rx offset is 11 bit unsigned int with a 9 bit fractional.
152 */
153struct ice_eth56g_mac_reg_cfg {
154 struct {
155 u8 def;
156 u8 rs;
157 } tx_mode;
158 u8 tx_mk_dly;
159 struct {
160 u8 def;
161 u8 onestep;
162 } tx_cw_dly;
163 struct {
164 u8 def;
165 u8 rs;
166 } rx_mode;
167 struct {
168 u8 def;
169 u8 rs;
170 } rx_mk_dly;
171 struct {
172 u8 def;
173 u8 rs;
174 } rx_cw_dly;
175 u8 blks_per_clk;
176 u16 blktime;
177 u16 mktime;
178 struct {
179 u32 serdes;
180 u32 no_fec;
181 u32 fc;
182 u32 rs;
183 u32 sfd;
184 u32 onestep;
185 } tx_offset;
186 struct {
187 u32 serdes;
188 u32 no_fec;
189 u32 fc;
190 u32 rs;
191 u32 sfd;
192 u32 bs_ds;
193 } rx_offset;
194};
195
196extern
197const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD];
198
199/**
200 * struct ice_cgu_pll_params_e82x - E82X CGU parameters
201 * @refclk_pre_div: Reference clock pre-divisor
202 * @feedback_div: Feedback divisor
203 * @frac_n_div: Fractional divisor
204 * @post_pll_div: Post PLL divisor
205 *
206 * Clock Generation Unit parameters used to program the PLL based on the
207 * selected TIME_REF frequency.
208 */
209struct ice_cgu_pll_params_e82x {
210 u32 refclk_pre_div;
211 u32 feedback_div;
212 u32 frac_n_div;
213 u32 post_pll_div;
214};
215
216#define E810C_QSFP_C827_0_HANDLE 2
217#define E810C_QSFP_C827_1_HANDLE 3
218enum ice_e810_c827_idx {
219 C827_0,
220 C827_1
221};
222
223enum ice_phy_rclk_pins {
224 ICE_RCLKA_PIN = 0, /* SCL pin */
225 ICE_RCLKB_PIN, /* SDA pin */
226};
227
228#define ICE_E810_RCLK_PINS_NUM (ICE_RCLKB_PIN + 1)
229#define ICE_E82X_RCLK_PINS_NUM (ICE_RCLKA_PIN + 1)
230#define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \
231 (_pin) + ZL_REF1P)
232
233enum ice_zl_cgu_in_pins {
234 ZL_REF0P = 0,
235 ZL_REF0N,
236 ZL_REF1P,
237 ZL_REF1N,
238 ZL_REF2P,
239 ZL_REF2N,
240 ZL_REF3P,
241 ZL_REF3N,
242 ZL_REF4P,
243 ZL_REF4N,
244 NUM_ZL_CGU_INPUT_PINS
245};
246
247enum ice_zl_cgu_out_pins {
248 ZL_OUT0 = 0,
249 ZL_OUT1,
250 ZL_OUT2,
251 ZL_OUT3,
252 ZL_OUT4,
253 ZL_OUT5,
254 ZL_OUT6,
255 NUM_ZL_CGU_OUTPUT_PINS
256};
257
258enum ice_si_cgu_in_pins {
259 SI_REF0P = 0,
260 SI_REF0N,
261 SI_REF1P,
262 SI_REF1N,
263 SI_REF2P,
264 SI_REF2N,
265 SI_REF3,
266 SI_REF4,
267 NUM_SI_CGU_INPUT_PINS
268};
269
270enum ice_si_cgu_out_pins {
271 SI_OUT0 = 0,
272 SI_OUT1,
273 SI_OUT2,
274 SI_OUT3,
275 SI_OUT4,
276 NUM_SI_CGU_OUTPUT_PINS
277};
278
279struct ice_cgu_pin_desc {
280 char *name;
281 u8 index;
282 enum dpll_pin_type type;
283 u32 freq_supp_num;
284 struct dpll_pin_frequency *freq_supp;
285};
286
287extern const struct
288ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
289
290/**
291 * struct ice_cgu_pll_params_e825c - E825C CGU parameters
292 * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection
293 * @tspll_ndivratio: ndiv ratio that goes directly to the pll
294 * @tspll_fbdiv_intgr: TS PLL integer feedback divide
295 * @tspll_fbdiv_frac: TS PLL fractional feedback divide
296 * @ref1588_ck_div: clock divider for tspll ref
297 *
298 * Clock Generation Unit parameters used to program the PLL based on the
299 * selected TIME_REF/TCXO frequency.
300 */
301struct ice_cgu_pll_params_e825c {
302 u32 tspll_ck_refclkfreq;
303 u32 tspll_ndivratio;
304 u32 tspll_fbdiv_intgr;
305 u32 tspll_fbdiv_frac;
306 u32 ref1588_ck_div;
307};
308
309extern const struct
310ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ];
311
312#define E810C_QSFP_C827_0_HANDLE 2
313#define E810C_QSFP_C827_1_HANDLE 3
314
315/* Table of constants related to possible ETH56G PHY resources */
316extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES];
317
318/* Table of constants related to possible TIME_REF sources */
319extern const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ];
320
321/* Table of constants for Vernier calibration on E822 */
322extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
323
324/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
325 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
326 */
327#define ICE_E810_PLL_FREQ 812500000
328#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
329#define ICE_E810_OUT_PROP_DELAY_NS 1
330#define ICE_E825C_OUT_PROP_DELAY_NS 11
331
332/* Device agnostic functions */
333u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
334int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable);
335bool ice_ptp_lock(struct ice_hw *hw);
336void ice_ptp_unlock(struct ice_hw *hw);
337void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
338int ice_ptp_init_time(struct ice_hw *hw, u64 time);
339int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
340int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
341int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
342int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);
343int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
344int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
345void ice_ptp_reset_ts_memory(struct ice_hw *hw);
346int ice_ptp_init_phc(struct ice_hw *hw);
347void ice_ptp_init_hw(struct ice_hw *hw);
348int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
349int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
350 enum ice_ptp_tmr_cmd configured_cmd);
351
352/* E822 family functions */
353int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
354int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
355void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);
356
357/**
358 * ice_e82x_time_ref - Get the current TIME_REF from capabilities
359 * @hw: pointer to the HW structure
360 *
361 * Returns the current TIME_REF from the capabilities structure.
362 */
363static inline enum ice_time_ref_freq ice_e82x_time_ref(const struct ice_hw *hw)
364{
365 return hw->func_caps.ts_func_info.time_ref;
366}
367
368/**
369 * ice_set_e82x_time_ref - Set new TIME_REF
370 * @hw: pointer to the HW structure
371 * @time_ref: new TIME_REF to set
372 *
373 * Update the TIME_REF in the capabilities structure in response to some
374 * change, such as an update to the CGU registers.
375 */
376static inline void
377ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
378{
379 hw->func_caps.ts_func_info.time_ref = time_ref;
380}
381
382static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)
383{
384 return e82x_time_ref[time_ref].pll_freq;
385}
386
387static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)
388{
389 return e82x_time_ref[time_ref].nominal_incval;
390}
391
392static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)
393{
394 return e82x_time_ref[time_ref].pps_delay;
395}
396
397/* E822 Vernier calibration functions */
398int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
399int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
400int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
401int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
402int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);
403
404/* E810 family functions */
405int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data);
406int ice_write_sma_ctrl(struct ice_hw *hw, u8 data);
407int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
408int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries);
409int ice_cgu_get_num_pins(struct ice_hw *hw, bool input);
410enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
411struct dpll_pin_frequency *
412ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
413const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
414int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
415 enum dpll_lock_status last_dpll_state, u8 *pin,
416 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
417 enum dpll_lock_status *dpll_state);
418int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
419int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
420 unsigned long *caps);
421
422/* ETH56G family functions */
423int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
424int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
425int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);
426int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);
427int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);
428
429#define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
430#define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL
431#define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL
432#define ICE_ETH56G_NOMINAL_THRESH4 0x7777
433#define ICE_ETH56G_NOMINAL_TX_THRESH 0x6
434
435static inline u64 ice_prop_delay(const struct ice_hw *hw)
436{
437 switch (hw->ptp.phy_model) {
438 case ICE_PHY_ETH56G:
439 return ICE_E825C_OUT_PROP_DELAY_NS;
440 case ICE_PHY_E810:
441 return ICE_E810_OUT_PROP_DELAY_NS;
442 case ICE_PHY_E82X:
443 return ice_e82x_pps_delay(ice_e82x_time_ref(hw));
444 default:
445 return 0;
446 }
447}
448
449/**
450 * ice_get_base_incval - Get base clock increment value
451 * @hw: pointer to the HW struct
452 *
453 * Return: base clock increment value for supported PHYs, 0 otherwise
454 */
455static inline u64 ice_get_base_incval(struct ice_hw *hw)
456{
457 switch (hw->ptp.phy_model) {
458 case ICE_PHY_ETH56G:
459 return ICE_ETH56G_NOMINAL_INCVAL;
460 case ICE_PHY_E810:
461 return ICE_PTP_NOMINAL_INCVAL_E810;
462 case ICE_PHY_E82X:
463 return ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
464 default:
465 return 0;
466 }
467}
468
469static inline bool ice_is_dual(struct ice_hw *hw)
470{
471 return !!(hw->dev_caps.nac_topo.mode & ICE_NAC_TOPO_DUAL_M);
472}
473
474#define PFTSYN_SEM_BYTES 4
475
476#define ICE_PTP_CLOCK_INDEX_0 0x00
477#define ICE_PTP_CLOCK_INDEX_1 0x01
478
479/* PHY timer commands */
480#define SEL_CPK_SRC 8
481#define SEL_PHY_SRC 3
482
483/* Time Sync command Definitions */
484#define GLTSYN_CMD_INIT_TIME BIT(0)
485#define GLTSYN_CMD_INIT_INCVAL BIT(1)
486#define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
487#define GLTSYN_CMD_ADJ_TIME BIT(2)
488#define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
489#define GLTSYN_CMD_READ_TIME BIT(7)
490
491/* PHY port Time Sync command definitions */
492#define PHY_CMD_INIT_TIME BIT(0)
493#define PHY_CMD_INIT_INCVAL BIT(1)
494#define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
495#define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
496#define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
497
498#define TS_CMD_MASK_E810 0xFF
499#define TS_CMD_MASK 0xF
500#define SYNC_EXEC_CMD 0x3
501#define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
502
503/* Macros to derive port low and high addresses on both quads */
504#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
505#define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
506#define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
507#define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
508
509/* PHY QUAD register base addresses */
510#define Q_0_BASE 0x94000
511#define Q_1_BASE 0x114000
512
513/* Timestamp memory reset registers */
514#define Q_REG_TS_CTRL 0x618
515#define Q_REG_TS_CTRL_S 0
516#define Q_REG_TS_CTRL_M BIT(0)
517
518/* Timestamp availability status registers */
519#define Q_REG_TX_MEMORY_STATUS_L 0xCF0
520#define Q_REG_TX_MEMORY_STATUS_U 0xCF4
521
522/* Tx FIFO status registers */
523#define Q_REG_FIFO23_STATUS 0xCF8
524#define Q_REG_FIFO01_STATUS 0xCFC
525#define Q_REG_FIFO02_S 0
526#define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
527#define Q_REG_FIFO13_S 10
528#define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
529
530/* Interrupt control Config registers */
531#define Q_REG_TX_MEM_GBL_CFG 0xC08
532#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
533#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
534#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
535#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
536#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
537
538/* Tx Timestamp data registers */
539#define Q_REG_TX_MEMORY_BANK_START 0xA00
540
541/* PHY port register base addresses */
542#define P_0_BASE 0x80000
543#define P_4_BASE 0x106000
544
545/* Timestamp init registers */
546#define P_REG_RX_TIMER_INC_PRE_L 0x46C
547#define P_REG_RX_TIMER_INC_PRE_U 0x470
548#define P_REG_TX_TIMER_INC_PRE_L 0x44C
549#define P_REG_TX_TIMER_INC_PRE_U 0x450
550
551/* Timestamp match and adjust target registers */
552#define P_REG_RX_TIMER_CNT_ADJ_L 0x474
553#define P_REG_RX_TIMER_CNT_ADJ_U 0x478
554#define P_REG_TX_TIMER_CNT_ADJ_L 0x454
555#define P_REG_TX_TIMER_CNT_ADJ_U 0x458
556
557/* Timestamp capture registers */
558#define P_REG_RX_CAPTURE_L 0x4D8
559#define P_REG_RX_CAPTURE_U 0x4DC
560#define P_REG_TX_CAPTURE_L 0x4B4
561#define P_REG_TX_CAPTURE_U 0x4B8
562
563/* Timestamp PHY incval registers */
564#define P_REG_TIMETUS_L 0x410
565#define P_REG_TIMETUS_U 0x414
566
567#define P_REG_40B_LOW_M GENMASK(7, 0)
568#define P_REG_40B_HIGH_S 8
569
570/* PHY window length registers */
571#define P_REG_WL 0x40C
572
573#define PTP_VERNIER_WL 0x111ed
574
575/* PHY start registers */
576#define P_REG_PS 0x408
577#define P_REG_PS_START_S 0
578#define P_REG_PS_START_M BIT(0)
579#define P_REG_PS_BYPASS_MODE_S 1
580#define P_REG_PS_BYPASS_MODE_M BIT(1)
581#define P_REG_PS_ENA_CLK_S 2
582#define P_REG_PS_ENA_CLK_M BIT(2)
583#define P_REG_PS_LOAD_OFFSET_S 3
584#define P_REG_PS_LOAD_OFFSET_M BIT(3)
585#define P_REG_PS_SFT_RESET_S 11
586#define P_REG_PS_SFT_RESET_M BIT(11)
587
588/* PHY offset valid registers */
589#define P_REG_TX_OV_STATUS 0x4D4
590#define P_REG_TX_OV_STATUS_OV_S 0
591#define P_REG_TX_OV_STATUS_OV_M BIT(0)
592#define P_REG_RX_OV_STATUS 0x4F8
593#define P_REG_RX_OV_STATUS_OV_S 0
594#define P_REG_RX_OV_STATUS_OV_M BIT(0)
595
596/* PHY offset ready registers */
597#define P_REG_TX_OR 0x45C
598#define P_REG_RX_OR 0x47C
599
600/* PHY total offset registers */
601#define P_REG_TOTAL_RX_OFFSET_L 0x460
602#define P_REG_TOTAL_RX_OFFSET_U 0x464
603#define P_REG_TOTAL_TX_OFFSET_L 0x440
604#define P_REG_TOTAL_TX_OFFSET_U 0x444
605
606/* Timestamp PAR/PCS registers */
607#define P_REG_UIX66_10G_40G_L 0x480
608#define P_REG_UIX66_10G_40G_U 0x484
609#define P_REG_UIX66_25G_100G_L 0x488
610#define P_REG_UIX66_25G_100G_U 0x48C
611#define P_REG_DESK_PAR_RX_TUS_L 0x490
612#define P_REG_DESK_PAR_RX_TUS_U 0x494
613#define P_REG_DESK_PAR_TX_TUS_L 0x498
614#define P_REG_DESK_PAR_TX_TUS_U 0x49C
615#define P_REG_DESK_PCS_RX_TUS_L 0x4A0
616#define P_REG_DESK_PCS_RX_TUS_U 0x4A4
617#define P_REG_DESK_PCS_TX_TUS_L 0x4A8
618#define P_REG_DESK_PCS_TX_TUS_U 0x4AC
619#define P_REG_PAR_RX_TUS_L 0x420
620#define P_REG_PAR_RX_TUS_U 0x424
621#define P_REG_PAR_TX_TUS_L 0x428
622#define P_REG_PAR_TX_TUS_U 0x42C
623#define P_REG_PCS_RX_TUS_L 0x430
624#define P_REG_PCS_RX_TUS_U 0x434
625#define P_REG_PCS_TX_TUS_L 0x438
626#define P_REG_PCS_TX_TUS_U 0x43C
627#define P_REG_PAR_RX_TIME_L 0x4F0
628#define P_REG_PAR_RX_TIME_U 0x4F4
629#define P_REG_PAR_TX_TIME_L 0x4CC
630#define P_REG_PAR_TX_TIME_U 0x4D0
631#define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
632#define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
633#define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
634#define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
635#define P_REG_LINK_SPEED 0x4FC
636#define P_REG_LINK_SPEED_SERDES_S 0
637#define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
638#define P_REG_LINK_SPEED_FEC_MODE_S 3
639#define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
640#define P_REG_LINK_SPEED_FEC_MODE(reg) \
641 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
642 P_REG_LINK_SPEED_FEC_MODE_S)
643
644/* PHY timestamp related registers */
645#define P_REG_PMD_ALIGNMENT 0x0FC
646#define P_REG_RX_80_TO_160_CNT 0x6FC
647#define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
648#define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
649#define P_REG_RX_40_TO_160_CNT 0x8FC
650#define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
651#define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
652
653/* Rx FIFO status registers */
654#define P_REG_RX_OV_FS 0x4F8
655#define P_REG_RX_OV_FS_FIFO_STATUS_S 2
656#define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
657
658/* Timestamp command registers */
659#define P_REG_TX_TMR_CMD 0x448
660#define P_REG_RX_TMR_CMD 0x468
661
662/* E810 timesync enable register */
663#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
664
665/* E810 shadow init time registers */
666#define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
667#define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
668
669/* E810 shadow time adjust registers */
670#define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
671#define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
672
673/* E810 timer command register */
674#define E810_ETH_GLTSYN_CMD 0x03000344
675
676/* Source timer incval macros */
677#define INCVAL_HIGH_M 0xFF
678
679/* Timestamp block macros */
680#define TS_VALID BIT(0)
681#define TS_LOW_M 0xFFFFFFFF
682#define TS_HIGH_M 0xFF
683#define TS_HIGH_S 32
684
685#define TS_PHY_LOW_M GENMASK(7, 0)
686#define TS_PHY_HIGH_M GENMASK_ULL(39, 8)
687
688#define BYTES_PER_IDX_ADDR_L_U 8
689#define BYTES_PER_IDX_ADDR_L 4
690
691/* Tx timestamp low latency read definitions */
692#define TS_LL_READ_RETRIES 200
693#define TS_LL_READ_TS_HIGH GENMASK(23, 16)
694#define TS_LL_READ_TS_IDX GENMASK(29, 24)
695#define TS_LL_READ_TS_INTR BIT(30)
696#define TS_LL_READ_TS BIT(31)
697
698/* Internal PHY timestamp address */
699#define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
700#define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
701 BYTES_PER_IDX_ADDR_L))
702
703/* External PHY timestamp address */
704#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
705 ((idx) * BYTES_PER_IDX_ADDR_L_U))
706
707#define LOW_TX_MEMORY_BANK_START 0x03090000
708#define HIGH_TX_MEMORY_BANK_START 0x03090004
709
710/* SMA controller pin control */
711#define ICE_SMA1_DIR_EN BIT(4)
712#define ICE_SMA1_TX_EN BIT(5)
713#define ICE_SMA2_UFL2_RX_DIS BIT(3)
714#define ICE_SMA2_DIR_EN BIT(6)
715#define ICE_SMA2_TX_EN BIT(7)
716
717#define ICE_SMA1_MASK (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)
718#define ICE_SMA2_MASK (ICE_SMA2_UFL2_RX_DIS | ICE_SMA2_DIR_EN | \
719 ICE_SMA2_TX_EN)
720#define ICE_ALL_SMA_MASK (ICE_SMA1_MASK | ICE_SMA2_MASK)
721
722#define ICE_SMA_MIN_BIT 3
723#define ICE_SMA_MAX_BIT 7
724#define ICE_PCA9575_P1_OFFSET 8
725
726/* PCA9575 IO controller registers */
727#define ICE_PCA9575_P0_IN 0x0
728
729/* PCA9575 IO controller pin control */
730#define ICE_P0_GNSS_PRSNT_N BIT(4)
731
732/* ETH56G PHY register addresses */
733/* Timestamp PHY incval registers */
734#define PHY_REG_TIMETUS_L 0x8
735#define PHY_REG_TIMETUS_U 0xC
736
737/* Timestamp PCS registers */
738#define PHY_PCS_REF_TUS_L 0x18
739#define PHY_PCS_REF_TUS_U 0x1C
740
741/* Timestamp PCS ref incval registers */
742#define PHY_PCS_REF_INC_L 0x20
743#define PHY_PCS_REF_INC_U 0x24
744
745/* Timestamp init registers */
746#define PHY_REG_RX_TIMER_INC_PRE_L 0x64
747#define PHY_REG_RX_TIMER_INC_PRE_U 0x68
748#define PHY_REG_TX_TIMER_INC_PRE_L 0x44
749#define PHY_REG_TX_TIMER_INC_PRE_U 0x48
750
751/* Timestamp match and adjust target registers */
752#define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C
753#define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70
754#define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C
755#define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50
756
757/* Timestamp command registers */
758#define PHY_REG_TX_TMR_CMD 0x40
759#define PHY_REG_RX_TMR_CMD 0x60
760
761/* Phy offset ready registers */
762#define PHY_REG_TX_OFFSET_READY 0x54
763#define PHY_REG_RX_OFFSET_READY 0x74
764
765/* Phy total offset registers */
766#define PHY_REG_TOTAL_TX_OFFSET_L 0x38
767#define PHY_REG_TOTAL_TX_OFFSET_U 0x3C
768#define PHY_REG_TOTAL_RX_OFFSET_L 0x58
769#define PHY_REG_TOTAL_RX_OFFSET_U 0x5C
770
771/* Timestamp capture registers */
772#define PHY_REG_TX_CAPTURE_L 0x78
773#define PHY_REG_TX_CAPTURE_U 0x7C
774#define PHY_REG_RX_CAPTURE_L 0x8C
775#define PHY_REG_RX_CAPTURE_U 0x90
776
777/* Memory status registers */
778#define PHY_REG_TX_MEMORY_STATUS_L 0x80
779#define PHY_REG_TX_MEMORY_STATUS_U 0x84
780
781/* Interrupt config register */
782#define PHY_REG_TS_INT_CONFIG 0x88
783
784/* XIF mode config register */
785#define PHY_MAC_XIF_MODE 0x24
786#define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
787#define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
788#define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
789#define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
790
791/* GPCS config register */
792#define PHY_GPCS_CONFIG_REG0 0x268
793#define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24)
794#define PHY_GPCS_BITSLIP 0x5C
795
796#define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)
797#define PHY_TS_INT_CONFIG_ENA_M BIT(6)
798
799/* 1-step PTP config */
800#define PHY_PTP_1STEP_CONFIG 0x270
801#define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4)
802#define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8)
803#define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port))
804#define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0)
805#define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1)
806#define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31)
807
808/* Macros to derive offsets for TimeStampLow and TimeStampHigh */
809#define PHY_TSTAMP_L(x) (((x) * 8) + 0)
810#define PHY_TSTAMP_U(x) (((x) * 8) + 4)
811
812#define PHY_REG_REVISION 0x85000
813
814#define PHY_REG_DESKEW_0 0x94
815#define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)
816#define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7)
817#define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3
818#define PHY_REG_DESKEW_0_VALID GENMASK(10, 10)
819
820#define PHY_REG_GPCS_BITSLIP 0x5C
821#define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))
822#define PHY_REVISION_ETH56G 0x10200
823#define PHY_VENDOR_TXLANE_THRESH 0x2000C
824
825#define PHY_MAC_TSU_CONFIG 0x40
826#define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
827#define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M ICE_M(0x7, 4)
828#define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M ICE_M(0x7, 8)
829#define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
830#define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M ICE_M(0x1F, 16)
831#define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M ICE_M(0x1F, 21)
832#define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M ICE_M(0x1, 28)
833#define PHY_MAC_RX_MODULO 0x44
834#define PHY_MAC_RX_OFFSET 0x48
835#define PHY_MAC_RX_OFFSET_M ICE_M(0xFFFFFF, 0)
836#define PHY_MAC_TX_MODULO 0x4C
837#define PHY_MAC_BLOCKTIME 0x50
838#define PHY_MAC_MARKERTIME 0x54
839#define PHY_MAC_TX_OFFSET 0x58
840
841#define PHY_PTP_INT_STATUS 0x7FD140
842
843#endif /* _ICE_PTP_HW_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2021, Intel Corporation. */
3
4#ifndef _ICE_PTP_HW_H_
5#define _ICE_PTP_HW_H_
6#include <linux/dpll.h>
7
8enum ice_ptp_tmr_cmd {
9 ICE_PTP_INIT_TIME,
10 ICE_PTP_INIT_INCVAL,
11 ICE_PTP_ADJ_TIME,
12 ICE_PTP_ADJ_TIME_AT_TIME,
13 ICE_PTP_READ_TIME,
14 ICE_PTP_NOP,
15};
16
17enum ice_ptp_serdes {
18 ICE_PTP_SERDES_1G,
19 ICE_PTP_SERDES_10G,
20 ICE_PTP_SERDES_25G,
21 ICE_PTP_SERDES_40G,
22 ICE_PTP_SERDES_50G,
23 ICE_PTP_SERDES_100G
24};
25
26enum ice_ptp_link_spd {
27 ICE_PTP_LNK_SPD_1G,
28 ICE_PTP_LNK_SPD_10G,
29 ICE_PTP_LNK_SPD_25G,
30 ICE_PTP_LNK_SPD_25G_RS,
31 ICE_PTP_LNK_SPD_40G,
32 ICE_PTP_LNK_SPD_50G,
33 ICE_PTP_LNK_SPD_50G_RS,
34 ICE_PTP_LNK_SPD_100G_RS,
35 NUM_ICE_PTP_LNK_SPD /* Must be last */
36};
37
38enum ice_ptp_fec_mode {
39 ICE_PTP_FEC_MODE_NONE,
40 ICE_PTP_FEC_MODE_CLAUSE74,
41 ICE_PTP_FEC_MODE_RS_FEC
42};
43
44/**
45 * struct ice_time_ref_info_e82x
46 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
47 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
48 * @pps_delay: propagation delay of the PPS output signal
49 *
50 * Characteristic information for the various TIME_REF sources possible in the
51 * E822 devices
52 */
53struct ice_time_ref_info_e82x {
54 u64 pll_freq;
55 u64 nominal_incval;
56 u8 pps_delay;
57};
58
59/**
60 * struct ice_vernier_info_e82x
61 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
62 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
63 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
64 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
65 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
66 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
67 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
68 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
69 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
70 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
71 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
72 *
73 * Table of constants used during as part of the Vernier calibration of the Tx
74 * and Rx timestamps. This includes frequency values used to compute TUs per
75 * PAR/PCS clock cycle, and static delay values measured during hardware
76 * design.
77 *
78 * Note that some values are not used for all link speeds, and the
79 * P_REG_DESK_PAR* registers may represent different clock markers at
80 * different link speeds, either the deskew marker for multi-lane link speeds
81 * or the Reed Solomon gearbox marker for RS-FEC.
82 */
83struct ice_vernier_info_e82x {
84 u32 tx_par_clk;
85 u32 rx_par_clk;
86 u32 tx_pcs_clk;
87 u32 rx_pcs_clk;
88 u32 tx_desk_rsgb_par;
89 u32 rx_desk_rsgb_par;
90 u32 tx_desk_rsgb_pcs;
91 u32 rx_desk_rsgb_pcs;
92 u32 tx_fixed_delay;
93 u32 pmd_adj_divisor;
94 u32 rx_fixed_delay;
95};
96
97/**
98 * struct ice_cgu_pll_params_e82x
99 * @refclk_pre_div: Reference clock pre-divisor
100 * @feedback_div: Feedback divisor
101 * @frac_n_div: Fractional divisor
102 * @post_pll_div: Post PLL divisor
103 *
104 * Clock Generation Unit parameters used to program the PLL based on the
105 * selected TIME_REF frequency.
106 */
107struct ice_cgu_pll_params_e82x {
108 u32 refclk_pre_div;
109 u32 feedback_div;
110 u32 frac_n_div;
111 u32 post_pll_div;
112};
113
114#define E810C_QSFP_C827_0_HANDLE 2
115#define E810C_QSFP_C827_1_HANDLE 3
116enum ice_e810_c827_idx {
117 C827_0,
118 C827_1
119};
120
121enum ice_phy_rclk_pins {
122 ICE_RCLKA_PIN = 0, /* SCL pin */
123 ICE_RCLKB_PIN, /* SDA pin */
124};
125
126#define ICE_E810_RCLK_PINS_NUM (ICE_RCLKB_PIN + 1)
127#define ICE_E82X_RCLK_PINS_NUM (ICE_RCLKA_PIN + 1)
128#define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \
129 (_pin) + ZL_REF1P)
130
131enum ice_zl_cgu_in_pins {
132 ZL_REF0P = 0,
133 ZL_REF0N,
134 ZL_REF1P,
135 ZL_REF1N,
136 ZL_REF2P,
137 ZL_REF2N,
138 ZL_REF3P,
139 ZL_REF3N,
140 ZL_REF4P,
141 ZL_REF4N,
142 NUM_ZL_CGU_INPUT_PINS
143};
144
145enum ice_zl_cgu_out_pins {
146 ZL_OUT0 = 0,
147 ZL_OUT1,
148 ZL_OUT2,
149 ZL_OUT3,
150 ZL_OUT4,
151 ZL_OUT5,
152 ZL_OUT6,
153 NUM_ZL_CGU_OUTPUT_PINS
154};
155
156enum ice_si_cgu_in_pins {
157 SI_REF0P = 0,
158 SI_REF0N,
159 SI_REF1P,
160 SI_REF1N,
161 SI_REF2P,
162 SI_REF2N,
163 SI_REF3,
164 SI_REF4,
165 NUM_SI_CGU_INPUT_PINS
166};
167
168enum ice_si_cgu_out_pins {
169 SI_OUT0 = 0,
170 SI_OUT1,
171 SI_OUT2,
172 SI_OUT3,
173 SI_OUT4,
174 NUM_SI_CGU_OUTPUT_PINS
175};
176
177struct ice_cgu_pin_desc {
178 char *name;
179 u8 index;
180 enum dpll_pin_type type;
181 u32 freq_supp_num;
182 struct dpll_pin_frequency *freq_supp;
183};
184
185extern const struct
186ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
187
188#define E810C_QSFP_C827_0_HANDLE 2
189#define E810C_QSFP_C827_1_HANDLE 3
190
191/* Table of constants related to possible TIME_REF sources */
192extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ];
193
194/* Table of constants for Vernier calibration on E822 */
195extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
196
197/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
198 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
199 */
200#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
201
202/* Device agnostic functions */
203u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
204bool ice_ptp_lock(struct ice_hw *hw);
205void ice_ptp_unlock(struct ice_hw *hw);
206void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
207int ice_ptp_init_time(struct ice_hw *hw, u64 time);
208int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
209int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
210int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
211int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
212int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
213void ice_ptp_reset_ts_memory(struct ice_hw *hw);
214int ice_ptp_init_phc(struct ice_hw *hw);
215int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
216
217/* E822 family functions */
218int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
219int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
220void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);
221
222/**
223 * ice_e82x_time_ref - Get the current TIME_REF from capabilities
224 * @hw: pointer to the HW structure
225 *
226 * Returns the current TIME_REF from the capabilities structure.
227 */
228static inline enum ice_time_ref_freq ice_e82x_time_ref(struct ice_hw *hw)
229{
230 return hw->func_caps.ts_func_info.time_ref;
231}
232
233/**
234 * ice_set_e82x_time_ref - Set new TIME_REF
235 * @hw: pointer to the HW structure
236 * @time_ref: new TIME_REF to set
237 *
238 * Update the TIME_REF in the capabilities structure in response to some
239 * change, such as an update to the CGU registers.
240 */
241static inline void
242ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
243{
244 hw->func_caps.ts_func_info.time_ref = time_ref;
245}
246
247static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)
248{
249 return e822_time_ref[time_ref].pll_freq;
250}
251
252static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)
253{
254 return e822_time_ref[time_ref].nominal_incval;
255}
256
257static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)
258{
259 return e822_time_ref[time_ref].pps_delay;
260}
261
262/* E822 Vernier calibration functions */
263int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
264int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
265int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
266int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
267
268/* E810 family functions */
269int ice_ptp_init_phy_e810(struct ice_hw *hw);
270int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
271int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
272int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
273bool ice_is_pca9575_present(struct ice_hw *hw);
274enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
275struct dpll_pin_frequency *
276ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
277const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
278int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
279 enum dpll_lock_status last_dpll_state, u8 *pin,
280 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
281 enum dpll_lock_status *dpll_state);
282int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
283
284void ice_ptp_init_phy_model(struct ice_hw *hw);
285int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
286 unsigned long *caps);
287
288#define PFTSYN_SEM_BYTES 4
289
290#define ICE_PTP_CLOCK_INDEX_0 0x00
291#define ICE_PTP_CLOCK_INDEX_1 0x01
292
293/* PHY timer commands */
294#define SEL_CPK_SRC 8
295#define SEL_PHY_SRC 3
296
297/* Time Sync command Definitions */
298#define GLTSYN_CMD_INIT_TIME BIT(0)
299#define GLTSYN_CMD_INIT_INCVAL BIT(1)
300#define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
301#define GLTSYN_CMD_ADJ_TIME BIT(2)
302#define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
303#define GLTSYN_CMD_READ_TIME BIT(7)
304
305/* PHY port Time Sync command definitions */
306#define PHY_CMD_INIT_TIME BIT(0)
307#define PHY_CMD_INIT_INCVAL BIT(1)
308#define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
309#define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
310#define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
311
312#define TS_CMD_MASK_E810 0xFF
313#define TS_CMD_MASK 0xF
314#define SYNC_EXEC_CMD 0x3
315
316/* Macros to derive port low and high addresses on both quads */
317#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
318#define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
319#define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
320#define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
321
322/* PHY QUAD register base addresses */
323#define Q_0_BASE 0x94000
324#define Q_1_BASE 0x114000
325
326/* Timestamp memory reset registers */
327#define Q_REG_TS_CTRL 0x618
328#define Q_REG_TS_CTRL_S 0
329#define Q_REG_TS_CTRL_M BIT(0)
330
331/* Timestamp availability status registers */
332#define Q_REG_TX_MEMORY_STATUS_L 0xCF0
333#define Q_REG_TX_MEMORY_STATUS_U 0xCF4
334
335/* Tx FIFO status registers */
336#define Q_REG_FIFO23_STATUS 0xCF8
337#define Q_REG_FIFO01_STATUS 0xCFC
338#define Q_REG_FIFO02_S 0
339#define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
340#define Q_REG_FIFO13_S 10
341#define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
342
343/* Interrupt control Config registers */
344#define Q_REG_TX_MEM_GBL_CFG 0xC08
345#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
346#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
347#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
348#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
349#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
350#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
351#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
352#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
353
354/* Tx Timestamp data registers */
355#define Q_REG_TX_MEMORY_BANK_START 0xA00
356
357/* PHY port register base addresses */
358#define P_0_BASE 0x80000
359#define P_4_BASE 0x106000
360
361/* Timestamp init registers */
362#define P_REG_RX_TIMER_INC_PRE_L 0x46C
363#define P_REG_RX_TIMER_INC_PRE_U 0x470
364#define P_REG_TX_TIMER_INC_PRE_L 0x44C
365#define P_REG_TX_TIMER_INC_PRE_U 0x450
366
367/* Timestamp match and adjust target registers */
368#define P_REG_RX_TIMER_CNT_ADJ_L 0x474
369#define P_REG_RX_TIMER_CNT_ADJ_U 0x478
370#define P_REG_TX_TIMER_CNT_ADJ_L 0x454
371#define P_REG_TX_TIMER_CNT_ADJ_U 0x458
372
373/* Timestamp capture registers */
374#define P_REG_RX_CAPTURE_L 0x4D8
375#define P_REG_RX_CAPTURE_U 0x4DC
376#define P_REG_TX_CAPTURE_L 0x4B4
377#define P_REG_TX_CAPTURE_U 0x4B8
378
379/* Timestamp PHY incval registers */
380#define P_REG_TIMETUS_L 0x410
381#define P_REG_TIMETUS_U 0x414
382
383#define P_REG_40B_LOW_M 0xFF
384#define P_REG_40B_HIGH_S 8
385
386/* PHY window length registers */
387#define P_REG_WL 0x40C
388
389#define PTP_VERNIER_WL 0x111ed
390
391/* PHY start registers */
392#define P_REG_PS 0x408
393#define P_REG_PS_START_S 0
394#define P_REG_PS_START_M BIT(0)
395#define P_REG_PS_BYPASS_MODE_S 1
396#define P_REG_PS_BYPASS_MODE_M BIT(1)
397#define P_REG_PS_ENA_CLK_S 2
398#define P_REG_PS_ENA_CLK_M BIT(2)
399#define P_REG_PS_LOAD_OFFSET_S 3
400#define P_REG_PS_LOAD_OFFSET_M BIT(3)
401#define P_REG_PS_SFT_RESET_S 11
402#define P_REG_PS_SFT_RESET_M BIT(11)
403
404/* PHY offset valid registers */
405#define P_REG_TX_OV_STATUS 0x4D4
406#define P_REG_TX_OV_STATUS_OV_S 0
407#define P_REG_TX_OV_STATUS_OV_M BIT(0)
408#define P_REG_RX_OV_STATUS 0x4F8
409#define P_REG_RX_OV_STATUS_OV_S 0
410#define P_REG_RX_OV_STATUS_OV_M BIT(0)
411
412/* PHY offset ready registers */
413#define P_REG_TX_OR 0x45C
414#define P_REG_RX_OR 0x47C
415
416/* PHY total offset registers */
417#define P_REG_TOTAL_RX_OFFSET_L 0x460
418#define P_REG_TOTAL_RX_OFFSET_U 0x464
419#define P_REG_TOTAL_TX_OFFSET_L 0x440
420#define P_REG_TOTAL_TX_OFFSET_U 0x444
421
422/* Timestamp PAR/PCS registers */
423#define P_REG_UIX66_10G_40G_L 0x480
424#define P_REG_UIX66_10G_40G_U 0x484
425#define P_REG_UIX66_25G_100G_L 0x488
426#define P_REG_UIX66_25G_100G_U 0x48C
427#define P_REG_DESK_PAR_RX_TUS_L 0x490
428#define P_REG_DESK_PAR_RX_TUS_U 0x494
429#define P_REG_DESK_PAR_TX_TUS_L 0x498
430#define P_REG_DESK_PAR_TX_TUS_U 0x49C
431#define P_REG_DESK_PCS_RX_TUS_L 0x4A0
432#define P_REG_DESK_PCS_RX_TUS_U 0x4A4
433#define P_REG_DESK_PCS_TX_TUS_L 0x4A8
434#define P_REG_DESK_PCS_TX_TUS_U 0x4AC
435#define P_REG_PAR_RX_TUS_L 0x420
436#define P_REG_PAR_RX_TUS_U 0x424
437#define P_REG_PAR_TX_TUS_L 0x428
438#define P_REG_PAR_TX_TUS_U 0x42C
439#define P_REG_PCS_RX_TUS_L 0x430
440#define P_REG_PCS_RX_TUS_U 0x434
441#define P_REG_PCS_TX_TUS_L 0x438
442#define P_REG_PCS_TX_TUS_U 0x43C
443#define P_REG_PAR_RX_TIME_L 0x4F0
444#define P_REG_PAR_RX_TIME_U 0x4F4
445#define P_REG_PAR_TX_TIME_L 0x4CC
446#define P_REG_PAR_TX_TIME_U 0x4D0
447#define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
448#define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
449#define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
450#define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
451#define P_REG_LINK_SPEED 0x4FC
452#define P_REG_LINK_SPEED_SERDES_S 0
453#define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
454#define P_REG_LINK_SPEED_FEC_MODE_S 3
455#define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
456#define P_REG_LINK_SPEED_FEC_MODE(reg) \
457 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
458 P_REG_LINK_SPEED_FEC_MODE_S)
459
460/* PHY timestamp related registers */
461#define P_REG_PMD_ALIGNMENT 0x0FC
462#define P_REG_RX_80_TO_160_CNT 0x6FC
463#define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
464#define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
465#define P_REG_RX_40_TO_160_CNT 0x8FC
466#define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
467#define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
468
469/* Rx FIFO status registers */
470#define P_REG_RX_OV_FS 0x4F8
471#define P_REG_RX_OV_FS_FIFO_STATUS_S 2
472#define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
473
474/* Timestamp command registers */
475#define P_REG_TX_TMR_CMD 0x448
476#define P_REG_RX_TMR_CMD 0x468
477
478/* E810 timesync enable register */
479#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
480
481/* E810 shadow init time registers */
482#define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
483#define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
484
485/* E810 shadow time adjust registers */
486#define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
487#define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
488
489/* E810 timer command register */
490#define ETH_GLTSYN_CMD 0x03000344
491
492/* Source timer incval macros */
493#define INCVAL_HIGH_M 0xFF
494
495/* Timestamp block macros */
496#define TS_VALID BIT(0)
497#define TS_LOW_M 0xFFFFFFFF
498#define TS_HIGH_M 0xFF
499#define TS_HIGH_S 32
500
501#define TS_PHY_LOW_M 0xFF
502#define TS_PHY_HIGH_M 0xFFFFFFFF
503#define TS_PHY_HIGH_S 8
504
505#define BYTES_PER_IDX_ADDR_L_U 8
506#define BYTES_PER_IDX_ADDR_L 4
507
508/* Tx timestamp low latency read definitions */
509#define TS_LL_READ_RETRIES 200
510#define TS_LL_READ_TS_HIGH GENMASK(23, 16)
511#define TS_LL_READ_TS_IDX GENMASK(29, 24)
512#define TS_LL_READ_TS_INTR BIT(30)
513#define TS_LL_READ_TS BIT(31)
514
515/* Internal PHY timestamp address */
516#define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
517#define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
518 BYTES_PER_IDX_ADDR_L))
519
520/* External PHY timestamp address */
521#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
522 ((idx) * BYTES_PER_IDX_ADDR_L_U))
523
524#define LOW_TX_MEMORY_BANK_START 0x03090000
525#define HIGH_TX_MEMORY_BANK_START 0x03090004
526
527/* E810T SMA controller pin control */
528#define ICE_SMA1_DIR_EN_E810T BIT(4)
529#define ICE_SMA1_TX_EN_E810T BIT(5)
530#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
531#define ICE_SMA2_DIR_EN_E810T BIT(6)
532#define ICE_SMA2_TX_EN_E810T BIT(7)
533
534#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
535 ICE_SMA1_TX_EN_E810T)
536#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
537 ICE_SMA2_DIR_EN_E810T | \
538 ICE_SMA2_TX_EN_E810T)
539#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
540 ICE_SMA2_MASK_E810T)
541
542#define ICE_SMA_MIN_BIT_E810T 3
543#define ICE_SMA_MAX_BIT_E810T 7
544#define ICE_PCA9575_P1_OFFSET 8
545
546/* E810T PCA9575 IO controller registers */
547#define ICE_PCA9575_P0_IN 0x0
548
549/* E810T PCA9575 IO controller pin control */
550#define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
551
552#endif /* _ICE_PTP_HW_H_ */