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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_COMMON_H_
5#define _ICE_COMMON_H_
6
7#include <linux/bitfield.h>
8
9#include "ice.h"
10#include "ice_type.h"
11#include "ice_nvm.h"
12#include "ice_flex_pipe.h"
13#include "ice_parser.h"
14#include <linux/avf/virtchnl.h>
15#include "ice_switch.h"
16#include "ice_fdir.h"
17
18#define ICE_SQ_SEND_DELAY_TIME_MS 10
19#define ICE_SQ_SEND_MAX_EXECUTE 3
20
21#define FEC_REG_SHIFT 2
22#define FEC_RECV_ID_SHIFT 4
23#define FEC_CORR_LOW_REG_PORT0 (0x02 << FEC_REG_SHIFT)
24#define FEC_CORR_HIGH_REG_PORT0 (0x03 << FEC_REG_SHIFT)
25#define FEC_UNCORR_LOW_REG_PORT0 (0x04 << FEC_REG_SHIFT)
26#define FEC_UNCORR_HIGH_REG_PORT0 (0x05 << FEC_REG_SHIFT)
27#define FEC_CORR_LOW_REG_PORT1 (0x42 << FEC_REG_SHIFT)
28#define FEC_CORR_HIGH_REG_PORT1 (0x43 << FEC_REG_SHIFT)
29#define FEC_UNCORR_LOW_REG_PORT1 (0x44 << FEC_REG_SHIFT)
30#define FEC_UNCORR_HIGH_REG_PORT1 (0x45 << FEC_REG_SHIFT)
31#define FEC_CORR_LOW_REG_PORT2 (0x4A << FEC_REG_SHIFT)
32#define FEC_CORR_HIGH_REG_PORT2 (0x4B << FEC_REG_SHIFT)
33#define FEC_UNCORR_LOW_REG_PORT2 (0x4C << FEC_REG_SHIFT)
34#define FEC_UNCORR_HIGH_REG_PORT2 (0x4D << FEC_REG_SHIFT)
35#define FEC_CORR_LOW_REG_PORT3 (0x52 << FEC_REG_SHIFT)
36#define FEC_CORR_HIGH_REG_PORT3 (0x53 << FEC_REG_SHIFT)
37#define FEC_UNCORR_LOW_REG_PORT3 (0x54 << FEC_REG_SHIFT)
38#define FEC_UNCORR_HIGH_REG_PORT3 (0x55 << FEC_REG_SHIFT)
39#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)
40#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)
41
42int ice_init_hw(struct ice_hw *hw);
43void ice_deinit_hw(struct ice_hw *hw);
44int ice_check_reset(struct ice_hw *hw);
45int ice_reset(struct ice_hw *hw, enum ice_reset_req req);
46int ice_create_all_ctrlq(struct ice_hw *hw);
47int ice_init_all_ctrlq(struct ice_hw *hw);
48void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading);
49void ice_destroy_all_ctrlq(struct ice_hw *hw);
50int
51ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
52 struct ice_rq_event_info *e, u16 *pending);
53int
54ice_get_link_status(struct ice_port_info *pi, bool *link_up);
55int ice_update_link_info(struct ice_port_info *pi);
56int
57ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
58 enum ice_aq_res_access_type access, u32 timeout);
59void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
60int
61ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
62int
63ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
64int ice_aq_alloc_free_res(struct ice_hw *hw,
65 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
66 enum ice_adminq_opc opc);
67bool ice_is_sbq_supported(struct ice_hw *hw);
68struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw);
69int
70ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
71 struct ice_aq_desc *desc, void *buf, u16 buf_size,
72 struct ice_sq_cd *cd);
73void ice_clear_pxe_mode(struct ice_hw *hw);
74int ice_get_caps(struct ice_hw *hw);
75
76void ice_set_safe_mode_caps(struct ice_hw *hw);
77
78int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
79 u32 rxq_index);
80
81int
82ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
83int
84ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
85int
86ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
87 struct ice_aqc_get_set_rss_keys *keys);
88int
89ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
90 struct ice_aqc_get_set_rss_keys *keys);
91
92bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
93int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
94void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
95extern const struct ice_ctx_ele ice_tlan_ctx_info[];
96int ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
97 const struct ice_ctx_ele *ce_info);
98
99extern struct mutex ice_global_cfg_lock_sw;
100
101int
102ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
103 void *buf, u16 buf_size, struct ice_sq_cd *cd);
104int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
105
106int
107ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
108 struct ice_sq_cd *cd);
109int
110ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
111 struct ice_sq_cd *cd);
112int
113ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
114 struct ice_aqc_get_phy_caps_data *caps,
115 struct ice_sq_cd *cd);
116bool ice_is_pf_c827(struct ice_hw *hw);
117bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw);
118bool ice_is_clock_mux_in_netlist(struct ice_hw *hw);
119bool ice_is_cgu_in_netlist(struct ice_hw *hw);
120bool ice_is_gps_in_netlist(struct ice_hw *hw);
121int
122ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
123 u8 *node_part_number, u16 *node_handle);
124int
125ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
126 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
127int
128ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps);
129void
130ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
131 u16 link_speeds_bitmap);
132int
133ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
134 struct ice_sq_cd *cd);
135bool ice_is_generic_mac(struct ice_hw *hw);
136bool ice_is_e810(struct ice_hw *hw);
137int ice_clear_pf_cfg(struct ice_hw *hw);
138int
139ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
140 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
141bool ice_fw_supports_link_override(struct ice_hw *hw);
142int
143ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
144 struct ice_port_info *pi);
145bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
146int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
147 u8 serdes_num, int *output);
148int
149ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port,
150 enum ice_fec_stats_types fec_type, u32 *output);
151
152enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
153enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
154int
155ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
156 bool ena_auto_link_update);
157int
158ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
159 enum ice_fc_mode req_mode);
160bool
161ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
162 struct ice_aqc_set_phy_cfg_data *cfg);
163void
164ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
165 struct ice_aqc_get_phy_caps_data *caps,
166 struct ice_aqc_set_phy_cfg_data *cfg);
167int
168ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
169 enum ice_fec_mode fec);
170int
171ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
172 struct ice_sq_cd *cd);
173int
174ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
175int
176ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
177 struct ice_link_status *link, struct ice_sq_cd *cd);
178int
179ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
180 struct ice_sq_cd *cd);
181int
182ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
183
184int
185ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
186 struct ice_sq_cd *cd);
187int
188ice_aq_get_port_options(struct ice_hw *hw,
189 struct ice_aqc_get_port_options_elem *options,
190 u8 *option_count, u8 lport, bool lport_valid,
191 u8 *active_option_idx, bool *active_option_valid,
192 u8 *pending_option_idx, bool *pending_option_valid);
193int
194ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
195 u8 new_option);
196int ice_get_phy_lane_number(struct ice_hw *hw);
197int
198ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
199 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
200 bool write, struct ice_sq_cd *cd);
201u32 ice_get_link_speed(u16 index);
202
203int
204ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
205 u16 *max_rdmaqs);
206int
207ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
208 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid);
209int
210ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
211 u16 *q_id);
212int
213ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
214 u16 *q_handle, u16 *q_ids, u32 *q_teids,
215 enum ice_disq_rst_src rst_src, u16 vmvf_num,
216 struct ice_sq_cd *cd);
217int
218ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
219 u16 *max_lanqs);
220int
221ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
222 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
223 struct ice_sq_cd *cd);
224int
225ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
226 u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
227 struct ice_sq_cd *cd);
228int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
229void ice_replay_post(struct ice_hw *hw);
230struct ice_q_ctx *
231ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
232int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag);
233int
234ice_aq_get_cgu_abilities(struct ice_hw *hw,
235 struct ice_aqc_get_cgu_abilities *abilities);
236int
237ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
238 u32 freq, s32 phase_delay);
239int
240ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,
241 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay);
242int
243ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
244 u8 src_sel, u32 freq, s32 phase_delay);
245int
246ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,
247 u8 *src_sel, u32 *freq, u32 *src_freq);
248int
249ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
250 u8 *dpll_state, u8 *config, s64 *phase_offset,
251 u8 *eec_mode);
252int
253ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
254 u8 config, u8 eec_mode);
255int
256ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
257 u8 ref_priority);
258int
259ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
260 u8 *ref_prio);
261int
262ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
263 u32 *cgu_fw_ver);
264
265int
266ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
267 u32 *freq);
268int
269ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
270 u8 *flags, u16 *node_handle);
271int ice_aq_get_sensor_reading(struct ice_hw *hw,
272 struct ice_aqc_get_sensor_reading_resp *data);
273void
274ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
275 u64 *prev_stat, u64 *cur_stat);
276void
277ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
278 u64 *prev_stat, u64 *cur_stat);
279bool ice_is_e810t(struct ice_hw *hw);
280bool ice_is_e822(struct ice_hw *hw);
281bool ice_is_e823(struct ice_hw *hw);
282bool ice_is_e825c(struct ice_hw *hw);
283int
284ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
285 struct ice_aqc_txsched_elem_data *buf);
286int
287ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
288 struct ice_sq_cd *cd);
289int
290ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
291 bool *value, struct ice_sq_cd *cd);
292bool ice_is_100m_speed_supported(struct ice_hw *hw);
293u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high);
294int
295ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
296 struct ice_sq_cd *cd);
297bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
298int
299ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
300int ice_lldp_execute_pending_mib(struct ice_hw *hw);
301int
302ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
303 u16 bus_addr, __le16 addr, u8 params, u8 *data,
304 struct ice_sq_cd *cd);
305int
306ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
307 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
308 struct ice_sq_cd *cd);
309bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
310#endif /* _ICE_COMMON_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_COMMON_H_
5#define _ICE_COMMON_H_
6
7#include <linux/bitfield.h>
8
9#include "ice.h"
10#include "ice_type.h"
11#include "ice_nvm.h"
12#include "ice_flex_pipe.h"
13#include <linux/avf/virtchnl.h>
14#include "ice_switch.h"
15#include "ice_fdir.h"
16
17#define ICE_SQ_SEND_DELAY_TIME_MS 10
18#define ICE_SQ_SEND_MAX_EXECUTE 3
19
20int ice_init_hw(struct ice_hw *hw);
21void ice_deinit_hw(struct ice_hw *hw);
22int ice_check_reset(struct ice_hw *hw);
23int ice_reset(struct ice_hw *hw, enum ice_reset_req req);
24int ice_create_all_ctrlq(struct ice_hw *hw);
25int ice_init_all_ctrlq(struct ice_hw *hw);
26void ice_shutdown_all_ctrlq(struct ice_hw *hw);
27void ice_destroy_all_ctrlq(struct ice_hw *hw);
28int
29ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
30 struct ice_rq_event_info *e, u16 *pending);
31int
32ice_get_link_status(struct ice_port_info *pi, bool *link_up);
33int ice_update_link_info(struct ice_port_info *pi);
34int
35ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
36 enum ice_aq_res_access_type access, u32 timeout);
37void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
38int
39ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
40int
41ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
42int ice_aq_alloc_free_res(struct ice_hw *hw,
43 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
44 enum ice_adminq_opc opc);
45bool ice_is_sbq_supported(struct ice_hw *hw);
46struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw);
47int
48ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
49 struct ice_aq_desc *desc, void *buf, u16 buf_size,
50 struct ice_sq_cd *cd);
51void ice_clear_pxe_mode(struct ice_hw *hw);
52int ice_get_caps(struct ice_hw *hw);
53
54void ice_set_safe_mode_caps(struct ice_hw *hw);
55
56int
57ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
58 u32 rxq_index);
59
60int
61ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
62int
63ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
64int
65ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
66 struct ice_aqc_get_set_rss_keys *keys);
67int
68ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
69 struct ice_aqc_get_set_rss_keys *keys);
70
71bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
72int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
73void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
74extern const struct ice_ctx_ele ice_tlan_ctx_info[];
75int
76ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
77 const struct ice_ctx_ele *ce_info);
78
79extern struct mutex ice_global_cfg_lock_sw;
80
81int
82ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
83 void *buf, u16 buf_size, struct ice_sq_cd *cd);
84int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
85
86int
87ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
88 struct ice_sq_cd *cd);
89int
90ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
91 struct ice_sq_cd *cd);
92int
93ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
94 struct ice_aqc_get_phy_caps_data *caps,
95 struct ice_sq_cd *cd);
96bool ice_is_pf_c827(struct ice_hw *hw);
97bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw);
98bool ice_is_clock_mux_in_netlist(struct ice_hw *hw);
99bool ice_is_cgu_in_netlist(struct ice_hw *hw);
100bool ice_is_gps_in_netlist(struct ice_hw *hw);
101int
102ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
103 u8 *node_part_number, u16 *node_handle);
104int
105ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
106 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
107int
108ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps);
109void
110ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
111 u16 link_speeds_bitmap);
112int
113ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
114 struct ice_sq_cd *cd);
115bool ice_is_e810(struct ice_hw *hw);
116int ice_clear_pf_cfg(struct ice_hw *hw);
117int
118ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
119 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
120bool ice_fw_supports_link_override(struct ice_hw *hw);
121int
122ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
123 struct ice_port_info *pi);
124bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
125
126enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
127enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
128int
129ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
130 bool ena_auto_link_update);
131int
132ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
133 enum ice_fc_mode req_mode);
134bool
135ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
136 struct ice_aqc_set_phy_cfg_data *cfg);
137void
138ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
139 struct ice_aqc_get_phy_caps_data *caps,
140 struct ice_aqc_set_phy_cfg_data *cfg);
141int
142ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
143 enum ice_fec_mode fec);
144int
145ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
146 struct ice_sq_cd *cd);
147int
148ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
149int
150ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
151 struct ice_link_status *link, struct ice_sq_cd *cd);
152int
153ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
154 struct ice_sq_cd *cd);
155int
156ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
157
158int
159ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
160 struct ice_sq_cd *cd);
161int
162ice_aq_get_port_options(struct ice_hw *hw,
163 struct ice_aqc_get_port_options_elem *options,
164 u8 *option_count, u8 lport, bool lport_valid,
165 u8 *active_option_idx, bool *active_option_valid,
166 u8 *pending_option_idx, bool *pending_option_valid);
167int
168ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
169 u8 new_option);
170int
171ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
172 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
173 bool write, struct ice_sq_cd *cd);
174u32 ice_get_link_speed(u16 index);
175
176int
177ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
178 u16 *max_rdmaqs);
179int
180ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
181 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid);
182int
183ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
184 u16 *q_id);
185int
186ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
187 u16 *q_handle, u16 *q_ids, u32 *q_teids,
188 enum ice_disq_rst_src rst_src, u16 vmvf_num,
189 struct ice_sq_cd *cd);
190int
191ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
192 u16 *max_lanqs);
193int
194ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
195 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
196 struct ice_sq_cd *cd);
197int
198ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
199 u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
200 struct ice_sq_cd *cd);
201int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
202void ice_replay_post(struct ice_hw *hw);
203struct ice_q_ctx *
204ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
205int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in);
206int
207ice_aq_get_cgu_abilities(struct ice_hw *hw,
208 struct ice_aqc_get_cgu_abilities *abilities);
209int
210ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
211 u32 freq, s32 phase_delay);
212int
213ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,
214 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay);
215int
216ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
217 u8 src_sel, u32 freq, s32 phase_delay);
218int
219ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,
220 u8 *src_sel, u32 *freq, u32 *src_freq);
221int
222ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
223 u8 *dpll_state, u8 *config, s64 *phase_offset,
224 u8 *eec_mode);
225int
226ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
227 u8 config, u8 eec_mode);
228int
229ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
230 u8 ref_priority);
231int
232ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
233 u8 *ref_prio);
234int
235ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
236 u32 *cgu_fw_ver);
237
238int
239ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
240 u32 *freq);
241int
242ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
243 u8 *flags, u16 *node_handle);
244int ice_aq_get_sensor_reading(struct ice_hw *hw,
245 struct ice_aqc_get_sensor_reading_resp *data);
246void
247ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
248 u64 *prev_stat, u64 *cur_stat);
249void
250ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
251 u64 *prev_stat, u64 *cur_stat);
252bool ice_is_e810t(struct ice_hw *hw);
253bool ice_is_e823(struct ice_hw *hw);
254int
255ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
256 struct ice_aqc_txsched_elem_data *buf);
257int
258ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
259 struct ice_sq_cd *cd);
260int
261ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
262 bool *value, struct ice_sq_cd *cd);
263bool ice_is_100m_speed_supported(struct ice_hw *hw);
264int
265ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
266 struct ice_sq_cd *cd);
267bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
268int
269ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
270int ice_lldp_execute_pending_mib(struct ice_hw *hw);
271int
272ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
273 u16 bus_addr, __le16 addr, u8 params, u8 *data,
274 struct ice_sq_cd *cd);
275int
276ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
277 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
278 struct ice_sq_cd *cd);
279bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
280#endif /* _ICE_COMMON_H_ */