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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
4 */
5
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include <linux/delay.h>
9#include <linux/module.h>
10#include <linux/printk.h>
11#include <linux/spi/spi.h>
12#include <linux/errno.h>
13#include <linux/gpio/consumer.h>
14#include <linux/phylink.h>
15#include <linux/of.h>
16#include <linux/of_net.h>
17#include <linux/of_mdio.h>
18#include <linux/netdev_features.h>
19#include <linux/netdevice.h>
20#include <linux/if_bridge.h>
21#include <linux/if_ether.h>
22#include <linux/dsa/8021q.h>
23#include <linux/units.h>
24
25#include "sja1105.h"
26#include "sja1105_tas.h"
27
28#define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull
29
30/* Configure the optional reset pin and bring up switch */
31static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
32 unsigned int startup_delay)
33{
34 struct gpio_desc *gpio;
35
36 gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
37 if (IS_ERR(gpio))
38 return PTR_ERR(gpio);
39
40 if (!gpio)
41 return 0;
42
43 gpiod_set_value_cansleep(gpio, 1);
44 /* Wait for minimum reset pulse length */
45 msleep(pulse_len);
46 gpiod_set_value_cansleep(gpio, 0);
47 /* Wait until chip is ready after reset */
48 msleep(startup_delay);
49
50 gpiod_put(gpio);
51
52 return 0;
53}
54
55static void
56sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
57 int from, int to, bool allow)
58{
59 if (allow)
60 l2_fwd[from].reach_port |= BIT(to);
61 else
62 l2_fwd[from].reach_port &= ~BIT(to);
63}
64
65static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
66 int from, int to)
67{
68 return !!(l2_fwd[from].reach_port & BIT(to));
69}
70
71static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
72{
73 struct sja1105_vlan_lookup_entry *vlan;
74 int count, i;
75
76 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
77 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
78
79 for (i = 0; i < count; i++)
80 if (vlan[i].vlanid == vid)
81 return i;
82
83 /* Return an invalid entry index if not found */
84 return -1;
85}
86
87static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
88{
89 struct sja1105_private *priv = ds->priv;
90 struct sja1105_mac_config_entry *mac;
91
92 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
93
94 if (mac[port].drpuntag == drop)
95 return 0;
96
97 mac[port].drpuntag = drop;
98
99 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
100 &mac[port], true);
101}
102
103static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
104{
105 struct sja1105_mac_config_entry *mac;
106
107 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
108
109 if (mac[port].vlanid == pvid)
110 return 0;
111
112 mac[port].vlanid = pvid;
113
114 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
115 &mac[port], true);
116}
117
118static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
119{
120 struct dsa_port *dp = dsa_to_port(ds, port);
121 struct net_device *br = dsa_port_bridge_dev_get(dp);
122 struct sja1105_private *priv = ds->priv;
123 struct sja1105_vlan_lookup_entry *vlan;
124 bool drop_untagged = false;
125 int match, rc;
126 u16 pvid;
127
128 if (br && br_vlan_enabled(br))
129 pvid = priv->bridge_pvid[port];
130 else
131 pvid = priv->tag_8021q_pvid[port];
132
133 rc = sja1105_pvid_apply(priv, port, pvid);
134 if (rc)
135 return rc;
136
137 /* Only force dropping of untagged packets when the port is under a
138 * VLAN-aware bridge. When the tag_8021q pvid is used, we are
139 * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
140 * to prevent DSA tag spoofing from the link partner. Untagged packets
141 * are the only ones that should be received with tag_8021q, so
142 * definitely don't drop them.
143 */
144 if (pvid == priv->bridge_pvid[port]) {
145 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
146
147 match = sja1105_is_vlan_configured(priv, pvid);
148
149 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
150 drop_untagged = true;
151 }
152
153 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
154 drop_untagged = true;
155
156 return sja1105_drop_untagged(ds, port, drop_untagged);
157}
158
159static int sja1105_init_mac_settings(struct sja1105_private *priv)
160{
161 struct sja1105_mac_config_entry default_mac = {
162 /* Enable all 8 priority queues on egress.
163 * Every queue i holds top[i] - base[i] frames.
164 * Sum of top[i] - base[i] is 511 (max hardware limit).
165 */
166 .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
167 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
168 .enabled = {true, true, true, true, true, true, true, true},
169 /* Keep standard IFG of 12 bytes on egress. */
170 .ifg = 0,
171 /* Always put the MAC speed in automatic mode, where it can be
172 * adjusted at runtime by PHYLINK.
173 */
174 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
175 /* No static correction for 1-step 1588 events */
176 .tp_delin = 0,
177 .tp_delout = 0,
178 /* Disable aging for critical TTEthernet traffic */
179 .maxage = 0xFF,
180 /* Internal VLAN (pvid) to apply to untagged ingress */
181 .vlanprio = 0,
182 .vlanid = 1,
183 .ing_mirr = false,
184 .egr_mirr = false,
185 /* Don't drop traffic with other EtherType than ETH_P_IP */
186 .drpnona664 = false,
187 /* Don't drop double-tagged traffic */
188 .drpdtag = false,
189 /* Don't drop untagged traffic */
190 .drpuntag = false,
191 /* Don't retag 802.1p (VID 0) traffic with the pvid */
192 .retag = false,
193 /* Disable learning and I/O on user ports by default -
194 * STP will enable it.
195 */
196 .dyn_learn = false,
197 .egress = false,
198 .ingress = false,
199 };
200 struct sja1105_mac_config_entry *mac;
201 struct dsa_switch *ds = priv->ds;
202 struct sja1105_table *table;
203 struct dsa_port *dp;
204
205 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
206
207 /* Discard previous MAC Configuration Table */
208 if (table->entry_count) {
209 kfree(table->entries);
210 table->entry_count = 0;
211 }
212
213 table->entries = kcalloc(table->ops->max_entry_count,
214 table->ops->unpacked_entry_size, GFP_KERNEL);
215 if (!table->entries)
216 return -ENOMEM;
217
218 table->entry_count = table->ops->max_entry_count;
219
220 mac = table->entries;
221
222 list_for_each_entry(dp, &ds->dst->ports, list) {
223 if (dp->ds != ds)
224 continue;
225
226 mac[dp->index] = default_mac;
227
228 /* Let sja1105_bridge_stp_state_set() keep address learning
229 * enabled for the DSA ports. CPU ports use software-assisted
230 * learning to ensure that only FDB entries belonging to the
231 * bridge are learned, and that they are learned towards all
232 * CPU ports in a cross-chip topology if multiple CPU ports
233 * exist.
234 */
235 if (dsa_port_is_dsa(dp))
236 dp->learning = true;
237
238 /* Disallow untagged packets from being received on the
239 * CPU and DSA ports.
240 */
241 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
242 mac[dp->index].drpuntag = true;
243 }
244
245 return 0;
246}
247
248static int sja1105_init_mii_settings(struct sja1105_private *priv)
249{
250 struct device *dev = &priv->spidev->dev;
251 struct sja1105_xmii_params_entry *mii;
252 struct dsa_switch *ds = priv->ds;
253 struct sja1105_table *table;
254 int i;
255
256 table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
257
258 /* Discard previous xMII Mode Parameters Table */
259 if (table->entry_count) {
260 kfree(table->entries);
261 table->entry_count = 0;
262 }
263
264 table->entries = kcalloc(table->ops->max_entry_count,
265 table->ops->unpacked_entry_size, GFP_KERNEL);
266 if (!table->entries)
267 return -ENOMEM;
268
269 /* Override table based on PHYLINK DT bindings */
270 table->entry_count = table->ops->max_entry_count;
271
272 mii = table->entries;
273
274 for (i = 0; i < ds->num_ports; i++) {
275 sja1105_mii_role_t role = XMII_MAC;
276
277 if (dsa_is_unused_port(priv->ds, i))
278 continue;
279
280 switch (priv->phy_mode[i]) {
281 case PHY_INTERFACE_MODE_INTERNAL:
282 if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
283 goto unsupported;
284
285 mii->xmii_mode[i] = XMII_MODE_MII;
286 if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
287 mii->special[i] = true;
288
289 break;
290 case PHY_INTERFACE_MODE_REVMII:
291 role = XMII_PHY;
292 fallthrough;
293 case PHY_INTERFACE_MODE_MII:
294 if (!priv->info->supports_mii[i])
295 goto unsupported;
296
297 mii->xmii_mode[i] = XMII_MODE_MII;
298 break;
299 case PHY_INTERFACE_MODE_REVRMII:
300 role = XMII_PHY;
301 fallthrough;
302 case PHY_INTERFACE_MODE_RMII:
303 if (!priv->info->supports_rmii[i])
304 goto unsupported;
305
306 mii->xmii_mode[i] = XMII_MODE_RMII;
307 break;
308 case PHY_INTERFACE_MODE_RGMII:
309 case PHY_INTERFACE_MODE_RGMII_ID:
310 case PHY_INTERFACE_MODE_RGMII_RXID:
311 case PHY_INTERFACE_MODE_RGMII_TXID:
312 if (!priv->info->supports_rgmii[i])
313 goto unsupported;
314
315 mii->xmii_mode[i] = XMII_MODE_RGMII;
316 break;
317 case PHY_INTERFACE_MODE_SGMII:
318 if (!priv->info->supports_sgmii[i])
319 goto unsupported;
320
321 mii->xmii_mode[i] = XMII_MODE_SGMII;
322 mii->special[i] = true;
323 break;
324 case PHY_INTERFACE_MODE_2500BASEX:
325 if (!priv->info->supports_2500basex[i])
326 goto unsupported;
327
328 mii->xmii_mode[i] = XMII_MODE_SGMII;
329 mii->special[i] = true;
330 break;
331unsupported:
332 default:
333 dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
334 phy_modes(priv->phy_mode[i]), i);
335 return -EINVAL;
336 }
337
338 mii->phy_mac[i] = role;
339 }
340 return 0;
341}
342
343static int sja1105_init_static_fdb(struct sja1105_private *priv)
344{
345 struct sja1105_l2_lookup_entry *l2_lookup;
346 struct sja1105_table *table;
347 int port;
348
349 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
350
351 /* We only populate the FDB table through dynamic L2 Address Lookup
352 * entries, except for a special entry at the end which is a catch-all
353 * for unknown multicast and will be used to control flooding domain.
354 */
355 if (table->entry_count) {
356 kfree(table->entries);
357 table->entry_count = 0;
358 }
359
360 if (!priv->info->can_limit_mcast_flood)
361 return 0;
362
363 table->entries = kcalloc(1, table->ops->unpacked_entry_size,
364 GFP_KERNEL);
365 if (!table->entries)
366 return -ENOMEM;
367
368 table->entry_count = 1;
369 l2_lookup = table->entries;
370
371 /* All L2 multicast addresses have an odd first octet */
372 l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
373 l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
374 l2_lookup[0].lockeds = true;
375 l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
376
377 /* Flood multicast to every port by default */
378 for (port = 0; port < priv->ds->num_ports; port++)
379 if (!dsa_is_unused_port(priv->ds, port))
380 l2_lookup[0].destports |= BIT(port);
381
382 return 0;
383}
384
385static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
386{
387 struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
388 /* Learned FDB entries are forgotten after 300 seconds */
389 .maxage = SJA1105_AGEING_TIME_MS(300000),
390 /* All entries within a FDB bin are available for learning */
391 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
392 /* And the P/Q/R/S equivalent setting: */
393 .start_dynspc = 0,
394 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
395 .poly = 0x97,
396 /* Always use Independent VLAN Learning (IVL) */
397 .shared_learn = false,
398 /* Don't discard management traffic based on ENFPORT -
399 * we don't perform SMAC port enforcement anyway, so
400 * what we are setting here doesn't matter.
401 */
402 .no_enf_hostprt = false,
403 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
404 * Maybe correlate with no_linklocal_learn from bridge driver?
405 */
406 .no_mgmt_learn = true,
407 /* P/Q/R/S only */
408 .use_static = true,
409 /* Dynamically learned FDB entries can overwrite other (older)
410 * dynamic FDB entries
411 */
412 .owr_dyn = true,
413 .drpnolearn = true,
414 };
415 struct dsa_switch *ds = priv->ds;
416 int port, num_used_ports = 0;
417 struct sja1105_table *table;
418 u64 max_fdb_entries;
419
420 for (port = 0; port < ds->num_ports; port++)
421 if (!dsa_is_unused_port(ds, port))
422 num_used_ports++;
423
424 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
425
426 for (port = 0; port < ds->num_ports; port++) {
427 if (dsa_is_unused_port(ds, port))
428 continue;
429
430 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
431 }
432
433 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
434
435 if (table->entry_count) {
436 kfree(table->entries);
437 table->entry_count = 0;
438 }
439
440 table->entries = kcalloc(table->ops->max_entry_count,
441 table->ops->unpacked_entry_size, GFP_KERNEL);
442 if (!table->entries)
443 return -ENOMEM;
444
445 table->entry_count = table->ops->max_entry_count;
446
447 /* This table only has a single entry */
448 ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
449 default_l2_lookup_params;
450
451 return 0;
452}
453
454/* Set up a default VLAN for untagged traffic injected from the CPU
455 * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
456 * All DT-defined ports are members of this VLAN, and there are no
457 * restrictions on forwarding (since the CPU selects the destination).
458 * Frames from this VLAN will always be transmitted as untagged, and
459 * neither the bridge nor the 8021q module cannot create this VLAN ID.
460 */
461static int sja1105_init_static_vlan(struct sja1105_private *priv)
462{
463 struct sja1105_table *table;
464 struct sja1105_vlan_lookup_entry pvid = {
465 .type_entry = SJA1110_VLAN_D_TAG,
466 .ving_mirr = 0,
467 .vegr_mirr = 0,
468 .vmemb_port = 0,
469 .vlan_bc = 0,
470 .tag_port = 0,
471 .vlanid = SJA1105_DEFAULT_VLAN,
472 };
473 struct dsa_switch *ds = priv->ds;
474 int port;
475
476 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
477
478 if (table->entry_count) {
479 kfree(table->entries);
480 table->entry_count = 0;
481 }
482
483 table->entries = kzalloc(table->ops->unpacked_entry_size,
484 GFP_KERNEL);
485 if (!table->entries)
486 return -ENOMEM;
487
488 table->entry_count = 1;
489
490 for (port = 0; port < ds->num_ports; port++) {
491 if (dsa_is_unused_port(ds, port))
492 continue;
493
494 pvid.vmemb_port |= BIT(port);
495 pvid.vlan_bc |= BIT(port);
496 pvid.tag_port &= ~BIT(port);
497
498 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
499 priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
500 priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
501 }
502 }
503
504 ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
505 return 0;
506}
507
508static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
509{
510 struct sja1105_l2_forwarding_entry *l2fwd;
511 struct dsa_switch *ds = priv->ds;
512 struct dsa_switch_tree *dst;
513 struct sja1105_table *table;
514 struct dsa_link *dl;
515 int port, tc;
516 int from, to;
517
518 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
519
520 if (table->entry_count) {
521 kfree(table->entries);
522 table->entry_count = 0;
523 }
524
525 table->entries = kcalloc(table->ops->max_entry_count,
526 table->ops->unpacked_entry_size, GFP_KERNEL);
527 if (!table->entries)
528 return -ENOMEM;
529
530 table->entry_count = table->ops->max_entry_count;
531
532 l2fwd = table->entries;
533
534 /* First 5 entries in the L2 Forwarding Table define the forwarding
535 * rules and the VLAN PCP to ingress queue mapping.
536 * Set up the ingress queue mapping first.
537 */
538 for (port = 0; port < ds->num_ports; port++) {
539 if (dsa_is_unused_port(ds, port))
540 continue;
541
542 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
543 l2fwd[port].vlan_pmap[tc] = tc;
544 }
545
546 /* Then manage the forwarding domain for user ports. These can forward
547 * only to the always-on domain (CPU port and DSA links)
548 */
549 for (from = 0; from < ds->num_ports; from++) {
550 if (!dsa_is_user_port(ds, from))
551 continue;
552
553 for (to = 0; to < ds->num_ports; to++) {
554 if (!dsa_is_cpu_port(ds, to) &&
555 !dsa_is_dsa_port(ds, to))
556 continue;
557
558 l2fwd[from].bc_domain |= BIT(to);
559 l2fwd[from].fl_domain |= BIT(to);
560
561 sja1105_port_allow_traffic(l2fwd, from, to, true);
562 }
563 }
564
565 /* Then manage the forwarding domain for DSA links and CPU ports (the
566 * always-on domain). These can send packets to any enabled port except
567 * themselves.
568 */
569 for (from = 0; from < ds->num_ports; from++) {
570 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
571 continue;
572
573 for (to = 0; to < ds->num_ports; to++) {
574 if (dsa_is_unused_port(ds, to))
575 continue;
576
577 if (from == to)
578 continue;
579
580 l2fwd[from].bc_domain |= BIT(to);
581 l2fwd[from].fl_domain |= BIT(to);
582
583 sja1105_port_allow_traffic(l2fwd, from, to, true);
584 }
585 }
586
587 /* In odd topologies ("H" connections where there is a DSA link to
588 * another switch which also has its own CPU port), TX packets can loop
589 * back into the system (they are flooded from CPU port 1 to the DSA
590 * link, and from there to CPU port 2). Prevent this from happening by
591 * cutting RX from DSA links towards our CPU port, if the remote switch
592 * has its own CPU port and therefore doesn't need ours for network
593 * stack termination.
594 */
595 dst = ds->dst;
596
597 list_for_each_entry(dl, &dst->rtable, list) {
598 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
599 continue;
600
601 from = dl->dp->index;
602 to = dsa_upstream_port(ds, from);
603
604 dev_warn(ds->dev,
605 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
606 from, to);
607
608 sja1105_port_allow_traffic(l2fwd, from, to, false);
609
610 l2fwd[from].bc_domain &= ~BIT(to);
611 l2fwd[from].fl_domain &= ~BIT(to);
612 }
613
614 /* Finally, manage the egress flooding domain. All ports start up with
615 * flooding enabled, including the CPU port and DSA links.
616 */
617 for (port = 0; port < ds->num_ports; port++) {
618 if (dsa_is_unused_port(ds, port))
619 continue;
620
621 priv->ucast_egress_floods |= BIT(port);
622 priv->bcast_egress_floods |= BIT(port);
623 }
624
625 /* Next 8 entries define VLAN PCP mapping from ingress to egress.
626 * Create a one-to-one mapping.
627 */
628 for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
629 for (port = 0; port < ds->num_ports; port++) {
630 if (dsa_is_unused_port(ds, port))
631 continue;
632
633 l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
634 }
635
636 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
637 }
638
639 return 0;
640}
641
642static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
643{
644 struct sja1110_pcp_remapping_entry *pcp_remap;
645 struct dsa_switch *ds = priv->ds;
646 struct sja1105_table *table;
647 int port, tc;
648
649 table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
650
651 /* Nothing to do for SJA1105 */
652 if (!table->ops->max_entry_count)
653 return 0;
654
655 if (table->entry_count) {
656 kfree(table->entries);
657 table->entry_count = 0;
658 }
659
660 table->entries = kcalloc(table->ops->max_entry_count,
661 table->ops->unpacked_entry_size, GFP_KERNEL);
662 if (!table->entries)
663 return -ENOMEM;
664
665 table->entry_count = table->ops->max_entry_count;
666
667 pcp_remap = table->entries;
668
669 /* Repeat the configuration done for vlan_pmap */
670 for (port = 0; port < ds->num_ports; port++) {
671 if (dsa_is_unused_port(ds, port))
672 continue;
673
674 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
675 pcp_remap[port].egrpcp[tc] = tc;
676 }
677
678 return 0;
679}
680
681static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
682{
683 struct sja1105_l2_forwarding_params_entry *l2fwd_params;
684 struct sja1105_table *table;
685
686 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
687
688 if (table->entry_count) {
689 kfree(table->entries);
690 table->entry_count = 0;
691 }
692
693 table->entries = kcalloc(table->ops->max_entry_count,
694 table->ops->unpacked_entry_size, GFP_KERNEL);
695 if (!table->entries)
696 return -ENOMEM;
697
698 table->entry_count = table->ops->max_entry_count;
699
700 /* This table only has a single entry */
701 l2fwd_params = table->entries;
702
703 /* Disallow dynamic reconfiguration of vlan_pmap */
704 l2fwd_params->max_dynp = 0;
705 /* Use a single memory partition for all ingress queues */
706 l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
707
708 return 0;
709}
710
711void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
712{
713 struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
714 struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
715 struct sja1105_table *table;
716
717 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
718 l2_fwd_params = table->entries;
719 l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
720
721 /* If we have any critical-traffic virtual links, we need to reserve
722 * some frame buffer memory for them. At the moment, hardcode the value
723 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
724 * remaining for best-effort traffic. TODO: figure out a more flexible
725 * way to perform the frame buffer partitioning.
726 */
727 if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
728 return;
729
730 table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
731 vl_fwd_params = table->entries;
732
733 l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
734 vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
735}
736
737/* SJA1110 TDMACONFIGIDX values:
738 *
739 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports
740 * -----+----------------+---------------+---------------+---------------
741 * 0 | 0, [5:10] | [1:2] | [3:4] | retag
742 * 1 |0, [5:10], retag| [1:2] | [3:4] | -
743 * 2 | 0, [5:10] | [1:3], retag | 4 | -
744 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | -
745 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | -
746 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | -
747 * 14 | 0, [5:10] | [1:4], retag | - | -
748 * 15 | [5:10] | [0:4], retag | - | -
749 */
750static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
751{
752 struct sja1105_general_params_entry *general_params;
753 struct sja1105_table *table;
754 bool port_1_is_base_tx;
755 bool port_3_is_2500;
756 bool port_4_is_2500;
757 u64 tdmaconfigidx;
758
759 if (priv->info->device_id != SJA1110_DEVICE_ID)
760 return;
761
762 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
763 general_params = table->entries;
764
765 /* All the settings below are "as opposed to SGMII", which is the
766 * other pinmuxing option.
767 */
768 port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
769 port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
770 port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
771
772 if (port_1_is_base_tx)
773 /* Retagging port will operate at 1 Gbps */
774 tdmaconfigidx = 5;
775 else if (port_3_is_2500 && port_4_is_2500)
776 /* Retagging port will operate at 100 Mbps */
777 tdmaconfigidx = 1;
778 else if (port_3_is_2500)
779 /* Retagging port will operate at 1 Gbps */
780 tdmaconfigidx = 3;
781 else if (port_4_is_2500)
782 /* Retagging port will operate at 1 Gbps */
783 tdmaconfigidx = 2;
784 else
785 /* Retagging port will operate at 1 Gbps */
786 tdmaconfigidx = 14;
787
788 general_params->tdmaconfigidx = tdmaconfigidx;
789}
790
791static int sja1105_init_topology(struct sja1105_private *priv,
792 struct sja1105_general_params_entry *general_params)
793{
794 struct dsa_switch *ds = priv->ds;
795 int port;
796
797 /* The host port is the destination for traffic matching mac_fltres1
798 * and mac_fltres0 on all ports except itself. Default to an invalid
799 * value.
800 */
801 general_params->host_port = ds->num_ports;
802
803 /* Link-local traffic received on casc_port will be forwarded
804 * to host_port without embedding the source port and device ID
805 * info in the destination MAC address, and no RX timestamps will be
806 * taken either (presumably because it is a cascaded port and a
807 * downstream SJA switch already did that).
808 * To disable the feature, we need to do different things depending on
809 * switch generation. On SJA1105 we need to set an invalid port, while
810 * on SJA1110 which support multiple cascaded ports, this field is a
811 * bitmask so it must be left zero.
812 */
813 if (!priv->info->multiple_cascade_ports)
814 general_params->casc_port = ds->num_ports;
815
816 for (port = 0; port < ds->num_ports; port++) {
817 bool is_upstream = dsa_is_upstream_port(ds, port);
818 bool is_dsa_link = dsa_is_dsa_port(ds, port);
819
820 /* Upstream ports can be dedicated CPU ports or
821 * upstream-facing DSA links
822 */
823 if (is_upstream) {
824 if (general_params->host_port == ds->num_ports) {
825 general_params->host_port = port;
826 } else {
827 dev_err(ds->dev,
828 "Port %llu is already a host port, configuring %d as one too is not supported\n",
829 general_params->host_port, port);
830 return -EINVAL;
831 }
832 }
833
834 /* Cascade ports are downstream-facing DSA links */
835 if (is_dsa_link && !is_upstream) {
836 if (priv->info->multiple_cascade_ports) {
837 general_params->casc_port |= BIT(port);
838 } else if (general_params->casc_port == ds->num_ports) {
839 general_params->casc_port = port;
840 } else {
841 dev_err(ds->dev,
842 "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
843 general_params->casc_port, port);
844 return -EINVAL;
845 }
846 }
847 }
848
849 if (general_params->host_port == ds->num_ports) {
850 dev_err(ds->dev, "No host port configured\n");
851 return -EINVAL;
852 }
853
854 return 0;
855}
856
857static int sja1105_init_general_params(struct sja1105_private *priv)
858{
859 struct sja1105_general_params_entry default_general_params = {
860 /* Allow dynamic changing of the mirror port */
861 .mirr_ptacu = true,
862 .switchid = priv->ds->index,
863 /* Priority queue for link-local management frames
864 * (both ingress to and egress from CPU - PTP, STP etc)
865 */
866 .hostprio = 7,
867 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
868 .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK,
869 .incl_srcpt1 = true,
870 .send_meta1 = true,
871 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
872 .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK,
873 .incl_srcpt0 = true,
874 .send_meta0 = true,
875 /* Default to an invalid value */
876 .mirr_port = priv->ds->num_ports,
877 /* No TTEthernet */
878 .vllupformat = SJA1105_VL_FORMAT_PSFP,
879 .vlmarker = 0,
880 .vlmask = 0,
881 /* Only update correctionField for 1-step PTP (L2 transport) */
882 .ignore2stf = 0,
883 /* Forcefully disable VLAN filtering by telling
884 * the switch that VLAN has a different EtherType.
885 */
886 .tpid = ETH_P_SJA1105,
887 .tpid2 = ETH_P_SJA1105,
888 /* Enable the TTEthernet engine on SJA1110 */
889 .tte_en = true,
890 /* Set up the EtherType for control packets on SJA1110 */
891 .header_type = ETH_P_SJA1110,
892 };
893 struct sja1105_general_params_entry *general_params;
894 struct sja1105_table *table;
895 int rc;
896
897 rc = sja1105_init_topology(priv, &default_general_params);
898 if (rc)
899 return rc;
900
901 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
902
903 if (table->entry_count) {
904 kfree(table->entries);
905 table->entry_count = 0;
906 }
907
908 table->entries = kcalloc(table->ops->max_entry_count,
909 table->ops->unpacked_entry_size, GFP_KERNEL);
910 if (!table->entries)
911 return -ENOMEM;
912
913 table->entry_count = table->ops->max_entry_count;
914
915 general_params = table->entries;
916
917 /* This table only has a single entry */
918 general_params[0] = default_general_params;
919
920 sja1110_select_tdmaconfigidx(priv);
921
922 return 0;
923}
924
925static int sja1105_init_avb_params(struct sja1105_private *priv)
926{
927 struct sja1105_avb_params_entry *avb;
928 struct sja1105_table *table;
929
930 table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
931
932 /* Discard previous AVB Parameters Table */
933 if (table->entry_count) {
934 kfree(table->entries);
935 table->entry_count = 0;
936 }
937
938 table->entries = kcalloc(table->ops->max_entry_count,
939 table->ops->unpacked_entry_size, GFP_KERNEL);
940 if (!table->entries)
941 return -ENOMEM;
942
943 table->entry_count = table->ops->max_entry_count;
944
945 avb = table->entries;
946
947 /* Configure the MAC addresses for meta frames */
948 avb->destmeta = SJA1105_META_DMAC;
949 avb->srcmeta = SJA1105_META_SMAC;
950 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
951 * default. This is because there might be boards with a hardware
952 * layout where enabling the pin as output might cause an electrical
953 * clash. On E/T the pin is always an output, which the board designers
954 * probably already knew, so even if there are going to be electrical
955 * issues, there's nothing we can do.
956 */
957 avb->cas_master = false;
958
959 return 0;
960}
961
962/* The L2 policing table is 2-stage. The table is looked up for each frame
963 * according to the ingress port, whether it was broadcast or not, and the
964 * classified traffic class (given by VLAN PCP). This portion of the lookup is
965 * fixed, and gives access to the SHARINDX, an indirection register pointing
966 * within the policing table itself, which is used to resolve the policer that
967 * will be used for this frame.
968 *
969 * Stage 1 Stage 2
970 * +------------+--------+ +---------------------------------+
971 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU |
972 * +------------+--------+ +---------------------------------+
973 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU |
974 * +------------+--------+ +---------------------------------+
975 * ... | Policer 2: Rate, Burst, MTU |
976 * +------------+--------+ +---------------------------------+
977 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU |
978 * +------------+--------+ +---------------------------------+
979 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU |
980 * +------------+--------+ +---------------------------------+
981 * ... | Policer 5: Rate, Burst, MTU |
982 * +------------+--------+ +---------------------------------+
983 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU |
984 * +------------+--------+ +---------------------------------+
985 * ... | Policer 7: Rate, Burst, MTU |
986 * +------------+--------+ +---------------------------------+
987 * |Port 4 TC 7 |SHARINDX| ...
988 * +------------+--------+
989 * |Port 0 BCAST|SHARINDX| ...
990 * +------------+--------+
991 * |Port 1 BCAST|SHARINDX| ...
992 * +------------+--------+
993 * ... ...
994 * +------------+--------+ +---------------------------------+
995 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU |
996 * +------------+--------+ +---------------------------------+
997 *
998 * In this driver, we shall use policers 0-4 as statically alocated port
999 * (matchall) policers. So we need to make the SHARINDX for all lookups
1000 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1001 * lookup) equal.
1002 * The remaining policers (40) shall be dynamically allocated for flower
1003 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1004 */
1005#define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1006
1007static int sja1105_init_l2_policing(struct sja1105_private *priv)
1008{
1009 struct sja1105_l2_policing_entry *policing;
1010 struct dsa_switch *ds = priv->ds;
1011 struct sja1105_table *table;
1012 int port, tc;
1013
1014 table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1015
1016 /* Discard previous L2 Policing Table */
1017 if (table->entry_count) {
1018 kfree(table->entries);
1019 table->entry_count = 0;
1020 }
1021
1022 table->entries = kcalloc(table->ops->max_entry_count,
1023 table->ops->unpacked_entry_size, GFP_KERNEL);
1024 if (!table->entries)
1025 return -ENOMEM;
1026
1027 table->entry_count = table->ops->max_entry_count;
1028
1029 policing = table->entries;
1030
1031 /* Setup shared indices for the matchall policers */
1032 for (port = 0; port < ds->num_ports; port++) {
1033 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1034 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1035
1036 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1037 policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1038
1039 policing[bcast].sharindx = port;
1040 /* Only SJA1110 has multicast policers */
1041 if (mcast < table->ops->max_entry_count)
1042 policing[mcast].sharindx = port;
1043 }
1044
1045 /* Setup the matchall policer parameters */
1046 for (port = 0; port < ds->num_ports; port++) {
1047 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1048
1049 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1050 mtu += VLAN_HLEN;
1051
1052 policing[port].smax = 65535; /* Burst size in bytes */
1053 policing[port].rate = SJA1105_RATE_MBPS(1000);
1054 policing[port].maxlen = mtu;
1055 policing[port].partition = 0;
1056 }
1057
1058 return 0;
1059}
1060
1061static int sja1105_static_config_load(struct sja1105_private *priv)
1062{
1063 int rc;
1064
1065 sja1105_static_config_free(&priv->static_config);
1066 rc = sja1105_static_config_init(&priv->static_config,
1067 priv->info->static_ops,
1068 priv->info->device_id);
1069 if (rc)
1070 return rc;
1071
1072 /* Build static configuration */
1073 rc = sja1105_init_mac_settings(priv);
1074 if (rc < 0)
1075 return rc;
1076 rc = sja1105_init_mii_settings(priv);
1077 if (rc < 0)
1078 return rc;
1079 rc = sja1105_init_static_fdb(priv);
1080 if (rc < 0)
1081 return rc;
1082 rc = sja1105_init_static_vlan(priv);
1083 if (rc < 0)
1084 return rc;
1085 rc = sja1105_init_l2_lookup_params(priv);
1086 if (rc < 0)
1087 return rc;
1088 rc = sja1105_init_l2_forwarding(priv);
1089 if (rc < 0)
1090 return rc;
1091 rc = sja1105_init_l2_forwarding_params(priv);
1092 if (rc < 0)
1093 return rc;
1094 rc = sja1105_init_l2_policing(priv);
1095 if (rc < 0)
1096 return rc;
1097 rc = sja1105_init_general_params(priv);
1098 if (rc < 0)
1099 return rc;
1100 rc = sja1105_init_avb_params(priv);
1101 if (rc < 0)
1102 return rc;
1103 rc = sja1110_init_pcp_remapping(priv);
1104 if (rc < 0)
1105 return rc;
1106
1107 /* Send initial configuration to hardware via SPI */
1108 return sja1105_static_config_upload(priv);
1109}
1110
1111/* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1112 * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1113 * properties. It has the advantage of working with fixed links and with PHYs
1114 * that apply RGMII delays too, and the MAC driver needs not perform any
1115 * special checks.
1116 *
1117 * Previously we were acting upon the "phy-mode" property when we were
1118 * operating in fixed-link, basically acting as a PHY, but with a reversed
1119 * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1120 * behave as if it is connected to a PHY which has applied RGMII delays in the
1121 * TX direction. So if anything, RX delays should have been added by the MAC,
1122 * but we were adding TX delays.
1123 *
1124 * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1125 * back to the legacy behavior and apply delays on fixed-link ports based on
1126 * the reverse interpretation of the phy-mode. This is a deviation from the
1127 * expected default behavior which is to simply apply no delays. To achieve
1128 * that behavior with the new bindings, it is mandatory to specify
1129 * "{rx,tx}-internal-delay-ps" with a value of 0.
1130 */
1131static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1132 struct device_node *port_dn)
1133{
1134 phy_interface_t phy_mode = priv->phy_mode[port];
1135 struct device *dev = &priv->spidev->dev;
1136 int rx_delay = -1, tx_delay = -1;
1137
1138 if (!phy_interface_mode_is_rgmii(phy_mode))
1139 return 0;
1140
1141 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1142 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1143
1144 if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1145 dev_warn(dev,
1146 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1147 "please update device tree to specify \"rx-internal-delay-ps\" and "
1148 "\"tx-internal-delay-ps\"",
1149 port);
1150
1151 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1152 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1153 rx_delay = 2000;
1154
1155 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1156 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1157 tx_delay = 2000;
1158 }
1159
1160 if (rx_delay < 0)
1161 rx_delay = 0;
1162 if (tx_delay < 0)
1163 tx_delay = 0;
1164
1165 if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1166 dev_err(dev, "Chip cannot apply RGMII delays\n");
1167 return -EINVAL;
1168 }
1169
1170 if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1171 (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1172 (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1173 (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1174 dev_err(dev,
1175 "port %d RGMII delay values out of range, must be between %d and %d ps\n",
1176 port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1177 return -ERANGE;
1178 }
1179
1180 priv->rgmii_rx_delay_ps[port] = rx_delay;
1181 priv->rgmii_tx_delay_ps[port] = tx_delay;
1182
1183 return 0;
1184}
1185
1186static int sja1105_parse_ports_node(struct sja1105_private *priv,
1187 struct device_node *ports_node)
1188{
1189 struct device *dev = &priv->spidev->dev;
1190
1191 for_each_available_child_of_node_scoped(ports_node, child) {
1192 struct device_node *phy_node;
1193 phy_interface_t phy_mode;
1194 u32 index;
1195 int err;
1196
1197 /* Get switch port number from DT */
1198 if (of_property_read_u32(child, "reg", &index) < 0) {
1199 dev_err(dev, "Port number not defined in device tree "
1200 "(property \"reg\")\n");
1201 return -ENODEV;
1202 }
1203
1204 /* Get PHY mode from DT */
1205 err = of_get_phy_mode(child, &phy_mode);
1206 if (err) {
1207 dev_err(dev, "Failed to read phy-mode or "
1208 "phy-interface-type property for port %d\n",
1209 index);
1210 return -ENODEV;
1211 }
1212
1213 phy_node = of_parse_phandle(child, "phy-handle", 0);
1214 if (!phy_node) {
1215 if (!of_phy_is_fixed_link(child)) {
1216 dev_err(dev, "phy-handle or fixed-link "
1217 "properties missing!\n");
1218 return -ENODEV;
1219 }
1220 /* phy-handle is missing, but fixed-link isn't.
1221 * So it's a fixed link. Default to PHY role.
1222 */
1223 priv->fixed_link[index] = true;
1224 } else {
1225 of_node_put(phy_node);
1226 }
1227
1228 priv->phy_mode[index] = phy_mode;
1229
1230 err = sja1105_parse_rgmii_delays(priv, index, child);
1231 if (err)
1232 return err;
1233 }
1234
1235 return 0;
1236}
1237
1238static int sja1105_parse_dt(struct sja1105_private *priv)
1239{
1240 struct device *dev = &priv->spidev->dev;
1241 struct device_node *switch_node = dev->of_node;
1242 struct device_node *ports_node;
1243 int rc;
1244
1245 ports_node = of_get_child_by_name(switch_node, "ports");
1246 if (!ports_node)
1247 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1248 if (!ports_node) {
1249 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1250 return -ENODEV;
1251 }
1252
1253 rc = sja1105_parse_ports_node(priv, ports_node);
1254 of_node_put(ports_node);
1255
1256 return rc;
1257}
1258
1259static int sja1105_set_port_speed(struct sja1105_private *priv, int port,
1260 int speed_mbps)
1261{
1262 struct sja1105_mac_config_entry *mac;
1263 u64 speed;
1264
1265 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1266 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1267 * We have to *know* what the MAC looks like. For the sake of keeping
1268 * the code common, we'll use the static configuration tables as a
1269 * reasonable approximation for both E/T and P/Q/R/S.
1270 */
1271 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1272
1273 switch (speed_mbps) {
1274 case SPEED_UNKNOWN:
1275 /* PHYLINK called sja1105_mac_config() to inform us about
1276 * the state->interface, but AN has not completed and the
1277 * speed is not yet valid. UM10944.pdf says that setting
1278 * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1279 * ok for power consumption in case AN will never complete -
1280 * otherwise PHYLINK should come back with a new update.
1281 */
1282 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1283 break;
1284 case SPEED_10:
1285 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1286 break;
1287 case SPEED_100:
1288 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1289 break;
1290 case SPEED_1000:
1291 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1292 break;
1293 case SPEED_2500:
1294 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1295 break;
1296 default:
1297 dev_err(priv->ds->dev, "Invalid speed %iMbps\n", speed_mbps);
1298 return -EINVAL;
1299 }
1300
1301 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1302 * table, since this will be used for the clocking setup, and we no
1303 * longer need to store it in the static config (already told hardware
1304 * we want auto during upload phase).
1305 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1306 * we need to configure the PCS only (if even that).
1307 */
1308 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1309 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1310 else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1311 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1312
1313 mac[port].speed = speed;
1314
1315 return 0;
1316}
1317
1318/* Write the MAC Configuration Table entry and, if necessary, the CGU settings,
1319 * after a link speedchange for this port.
1320 */
1321static int sja1105_set_port_config(struct sja1105_private *priv, int port)
1322{
1323 struct sja1105_mac_config_entry *mac;
1324 struct device *dev = priv->ds->dev;
1325 int rc;
1326
1327 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1328 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1329 * We have to *know* what the MAC looks like. For the sake of keeping
1330 * the code common, we'll use the static configuration tables as a
1331 * reasonable approximation for both E/T and P/Q/R/S.
1332 */
1333 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1334
1335 /* Write to the dynamic reconfiguration tables */
1336 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1337 &mac[port], true);
1338 if (rc < 0) {
1339 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1340 return rc;
1341 }
1342
1343 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1344 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1345 * RMII no change of the clock setup is required. Actually, changing
1346 * the clock setup does interrupt the clock signal for a certain time
1347 * which causes trouble for all PHYs relying on this signal.
1348 */
1349 if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1350 return 0;
1351
1352 return sja1105_clocking_setup_port(priv, port);
1353}
1354
1355static struct phylink_pcs *
1356sja1105_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
1357{
1358 struct dsa_port *dp = dsa_phylink_to_port(config);
1359 struct sja1105_private *priv = dp->ds->priv;
1360
1361 return priv->pcs[dp->index];
1362}
1363
1364static void sja1105_mac_config(struct phylink_config *config,
1365 unsigned int mode,
1366 const struct phylink_link_state *state)
1367{
1368}
1369
1370static void sja1105_mac_link_down(struct phylink_config *config,
1371 unsigned int mode,
1372 phy_interface_t interface)
1373{
1374 struct dsa_port *dp = dsa_phylink_to_port(config);
1375
1376 sja1105_inhibit_tx(dp->ds->priv, BIT(dp->index), true);
1377}
1378
1379static void sja1105_mac_link_up(struct phylink_config *config,
1380 struct phy_device *phydev,
1381 unsigned int mode,
1382 phy_interface_t interface,
1383 int speed, int duplex,
1384 bool tx_pause, bool rx_pause)
1385{
1386 struct dsa_port *dp = dsa_phylink_to_port(config);
1387 struct sja1105_private *priv = dp->ds->priv;
1388 int port = dp->index;
1389
1390 if (!sja1105_set_port_speed(priv, port, speed))
1391 sja1105_set_port_config(priv, port);
1392
1393 sja1105_inhibit_tx(priv, BIT(port), false);
1394}
1395
1396static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port,
1397 struct phylink_config *config)
1398{
1399 struct sja1105_private *priv = ds->priv;
1400 struct sja1105_xmii_params_entry *mii;
1401 phy_interface_t phy_mode;
1402
1403 phy_mode = priv->phy_mode[port];
1404 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
1405 phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
1406 /* Changing the PHY mode on SERDES ports is possible and makes
1407 * sense, because that is done through the XPCS. We allow
1408 * changes between SGMII and 2500base-X.
1409 */
1410 if (priv->info->supports_sgmii[port])
1411 __set_bit(PHY_INTERFACE_MODE_SGMII,
1412 config->supported_interfaces);
1413
1414 if (priv->info->supports_2500basex[port])
1415 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1416 config->supported_interfaces);
1417 } else {
1418 /* The SJA1105 MAC programming model is through the static
1419 * config (the xMII Mode table cannot be dynamically
1420 * reconfigured), and we have to program that early.
1421 */
1422 __set_bit(phy_mode, config->supported_interfaces);
1423 }
1424
1425 /* The MAC does not support pause frames, and also doesn't
1426 * support half-duplex traffic modes.
1427 */
1428 config->mac_capabilities = MAC_10FD | MAC_100FD;
1429
1430 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1431 if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1432 mii->xmii_mode[port] == XMII_MODE_SGMII)
1433 config->mac_capabilities |= MAC_1000FD;
1434
1435 if (priv->info->supports_2500basex[port])
1436 config->mac_capabilities |= MAC_2500FD;
1437}
1438
1439static int
1440sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1441 const struct sja1105_l2_lookup_entry *requested)
1442{
1443 struct sja1105_l2_lookup_entry *l2_lookup;
1444 struct sja1105_table *table;
1445 int i;
1446
1447 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1448 l2_lookup = table->entries;
1449
1450 for (i = 0; i < table->entry_count; i++)
1451 if (l2_lookup[i].macaddr == requested->macaddr &&
1452 l2_lookup[i].vlanid == requested->vlanid &&
1453 l2_lookup[i].destports & BIT(port))
1454 return i;
1455
1456 return -1;
1457}
1458
1459/* We want FDB entries added statically through the bridge command to persist
1460 * across switch resets, which are a common thing during normal SJA1105
1461 * operation. So we have to back them up in the static configuration tables
1462 * and hence apply them on next static config upload... yay!
1463 */
1464static int
1465sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1466 const struct sja1105_l2_lookup_entry *requested,
1467 bool keep)
1468{
1469 struct sja1105_l2_lookup_entry *l2_lookup;
1470 struct sja1105_table *table;
1471 int rc, match;
1472
1473 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1474
1475 match = sja1105_find_static_fdb_entry(priv, port, requested);
1476 if (match < 0) {
1477 /* Can't delete a missing entry. */
1478 if (!keep)
1479 return 0;
1480
1481 /* No match => new entry */
1482 rc = sja1105_table_resize(table, table->entry_count + 1);
1483 if (rc)
1484 return rc;
1485
1486 match = table->entry_count - 1;
1487 }
1488
1489 /* Assign pointer after the resize (it may be new memory) */
1490 l2_lookup = table->entries;
1491
1492 /* We have a match.
1493 * If the job was to add this FDB entry, it's already done (mostly
1494 * anyway, since the port forwarding mask may have changed, case in
1495 * which we update it).
1496 * Otherwise we have to delete it.
1497 */
1498 if (keep) {
1499 l2_lookup[match] = *requested;
1500 return 0;
1501 }
1502
1503 /* To remove, the strategy is to overwrite the element with
1504 * the last one, and then reduce the array size by 1
1505 */
1506 l2_lookup[match] = l2_lookup[table->entry_count - 1];
1507 return sja1105_table_resize(table, table->entry_count - 1);
1508}
1509
1510/* First-generation switches have a 4-way set associative TCAM that
1511 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1512 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1513 * For the placement of a newly learnt FDB entry, the switch selects the bin
1514 * based on a hash function, and the way within that bin incrementally.
1515 */
1516static int sja1105et_fdb_index(int bin, int way)
1517{
1518 return bin * SJA1105ET_FDB_BIN_SIZE + way;
1519}
1520
1521static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1522 const u8 *addr, u16 vid,
1523 struct sja1105_l2_lookup_entry *match,
1524 int *last_unused)
1525{
1526 int way;
1527
1528 for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1529 struct sja1105_l2_lookup_entry l2_lookup = {0};
1530 int index = sja1105et_fdb_index(bin, way);
1531
1532 /* Skip unused entries, optionally marking them
1533 * into the return value
1534 */
1535 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1536 index, &l2_lookup)) {
1537 if (last_unused)
1538 *last_unused = way;
1539 continue;
1540 }
1541
1542 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1543 l2_lookup.vlanid == vid) {
1544 if (match)
1545 *match = l2_lookup;
1546 return way;
1547 }
1548 }
1549 /* Return an invalid entry index if not found */
1550 return -1;
1551}
1552
1553int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1554 const unsigned char *addr, u16 vid)
1555{
1556 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1557 struct sja1105_private *priv = ds->priv;
1558 struct device *dev = ds->dev;
1559 int last_unused = -1;
1560 int start, end, i;
1561 int bin, way, rc;
1562
1563 bin = sja1105et_fdb_hash(priv, addr, vid);
1564
1565 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1566 &l2_lookup, &last_unused);
1567 if (way >= 0) {
1568 /* We have an FDB entry. Is our port in the destination
1569 * mask? If yes, we need to do nothing. If not, we need
1570 * to rewrite the entry by adding this port to it.
1571 */
1572 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1573 return 0;
1574 l2_lookup.destports |= BIT(port);
1575 } else {
1576 int index = sja1105et_fdb_index(bin, way);
1577
1578 /* We don't have an FDB entry. We construct a new one and
1579 * try to find a place for it within the FDB table.
1580 */
1581 l2_lookup.macaddr = ether_addr_to_u64(addr);
1582 l2_lookup.destports = BIT(port);
1583 l2_lookup.vlanid = vid;
1584
1585 if (last_unused >= 0) {
1586 way = last_unused;
1587 } else {
1588 /* Bin is full, need to evict somebody.
1589 * Choose victim at random. If you get these messages
1590 * often, you may need to consider changing the
1591 * distribution function:
1592 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1593 */
1594 get_random_bytes(&way, sizeof(u8));
1595 way %= SJA1105ET_FDB_BIN_SIZE;
1596 dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1597 bin, addr, way);
1598 /* Evict entry */
1599 sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1600 index, NULL, false);
1601 }
1602 }
1603 l2_lookup.lockeds = true;
1604 l2_lookup.index = sja1105et_fdb_index(bin, way);
1605
1606 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1607 l2_lookup.index, &l2_lookup,
1608 true);
1609 if (rc < 0)
1610 return rc;
1611
1612 /* Invalidate a dynamically learned entry if that exists */
1613 start = sja1105et_fdb_index(bin, 0);
1614 end = sja1105et_fdb_index(bin, way);
1615
1616 for (i = start; i < end; i++) {
1617 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1618 i, &tmp);
1619 if (rc == -ENOENT)
1620 continue;
1621 if (rc)
1622 return rc;
1623
1624 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1625 continue;
1626
1627 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1628 i, NULL, false);
1629 if (rc)
1630 return rc;
1631
1632 break;
1633 }
1634
1635 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1636}
1637
1638int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1639 const unsigned char *addr, u16 vid)
1640{
1641 struct sja1105_l2_lookup_entry l2_lookup = {0};
1642 struct sja1105_private *priv = ds->priv;
1643 int index, bin, way, rc;
1644 bool keep;
1645
1646 bin = sja1105et_fdb_hash(priv, addr, vid);
1647 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1648 &l2_lookup, NULL);
1649 if (way < 0)
1650 return 0;
1651 index = sja1105et_fdb_index(bin, way);
1652
1653 /* We have an FDB entry. Is our port in the destination mask? If yes,
1654 * we need to remove it. If the resulting port mask becomes empty, we
1655 * need to completely evict the FDB entry.
1656 * Otherwise we just write it back.
1657 */
1658 l2_lookup.destports &= ~BIT(port);
1659
1660 if (l2_lookup.destports)
1661 keep = true;
1662 else
1663 keep = false;
1664
1665 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1666 index, &l2_lookup, keep);
1667 if (rc < 0)
1668 return rc;
1669
1670 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1671}
1672
1673int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1674 const unsigned char *addr, u16 vid)
1675{
1676 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1677 struct sja1105_private *priv = ds->priv;
1678 int rc, i;
1679
1680 /* Search for an existing entry in the FDB table */
1681 l2_lookup.macaddr = ether_addr_to_u64(addr);
1682 l2_lookup.vlanid = vid;
1683 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1684 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1685 l2_lookup.destports = BIT(port);
1686
1687 tmp = l2_lookup;
1688
1689 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1690 SJA1105_SEARCH, &tmp);
1691 if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1692 /* Found a static entry and this port is already in the entry's
1693 * port mask => job done
1694 */
1695 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1696 return 0;
1697
1698 l2_lookup = tmp;
1699
1700 /* l2_lookup.index is populated by the switch in case it
1701 * found something.
1702 */
1703 l2_lookup.destports |= BIT(port);
1704 goto skip_finding_an_index;
1705 }
1706
1707 /* Not found, so try to find an unused spot in the FDB.
1708 * This is slightly inefficient because the strategy is knock-knock at
1709 * every possible position from 0 to 1023.
1710 */
1711 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1712 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1713 i, NULL);
1714 if (rc < 0)
1715 break;
1716 }
1717 if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1718 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1719 return -EINVAL;
1720 }
1721 l2_lookup.index = i;
1722
1723skip_finding_an_index:
1724 l2_lookup.lockeds = true;
1725
1726 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1727 l2_lookup.index, &l2_lookup,
1728 true);
1729 if (rc < 0)
1730 return rc;
1731
1732 /* The switch learns dynamic entries and looks up the FDB left to
1733 * right. It is possible that our addition was concurrent with the
1734 * dynamic learning of the same address, so now that the static entry
1735 * has been installed, we are certain that address learning for this
1736 * particular address has been turned off, so the dynamic entry either
1737 * is in the FDB at an index smaller than the static one, or isn't (it
1738 * can also be at a larger index, but in that case it is inactive
1739 * because the static FDB entry will match first, and the dynamic one
1740 * will eventually age out). Search for a dynamically learned address
1741 * prior to our static one and invalidate it.
1742 */
1743 tmp = l2_lookup;
1744
1745 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1746 SJA1105_SEARCH, &tmp);
1747 if (rc < 0) {
1748 dev_err(ds->dev,
1749 "port %d failed to read back entry for %pM vid %d: %pe\n",
1750 port, addr, vid, ERR_PTR(rc));
1751 return rc;
1752 }
1753
1754 if (tmp.index < l2_lookup.index) {
1755 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1756 tmp.index, NULL, false);
1757 if (rc < 0)
1758 return rc;
1759 }
1760
1761 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1762}
1763
1764int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1765 const unsigned char *addr, u16 vid)
1766{
1767 struct sja1105_l2_lookup_entry l2_lookup = {0};
1768 struct sja1105_private *priv = ds->priv;
1769 bool keep;
1770 int rc;
1771
1772 l2_lookup.macaddr = ether_addr_to_u64(addr);
1773 l2_lookup.vlanid = vid;
1774 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1775 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1776 l2_lookup.destports = BIT(port);
1777
1778 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1779 SJA1105_SEARCH, &l2_lookup);
1780 if (rc < 0)
1781 return 0;
1782
1783 l2_lookup.destports &= ~BIT(port);
1784
1785 /* Decide whether we remove just this port from the FDB entry,
1786 * or if we remove it completely.
1787 */
1788 if (l2_lookup.destports)
1789 keep = true;
1790 else
1791 keep = false;
1792
1793 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1794 l2_lookup.index, &l2_lookup, keep);
1795 if (rc < 0)
1796 return rc;
1797
1798 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1799}
1800
1801static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1802 const unsigned char *addr, u16 vid,
1803 struct dsa_db db)
1804{
1805 struct sja1105_private *priv = ds->priv;
1806 int rc;
1807
1808 if (!vid) {
1809 switch (db.type) {
1810 case DSA_DB_PORT:
1811 vid = dsa_tag_8021q_standalone_vid(db.dp);
1812 break;
1813 case DSA_DB_BRIDGE:
1814 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1815 break;
1816 default:
1817 return -EOPNOTSUPP;
1818 }
1819 }
1820
1821 mutex_lock(&priv->fdb_lock);
1822 rc = priv->info->fdb_add_cmd(ds, port, addr, vid);
1823 mutex_unlock(&priv->fdb_lock);
1824
1825 return rc;
1826}
1827
1828static int __sja1105_fdb_del(struct dsa_switch *ds, int port,
1829 const unsigned char *addr, u16 vid,
1830 struct dsa_db db)
1831{
1832 struct sja1105_private *priv = ds->priv;
1833
1834 if (!vid) {
1835 switch (db.type) {
1836 case DSA_DB_PORT:
1837 vid = dsa_tag_8021q_standalone_vid(db.dp);
1838 break;
1839 case DSA_DB_BRIDGE:
1840 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1841 break;
1842 default:
1843 return -EOPNOTSUPP;
1844 }
1845 }
1846
1847 return priv->info->fdb_del_cmd(ds, port, addr, vid);
1848}
1849
1850static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1851 const unsigned char *addr, u16 vid,
1852 struct dsa_db db)
1853{
1854 struct sja1105_private *priv = ds->priv;
1855 int rc;
1856
1857 mutex_lock(&priv->fdb_lock);
1858 rc = __sja1105_fdb_del(ds, port, addr, vid, db);
1859 mutex_unlock(&priv->fdb_lock);
1860
1861 return rc;
1862}
1863
1864static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1865 dsa_fdb_dump_cb_t *cb, void *data)
1866{
1867 struct sja1105_private *priv = ds->priv;
1868 struct device *dev = ds->dev;
1869 int i;
1870
1871 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1872 struct sja1105_l2_lookup_entry l2_lookup = {0};
1873 u8 macaddr[ETH_ALEN];
1874 int rc;
1875
1876 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1877 i, &l2_lookup);
1878 /* No fdb entry at i, not an issue */
1879 if (rc == -ENOENT)
1880 continue;
1881 if (rc) {
1882 dev_err(dev, "Failed to dump FDB: %d\n", rc);
1883 return rc;
1884 }
1885
1886 /* FDB dump callback is per port. This means we have to
1887 * disregard a valid entry if it's not for this port, even if
1888 * only to revisit it later. This is inefficient because the
1889 * 1024-sized FDB table needs to be traversed 4 times through
1890 * SPI during a 'bridge fdb show' command.
1891 */
1892 if (!(l2_lookup.destports & BIT(port)))
1893 continue;
1894
1895 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1896
1897 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show"
1898 * only wants to see unicast
1899 */
1900 if (is_multicast_ether_addr(macaddr))
1901 continue;
1902
1903 /* We need to hide the dsa_8021q VLANs from the user. */
1904 if (vid_is_dsa_8021q(l2_lookup.vlanid))
1905 l2_lookup.vlanid = 0;
1906 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1907 if (rc)
1908 return rc;
1909 }
1910 return 0;
1911}
1912
1913static void sja1105_fast_age(struct dsa_switch *ds, int port)
1914{
1915 struct dsa_port *dp = dsa_to_port(ds, port);
1916 struct sja1105_private *priv = ds->priv;
1917 struct dsa_db db = {
1918 .type = DSA_DB_BRIDGE,
1919 .bridge = {
1920 .dev = dsa_port_bridge_dev_get(dp),
1921 .num = dsa_port_bridge_num_get(dp),
1922 },
1923 };
1924 int i;
1925
1926 mutex_lock(&priv->fdb_lock);
1927
1928 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1929 struct sja1105_l2_lookup_entry l2_lookup = {0};
1930 u8 macaddr[ETH_ALEN];
1931 int rc;
1932
1933 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1934 i, &l2_lookup);
1935 /* No fdb entry at i, not an issue */
1936 if (rc == -ENOENT)
1937 continue;
1938 if (rc) {
1939 dev_err(ds->dev, "Failed to read FDB: %pe\n",
1940 ERR_PTR(rc));
1941 break;
1942 }
1943
1944 if (!(l2_lookup.destports & BIT(port)))
1945 continue;
1946
1947 /* Don't delete static FDB entries */
1948 if (l2_lookup.lockeds)
1949 continue;
1950
1951 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1952
1953 rc = __sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db);
1954 if (rc) {
1955 dev_err(ds->dev,
1956 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1957 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1958 break;
1959 }
1960 }
1961
1962 mutex_unlock(&priv->fdb_lock);
1963}
1964
1965static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1966 const struct switchdev_obj_port_mdb *mdb,
1967 struct dsa_db db)
1968{
1969 return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db);
1970}
1971
1972static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1973 const struct switchdev_obj_port_mdb *mdb,
1974 struct dsa_db db)
1975{
1976 return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db);
1977}
1978
1979/* Common function for unicast and broadcast flood configuration.
1980 * Flooding is configured between each {ingress, egress} port pair, and since
1981 * the bridge's semantics are those of "egress flooding", it means we must
1982 * enable flooding towards this port from all ingress ports that are in the
1983 * same forwarding domain.
1984 */
1985static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1986{
1987 struct sja1105_l2_forwarding_entry *l2_fwd;
1988 struct dsa_switch *ds = priv->ds;
1989 int from, to, rc;
1990
1991 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1992
1993 for (from = 0; from < ds->num_ports; from++) {
1994 u64 fl_domain = 0, bc_domain = 0;
1995
1996 for (to = 0; to < priv->ds->num_ports; to++) {
1997 if (!sja1105_can_forward(l2_fwd, from, to))
1998 continue;
1999
2000 if (priv->ucast_egress_floods & BIT(to))
2001 fl_domain |= BIT(to);
2002 if (priv->bcast_egress_floods & BIT(to))
2003 bc_domain |= BIT(to);
2004 }
2005
2006 /* Nothing changed, nothing to do */
2007 if (l2_fwd[from].fl_domain == fl_domain &&
2008 l2_fwd[from].bc_domain == bc_domain)
2009 continue;
2010
2011 l2_fwd[from].fl_domain = fl_domain;
2012 l2_fwd[from].bc_domain = bc_domain;
2013
2014 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2015 from, &l2_fwd[from], true);
2016 if (rc < 0)
2017 return rc;
2018 }
2019
2020 return 0;
2021}
2022
2023static int sja1105_bridge_member(struct dsa_switch *ds, int port,
2024 struct dsa_bridge bridge, bool member)
2025{
2026 struct sja1105_l2_forwarding_entry *l2_fwd;
2027 struct sja1105_private *priv = ds->priv;
2028 int i, rc;
2029
2030 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
2031
2032 for (i = 0; i < ds->num_ports; i++) {
2033 /* Add this port to the forwarding matrix of the
2034 * other ports in the same bridge, and viceversa.
2035 */
2036 if (!dsa_is_user_port(ds, i))
2037 continue;
2038 /* For the ports already under the bridge, only one thing needs
2039 * to be done, and that is to add this port to their
2040 * reachability domain. So we can perform the SPI write for
2041 * them immediately. However, for this port itself (the one
2042 * that is new to the bridge), we need to add all other ports
2043 * to its reachability domain. So we do that incrementally in
2044 * this loop, and perform the SPI write only at the end, once
2045 * the domain contains all other bridge ports.
2046 */
2047 if (i == port)
2048 continue;
2049 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2050 continue;
2051 sja1105_port_allow_traffic(l2_fwd, i, port, member);
2052 sja1105_port_allow_traffic(l2_fwd, port, i, member);
2053
2054 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2055 i, &l2_fwd[i], true);
2056 if (rc < 0)
2057 return rc;
2058 }
2059
2060 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2061 port, &l2_fwd[port], true);
2062 if (rc)
2063 return rc;
2064
2065 rc = sja1105_commit_pvid(ds, port);
2066 if (rc)
2067 return rc;
2068
2069 return sja1105_manage_flood_domains(priv);
2070}
2071
2072static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2073 u8 state)
2074{
2075 struct dsa_port *dp = dsa_to_port(ds, port);
2076 struct sja1105_private *priv = ds->priv;
2077 struct sja1105_mac_config_entry *mac;
2078
2079 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2080
2081 switch (state) {
2082 case BR_STATE_DISABLED:
2083 case BR_STATE_BLOCKING:
2084 /* From UM10944 description of DRPDTAG (why put this there?):
2085 * "Management traffic flows to the port regardless of the state
2086 * of the INGRESS flag". So BPDUs are still be allowed to pass.
2087 * At the moment no difference between DISABLED and BLOCKING.
2088 */
2089 mac[port].ingress = false;
2090 mac[port].egress = false;
2091 mac[port].dyn_learn = false;
2092 break;
2093 case BR_STATE_LISTENING:
2094 mac[port].ingress = true;
2095 mac[port].egress = false;
2096 mac[port].dyn_learn = false;
2097 break;
2098 case BR_STATE_LEARNING:
2099 mac[port].ingress = true;
2100 mac[port].egress = false;
2101 mac[port].dyn_learn = dp->learning;
2102 break;
2103 case BR_STATE_FORWARDING:
2104 mac[port].ingress = true;
2105 mac[port].egress = true;
2106 mac[port].dyn_learn = dp->learning;
2107 break;
2108 default:
2109 dev_err(ds->dev, "invalid STP state: %d\n", state);
2110 return;
2111 }
2112
2113 sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2114 &mac[port], true);
2115}
2116
2117static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2118 struct dsa_bridge bridge,
2119 bool *tx_fwd_offload,
2120 struct netlink_ext_ack *extack)
2121{
2122 int rc;
2123
2124 rc = sja1105_bridge_member(ds, port, bridge, true);
2125 if (rc)
2126 return rc;
2127
2128 rc = dsa_tag_8021q_bridge_join(ds, port, bridge, tx_fwd_offload,
2129 extack);
2130 if (rc) {
2131 sja1105_bridge_member(ds, port, bridge, false);
2132 return rc;
2133 }
2134
2135 return 0;
2136}
2137
2138static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2139 struct dsa_bridge bridge)
2140{
2141 dsa_tag_8021q_bridge_leave(ds, port, bridge);
2142 sja1105_bridge_member(ds, port, bridge, false);
2143}
2144
2145/* Port 0 (the uC port) does not have CBS shapers */
2146#define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio))
2147
2148static int sja1105_find_cbs_shaper(struct sja1105_private *priv,
2149 int port, int prio)
2150{
2151 int i;
2152
2153 if (priv->info->fixed_cbs_mapping) {
2154 i = SJA1110_FIXED_CBS(port, prio);
2155 if (i >= 0 && i < priv->info->num_cbs_shapers)
2156 return i;
2157
2158 return -1;
2159 }
2160
2161 for (i = 0; i < priv->info->num_cbs_shapers; i++)
2162 if (priv->cbs[i].port == port && priv->cbs[i].prio == prio)
2163 return i;
2164
2165 return -1;
2166}
2167
2168static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2169{
2170 int i;
2171
2172 if (priv->info->fixed_cbs_mapping)
2173 return -1;
2174
2175 for (i = 0; i < priv->info->num_cbs_shapers; i++)
2176 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2177 return i;
2178
2179 return -1;
2180}
2181
2182static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2183 int prio)
2184{
2185 int i;
2186
2187 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2188 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2189
2190 if (cbs->port == port && cbs->prio == prio) {
2191 memset(cbs, 0, sizeof(*cbs));
2192 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2193 i, cbs, true);
2194 }
2195 }
2196
2197 return 0;
2198}
2199
2200static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2201 struct tc_cbs_qopt_offload *offload)
2202{
2203 struct sja1105_private *priv = ds->priv;
2204 struct sja1105_cbs_entry *cbs;
2205 s64 port_transmit_rate_kbps;
2206 int index;
2207
2208 if (!offload->enable)
2209 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2210
2211 /* The user may be replacing an existing shaper */
2212 index = sja1105_find_cbs_shaper(priv, port, offload->queue);
2213 if (index < 0) {
2214 /* That isn't the case - see if we can allocate a new one */
2215 index = sja1105_find_unused_cbs_shaper(priv);
2216 if (index < 0)
2217 return -ENOSPC;
2218 }
2219
2220 cbs = &priv->cbs[index];
2221 cbs->port = port;
2222 cbs->prio = offload->queue;
2223 /* locredit and sendslope are negative by definition. In hardware,
2224 * positive values must be provided, and the negative sign is implicit.
2225 */
2226 cbs->credit_hi = offload->hicredit;
2227 cbs->credit_lo = abs(offload->locredit);
2228 /* User space is in kbits/sec, while the hardware in bytes/sec times
2229 * link speed. Since the given offload->sendslope is good only for the
2230 * current link speed anyway, and user space is likely to reprogram it
2231 * when that changes, don't even bother to track the port's link speed,
2232 * but deduce the port transmit rate from idleslope - sendslope.
2233 */
2234 port_transmit_rate_kbps = offload->idleslope - offload->sendslope;
2235 cbs->idle_slope = div_s64(offload->idleslope * BYTES_PER_KBIT,
2236 port_transmit_rate_kbps);
2237 cbs->send_slope = div_s64(abs(offload->sendslope * BYTES_PER_KBIT),
2238 port_transmit_rate_kbps);
2239 /* Convert the negative values from 64-bit 2's complement
2240 * to 32-bit 2's complement (for the case of 0x80000000 whose
2241 * negative is still negative).
2242 */
2243 cbs->credit_lo &= GENMASK_ULL(31, 0);
2244 cbs->send_slope &= GENMASK_ULL(31, 0);
2245
2246 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2247 true);
2248}
2249
2250static int sja1105_reload_cbs(struct sja1105_private *priv)
2251{
2252 int rc = 0, i;
2253
2254 /* The credit based shapers are only allocated if
2255 * CONFIG_NET_SCH_CBS is enabled.
2256 */
2257 if (!priv->cbs)
2258 return 0;
2259
2260 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2261 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2262
2263 if (!cbs->idle_slope && !cbs->send_slope)
2264 continue;
2265
2266 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2267 true);
2268 if (rc)
2269 break;
2270 }
2271
2272 return rc;
2273}
2274
2275static const char * const sja1105_reset_reasons[] = {
2276 [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2277 [SJA1105_AGEING_TIME] = "Ageing time",
2278 [SJA1105_SCHEDULING] = "Time-aware scheduling",
2279 [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2280 [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2281};
2282
2283/* For situations where we need to change a setting at runtime that is only
2284 * available through the static configuration, resetting the switch in order
2285 * to upload the new static config is unavoidable. Back up the settings we
2286 * modify at runtime (currently only MAC) and restore them after uploading,
2287 * such that this operation is relatively seamless.
2288 */
2289int sja1105_static_config_reload(struct sja1105_private *priv,
2290 enum sja1105_reset_reason reason)
2291{
2292 struct ptp_system_timestamp ptp_sts_before;
2293 struct ptp_system_timestamp ptp_sts_after;
2294 u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2295 u64 mac_speed[SJA1105_MAX_NUM_PORTS];
2296 struct sja1105_mac_config_entry *mac;
2297 struct dsa_switch *ds = priv->ds;
2298 s64 t1, t2, t3, t4;
2299 s64 t12, t34;
2300 int rc, i;
2301 s64 now;
2302
2303 mutex_lock(&priv->fdb_lock);
2304 mutex_lock(&priv->mgmt_lock);
2305
2306 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2307
2308 /* Back up the dynamic link speed changed by sja1105_set_port_speed()
2309 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2310 * switch wants to see in the static config in order to allow us to
2311 * change it through the dynamic interface later.
2312 */
2313 for (i = 0; i < ds->num_ports; i++) {
2314 mac_speed[i] = mac[i].speed;
2315 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2316
2317 if (priv->pcs[i])
2318 bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i,
2319 MDIO_MMD_VEND2, MDIO_CTRL1);
2320 }
2321
2322 /* No PTP operations can run right now */
2323 mutex_lock(&priv->ptp_data.lock);
2324
2325 rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2326 if (rc < 0) {
2327 mutex_unlock(&priv->ptp_data.lock);
2328 goto out;
2329 }
2330
2331 /* Reset switch and send updated static configuration */
2332 rc = sja1105_static_config_upload(priv);
2333 if (rc < 0) {
2334 mutex_unlock(&priv->ptp_data.lock);
2335 goto out;
2336 }
2337
2338 rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2339 if (rc < 0) {
2340 mutex_unlock(&priv->ptp_data.lock);
2341 goto out;
2342 }
2343
2344 t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2345 t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2346 t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2347 t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2348 /* Mid point, corresponds to pre-reset PTPCLKVAL */
2349 t12 = t1 + (t2 - t1) / 2;
2350 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2351 t34 = t3 + (t4 - t3) / 2;
2352 /* Advance PTPCLKVAL by the time it took since its readout */
2353 now += (t34 - t12);
2354
2355 __sja1105_ptp_adjtime(ds, now);
2356
2357 mutex_unlock(&priv->ptp_data.lock);
2358
2359 dev_info(priv->ds->dev,
2360 "Reset switch and programmed static config. Reason: %s\n",
2361 sja1105_reset_reasons[reason]);
2362
2363 /* Configure the CGU (PLLs) for MII and RMII PHYs.
2364 * For these interfaces there is no dynamic configuration
2365 * needed, since PLLs have same settings at all speeds.
2366 */
2367 if (priv->info->clocking_setup) {
2368 rc = priv->info->clocking_setup(priv);
2369 if (rc < 0)
2370 goto out;
2371 }
2372
2373 for (i = 0; i < ds->num_ports; i++) {
2374 struct phylink_pcs *pcs = priv->pcs[i];
2375 unsigned int neg_mode;
2376
2377 mac[i].speed = mac_speed[i];
2378 rc = sja1105_set_port_config(priv, i);
2379 if (rc < 0)
2380 goto out;
2381
2382 if (!pcs)
2383 continue;
2384
2385 if (bmcr[i] & BMCR_ANENABLE)
2386 neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
2387 else
2388 neg_mode = PHYLINK_PCS_NEG_OUTBAND;
2389
2390 rc = pcs->ops->pcs_config(pcs, neg_mode, priv->phy_mode[i],
2391 NULL, true);
2392 if (rc < 0)
2393 goto out;
2394
2395 if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) {
2396 int speed = SPEED_UNKNOWN;
2397
2398 if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2399 speed = SPEED_2500;
2400 else if (bmcr[i] & BMCR_SPEED1000)
2401 speed = SPEED_1000;
2402 else if (bmcr[i] & BMCR_SPEED100)
2403 speed = SPEED_100;
2404 else
2405 speed = SPEED_10;
2406
2407 pcs->ops->pcs_link_up(pcs, neg_mode, priv->phy_mode[i],
2408 speed, DUPLEX_FULL);
2409 }
2410 }
2411
2412 rc = sja1105_reload_cbs(priv);
2413 if (rc < 0)
2414 goto out;
2415out:
2416 mutex_unlock(&priv->mgmt_lock);
2417 mutex_unlock(&priv->fdb_lock);
2418
2419 return rc;
2420}
2421
2422static enum dsa_tag_protocol
2423sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2424 enum dsa_tag_protocol mp)
2425{
2426 struct sja1105_private *priv = ds->priv;
2427
2428 return priv->info->tag_proto;
2429}
2430
2431/* The TPID setting belongs to the General Parameters table,
2432 * which can only be partially reconfigured at runtime (and not the TPID).
2433 * So a switch reset is required.
2434 */
2435int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2436 struct netlink_ext_ack *extack)
2437{
2438 struct sja1105_general_params_entry *general_params;
2439 struct sja1105_private *priv = ds->priv;
2440 struct sja1105_table *table;
2441 struct sja1105_rule *rule;
2442 u16 tpid, tpid2;
2443 int rc;
2444
2445 list_for_each_entry(rule, &priv->flow_block.rules, list) {
2446 if (rule->type == SJA1105_RULE_VL) {
2447 NL_SET_ERR_MSG_MOD(extack,
2448 "Cannot change VLAN filtering with active VL rules");
2449 return -EBUSY;
2450 }
2451 }
2452
2453 if (enabled) {
2454 /* Enable VLAN filtering. */
2455 tpid = ETH_P_8021Q;
2456 tpid2 = ETH_P_8021AD;
2457 } else {
2458 /* Disable VLAN filtering. */
2459 tpid = ETH_P_SJA1105;
2460 tpid2 = ETH_P_SJA1105;
2461 }
2462
2463 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2464 general_params = table->entries;
2465 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2466 general_params->tpid = tpid;
2467 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2468 general_params->tpid2 = tpid2;
2469
2470 for (port = 0; port < ds->num_ports; port++) {
2471 if (dsa_is_unused_port(ds, port))
2472 continue;
2473
2474 rc = sja1105_commit_pvid(ds, port);
2475 if (rc)
2476 return rc;
2477 }
2478
2479 rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2480 if (rc)
2481 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2482
2483 return rc;
2484}
2485
2486static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2487 u16 flags, bool allowed_ingress)
2488{
2489 struct sja1105_vlan_lookup_entry *vlan;
2490 struct sja1105_table *table;
2491 int match, rc;
2492
2493 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2494
2495 match = sja1105_is_vlan_configured(priv, vid);
2496 if (match < 0) {
2497 rc = sja1105_table_resize(table, table->entry_count + 1);
2498 if (rc)
2499 return rc;
2500 match = table->entry_count - 1;
2501 }
2502
2503 /* Assign pointer after the resize (it's new memory) */
2504 vlan = table->entries;
2505
2506 vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2507 vlan[match].vlanid = vid;
2508 vlan[match].vlan_bc |= BIT(port);
2509
2510 if (allowed_ingress)
2511 vlan[match].vmemb_port |= BIT(port);
2512 else
2513 vlan[match].vmemb_port &= ~BIT(port);
2514
2515 if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2516 vlan[match].tag_port &= ~BIT(port);
2517 else
2518 vlan[match].tag_port |= BIT(port);
2519
2520 return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2521 &vlan[match], true);
2522}
2523
2524static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2525{
2526 struct sja1105_vlan_lookup_entry *vlan;
2527 struct sja1105_table *table;
2528 bool keep = true;
2529 int match, rc;
2530
2531 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2532
2533 match = sja1105_is_vlan_configured(priv, vid);
2534 /* Can't delete a missing entry. */
2535 if (match < 0)
2536 return 0;
2537
2538 /* Assign pointer after the resize (it's new memory) */
2539 vlan = table->entries;
2540
2541 vlan[match].vlanid = vid;
2542 vlan[match].vlan_bc &= ~BIT(port);
2543 vlan[match].vmemb_port &= ~BIT(port);
2544 /* Also unset tag_port, just so we don't have a confusing bitmap
2545 * (no practical purpose).
2546 */
2547 vlan[match].tag_port &= ~BIT(port);
2548
2549 /* If there's no port left as member of this VLAN,
2550 * it's time for it to go.
2551 */
2552 if (!vlan[match].vmemb_port)
2553 keep = false;
2554
2555 rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2556 &vlan[match], keep);
2557 if (rc < 0)
2558 return rc;
2559
2560 if (!keep)
2561 return sja1105_table_delete_entry(table, match);
2562
2563 return 0;
2564}
2565
2566static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2567 const struct switchdev_obj_port_vlan *vlan,
2568 struct netlink_ext_ack *extack)
2569{
2570 struct sja1105_private *priv = ds->priv;
2571 u16 flags = vlan->flags;
2572 int rc;
2573
2574 /* Be sure to deny alterations to the configuration done by tag_8021q.
2575 */
2576 if (vid_is_dsa_8021q(vlan->vid)) {
2577 NL_SET_ERR_MSG_MOD(extack,
2578 "Range 3072-4095 reserved for dsa_8021q operation");
2579 return -EBUSY;
2580 }
2581
2582 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2583 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2584 flags = 0;
2585
2586 rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2587 if (rc)
2588 return rc;
2589
2590 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2591 priv->bridge_pvid[port] = vlan->vid;
2592
2593 return sja1105_commit_pvid(ds, port);
2594}
2595
2596static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2597 const struct switchdev_obj_port_vlan *vlan)
2598{
2599 struct sja1105_private *priv = ds->priv;
2600 int rc;
2601
2602 rc = sja1105_vlan_del(priv, port, vlan->vid);
2603 if (rc)
2604 return rc;
2605
2606 /* In case the pvid was deleted, make sure that untagged packets will
2607 * be dropped.
2608 */
2609 return sja1105_commit_pvid(ds, port);
2610}
2611
2612static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2613 u16 flags)
2614{
2615 struct sja1105_private *priv = ds->priv;
2616 bool allowed_ingress = true;
2617 int rc;
2618
2619 /* Prevent attackers from trying to inject a DSA tag from
2620 * the outside world.
2621 */
2622 if (dsa_is_user_port(ds, port))
2623 allowed_ingress = false;
2624
2625 rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2626 if (rc)
2627 return rc;
2628
2629 if (flags & BRIDGE_VLAN_INFO_PVID)
2630 priv->tag_8021q_pvid[port] = vid;
2631
2632 return sja1105_commit_pvid(ds, port);
2633}
2634
2635static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2636{
2637 struct sja1105_private *priv = ds->priv;
2638
2639 return sja1105_vlan_del(priv, port, vid);
2640}
2641
2642static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2643 struct netdev_notifier_changeupper_info *info)
2644{
2645 struct netlink_ext_ack *extack = info->info.extack;
2646 struct net_device *upper = info->upper_dev;
2647 struct dsa_switch_tree *dst = ds->dst;
2648 struct dsa_port *dp;
2649
2650 if (is_vlan_dev(upper)) {
2651 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2652 return -EBUSY;
2653 }
2654
2655 if (netif_is_bridge_master(upper)) {
2656 list_for_each_entry(dp, &dst->ports, list) {
2657 struct net_device *br = dsa_port_bridge_dev_get(dp);
2658
2659 if (br && br != upper && br_vlan_enabled(br)) {
2660 NL_SET_ERR_MSG_MOD(extack,
2661 "Only one VLAN-aware bridge is supported");
2662 return -EBUSY;
2663 }
2664 }
2665 }
2666
2667 return 0;
2668}
2669
2670static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2671 struct sk_buff *skb, bool takets)
2672{
2673 struct sja1105_mgmt_entry mgmt_route = {0};
2674 struct sja1105_private *priv = ds->priv;
2675 struct ethhdr *hdr;
2676 int timeout = 10;
2677 int rc;
2678
2679 hdr = eth_hdr(skb);
2680
2681 mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2682 mgmt_route.destports = BIT(port);
2683 mgmt_route.enfport = 1;
2684 mgmt_route.tsreg = 0;
2685 mgmt_route.takets = takets;
2686
2687 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2688 slot, &mgmt_route, true);
2689 if (rc < 0) {
2690 kfree_skb(skb);
2691 return rc;
2692 }
2693
2694 /* Transfer skb to the host port. */
2695 dsa_enqueue_skb(skb, dsa_to_port(ds, port)->user);
2696
2697 /* Wait until the switch has processed the frame */
2698 do {
2699 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2700 slot, &mgmt_route);
2701 if (rc < 0) {
2702 dev_err_ratelimited(priv->ds->dev,
2703 "failed to poll for mgmt route\n");
2704 continue;
2705 }
2706
2707 /* UM10944: The ENFPORT flag of the respective entry is
2708 * cleared when a match is found. The host can use this
2709 * flag as an acknowledgment.
2710 */
2711 cpu_relax();
2712 } while (mgmt_route.enfport && --timeout);
2713
2714 if (!timeout) {
2715 /* Clean up the management route so that a follow-up
2716 * frame may not match on it by mistake.
2717 * This is only hardware supported on P/Q/R/S - on E/T it is
2718 * a no-op and we are silently discarding the -EOPNOTSUPP.
2719 */
2720 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2721 slot, &mgmt_route, false);
2722 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2723 }
2724
2725 return NETDEV_TX_OK;
2726}
2727
2728#define work_to_xmit_work(w) \
2729 container_of((w), struct sja1105_deferred_xmit_work, work)
2730
2731/* Deferred work is unfortunately necessary because setting up the management
2732 * route cannot be done from atomit context (SPI transfer takes a sleepable
2733 * lock on the bus)
2734 */
2735static void sja1105_port_deferred_xmit(struct kthread_work *work)
2736{
2737 struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
2738 struct sk_buff *clone, *skb = xmit_work->skb;
2739 struct dsa_switch *ds = xmit_work->dp->ds;
2740 struct sja1105_private *priv = ds->priv;
2741 int port = xmit_work->dp->index;
2742
2743 clone = SJA1105_SKB_CB(skb)->clone;
2744
2745 mutex_lock(&priv->mgmt_lock);
2746
2747 sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);
2748
2749 /* The clone, if there, was made by dsa_skb_tx_timestamp */
2750 if (clone)
2751 sja1105_ptp_txtstamp_skb(ds, port, clone);
2752
2753 mutex_unlock(&priv->mgmt_lock);
2754
2755 kfree(xmit_work);
2756}
2757
2758static int sja1105_connect_tag_protocol(struct dsa_switch *ds,
2759 enum dsa_tag_protocol proto)
2760{
2761 struct sja1105_private *priv = ds->priv;
2762 struct sja1105_tagger_data *tagger_data;
2763
2764 if (proto != priv->info->tag_proto)
2765 return -EPROTONOSUPPORT;
2766
2767 tagger_data = sja1105_tagger_data(ds);
2768 tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;
2769 tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;
2770
2771 return 0;
2772}
2773
2774/* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2775 * which cannot be reconfigured at runtime. So a switch reset is required.
2776 */
2777static int sja1105_set_ageing_time(struct dsa_switch *ds,
2778 unsigned int ageing_time)
2779{
2780 struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2781 struct sja1105_private *priv = ds->priv;
2782 struct sja1105_table *table;
2783 unsigned int maxage;
2784
2785 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2786 l2_lookup_params = table->entries;
2787
2788 maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2789
2790 if (l2_lookup_params->maxage == maxage)
2791 return 0;
2792
2793 l2_lookup_params->maxage = maxage;
2794
2795 return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2796}
2797
2798static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2799{
2800 struct sja1105_l2_policing_entry *policing;
2801 struct sja1105_private *priv = ds->priv;
2802
2803 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2804
2805 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2806 new_mtu += VLAN_HLEN;
2807
2808 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2809
2810 if (policing[port].maxlen == new_mtu)
2811 return 0;
2812
2813 policing[port].maxlen = new_mtu;
2814
2815 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2816}
2817
2818static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2819{
2820 return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2821}
2822
2823static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2824 enum tc_setup_type type,
2825 void *type_data)
2826{
2827 switch (type) {
2828 case TC_SETUP_QDISC_TAPRIO:
2829 return sja1105_setup_tc_taprio(ds, port, type_data);
2830 case TC_SETUP_QDISC_CBS:
2831 return sja1105_setup_tc_cbs(ds, port, type_data);
2832 default:
2833 return -EOPNOTSUPP;
2834 }
2835}
2836
2837/* We have a single mirror (@to) port, but can configure ingress and egress
2838 * mirroring on all other (@from) ports.
2839 * We need to allow mirroring rules only as long as the @to port is always the
2840 * same, and we need to unset the @to port from mirr_port only when there is no
2841 * mirroring rule that references it.
2842 */
2843static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2844 bool ingress, bool enabled)
2845{
2846 struct sja1105_general_params_entry *general_params;
2847 struct sja1105_mac_config_entry *mac;
2848 struct dsa_switch *ds = priv->ds;
2849 struct sja1105_table *table;
2850 bool already_enabled;
2851 u64 new_mirr_port;
2852 int rc;
2853
2854 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2855 general_params = table->entries;
2856
2857 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2858
2859 already_enabled = (general_params->mirr_port != ds->num_ports);
2860 if (already_enabled && enabled && general_params->mirr_port != to) {
2861 dev_err(priv->ds->dev,
2862 "Delete mirroring rules towards port %llu first\n",
2863 general_params->mirr_port);
2864 return -EBUSY;
2865 }
2866
2867 new_mirr_port = to;
2868 if (!enabled) {
2869 bool keep = false;
2870 int port;
2871
2872 /* Anybody still referencing mirr_port? */
2873 for (port = 0; port < ds->num_ports; port++) {
2874 if (mac[port].ing_mirr || mac[port].egr_mirr) {
2875 keep = true;
2876 break;
2877 }
2878 }
2879 /* Unset already_enabled for next time */
2880 if (!keep)
2881 new_mirr_port = ds->num_ports;
2882 }
2883 if (new_mirr_port != general_params->mirr_port) {
2884 general_params->mirr_port = new_mirr_port;
2885
2886 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2887 0, general_params, true);
2888 if (rc < 0)
2889 return rc;
2890 }
2891
2892 if (ingress)
2893 mac[from].ing_mirr = enabled;
2894 else
2895 mac[from].egr_mirr = enabled;
2896
2897 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2898 &mac[from], true);
2899}
2900
2901static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2902 struct dsa_mall_mirror_tc_entry *mirror,
2903 bool ingress, struct netlink_ext_ack *extack)
2904{
2905 return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2906 ingress, true);
2907}
2908
2909static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2910 struct dsa_mall_mirror_tc_entry *mirror)
2911{
2912 sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2913 mirror->ingress, false);
2914}
2915
2916static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2917 struct dsa_mall_policer_tc_entry *policer)
2918{
2919 struct sja1105_l2_policing_entry *policing;
2920 struct sja1105_private *priv = ds->priv;
2921
2922 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2923
2924 /* In hardware, every 8 microseconds the credit level is incremented by
2925 * the value of RATE bytes divided by 64, up to a maximum of SMAX
2926 * bytes.
2927 */
2928 policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2929 1000000);
2930 policing[port].smax = policer->burst;
2931
2932 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2933}
2934
2935static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2936{
2937 struct sja1105_l2_policing_entry *policing;
2938 struct sja1105_private *priv = ds->priv;
2939
2940 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2941
2942 policing[port].rate = SJA1105_RATE_MBPS(1000);
2943 policing[port].smax = 65535;
2944
2945 sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2946}
2947
2948static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2949 bool enabled)
2950{
2951 struct sja1105_mac_config_entry *mac;
2952
2953 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2954
2955 mac[port].dyn_learn = enabled;
2956
2957 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2958 &mac[port], true);
2959}
2960
2961static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2962 struct switchdev_brport_flags flags)
2963{
2964 if (flags.mask & BR_FLOOD) {
2965 if (flags.val & BR_FLOOD)
2966 priv->ucast_egress_floods |= BIT(to);
2967 else
2968 priv->ucast_egress_floods &= ~BIT(to);
2969 }
2970
2971 if (flags.mask & BR_BCAST_FLOOD) {
2972 if (flags.val & BR_BCAST_FLOOD)
2973 priv->bcast_egress_floods |= BIT(to);
2974 else
2975 priv->bcast_egress_floods &= ~BIT(to);
2976 }
2977
2978 return sja1105_manage_flood_domains(priv);
2979}
2980
2981static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2982 struct switchdev_brport_flags flags,
2983 struct netlink_ext_ack *extack)
2984{
2985 struct sja1105_l2_lookup_entry *l2_lookup;
2986 struct sja1105_table *table;
2987 int match, rc;
2988
2989 mutex_lock(&priv->fdb_lock);
2990
2991 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2992 l2_lookup = table->entries;
2993
2994 for (match = 0; match < table->entry_count; match++)
2995 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2996 l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2997 break;
2998
2999 if (match == table->entry_count) {
3000 NL_SET_ERR_MSG_MOD(extack,
3001 "Could not find FDB entry for unknown multicast");
3002 rc = -ENOSPC;
3003 goto out;
3004 }
3005
3006 if (flags.val & BR_MCAST_FLOOD)
3007 l2_lookup[match].destports |= BIT(to);
3008 else
3009 l2_lookup[match].destports &= ~BIT(to);
3010
3011 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
3012 l2_lookup[match].index,
3013 &l2_lookup[match], true);
3014out:
3015 mutex_unlock(&priv->fdb_lock);
3016
3017 return rc;
3018}
3019
3020static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3021 struct switchdev_brport_flags flags,
3022 struct netlink_ext_ack *extack)
3023{
3024 struct sja1105_private *priv = ds->priv;
3025
3026 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
3027 BR_BCAST_FLOOD))
3028 return -EINVAL;
3029
3030 if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
3031 !priv->info->can_limit_mcast_flood) {
3032 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
3033 bool unicast = !!(flags.val & BR_FLOOD);
3034
3035 if (unicast != multicast) {
3036 NL_SET_ERR_MSG_MOD(extack,
3037 "This chip cannot configure multicast flooding independently of unicast");
3038 return -EINVAL;
3039 }
3040 }
3041
3042 return 0;
3043}
3044
3045static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
3046 struct switchdev_brport_flags flags,
3047 struct netlink_ext_ack *extack)
3048{
3049 struct sja1105_private *priv = ds->priv;
3050 int rc;
3051
3052 if (flags.mask & BR_LEARNING) {
3053 bool learn_ena = !!(flags.val & BR_LEARNING);
3054
3055 rc = sja1105_port_set_learning(priv, port, learn_ena);
3056 if (rc)
3057 return rc;
3058 }
3059
3060 if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
3061 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
3062 if (rc)
3063 return rc;
3064 }
3065
3066 /* For chips that can't offload BR_MCAST_FLOOD independently, there
3067 * is nothing to do here, we ensured the configuration is in sync by
3068 * offloading BR_FLOOD.
3069 */
3070 if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
3071 rc = sja1105_port_mcast_flood(priv, port, flags,
3072 extack);
3073 if (rc)
3074 return rc;
3075 }
3076
3077 return 0;
3078}
3079
3080/* The programming model for the SJA1105 switch is "all-at-once" via static
3081 * configuration tables. Some of these can be dynamically modified at runtime,
3082 * but not the xMII mode parameters table.
3083 * Furthermode, some PHYs may not have crystals for generating their clocks
3084 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3085 * ref_clk pin. So port clocking needs to be initialized early, before
3086 * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3087 * Setting correct PHY link speed does not matter now.
3088 * But dsa_user_phy_setup is called later than sja1105_setup, so the PHY
3089 * bindings are not yet parsed by DSA core. We need to parse early so that we
3090 * can populate the xMII mode parameters table.
3091 */
3092static int sja1105_setup(struct dsa_switch *ds)
3093{
3094 struct sja1105_private *priv = ds->priv;
3095 int rc;
3096
3097 if (priv->info->disable_microcontroller) {
3098 rc = priv->info->disable_microcontroller(priv);
3099 if (rc < 0) {
3100 dev_err(ds->dev,
3101 "Failed to disable microcontroller: %pe\n",
3102 ERR_PTR(rc));
3103 return rc;
3104 }
3105 }
3106
3107 /* Create and send configuration down to device */
3108 rc = sja1105_static_config_load(priv);
3109 if (rc < 0) {
3110 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3111 return rc;
3112 }
3113
3114 /* Configure the CGU (PHY link modes and speeds) */
3115 if (priv->info->clocking_setup) {
3116 rc = priv->info->clocking_setup(priv);
3117 if (rc < 0) {
3118 dev_err(ds->dev,
3119 "Failed to configure MII clocking: %pe\n",
3120 ERR_PTR(rc));
3121 goto out_static_config_free;
3122 }
3123 }
3124
3125 sja1105_tas_setup(ds);
3126 sja1105_flower_setup(ds);
3127
3128 rc = sja1105_ptp_clock_register(ds);
3129 if (rc < 0) {
3130 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3131 goto out_flower_teardown;
3132 }
3133
3134 rc = sja1105_mdiobus_register(ds);
3135 if (rc < 0) {
3136 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3137 ERR_PTR(rc));
3138 goto out_ptp_clock_unregister;
3139 }
3140
3141 rc = sja1105_devlink_setup(ds);
3142 if (rc < 0)
3143 goto out_mdiobus_unregister;
3144
3145 rtnl_lock();
3146 rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3147 rtnl_unlock();
3148 if (rc)
3149 goto out_devlink_teardown;
3150
3151 /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3152 * The only thing we can do to disable it is lie about what the 802.1Q
3153 * EtherType is.
3154 * So it will still try to apply VLAN filtering, but all ingress
3155 * traffic (except frames received with EtherType of ETH_P_SJA1105)
3156 * will be internally tagged with a distorted VLAN header where the
3157 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3158 */
3159 ds->vlan_filtering_is_global = true;
3160 ds->fdb_isolation = true;
3161 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES;
3162
3163 /* Advertise the 8 egress queues */
3164 ds->num_tx_queues = SJA1105_NUM_TC;
3165
3166 ds->mtu_enforcement_ingress = true;
3167 ds->assisted_learning_on_cpu_port = true;
3168
3169 return 0;
3170
3171out_devlink_teardown:
3172 sja1105_devlink_teardown(ds);
3173out_mdiobus_unregister:
3174 sja1105_mdiobus_unregister(ds);
3175out_ptp_clock_unregister:
3176 sja1105_ptp_clock_unregister(ds);
3177out_flower_teardown:
3178 sja1105_flower_teardown(ds);
3179 sja1105_tas_teardown(ds);
3180out_static_config_free:
3181 sja1105_static_config_free(&priv->static_config);
3182
3183 return rc;
3184}
3185
3186static void sja1105_teardown(struct dsa_switch *ds)
3187{
3188 struct sja1105_private *priv = ds->priv;
3189
3190 rtnl_lock();
3191 dsa_tag_8021q_unregister(ds);
3192 rtnl_unlock();
3193
3194 sja1105_devlink_teardown(ds);
3195 sja1105_mdiobus_unregister(ds);
3196 sja1105_ptp_clock_unregister(ds);
3197 sja1105_flower_teardown(ds);
3198 sja1105_tas_teardown(ds);
3199 sja1105_static_config_free(&priv->static_config);
3200}
3201
3202static const struct phylink_mac_ops sja1105_phylink_mac_ops = {
3203 .mac_select_pcs = sja1105_mac_select_pcs,
3204 .mac_config = sja1105_mac_config,
3205 .mac_link_up = sja1105_mac_link_up,
3206 .mac_link_down = sja1105_mac_link_down,
3207};
3208
3209static const struct dsa_switch_ops sja1105_switch_ops = {
3210 .get_tag_protocol = sja1105_get_tag_protocol,
3211 .connect_tag_protocol = sja1105_connect_tag_protocol,
3212 .setup = sja1105_setup,
3213 .teardown = sja1105_teardown,
3214 .set_ageing_time = sja1105_set_ageing_time,
3215 .port_change_mtu = sja1105_change_mtu,
3216 .port_max_mtu = sja1105_get_max_mtu,
3217 .phylink_get_caps = sja1105_phylink_get_caps,
3218 .get_strings = sja1105_get_strings,
3219 .get_ethtool_stats = sja1105_get_ethtool_stats,
3220 .get_sset_count = sja1105_get_sset_count,
3221 .get_ts_info = sja1105_get_ts_info,
3222 .port_fdb_dump = sja1105_fdb_dump,
3223 .port_fdb_add = sja1105_fdb_add,
3224 .port_fdb_del = sja1105_fdb_del,
3225 .port_fast_age = sja1105_fast_age,
3226 .port_bridge_join = sja1105_bridge_join,
3227 .port_bridge_leave = sja1105_bridge_leave,
3228 .port_pre_bridge_flags = sja1105_port_pre_bridge_flags,
3229 .port_bridge_flags = sja1105_port_bridge_flags,
3230 .port_stp_state_set = sja1105_bridge_stp_state_set,
3231 .port_vlan_filtering = sja1105_vlan_filtering,
3232 .port_vlan_add = sja1105_bridge_vlan_add,
3233 .port_vlan_del = sja1105_bridge_vlan_del,
3234 .port_mdb_add = sja1105_mdb_add,
3235 .port_mdb_del = sja1105_mdb_del,
3236 .port_hwtstamp_get = sja1105_hwtstamp_get,
3237 .port_hwtstamp_set = sja1105_hwtstamp_set,
3238 .port_rxtstamp = sja1105_port_rxtstamp,
3239 .port_txtstamp = sja1105_port_txtstamp,
3240 .port_setup_tc = sja1105_port_setup_tc,
3241 .port_mirror_add = sja1105_mirror_add,
3242 .port_mirror_del = sja1105_mirror_del,
3243 .port_policer_add = sja1105_port_policer_add,
3244 .port_policer_del = sja1105_port_policer_del,
3245 .cls_flower_add = sja1105_cls_flower_add,
3246 .cls_flower_del = sja1105_cls_flower_del,
3247 .cls_flower_stats = sja1105_cls_flower_stats,
3248 .devlink_info_get = sja1105_devlink_info_get,
3249 .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add,
3250 .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del,
3251 .port_prechangeupper = sja1105_prechangeupper,
3252};
3253
3254static const struct of_device_id sja1105_dt_ids[];
3255
3256static int sja1105_check_device_id(struct sja1105_private *priv)
3257{
3258 const struct sja1105_regs *regs = priv->info->regs;
3259 u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3260 struct device *dev = &priv->spidev->dev;
3261 const struct of_device_id *match;
3262 u32 device_id;
3263 u64 part_no;
3264 int rc;
3265
3266 rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3267 NULL);
3268 if (rc < 0)
3269 return rc;
3270
3271 rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3272 SJA1105_SIZE_DEVICE_ID);
3273 if (rc < 0)
3274 return rc;
3275
3276 sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3277
3278 for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3279 const struct sja1105_info *info = match->data;
3280
3281 /* Is what's been probed in our match table at all? */
3282 if (info->device_id != device_id || info->part_no != part_no)
3283 continue;
3284
3285 /* But is it what's in the device tree? */
3286 if (priv->info->device_id != device_id ||
3287 priv->info->part_no != part_no) {
3288 dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3289 priv->info->name, info->name);
3290 /* It isn't. No problem, pick that up. */
3291 priv->info = info;
3292 }
3293
3294 return 0;
3295 }
3296
3297 dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3298 device_id, part_no);
3299
3300 return -ENODEV;
3301}
3302
3303static int sja1105_probe(struct spi_device *spi)
3304{
3305 struct device *dev = &spi->dev;
3306 struct sja1105_private *priv;
3307 size_t max_xfer, max_msg;
3308 struct dsa_switch *ds;
3309 int rc;
3310
3311 if (!dev->of_node) {
3312 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3313 return -EINVAL;
3314 }
3315
3316 rc = sja1105_hw_reset(dev, 1, 1);
3317 if (rc)
3318 return rc;
3319
3320 priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3321 if (!priv)
3322 return -ENOMEM;
3323
3324 /* Populate our driver private structure (priv) based on
3325 * the device tree node that was probed (spi)
3326 */
3327 priv->spidev = spi;
3328 spi_set_drvdata(spi, priv);
3329
3330 /* Configure the SPI bus */
3331 spi->bits_per_word = 8;
3332 rc = spi_setup(spi);
3333 if (rc < 0) {
3334 dev_err(dev, "Could not init SPI\n");
3335 return rc;
3336 }
3337
3338 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3339 * a small one for the message header and another one for the current
3340 * chunk of the packed buffer.
3341 * Check that the restrictions imposed by the SPI controller are
3342 * respected: the chunk buffer is smaller than the max transfer size,
3343 * and the total length of the chunk plus its message header is smaller
3344 * than the max message size.
3345 * We do that during probe time since the maximum transfer size is a
3346 * runtime invariant.
3347 */
3348 max_xfer = spi_max_transfer_size(spi);
3349 max_msg = spi_max_message_size(spi);
3350
3351 /* We need to send at least one 64-bit word of SPI payload per message
3352 * in order to be able to make useful progress.
3353 */
3354 if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3355 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3356 return -EINVAL;
3357 }
3358
3359 priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3360 if (priv->max_xfer_len > max_xfer)
3361 priv->max_xfer_len = max_xfer;
3362 if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3363 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3364
3365 priv->info = of_device_get_match_data(dev);
3366
3367 /* Detect hardware device */
3368 rc = sja1105_check_device_id(priv);
3369 if (rc < 0) {
3370 dev_err(dev, "Device ID check failed: %d\n", rc);
3371 return rc;
3372 }
3373
3374 dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3375
3376 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3377 if (!ds)
3378 return -ENOMEM;
3379
3380 ds->dev = dev;
3381 ds->num_ports = priv->info->num_ports;
3382 ds->ops = &sja1105_switch_ops;
3383 ds->phylink_mac_ops = &sja1105_phylink_mac_ops;
3384 ds->priv = priv;
3385 priv->ds = ds;
3386
3387 mutex_init(&priv->ptp_data.lock);
3388 mutex_init(&priv->dynamic_config_lock);
3389 mutex_init(&priv->mgmt_lock);
3390 mutex_init(&priv->fdb_lock);
3391 spin_lock_init(&priv->ts_id_lock);
3392
3393 rc = sja1105_parse_dt(priv);
3394 if (rc < 0) {
3395 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3396 return rc;
3397 }
3398
3399 if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3400 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3401 sizeof(struct sja1105_cbs_entry),
3402 GFP_KERNEL);
3403 if (!priv->cbs)
3404 return -ENOMEM;
3405 }
3406
3407 return dsa_register_switch(priv->ds);
3408}
3409
3410static void sja1105_remove(struct spi_device *spi)
3411{
3412 struct sja1105_private *priv = spi_get_drvdata(spi);
3413
3414 if (!priv)
3415 return;
3416
3417 dsa_unregister_switch(priv->ds);
3418}
3419
3420static void sja1105_shutdown(struct spi_device *spi)
3421{
3422 struct sja1105_private *priv = spi_get_drvdata(spi);
3423
3424 if (!priv)
3425 return;
3426
3427 dsa_switch_shutdown(priv->ds);
3428
3429 spi_set_drvdata(spi, NULL);
3430}
3431
3432static const struct of_device_id sja1105_dt_ids[] = {
3433 { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3434 { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3435 { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3436 { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3437 { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3438 { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3439 { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3440 { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3441 { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3442 { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3443 { /* sentinel */ },
3444};
3445MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3446
3447static const struct spi_device_id sja1105_spi_ids[] = {
3448 { "sja1105e" },
3449 { "sja1105t" },
3450 { "sja1105p" },
3451 { "sja1105q" },
3452 { "sja1105r" },
3453 { "sja1105s" },
3454 { "sja1110a" },
3455 { "sja1110b" },
3456 { "sja1110c" },
3457 { "sja1110d" },
3458 { },
3459};
3460MODULE_DEVICE_TABLE(spi, sja1105_spi_ids);
3461
3462static struct spi_driver sja1105_driver = {
3463 .driver = {
3464 .name = "sja1105",
3465 .of_match_table = of_match_ptr(sja1105_dt_ids),
3466 },
3467 .id_table = sja1105_spi_ids,
3468 .probe = sja1105_probe,
3469 .remove = sja1105_remove,
3470 .shutdown = sja1105_shutdown,
3471};
3472
3473module_spi_driver(sja1105_driver);
3474
3475MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3476MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3477MODULE_DESCRIPTION("SJA1105 Driver");
3478MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
4 */
5
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include <linux/delay.h>
9#include <linux/module.h>
10#include <linux/printk.h>
11#include <linux/spi/spi.h>
12#include <linux/errno.h>
13#include <linux/gpio/consumer.h>
14#include <linux/phylink.h>
15#include <linux/of.h>
16#include <linux/of_net.h>
17#include <linux/of_mdio.h>
18#include <linux/pcs/pcs-xpcs.h>
19#include <linux/netdev_features.h>
20#include <linux/netdevice.h>
21#include <linux/if_bridge.h>
22#include <linux/if_ether.h>
23#include <linux/dsa/8021q.h>
24#include <linux/units.h>
25
26#include "sja1105.h"
27#include "sja1105_tas.h"
28
29#define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull
30
31/* Configure the optional reset pin and bring up switch */
32static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
33 unsigned int startup_delay)
34{
35 struct gpio_desc *gpio;
36
37 gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
38 if (IS_ERR(gpio))
39 return PTR_ERR(gpio);
40
41 if (!gpio)
42 return 0;
43
44 gpiod_set_value_cansleep(gpio, 1);
45 /* Wait for minimum reset pulse length */
46 msleep(pulse_len);
47 gpiod_set_value_cansleep(gpio, 0);
48 /* Wait until chip is ready after reset */
49 msleep(startup_delay);
50
51 gpiod_put(gpio);
52
53 return 0;
54}
55
56static void
57sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
58 int from, int to, bool allow)
59{
60 if (allow)
61 l2_fwd[from].reach_port |= BIT(to);
62 else
63 l2_fwd[from].reach_port &= ~BIT(to);
64}
65
66static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
67 int from, int to)
68{
69 return !!(l2_fwd[from].reach_port & BIT(to));
70}
71
72static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
73{
74 struct sja1105_vlan_lookup_entry *vlan;
75 int count, i;
76
77 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
78 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
79
80 for (i = 0; i < count; i++)
81 if (vlan[i].vlanid == vid)
82 return i;
83
84 /* Return an invalid entry index if not found */
85 return -1;
86}
87
88static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
89{
90 struct sja1105_private *priv = ds->priv;
91 struct sja1105_mac_config_entry *mac;
92
93 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
94
95 if (mac[port].drpuntag == drop)
96 return 0;
97
98 mac[port].drpuntag = drop;
99
100 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
101 &mac[port], true);
102}
103
104static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
105{
106 struct sja1105_mac_config_entry *mac;
107
108 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
109
110 if (mac[port].vlanid == pvid)
111 return 0;
112
113 mac[port].vlanid = pvid;
114
115 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
116 &mac[port], true);
117}
118
119static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
120{
121 struct dsa_port *dp = dsa_to_port(ds, port);
122 struct net_device *br = dsa_port_bridge_dev_get(dp);
123 struct sja1105_private *priv = ds->priv;
124 struct sja1105_vlan_lookup_entry *vlan;
125 bool drop_untagged = false;
126 int match, rc;
127 u16 pvid;
128
129 if (br && br_vlan_enabled(br))
130 pvid = priv->bridge_pvid[port];
131 else
132 pvid = priv->tag_8021q_pvid[port];
133
134 rc = sja1105_pvid_apply(priv, port, pvid);
135 if (rc)
136 return rc;
137
138 /* Only force dropping of untagged packets when the port is under a
139 * VLAN-aware bridge. When the tag_8021q pvid is used, we are
140 * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
141 * to prevent DSA tag spoofing from the link partner. Untagged packets
142 * are the only ones that should be received with tag_8021q, so
143 * definitely don't drop them.
144 */
145 if (pvid == priv->bridge_pvid[port]) {
146 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
147
148 match = sja1105_is_vlan_configured(priv, pvid);
149
150 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
151 drop_untagged = true;
152 }
153
154 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
155 drop_untagged = true;
156
157 return sja1105_drop_untagged(ds, port, drop_untagged);
158}
159
160static int sja1105_init_mac_settings(struct sja1105_private *priv)
161{
162 struct sja1105_mac_config_entry default_mac = {
163 /* Enable all 8 priority queues on egress.
164 * Every queue i holds top[i] - base[i] frames.
165 * Sum of top[i] - base[i] is 511 (max hardware limit).
166 */
167 .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
168 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
169 .enabled = {true, true, true, true, true, true, true, true},
170 /* Keep standard IFG of 12 bytes on egress. */
171 .ifg = 0,
172 /* Always put the MAC speed in automatic mode, where it can be
173 * adjusted at runtime by PHYLINK.
174 */
175 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
176 /* No static correction for 1-step 1588 events */
177 .tp_delin = 0,
178 .tp_delout = 0,
179 /* Disable aging for critical TTEthernet traffic */
180 .maxage = 0xFF,
181 /* Internal VLAN (pvid) to apply to untagged ingress */
182 .vlanprio = 0,
183 .vlanid = 1,
184 .ing_mirr = false,
185 .egr_mirr = false,
186 /* Don't drop traffic with other EtherType than ETH_P_IP */
187 .drpnona664 = false,
188 /* Don't drop double-tagged traffic */
189 .drpdtag = false,
190 /* Don't drop untagged traffic */
191 .drpuntag = false,
192 /* Don't retag 802.1p (VID 0) traffic with the pvid */
193 .retag = false,
194 /* Disable learning and I/O on user ports by default -
195 * STP will enable it.
196 */
197 .dyn_learn = false,
198 .egress = false,
199 .ingress = false,
200 };
201 struct sja1105_mac_config_entry *mac;
202 struct dsa_switch *ds = priv->ds;
203 struct sja1105_table *table;
204 struct dsa_port *dp;
205
206 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
207
208 /* Discard previous MAC Configuration Table */
209 if (table->entry_count) {
210 kfree(table->entries);
211 table->entry_count = 0;
212 }
213
214 table->entries = kcalloc(table->ops->max_entry_count,
215 table->ops->unpacked_entry_size, GFP_KERNEL);
216 if (!table->entries)
217 return -ENOMEM;
218
219 table->entry_count = table->ops->max_entry_count;
220
221 mac = table->entries;
222
223 list_for_each_entry(dp, &ds->dst->ports, list) {
224 if (dp->ds != ds)
225 continue;
226
227 mac[dp->index] = default_mac;
228
229 /* Let sja1105_bridge_stp_state_set() keep address learning
230 * enabled for the DSA ports. CPU ports use software-assisted
231 * learning to ensure that only FDB entries belonging to the
232 * bridge are learned, and that they are learned towards all
233 * CPU ports in a cross-chip topology if multiple CPU ports
234 * exist.
235 */
236 if (dsa_port_is_dsa(dp))
237 dp->learning = true;
238
239 /* Disallow untagged packets from being received on the
240 * CPU and DSA ports.
241 */
242 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
243 mac[dp->index].drpuntag = true;
244 }
245
246 return 0;
247}
248
249static int sja1105_init_mii_settings(struct sja1105_private *priv)
250{
251 struct device *dev = &priv->spidev->dev;
252 struct sja1105_xmii_params_entry *mii;
253 struct dsa_switch *ds = priv->ds;
254 struct sja1105_table *table;
255 int i;
256
257 table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
258
259 /* Discard previous xMII Mode Parameters Table */
260 if (table->entry_count) {
261 kfree(table->entries);
262 table->entry_count = 0;
263 }
264
265 table->entries = kcalloc(table->ops->max_entry_count,
266 table->ops->unpacked_entry_size, GFP_KERNEL);
267 if (!table->entries)
268 return -ENOMEM;
269
270 /* Override table based on PHYLINK DT bindings */
271 table->entry_count = table->ops->max_entry_count;
272
273 mii = table->entries;
274
275 for (i = 0; i < ds->num_ports; i++) {
276 sja1105_mii_role_t role = XMII_MAC;
277
278 if (dsa_is_unused_port(priv->ds, i))
279 continue;
280
281 switch (priv->phy_mode[i]) {
282 case PHY_INTERFACE_MODE_INTERNAL:
283 if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
284 goto unsupported;
285
286 mii->xmii_mode[i] = XMII_MODE_MII;
287 if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
288 mii->special[i] = true;
289
290 break;
291 case PHY_INTERFACE_MODE_REVMII:
292 role = XMII_PHY;
293 fallthrough;
294 case PHY_INTERFACE_MODE_MII:
295 if (!priv->info->supports_mii[i])
296 goto unsupported;
297
298 mii->xmii_mode[i] = XMII_MODE_MII;
299 break;
300 case PHY_INTERFACE_MODE_REVRMII:
301 role = XMII_PHY;
302 fallthrough;
303 case PHY_INTERFACE_MODE_RMII:
304 if (!priv->info->supports_rmii[i])
305 goto unsupported;
306
307 mii->xmii_mode[i] = XMII_MODE_RMII;
308 break;
309 case PHY_INTERFACE_MODE_RGMII:
310 case PHY_INTERFACE_MODE_RGMII_ID:
311 case PHY_INTERFACE_MODE_RGMII_RXID:
312 case PHY_INTERFACE_MODE_RGMII_TXID:
313 if (!priv->info->supports_rgmii[i])
314 goto unsupported;
315
316 mii->xmii_mode[i] = XMII_MODE_RGMII;
317 break;
318 case PHY_INTERFACE_MODE_SGMII:
319 if (!priv->info->supports_sgmii[i])
320 goto unsupported;
321
322 mii->xmii_mode[i] = XMII_MODE_SGMII;
323 mii->special[i] = true;
324 break;
325 case PHY_INTERFACE_MODE_2500BASEX:
326 if (!priv->info->supports_2500basex[i])
327 goto unsupported;
328
329 mii->xmii_mode[i] = XMII_MODE_SGMII;
330 mii->special[i] = true;
331 break;
332unsupported:
333 default:
334 dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
335 phy_modes(priv->phy_mode[i]), i);
336 return -EINVAL;
337 }
338
339 mii->phy_mac[i] = role;
340 }
341 return 0;
342}
343
344static int sja1105_init_static_fdb(struct sja1105_private *priv)
345{
346 struct sja1105_l2_lookup_entry *l2_lookup;
347 struct sja1105_table *table;
348 int port;
349
350 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
351
352 /* We only populate the FDB table through dynamic L2 Address Lookup
353 * entries, except for a special entry at the end which is a catch-all
354 * for unknown multicast and will be used to control flooding domain.
355 */
356 if (table->entry_count) {
357 kfree(table->entries);
358 table->entry_count = 0;
359 }
360
361 if (!priv->info->can_limit_mcast_flood)
362 return 0;
363
364 table->entries = kcalloc(1, table->ops->unpacked_entry_size,
365 GFP_KERNEL);
366 if (!table->entries)
367 return -ENOMEM;
368
369 table->entry_count = 1;
370 l2_lookup = table->entries;
371
372 /* All L2 multicast addresses have an odd first octet */
373 l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
374 l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
375 l2_lookup[0].lockeds = true;
376 l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
377
378 /* Flood multicast to every port by default */
379 for (port = 0; port < priv->ds->num_ports; port++)
380 if (!dsa_is_unused_port(priv->ds, port))
381 l2_lookup[0].destports |= BIT(port);
382
383 return 0;
384}
385
386static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
387{
388 struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
389 /* Learned FDB entries are forgotten after 300 seconds */
390 .maxage = SJA1105_AGEING_TIME_MS(300000),
391 /* All entries within a FDB bin are available for learning */
392 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
393 /* And the P/Q/R/S equivalent setting: */
394 .start_dynspc = 0,
395 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
396 .poly = 0x97,
397 /* Always use Independent VLAN Learning (IVL) */
398 .shared_learn = false,
399 /* Don't discard management traffic based on ENFPORT -
400 * we don't perform SMAC port enforcement anyway, so
401 * what we are setting here doesn't matter.
402 */
403 .no_enf_hostprt = false,
404 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
405 * Maybe correlate with no_linklocal_learn from bridge driver?
406 */
407 .no_mgmt_learn = true,
408 /* P/Q/R/S only */
409 .use_static = true,
410 /* Dynamically learned FDB entries can overwrite other (older)
411 * dynamic FDB entries
412 */
413 .owr_dyn = true,
414 .drpnolearn = true,
415 };
416 struct dsa_switch *ds = priv->ds;
417 int port, num_used_ports = 0;
418 struct sja1105_table *table;
419 u64 max_fdb_entries;
420
421 for (port = 0; port < ds->num_ports; port++)
422 if (!dsa_is_unused_port(ds, port))
423 num_used_ports++;
424
425 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
426
427 for (port = 0; port < ds->num_ports; port++) {
428 if (dsa_is_unused_port(ds, port))
429 continue;
430
431 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
432 }
433
434 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
435
436 if (table->entry_count) {
437 kfree(table->entries);
438 table->entry_count = 0;
439 }
440
441 table->entries = kcalloc(table->ops->max_entry_count,
442 table->ops->unpacked_entry_size, GFP_KERNEL);
443 if (!table->entries)
444 return -ENOMEM;
445
446 table->entry_count = table->ops->max_entry_count;
447
448 /* This table only has a single entry */
449 ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
450 default_l2_lookup_params;
451
452 return 0;
453}
454
455/* Set up a default VLAN for untagged traffic injected from the CPU
456 * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
457 * All DT-defined ports are members of this VLAN, and there are no
458 * restrictions on forwarding (since the CPU selects the destination).
459 * Frames from this VLAN will always be transmitted as untagged, and
460 * neither the bridge nor the 8021q module cannot create this VLAN ID.
461 */
462static int sja1105_init_static_vlan(struct sja1105_private *priv)
463{
464 struct sja1105_table *table;
465 struct sja1105_vlan_lookup_entry pvid = {
466 .type_entry = SJA1110_VLAN_D_TAG,
467 .ving_mirr = 0,
468 .vegr_mirr = 0,
469 .vmemb_port = 0,
470 .vlan_bc = 0,
471 .tag_port = 0,
472 .vlanid = SJA1105_DEFAULT_VLAN,
473 };
474 struct dsa_switch *ds = priv->ds;
475 int port;
476
477 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
478
479 if (table->entry_count) {
480 kfree(table->entries);
481 table->entry_count = 0;
482 }
483
484 table->entries = kzalloc(table->ops->unpacked_entry_size,
485 GFP_KERNEL);
486 if (!table->entries)
487 return -ENOMEM;
488
489 table->entry_count = 1;
490
491 for (port = 0; port < ds->num_ports; port++) {
492 if (dsa_is_unused_port(ds, port))
493 continue;
494
495 pvid.vmemb_port |= BIT(port);
496 pvid.vlan_bc |= BIT(port);
497 pvid.tag_port &= ~BIT(port);
498
499 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
500 priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
501 priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
502 }
503 }
504
505 ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
506 return 0;
507}
508
509static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
510{
511 struct sja1105_l2_forwarding_entry *l2fwd;
512 struct dsa_switch *ds = priv->ds;
513 struct dsa_switch_tree *dst;
514 struct sja1105_table *table;
515 struct dsa_link *dl;
516 int port, tc;
517 int from, to;
518
519 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
520
521 if (table->entry_count) {
522 kfree(table->entries);
523 table->entry_count = 0;
524 }
525
526 table->entries = kcalloc(table->ops->max_entry_count,
527 table->ops->unpacked_entry_size, GFP_KERNEL);
528 if (!table->entries)
529 return -ENOMEM;
530
531 table->entry_count = table->ops->max_entry_count;
532
533 l2fwd = table->entries;
534
535 /* First 5 entries in the L2 Forwarding Table define the forwarding
536 * rules and the VLAN PCP to ingress queue mapping.
537 * Set up the ingress queue mapping first.
538 */
539 for (port = 0; port < ds->num_ports; port++) {
540 if (dsa_is_unused_port(ds, port))
541 continue;
542
543 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
544 l2fwd[port].vlan_pmap[tc] = tc;
545 }
546
547 /* Then manage the forwarding domain for user ports. These can forward
548 * only to the always-on domain (CPU port and DSA links)
549 */
550 for (from = 0; from < ds->num_ports; from++) {
551 if (!dsa_is_user_port(ds, from))
552 continue;
553
554 for (to = 0; to < ds->num_ports; to++) {
555 if (!dsa_is_cpu_port(ds, to) &&
556 !dsa_is_dsa_port(ds, to))
557 continue;
558
559 l2fwd[from].bc_domain |= BIT(to);
560 l2fwd[from].fl_domain |= BIT(to);
561
562 sja1105_port_allow_traffic(l2fwd, from, to, true);
563 }
564 }
565
566 /* Then manage the forwarding domain for DSA links and CPU ports (the
567 * always-on domain). These can send packets to any enabled port except
568 * themselves.
569 */
570 for (from = 0; from < ds->num_ports; from++) {
571 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
572 continue;
573
574 for (to = 0; to < ds->num_ports; to++) {
575 if (dsa_is_unused_port(ds, to))
576 continue;
577
578 if (from == to)
579 continue;
580
581 l2fwd[from].bc_domain |= BIT(to);
582 l2fwd[from].fl_domain |= BIT(to);
583
584 sja1105_port_allow_traffic(l2fwd, from, to, true);
585 }
586 }
587
588 /* In odd topologies ("H" connections where there is a DSA link to
589 * another switch which also has its own CPU port), TX packets can loop
590 * back into the system (they are flooded from CPU port 1 to the DSA
591 * link, and from there to CPU port 2). Prevent this from happening by
592 * cutting RX from DSA links towards our CPU port, if the remote switch
593 * has its own CPU port and therefore doesn't need ours for network
594 * stack termination.
595 */
596 dst = ds->dst;
597
598 list_for_each_entry(dl, &dst->rtable, list) {
599 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
600 continue;
601
602 from = dl->dp->index;
603 to = dsa_upstream_port(ds, from);
604
605 dev_warn(ds->dev,
606 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
607 from, to);
608
609 sja1105_port_allow_traffic(l2fwd, from, to, false);
610
611 l2fwd[from].bc_domain &= ~BIT(to);
612 l2fwd[from].fl_domain &= ~BIT(to);
613 }
614
615 /* Finally, manage the egress flooding domain. All ports start up with
616 * flooding enabled, including the CPU port and DSA links.
617 */
618 for (port = 0; port < ds->num_ports; port++) {
619 if (dsa_is_unused_port(ds, port))
620 continue;
621
622 priv->ucast_egress_floods |= BIT(port);
623 priv->bcast_egress_floods |= BIT(port);
624 }
625
626 /* Next 8 entries define VLAN PCP mapping from ingress to egress.
627 * Create a one-to-one mapping.
628 */
629 for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
630 for (port = 0; port < ds->num_ports; port++) {
631 if (dsa_is_unused_port(ds, port))
632 continue;
633
634 l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
635 }
636
637 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
638 }
639
640 return 0;
641}
642
643static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
644{
645 struct sja1110_pcp_remapping_entry *pcp_remap;
646 struct dsa_switch *ds = priv->ds;
647 struct sja1105_table *table;
648 int port, tc;
649
650 table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
651
652 /* Nothing to do for SJA1105 */
653 if (!table->ops->max_entry_count)
654 return 0;
655
656 if (table->entry_count) {
657 kfree(table->entries);
658 table->entry_count = 0;
659 }
660
661 table->entries = kcalloc(table->ops->max_entry_count,
662 table->ops->unpacked_entry_size, GFP_KERNEL);
663 if (!table->entries)
664 return -ENOMEM;
665
666 table->entry_count = table->ops->max_entry_count;
667
668 pcp_remap = table->entries;
669
670 /* Repeat the configuration done for vlan_pmap */
671 for (port = 0; port < ds->num_ports; port++) {
672 if (dsa_is_unused_port(ds, port))
673 continue;
674
675 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
676 pcp_remap[port].egrpcp[tc] = tc;
677 }
678
679 return 0;
680}
681
682static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
683{
684 struct sja1105_l2_forwarding_params_entry *l2fwd_params;
685 struct sja1105_table *table;
686
687 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
688
689 if (table->entry_count) {
690 kfree(table->entries);
691 table->entry_count = 0;
692 }
693
694 table->entries = kcalloc(table->ops->max_entry_count,
695 table->ops->unpacked_entry_size, GFP_KERNEL);
696 if (!table->entries)
697 return -ENOMEM;
698
699 table->entry_count = table->ops->max_entry_count;
700
701 /* This table only has a single entry */
702 l2fwd_params = table->entries;
703
704 /* Disallow dynamic reconfiguration of vlan_pmap */
705 l2fwd_params->max_dynp = 0;
706 /* Use a single memory partition for all ingress queues */
707 l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
708
709 return 0;
710}
711
712void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
713{
714 struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
715 struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
716 struct sja1105_table *table;
717
718 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
719 l2_fwd_params = table->entries;
720 l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
721
722 /* If we have any critical-traffic virtual links, we need to reserve
723 * some frame buffer memory for them. At the moment, hardcode the value
724 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
725 * remaining for best-effort traffic. TODO: figure out a more flexible
726 * way to perform the frame buffer partitioning.
727 */
728 if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
729 return;
730
731 table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
732 vl_fwd_params = table->entries;
733
734 l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
735 vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
736}
737
738/* SJA1110 TDMACONFIGIDX values:
739 *
740 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports
741 * -----+----------------+---------------+---------------+---------------
742 * 0 | 0, [5:10] | [1:2] | [3:4] | retag
743 * 1 |0, [5:10], retag| [1:2] | [3:4] | -
744 * 2 | 0, [5:10] | [1:3], retag | 4 | -
745 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | -
746 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | -
747 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | -
748 * 14 | 0, [5:10] | [1:4], retag | - | -
749 * 15 | [5:10] | [0:4], retag | - | -
750 */
751static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
752{
753 struct sja1105_general_params_entry *general_params;
754 struct sja1105_table *table;
755 bool port_1_is_base_tx;
756 bool port_3_is_2500;
757 bool port_4_is_2500;
758 u64 tdmaconfigidx;
759
760 if (priv->info->device_id != SJA1110_DEVICE_ID)
761 return;
762
763 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
764 general_params = table->entries;
765
766 /* All the settings below are "as opposed to SGMII", which is the
767 * other pinmuxing option.
768 */
769 port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
770 port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
771 port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
772
773 if (port_1_is_base_tx)
774 /* Retagging port will operate at 1 Gbps */
775 tdmaconfigidx = 5;
776 else if (port_3_is_2500 && port_4_is_2500)
777 /* Retagging port will operate at 100 Mbps */
778 tdmaconfigidx = 1;
779 else if (port_3_is_2500)
780 /* Retagging port will operate at 1 Gbps */
781 tdmaconfigidx = 3;
782 else if (port_4_is_2500)
783 /* Retagging port will operate at 1 Gbps */
784 tdmaconfigidx = 2;
785 else
786 /* Retagging port will operate at 1 Gbps */
787 tdmaconfigidx = 14;
788
789 general_params->tdmaconfigidx = tdmaconfigidx;
790}
791
792static int sja1105_init_topology(struct sja1105_private *priv,
793 struct sja1105_general_params_entry *general_params)
794{
795 struct dsa_switch *ds = priv->ds;
796 int port;
797
798 /* The host port is the destination for traffic matching mac_fltres1
799 * and mac_fltres0 on all ports except itself. Default to an invalid
800 * value.
801 */
802 general_params->host_port = ds->num_ports;
803
804 /* Link-local traffic received on casc_port will be forwarded
805 * to host_port without embedding the source port and device ID
806 * info in the destination MAC address, and no RX timestamps will be
807 * taken either (presumably because it is a cascaded port and a
808 * downstream SJA switch already did that).
809 * To disable the feature, we need to do different things depending on
810 * switch generation. On SJA1105 we need to set an invalid port, while
811 * on SJA1110 which support multiple cascaded ports, this field is a
812 * bitmask so it must be left zero.
813 */
814 if (!priv->info->multiple_cascade_ports)
815 general_params->casc_port = ds->num_ports;
816
817 for (port = 0; port < ds->num_ports; port++) {
818 bool is_upstream = dsa_is_upstream_port(ds, port);
819 bool is_dsa_link = dsa_is_dsa_port(ds, port);
820
821 /* Upstream ports can be dedicated CPU ports or
822 * upstream-facing DSA links
823 */
824 if (is_upstream) {
825 if (general_params->host_port == ds->num_ports) {
826 general_params->host_port = port;
827 } else {
828 dev_err(ds->dev,
829 "Port %llu is already a host port, configuring %d as one too is not supported\n",
830 general_params->host_port, port);
831 return -EINVAL;
832 }
833 }
834
835 /* Cascade ports are downstream-facing DSA links */
836 if (is_dsa_link && !is_upstream) {
837 if (priv->info->multiple_cascade_ports) {
838 general_params->casc_port |= BIT(port);
839 } else if (general_params->casc_port == ds->num_ports) {
840 general_params->casc_port = port;
841 } else {
842 dev_err(ds->dev,
843 "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
844 general_params->casc_port, port);
845 return -EINVAL;
846 }
847 }
848 }
849
850 if (general_params->host_port == ds->num_ports) {
851 dev_err(ds->dev, "No host port configured\n");
852 return -EINVAL;
853 }
854
855 return 0;
856}
857
858static int sja1105_init_general_params(struct sja1105_private *priv)
859{
860 struct sja1105_general_params_entry default_general_params = {
861 /* Allow dynamic changing of the mirror port */
862 .mirr_ptacu = true,
863 .switchid = priv->ds->index,
864 /* Priority queue for link-local management frames
865 * (both ingress to and egress from CPU - PTP, STP etc)
866 */
867 .hostprio = 7,
868 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
869 .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK,
870 .incl_srcpt1 = true,
871 .send_meta1 = true,
872 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
873 .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK,
874 .incl_srcpt0 = true,
875 .send_meta0 = true,
876 /* Default to an invalid value */
877 .mirr_port = priv->ds->num_ports,
878 /* No TTEthernet */
879 .vllupformat = SJA1105_VL_FORMAT_PSFP,
880 .vlmarker = 0,
881 .vlmask = 0,
882 /* Only update correctionField for 1-step PTP (L2 transport) */
883 .ignore2stf = 0,
884 /* Forcefully disable VLAN filtering by telling
885 * the switch that VLAN has a different EtherType.
886 */
887 .tpid = ETH_P_SJA1105,
888 .tpid2 = ETH_P_SJA1105,
889 /* Enable the TTEthernet engine on SJA1110 */
890 .tte_en = true,
891 /* Set up the EtherType for control packets on SJA1110 */
892 .header_type = ETH_P_SJA1110,
893 };
894 struct sja1105_general_params_entry *general_params;
895 struct sja1105_table *table;
896 int rc;
897
898 rc = sja1105_init_topology(priv, &default_general_params);
899 if (rc)
900 return rc;
901
902 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
903
904 if (table->entry_count) {
905 kfree(table->entries);
906 table->entry_count = 0;
907 }
908
909 table->entries = kcalloc(table->ops->max_entry_count,
910 table->ops->unpacked_entry_size, GFP_KERNEL);
911 if (!table->entries)
912 return -ENOMEM;
913
914 table->entry_count = table->ops->max_entry_count;
915
916 general_params = table->entries;
917
918 /* This table only has a single entry */
919 general_params[0] = default_general_params;
920
921 sja1110_select_tdmaconfigidx(priv);
922
923 return 0;
924}
925
926static int sja1105_init_avb_params(struct sja1105_private *priv)
927{
928 struct sja1105_avb_params_entry *avb;
929 struct sja1105_table *table;
930
931 table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
932
933 /* Discard previous AVB Parameters Table */
934 if (table->entry_count) {
935 kfree(table->entries);
936 table->entry_count = 0;
937 }
938
939 table->entries = kcalloc(table->ops->max_entry_count,
940 table->ops->unpacked_entry_size, GFP_KERNEL);
941 if (!table->entries)
942 return -ENOMEM;
943
944 table->entry_count = table->ops->max_entry_count;
945
946 avb = table->entries;
947
948 /* Configure the MAC addresses for meta frames */
949 avb->destmeta = SJA1105_META_DMAC;
950 avb->srcmeta = SJA1105_META_SMAC;
951 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
952 * default. This is because there might be boards with a hardware
953 * layout where enabling the pin as output might cause an electrical
954 * clash. On E/T the pin is always an output, which the board designers
955 * probably already knew, so even if there are going to be electrical
956 * issues, there's nothing we can do.
957 */
958 avb->cas_master = false;
959
960 return 0;
961}
962
963/* The L2 policing table is 2-stage. The table is looked up for each frame
964 * according to the ingress port, whether it was broadcast or not, and the
965 * classified traffic class (given by VLAN PCP). This portion of the lookup is
966 * fixed, and gives access to the SHARINDX, an indirection register pointing
967 * within the policing table itself, which is used to resolve the policer that
968 * will be used for this frame.
969 *
970 * Stage 1 Stage 2
971 * +------------+--------+ +---------------------------------+
972 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU |
973 * +------------+--------+ +---------------------------------+
974 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU |
975 * +------------+--------+ +---------------------------------+
976 * ... | Policer 2: Rate, Burst, MTU |
977 * +------------+--------+ +---------------------------------+
978 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU |
979 * +------------+--------+ +---------------------------------+
980 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU |
981 * +------------+--------+ +---------------------------------+
982 * ... | Policer 5: Rate, Burst, MTU |
983 * +------------+--------+ +---------------------------------+
984 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU |
985 * +------------+--------+ +---------------------------------+
986 * ... | Policer 7: Rate, Burst, MTU |
987 * +------------+--------+ +---------------------------------+
988 * |Port 4 TC 7 |SHARINDX| ...
989 * +------------+--------+
990 * |Port 0 BCAST|SHARINDX| ...
991 * +------------+--------+
992 * |Port 1 BCAST|SHARINDX| ...
993 * +------------+--------+
994 * ... ...
995 * +------------+--------+ +---------------------------------+
996 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU |
997 * +------------+--------+ +---------------------------------+
998 *
999 * In this driver, we shall use policers 0-4 as statically alocated port
1000 * (matchall) policers. So we need to make the SHARINDX for all lookups
1001 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1002 * lookup) equal.
1003 * The remaining policers (40) shall be dynamically allocated for flower
1004 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1005 */
1006#define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1007
1008static int sja1105_init_l2_policing(struct sja1105_private *priv)
1009{
1010 struct sja1105_l2_policing_entry *policing;
1011 struct dsa_switch *ds = priv->ds;
1012 struct sja1105_table *table;
1013 int port, tc;
1014
1015 table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1016
1017 /* Discard previous L2 Policing Table */
1018 if (table->entry_count) {
1019 kfree(table->entries);
1020 table->entry_count = 0;
1021 }
1022
1023 table->entries = kcalloc(table->ops->max_entry_count,
1024 table->ops->unpacked_entry_size, GFP_KERNEL);
1025 if (!table->entries)
1026 return -ENOMEM;
1027
1028 table->entry_count = table->ops->max_entry_count;
1029
1030 policing = table->entries;
1031
1032 /* Setup shared indices for the matchall policers */
1033 for (port = 0; port < ds->num_ports; port++) {
1034 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1035 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1036
1037 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1038 policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1039
1040 policing[bcast].sharindx = port;
1041 /* Only SJA1110 has multicast policers */
1042 if (mcast < table->ops->max_entry_count)
1043 policing[mcast].sharindx = port;
1044 }
1045
1046 /* Setup the matchall policer parameters */
1047 for (port = 0; port < ds->num_ports; port++) {
1048 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1049
1050 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1051 mtu += VLAN_HLEN;
1052
1053 policing[port].smax = 65535; /* Burst size in bytes */
1054 policing[port].rate = SJA1105_RATE_MBPS(1000);
1055 policing[port].maxlen = mtu;
1056 policing[port].partition = 0;
1057 }
1058
1059 return 0;
1060}
1061
1062static int sja1105_static_config_load(struct sja1105_private *priv)
1063{
1064 int rc;
1065
1066 sja1105_static_config_free(&priv->static_config);
1067 rc = sja1105_static_config_init(&priv->static_config,
1068 priv->info->static_ops,
1069 priv->info->device_id);
1070 if (rc)
1071 return rc;
1072
1073 /* Build static configuration */
1074 rc = sja1105_init_mac_settings(priv);
1075 if (rc < 0)
1076 return rc;
1077 rc = sja1105_init_mii_settings(priv);
1078 if (rc < 0)
1079 return rc;
1080 rc = sja1105_init_static_fdb(priv);
1081 if (rc < 0)
1082 return rc;
1083 rc = sja1105_init_static_vlan(priv);
1084 if (rc < 0)
1085 return rc;
1086 rc = sja1105_init_l2_lookup_params(priv);
1087 if (rc < 0)
1088 return rc;
1089 rc = sja1105_init_l2_forwarding(priv);
1090 if (rc < 0)
1091 return rc;
1092 rc = sja1105_init_l2_forwarding_params(priv);
1093 if (rc < 0)
1094 return rc;
1095 rc = sja1105_init_l2_policing(priv);
1096 if (rc < 0)
1097 return rc;
1098 rc = sja1105_init_general_params(priv);
1099 if (rc < 0)
1100 return rc;
1101 rc = sja1105_init_avb_params(priv);
1102 if (rc < 0)
1103 return rc;
1104 rc = sja1110_init_pcp_remapping(priv);
1105 if (rc < 0)
1106 return rc;
1107
1108 /* Send initial configuration to hardware via SPI */
1109 return sja1105_static_config_upload(priv);
1110}
1111
1112/* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1113 * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1114 * properties. It has the advantage of working with fixed links and with PHYs
1115 * that apply RGMII delays too, and the MAC driver needs not perform any
1116 * special checks.
1117 *
1118 * Previously we were acting upon the "phy-mode" property when we were
1119 * operating in fixed-link, basically acting as a PHY, but with a reversed
1120 * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1121 * behave as if it is connected to a PHY which has applied RGMII delays in the
1122 * TX direction. So if anything, RX delays should have been added by the MAC,
1123 * but we were adding TX delays.
1124 *
1125 * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1126 * back to the legacy behavior and apply delays on fixed-link ports based on
1127 * the reverse interpretation of the phy-mode. This is a deviation from the
1128 * expected default behavior which is to simply apply no delays. To achieve
1129 * that behavior with the new bindings, it is mandatory to specify
1130 * "{rx,tx}-internal-delay-ps" with a value of 0.
1131 */
1132static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1133 struct device_node *port_dn)
1134{
1135 phy_interface_t phy_mode = priv->phy_mode[port];
1136 struct device *dev = &priv->spidev->dev;
1137 int rx_delay = -1, tx_delay = -1;
1138
1139 if (!phy_interface_mode_is_rgmii(phy_mode))
1140 return 0;
1141
1142 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1143 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1144
1145 if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1146 dev_warn(dev,
1147 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1148 "please update device tree to specify \"rx-internal-delay-ps\" and "
1149 "\"tx-internal-delay-ps\"",
1150 port);
1151
1152 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1153 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1154 rx_delay = 2000;
1155
1156 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1157 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1158 tx_delay = 2000;
1159 }
1160
1161 if (rx_delay < 0)
1162 rx_delay = 0;
1163 if (tx_delay < 0)
1164 tx_delay = 0;
1165
1166 if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1167 dev_err(dev, "Chip cannot apply RGMII delays\n");
1168 return -EINVAL;
1169 }
1170
1171 if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1172 (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1173 (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1174 (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1175 dev_err(dev,
1176 "port %d RGMII delay values out of range, must be between %d and %d ps\n",
1177 port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1178 return -ERANGE;
1179 }
1180
1181 priv->rgmii_rx_delay_ps[port] = rx_delay;
1182 priv->rgmii_tx_delay_ps[port] = tx_delay;
1183
1184 return 0;
1185}
1186
1187static int sja1105_parse_ports_node(struct sja1105_private *priv,
1188 struct device_node *ports_node)
1189{
1190 struct device *dev = &priv->spidev->dev;
1191 struct device_node *child;
1192
1193 for_each_available_child_of_node(ports_node, child) {
1194 struct device_node *phy_node;
1195 phy_interface_t phy_mode;
1196 u32 index;
1197 int err;
1198
1199 /* Get switch port number from DT */
1200 if (of_property_read_u32(child, "reg", &index) < 0) {
1201 dev_err(dev, "Port number not defined in device tree "
1202 "(property \"reg\")\n");
1203 of_node_put(child);
1204 return -ENODEV;
1205 }
1206
1207 /* Get PHY mode from DT */
1208 err = of_get_phy_mode(child, &phy_mode);
1209 if (err) {
1210 dev_err(dev, "Failed to read phy-mode or "
1211 "phy-interface-type property for port %d\n",
1212 index);
1213 of_node_put(child);
1214 return -ENODEV;
1215 }
1216
1217 phy_node = of_parse_phandle(child, "phy-handle", 0);
1218 if (!phy_node) {
1219 if (!of_phy_is_fixed_link(child)) {
1220 dev_err(dev, "phy-handle or fixed-link "
1221 "properties missing!\n");
1222 of_node_put(child);
1223 return -ENODEV;
1224 }
1225 /* phy-handle is missing, but fixed-link isn't.
1226 * So it's a fixed link. Default to PHY role.
1227 */
1228 priv->fixed_link[index] = true;
1229 } else {
1230 of_node_put(phy_node);
1231 }
1232
1233 priv->phy_mode[index] = phy_mode;
1234
1235 err = sja1105_parse_rgmii_delays(priv, index, child);
1236 if (err) {
1237 of_node_put(child);
1238 return err;
1239 }
1240 }
1241
1242 return 0;
1243}
1244
1245static int sja1105_parse_dt(struct sja1105_private *priv)
1246{
1247 struct device *dev = &priv->spidev->dev;
1248 struct device_node *switch_node = dev->of_node;
1249 struct device_node *ports_node;
1250 int rc;
1251
1252 ports_node = of_get_child_by_name(switch_node, "ports");
1253 if (!ports_node)
1254 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1255 if (!ports_node) {
1256 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1257 return -ENODEV;
1258 }
1259
1260 rc = sja1105_parse_ports_node(priv, ports_node);
1261 of_node_put(ports_node);
1262
1263 return rc;
1264}
1265
1266/* Convert link speed from SJA1105 to ethtool encoding */
1267static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1268 u64 speed)
1269{
1270 if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1271 return SPEED_10;
1272 if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1273 return SPEED_100;
1274 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1275 return SPEED_1000;
1276 if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1277 return SPEED_2500;
1278 return SPEED_UNKNOWN;
1279}
1280
1281/* Set link speed in the MAC configuration for a specific port. */
1282static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1283 int speed_mbps)
1284{
1285 struct sja1105_mac_config_entry *mac;
1286 struct device *dev = priv->ds->dev;
1287 u64 speed;
1288 int rc;
1289
1290 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1291 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1292 * We have to *know* what the MAC looks like. For the sake of keeping
1293 * the code common, we'll use the static configuration tables as a
1294 * reasonable approximation for both E/T and P/Q/R/S.
1295 */
1296 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1297
1298 switch (speed_mbps) {
1299 case SPEED_UNKNOWN:
1300 /* PHYLINK called sja1105_mac_config() to inform us about
1301 * the state->interface, but AN has not completed and the
1302 * speed is not yet valid. UM10944.pdf says that setting
1303 * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1304 * ok for power consumption in case AN will never complete -
1305 * otherwise PHYLINK should come back with a new update.
1306 */
1307 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1308 break;
1309 case SPEED_10:
1310 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1311 break;
1312 case SPEED_100:
1313 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1314 break;
1315 case SPEED_1000:
1316 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1317 break;
1318 case SPEED_2500:
1319 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1320 break;
1321 default:
1322 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1323 return -EINVAL;
1324 }
1325
1326 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1327 * table, since this will be used for the clocking setup, and we no
1328 * longer need to store it in the static config (already told hardware
1329 * we want auto during upload phase).
1330 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1331 * we need to configure the PCS only (if even that).
1332 */
1333 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1334 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1335 else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1336 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1337 else
1338 mac[port].speed = speed;
1339
1340 /* Write to the dynamic reconfiguration tables */
1341 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1342 &mac[port], true);
1343 if (rc < 0) {
1344 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1345 return rc;
1346 }
1347
1348 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1349 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1350 * RMII no change of the clock setup is required. Actually, changing
1351 * the clock setup does interrupt the clock signal for a certain time
1352 * which causes trouble for all PHYs relying on this signal.
1353 */
1354 if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1355 return 0;
1356
1357 return sja1105_clocking_setup_port(priv, port);
1358}
1359
1360static struct phylink_pcs *
1361sja1105_mac_select_pcs(struct dsa_switch *ds, int port, phy_interface_t iface)
1362{
1363 struct sja1105_private *priv = ds->priv;
1364 struct dw_xpcs *xpcs = priv->xpcs[port];
1365
1366 if (xpcs)
1367 return &xpcs->pcs;
1368
1369 return NULL;
1370}
1371
1372static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1373 unsigned int mode,
1374 phy_interface_t interface)
1375{
1376 sja1105_inhibit_tx(ds->priv, BIT(port), true);
1377}
1378
1379static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1380 unsigned int mode,
1381 phy_interface_t interface,
1382 struct phy_device *phydev,
1383 int speed, int duplex,
1384 bool tx_pause, bool rx_pause)
1385{
1386 struct sja1105_private *priv = ds->priv;
1387
1388 sja1105_adjust_port_config(priv, port, speed);
1389
1390 sja1105_inhibit_tx(priv, BIT(port), false);
1391}
1392
1393static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port,
1394 struct phylink_config *config)
1395{
1396 struct sja1105_private *priv = ds->priv;
1397 struct sja1105_xmii_params_entry *mii;
1398 phy_interface_t phy_mode;
1399
1400 phy_mode = priv->phy_mode[port];
1401 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
1402 phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
1403 /* Changing the PHY mode on SERDES ports is possible and makes
1404 * sense, because that is done through the XPCS. We allow
1405 * changes between SGMII and 2500base-X.
1406 */
1407 if (priv->info->supports_sgmii[port])
1408 __set_bit(PHY_INTERFACE_MODE_SGMII,
1409 config->supported_interfaces);
1410
1411 if (priv->info->supports_2500basex[port])
1412 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1413 config->supported_interfaces);
1414 } else {
1415 /* The SJA1105 MAC programming model is through the static
1416 * config (the xMII Mode table cannot be dynamically
1417 * reconfigured), and we have to program that early.
1418 */
1419 __set_bit(phy_mode, config->supported_interfaces);
1420 }
1421
1422 /* The MAC does not support pause frames, and also doesn't
1423 * support half-duplex traffic modes.
1424 */
1425 config->mac_capabilities = MAC_10FD | MAC_100FD;
1426
1427 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1428 if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1429 mii->xmii_mode[port] == XMII_MODE_SGMII)
1430 config->mac_capabilities |= MAC_1000FD;
1431
1432 if (priv->info->supports_2500basex[port])
1433 config->mac_capabilities |= MAC_2500FD;
1434}
1435
1436static int
1437sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1438 const struct sja1105_l2_lookup_entry *requested)
1439{
1440 struct sja1105_l2_lookup_entry *l2_lookup;
1441 struct sja1105_table *table;
1442 int i;
1443
1444 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1445 l2_lookup = table->entries;
1446
1447 for (i = 0; i < table->entry_count; i++)
1448 if (l2_lookup[i].macaddr == requested->macaddr &&
1449 l2_lookup[i].vlanid == requested->vlanid &&
1450 l2_lookup[i].destports & BIT(port))
1451 return i;
1452
1453 return -1;
1454}
1455
1456/* We want FDB entries added statically through the bridge command to persist
1457 * across switch resets, which are a common thing during normal SJA1105
1458 * operation. So we have to back them up in the static configuration tables
1459 * and hence apply them on next static config upload... yay!
1460 */
1461static int
1462sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1463 const struct sja1105_l2_lookup_entry *requested,
1464 bool keep)
1465{
1466 struct sja1105_l2_lookup_entry *l2_lookup;
1467 struct sja1105_table *table;
1468 int rc, match;
1469
1470 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1471
1472 match = sja1105_find_static_fdb_entry(priv, port, requested);
1473 if (match < 0) {
1474 /* Can't delete a missing entry. */
1475 if (!keep)
1476 return 0;
1477
1478 /* No match => new entry */
1479 rc = sja1105_table_resize(table, table->entry_count + 1);
1480 if (rc)
1481 return rc;
1482
1483 match = table->entry_count - 1;
1484 }
1485
1486 /* Assign pointer after the resize (it may be new memory) */
1487 l2_lookup = table->entries;
1488
1489 /* We have a match.
1490 * If the job was to add this FDB entry, it's already done (mostly
1491 * anyway, since the port forwarding mask may have changed, case in
1492 * which we update it).
1493 * Otherwise we have to delete it.
1494 */
1495 if (keep) {
1496 l2_lookup[match] = *requested;
1497 return 0;
1498 }
1499
1500 /* To remove, the strategy is to overwrite the element with
1501 * the last one, and then reduce the array size by 1
1502 */
1503 l2_lookup[match] = l2_lookup[table->entry_count - 1];
1504 return sja1105_table_resize(table, table->entry_count - 1);
1505}
1506
1507/* First-generation switches have a 4-way set associative TCAM that
1508 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1509 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1510 * For the placement of a newly learnt FDB entry, the switch selects the bin
1511 * based on a hash function, and the way within that bin incrementally.
1512 */
1513static int sja1105et_fdb_index(int bin, int way)
1514{
1515 return bin * SJA1105ET_FDB_BIN_SIZE + way;
1516}
1517
1518static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1519 const u8 *addr, u16 vid,
1520 struct sja1105_l2_lookup_entry *match,
1521 int *last_unused)
1522{
1523 int way;
1524
1525 for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1526 struct sja1105_l2_lookup_entry l2_lookup = {0};
1527 int index = sja1105et_fdb_index(bin, way);
1528
1529 /* Skip unused entries, optionally marking them
1530 * into the return value
1531 */
1532 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1533 index, &l2_lookup)) {
1534 if (last_unused)
1535 *last_unused = way;
1536 continue;
1537 }
1538
1539 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1540 l2_lookup.vlanid == vid) {
1541 if (match)
1542 *match = l2_lookup;
1543 return way;
1544 }
1545 }
1546 /* Return an invalid entry index if not found */
1547 return -1;
1548}
1549
1550int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1551 const unsigned char *addr, u16 vid)
1552{
1553 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1554 struct sja1105_private *priv = ds->priv;
1555 struct device *dev = ds->dev;
1556 int last_unused = -1;
1557 int start, end, i;
1558 int bin, way, rc;
1559
1560 bin = sja1105et_fdb_hash(priv, addr, vid);
1561
1562 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1563 &l2_lookup, &last_unused);
1564 if (way >= 0) {
1565 /* We have an FDB entry. Is our port in the destination
1566 * mask? If yes, we need to do nothing. If not, we need
1567 * to rewrite the entry by adding this port to it.
1568 */
1569 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1570 return 0;
1571 l2_lookup.destports |= BIT(port);
1572 } else {
1573 int index = sja1105et_fdb_index(bin, way);
1574
1575 /* We don't have an FDB entry. We construct a new one and
1576 * try to find a place for it within the FDB table.
1577 */
1578 l2_lookup.macaddr = ether_addr_to_u64(addr);
1579 l2_lookup.destports = BIT(port);
1580 l2_lookup.vlanid = vid;
1581
1582 if (last_unused >= 0) {
1583 way = last_unused;
1584 } else {
1585 /* Bin is full, need to evict somebody.
1586 * Choose victim at random. If you get these messages
1587 * often, you may need to consider changing the
1588 * distribution function:
1589 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1590 */
1591 get_random_bytes(&way, sizeof(u8));
1592 way %= SJA1105ET_FDB_BIN_SIZE;
1593 dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1594 bin, addr, way);
1595 /* Evict entry */
1596 sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1597 index, NULL, false);
1598 }
1599 }
1600 l2_lookup.lockeds = true;
1601 l2_lookup.index = sja1105et_fdb_index(bin, way);
1602
1603 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1604 l2_lookup.index, &l2_lookup,
1605 true);
1606 if (rc < 0)
1607 return rc;
1608
1609 /* Invalidate a dynamically learned entry if that exists */
1610 start = sja1105et_fdb_index(bin, 0);
1611 end = sja1105et_fdb_index(bin, way);
1612
1613 for (i = start; i < end; i++) {
1614 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1615 i, &tmp);
1616 if (rc == -ENOENT)
1617 continue;
1618 if (rc)
1619 return rc;
1620
1621 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1622 continue;
1623
1624 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1625 i, NULL, false);
1626 if (rc)
1627 return rc;
1628
1629 break;
1630 }
1631
1632 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1633}
1634
1635int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1636 const unsigned char *addr, u16 vid)
1637{
1638 struct sja1105_l2_lookup_entry l2_lookup = {0};
1639 struct sja1105_private *priv = ds->priv;
1640 int index, bin, way, rc;
1641 bool keep;
1642
1643 bin = sja1105et_fdb_hash(priv, addr, vid);
1644 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1645 &l2_lookup, NULL);
1646 if (way < 0)
1647 return 0;
1648 index = sja1105et_fdb_index(bin, way);
1649
1650 /* We have an FDB entry. Is our port in the destination mask? If yes,
1651 * we need to remove it. If the resulting port mask becomes empty, we
1652 * need to completely evict the FDB entry.
1653 * Otherwise we just write it back.
1654 */
1655 l2_lookup.destports &= ~BIT(port);
1656
1657 if (l2_lookup.destports)
1658 keep = true;
1659 else
1660 keep = false;
1661
1662 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1663 index, &l2_lookup, keep);
1664 if (rc < 0)
1665 return rc;
1666
1667 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1668}
1669
1670int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1671 const unsigned char *addr, u16 vid)
1672{
1673 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1674 struct sja1105_private *priv = ds->priv;
1675 int rc, i;
1676
1677 /* Search for an existing entry in the FDB table */
1678 l2_lookup.macaddr = ether_addr_to_u64(addr);
1679 l2_lookup.vlanid = vid;
1680 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1681 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1682 l2_lookup.destports = BIT(port);
1683
1684 tmp = l2_lookup;
1685
1686 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1687 SJA1105_SEARCH, &tmp);
1688 if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1689 /* Found a static entry and this port is already in the entry's
1690 * port mask => job done
1691 */
1692 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1693 return 0;
1694
1695 l2_lookup = tmp;
1696
1697 /* l2_lookup.index is populated by the switch in case it
1698 * found something.
1699 */
1700 l2_lookup.destports |= BIT(port);
1701 goto skip_finding_an_index;
1702 }
1703
1704 /* Not found, so try to find an unused spot in the FDB.
1705 * This is slightly inefficient because the strategy is knock-knock at
1706 * every possible position from 0 to 1023.
1707 */
1708 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1709 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1710 i, NULL);
1711 if (rc < 0)
1712 break;
1713 }
1714 if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1715 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1716 return -EINVAL;
1717 }
1718 l2_lookup.index = i;
1719
1720skip_finding_an_index:
1721 l2_lookup.lockeds = true;
1722
1723 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1724 l2_lookup.index, &l2_lookup,
1725 true);
1726 if (rc < 0)
1727 return rc;
1728
1729 /* The switch learns dynamic entries and looks up the FDB left to
1730 * right. It is possible that our addition was concurrent with the
1731 * dynamic learning of the same address, so now that the static entry
1732 * has been installed, we are certain that address learning for this
1733 * particular address has been turned off, so the dynamic entry either
1734 * is in the FDB at an index smaller than the static one, or isn't (it
1735 * can also be at a larger index, but in that case it is inactive
1736 * because the static FDB entry will match first, and the dynamic one
1737 * will eventually age out). Search for a dynamically learned address
1738 * prior to our static one and invalidate it.
1739 */
1740 tmp = l2_lookup;
1741
1742 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1743 SJA1105_SEARCH, &tmp);
1744 if (rc < 0) {
1745 dev_err(ds->dev,
1746 "port %d failed to read back entry for %pM vid %d: %pe\n",
1747 port, addr, vid, ERR_PTR(rc));
1748 return rc;
1749 }
1750
1751 if (tmp.index < l2_lookup.index) {
1752 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1753 tmp.index, NULL, false);
1754 if (rc < 0)
1755 return rc;
1756 }
1757
1758 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1759}
1760
1761int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1762 const unsigned char *addr, u16 vid)
1763{
1764 struct sja1105_l2_lookup_entry l2_lookup = {0};
1765 struct sja1105_private *priv = ds->priv;
1766 bool keep;
1767 int rc;
1768
1769 l2_lookup.macaddr = ether_addr_to_u64(addr);
1770 l2_lookup.vlanid = vid;
1771 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1772 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1773 l2_lookup.destports = BIT(port);
1774
1775 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1776 SJA1105_SEARCH, &l2_lookup);
1777 if (rc < 0)
1778 return 0;
1779
1780 l2_lookup.destports &= ~BIT(port);
1781
1782 /* Decide whether we remove just this port from the FDB entry,
1783 * or if we remove it completely.
1784 */
1785 if (l2_lookup.destports)
1786 keep = true;
1787 else
1788 keep = false;
1789
1790 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1791 l2_lookup.index, &l2_lookup, keep);
1792 if (rc < 0)
1793 return rc;
1794
1795 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1796}
1797
1798static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1799 const unsigned char *addr, u16 vid,
1800 struct dsa_db db)
1801{
1802 struct sja1105_private *priv = ds->priv;
1803 int rc;
1804
1805 if (!vid) {
1806 switch (db.type) {
1807 case DSA_DB_PORT:
1808 vid = dsa_tag_8021q_standalone_vid(db.dp);
1809 break;
1810 case DSA_DB_BRIDGE:
1811 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1812 break;
1813 default:
1814 return -EOPNOTSUPP;
1815 }
1816 }
1817
1818 mutex_lock(&priv->fdb_lock);
1819 rc = priv->info->fdb_add_cmd(ds, port, addr, vid);
1820 mutex_unlock(&priv->fdb_lock);
1821
1822 return rc;
1823}
1824
1825static int __sja1105_fdb_del(struct dsa_switch *ds, int port,
1826 const unsigned char *addr, u16 vid,
1827 struct dsa_db db)
1828{
1829 struct sja1105_private *priv = ds->priv;
1830
1831 if (!vid) {
1832 switch (db.type) {
1833 case DSA_DB_PORT:
1834 vid = dsa_tag_8021q_standalone_vid(db.dp);
1835 break;
1836 case DSA_DB_BRIDGE:
1837 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1838 break;
1839 default:
1840 return -EOPNOTSUPP;
1841 }
1842 }
1843
1844 return priv->info->fdb_del_cmd(ds, port, addr, vid);
1845}
1846
1847static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1848 const unsigned char *addr, u16 vid,
1849 struct dsa_db db)
1850{
1851 struct sja1105_private *priv = ds->priv;
1852 int rc;
1853
1854 mutex_lock(&priv->fdb_lock);
1855 rc = __sja1105_fdb_del(ds, port, addr, vid, db);
1856 mutex_unlock(&priv->fdb_lock);
1857
1858 return rc;
1859}
1860
1861static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1862 dsa_fdb_dump_cb_t *cb, void *data)
1863{
1864 struct sja1105_private *priv = ds->priv;
1865 struct device *dev = ds->dev;
1866 int i;
1867
1868 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1869 struct sja1105_l2_lookup_entry l2_lookup = {0};
1870 u8 macaddr[ETH_ALEN];
1871 int rc;
1872
1873 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1874 i, &l2_lookup);
1875 /* No fdb entry at i, not an issue */
1876 if (rc == -ENOENT)
1877 continue;
1878 if (rc) {
1879 dev_err(dev, "Failed to dump FDB: %d\n", rc);
1880 return rc;
1881 }
1882
1883 /* FDB dump callback is per port. This means we have to
1884 * disregard a valid entry if it's not for this port, even if
1885 * only to revisit it later. This is inefficient because the
1886 * 1024-sized FDB table needs to be traversed 4 times through
1887 * SPI during a 'bridge fdb show' command.
1888 */
1889 if (!(l2_lookup.destports & BIT(port)))
1890 continue;
1891
1892 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1893
1894 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show"
1895 * only wants to see unicast
1896 */
1897 if (is_multicast_ether_addr(macaddr))
1898 continue;
1899
1900 /* We need to hide the dsa_8021q VLANs from the user. */
1901 if (vid_is_dsa_8021q(l2_lookup.vlanid))
1902 l2_lookup.vlanid = 0;
1903 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1904 if (rc)
1905 return rc;
1906 }
1907 return 0;
1908}
1909
1910static void sja1105_fast_age(struct dsa_switch *ds, int port)
1911{
1912 struct dsa_port *dp = dsa_to_port(ds, port);
1913 struct sja1105_private *priv = ds->priv;
1914 struct dsa_db db = {
1915 .type = DSA_DB_BRIDGE,
1916 .bridge = {
1917 .dev = dsa_port_bridge_dev_get(dp),
1918 .num = dsa_port_bridge_num_get(dp),
1919 },
1920 };
1921 int i;
1922
1923 mutex_lock(&priv->fdb_lock);
1924
1925 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1926 struct sja1105_l2_lookup_entry l2_lookup = {0};
1927 u8 macaddr[ETH_ALEN];
1928 int rc;
1929
1930 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1931 i, &l2_lookup);
1932 /* No fdb entry at i, not an issue */
1933 if (rc == -ENOENT)
1934 continue;
1935 if (rc) {
1936 dev_err(ds->dev, "Failed to read FDB: %pe\n",
1937 ERR_PTR(rc));
1938 break;
1939 }
1940
1941 if (!(l2_lookup.destports & BIT(port)))
1942 continue;
1943
1944 /* Don't delete static FDB entries */
1945 if (l2_lookup.lockeds)
1946 continue;
1947
1948 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1949
1950 rc = __sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db);
1951 if (rc) {
1952 dev_err(ds->dev,
1953 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1954 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1955 break;
1956 }
1957 }
1958
1959 mutex_unlock(&priv->fdb_lock);
1960}
1961
1962static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1963 const struct switchdev_obj_port_mdb *mdb,
1964 struct dsa_db db)
1965{
1966 return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db);
1967}
1968
1969static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1970 const struct switchdev_obj_port_mdb *mdb,
1971 struct dsa_db db)
1972{
1973 return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db);
1974}
1975
1976/* Common function for unicast and broadcast flood configuration.
1977 * Flooding is configured between each {ingress, egress} port pair, and since
1978 * the bridge's semantics are those of "egress flooding", it means we must
1979 * enable flooding towards this port from all ingress ports that are in the
1980 * same forwarding domain.
1981 */
1982static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1983{
1984 struct sja1105_l2_forwarding_entry *l2_fwd;
1985 struct dsa_switch *ds = priv->ds;
1986 int from, to, rc;
1987
1988 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1989
1990 for (from = 0; from < ds->num_ports; from++) {
1991 u64 fl_domain = 0, bc_domain = 0;
1992
1993 for (to = 0; to < priv->ds->num_ports; to++) {
1994 if (!sja1105_can_forward(l2_fwd, from, to))
1995 continue;
1996
1997 if (priv->ucast_egress_floods & BIT(to))
1998 fl_domain |= BIT(to);
1999 if (priv->bcast_egress_floods & BIT(to))
2000 bc_domain |= BIT(to);
2001 }
2002
2003 /* Nothing changed, nothing to do */
2004 if (l2_fwd[from].fl_domain == fl_domain &&
2005 l2_fwd[from].bc_domain == bc_domain)
2006 continue;
2007
2008 l2_fwd[from].fl_domain = fl_domain;
2009 l2_fwd[from].bc_domain = bc_domain;
2010
2011 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2012 from, &l2_fwd[from], true);
2013 if (rc < 0)
2014 return rc;
2015 }
2016
2017 return 0;
2018}
2019
2020static int sja1105_bridge_member(struct dsa_switch *ds, int port,
2021 struct dsa_bridge bridge, bool member)
2022{
2023 struct sja1105_l2_forwarding_entry *l2_fwd;
2024 struct sja1105_private *priv = ds->priv;
2025 int i, rc;
2026
2027 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
2028
2029 for (i = 0; i < ds->num_ports; i++) {
2030 /* Add this port to the forwarding matrix of the
2031 * other ports in the same bridge, and viceversa.
2032 */
2033 if (!dsa_is_user_port(ds, i))
2034 continue;
2035 /* For the ports already under the bridge, only one thing needs
2036 * to be done, and that is to add this port to their
2037 * reachability domain. So we can perform the SPI write for
2038 * them immediately. However, for this port itself (the one
2039 * that is new to the bridge), we need to add all other ports
2040 * to its reachability domain. So we do that incrementally in
2041 * this loop, and perform the SPI write only at the end, once
2042 * the domain contains all other bridge ports.
2043 */
2044 if (i == port)
2045 continue;
2046 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2047 continue;
2048 sja1105_port_allow_traffic(l2_fwd, i, port, member);
2049 sja1105_port_allow_traffic(l2_fwd, port, i, member);
2050
2051 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2052 i, &l2_fwd[i], true);
2053 if (rc < 0)
2054 return rc;
2055 }
2056
2057 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2058 port, &l2_fwd[port], true);
2059 if (rc)
2060 return rc;
2061
2062 rc = sja1105_commit_pvid(ds, port);
2063 if (rc)
2064 return rc;
2065
2066 return sja1105_manage_flood_domains(priv);
2067}
2068
2069static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2070 u8 state)
2071{
2072 struct dsa_port *dp = dsa_to_port(ds, port);
2073 struct sja1105_private *priv = ds->priv;
2074 struct sja1105_mac_config_entry *mac;
2075
2076 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2077
2078 switch (state) {
2079 case BR_STATE_DISABLED:
2080 case BR_STATE_BLOCKING:
2081 /* From UM10944 description of DRPDTAG (why put this there?):
2082 * "Management traffic flows to the port regardless of the state
2083 * of the INGRESS flag". So BPDUs are still be allowed to pass.
2084 * At the moment no difference between DISABLED and BLOCKING.
2085 */
2086 mac[port].ingress = false;
2087 mac[port].egress = false;
2088 mac[port].dyn_learn = false;
2089 break;
2090 case BR_STATE_LISTENING:
2091 mac[port].ingress = true;
2092 mac[port].egress = false;
2093 mac[port].dyn_learn = false;
2094 break;
2095 case BR_STATE_LEARNING:
2096 mac[port].ingress = true;
2097 mac[port].egress = false;
2098 mac[port].dyn_learn = dp->learning;
2099 break;
2100 case BR_STATE_FORWARDING:
2101 mac[port].ingress = true;
2102 mac[port].egress = true;
2103 mac[port].dyn_learn = dp->learning;
2104 break;
2105 default:
2106 dev_err(ds->dev, "invalid STP state: %d\n", state);
2107 return;
2108 }
2109
2110 sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2111 &mac[port], true);
2112}
2113
2114static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2115 struct dsa_bridge bridge,
2116 bool *tx_fwd_offload,
2117 struct netlink_ext_ack *extack)
2118{
2119 int rc;
2120
2121 rc = sja1105_bridge_member(ds, port, bridge, true);
2122 if (rc)
2123 return rc;
2124
2125 rc = dsa_tag_8021q_bridge_join(ds, port, bridge);
2126 if (rc) {
2127 sja1105_bridge_member(ds, port, bridge, false);
2128 return rc;
2129 }
2130
2131 *tx_fwd_offload = true;
2132
2133 return 0;
2134}
2135
2136static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2137 struct dsa_bridge bridge)
2138{
2139 dsa_tag_8021q_bridge_leave(ds, port, bridge);
2140 sja1105_bridge_member(ds, port, bridge, false);
2141}
2142
2143/* Port 0 (the uC port) does not have CBS shapers */
2144#define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio))
2145
2146static int sja1105_find_cbs_shaper(struct sja1105_private *priv,
2147 int port, int prio)
2148{
2149 int i;
2150
2151 if (priv->info->fixed_cbs_mapping) {
2152 i = SJA1110_FIXED_CBS(port, prio);
2153 if (i >= 0 && i < priv->info->num_cbs_shapers)
2154 return i;
2155
2156 return -1;
2157 }
2158
2159 for (i = 0; i < priv->info->num_cbs_shapers; i++)
2160 if (priv->cbs[i].port == port && priv->cbs[i].prio == prio)
2161 return i;
2162
2163 return -1;
2164}
2165
2166static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2167{
2168 int i;
2169
2170 if (priv->info->fixed_cbs_mapping)
2171 return -1;
2172
2173 for (i = 0; i < priv->info->num_cbs_shapers; i++)
2174 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2175 return i;
2176
2177 return -1;
2178}
2179
2180static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2181 int prio)
2182{
2183 int i;
2184
2185 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2186 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2187
2188 if (cbs->port == port && cbs->prio == prio) {
2189 memset(cbs, 0, sizeof(*cbs));
2190 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2191 i, cbs, true);
2192 }
2193 }
2194
2195 return 0;
2196}
2197
2198static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2199 struct tc_cbs_qopt_offload *offload)
2200{
2201 struct sja1105_private *priv = ds->priv;
2202 struct sja1105_cbs_entry *cbs;
2203 s64 port_transmit_rate_kbps;
2204 int index;
2205
2206 if (!offload->enable)
2207 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2208
2209 /* The user may be replacing an existing shaper */
2210 index = sja1105_find_cbs_shaper(priv, port, offload->queue);
2211 if (index < 0) {
2212 /* That isn't the case - see if we can allocate a new one */
2213 index = sja1105_find_unused_cbs_shaper(priv);
2214 if (index < 0)
2215 return -ENOSPC;
2216 }
2217
2218 cbs = &priv->cbs[index];
2219 cbs->port = port;
2220 cbs->prio = offload->queue;
2221 /* locredit and sendslope are negative by definition. In hardware,
2222 * positive values must be provided, and the negative sign is implicit.
2223 */
2224 cbs->credit_hi = offload->hicredit;
2225 cbs->credit_lo = abs(offload->locredit);
2226 /* User space is in kbits/sec, while the hardware in bytes/sec times
2227 * link speed. Since the given offload->sendslope is good only for the
2228 * current link speed anyway, and user space is likely to reprogram it
2229 * when that changes, don't even bother to track the port's link speed,
2230 * but deduce the port transmit rate from idleslope - sendslope.
2231 */
2232 port_transmit_rate_kbps = offload->idleslope - offload->sendslope;
2233 cbs->idle_slope = div_s64(offload->idleslope * BYTES_PER_KBIT,
2234 port_transmit_rate_kbps);
2235 cbs->send_slope = div_s64(abs(offload->sendslope * BYTES_PER_KBIT),
2236 port_transmit_rate_kbps);
2237 /* Convert the negative values from 64-bit 2's complement
2238 * to 32-bit 2's complement (for the case of 0x80000000 whose
2239 * negative is still negative).
2240 */
2241 cbs->credit_lo &= GENMASK_ULL(31, 0);
2242 cbs->send_slope &= GENMASK_ULL(31, 0);
2243
2244 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2245 true);
2246}
2247
2248static int sja1105_reload_cbs(struct sja1105_private *priv)
2249{
2250 int rc = 0, i;
2251
2252 /* The credit based shapers are only allocated if
2253 * CONFIG_NET_SCH_CBS is enabled.
2254 */
2255 if (!priv->cbs)
2256 return 0;
2257
2258 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2259 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2260
2261 if (!cbs->idle_slope && !cbs->send_slope)
2262 continue;
2263
2264 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2265 true);
2266 if (rc)
2267 break;
2268 }
2269
2270 return rc;
2271}
2272
2273static const char * const sja1105_reset_reasons[] = {
2274 [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2275 [SJA1105_AGEING_TIME] = "Ageing time",
2276 [SJA1105_SCHEDULING] = "Time-aware scheduling",
2277 [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2278 [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2279};
2280
2281/* For situations where we need to change a setting at runtime that is only
2282 * available through the static configuration, resetting the switch in order
2283 * to upload the new static config is unavoidable. Back up the settings we
2284 * modify at runtime (currently only MAC) and restore them after uploading,
2285 * such that this operation is relatively seamless.
2286 */
2287int sja1105_static_config_reload(struct sja1105_private *priv,
2288 enum sja1105_reset_reason reason)
2289{
2290 struct ptp_system_timestamp ptp_sts_before;
2291 struct ptp_system_timestamp ptp_sts_after;
2292 int speed_mbps[SJA1105_MAX_NUM_PORTS];
2293 u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2294 struct sja1105_mac_config_entry *mac;
2295 struct dsa_switch *ds = priv->ds;
2296 s64 t1, t2, t3, t4;
2297 s64 t12, t34;
2298 int rc, i;
2299 s64 now;
2300
2301 mutex_lock(&priv->fdb_lock);
2302 mutex_lock(&priv->mgmt_lock);
2303
2304 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2305
2306 /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2307 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2308 * switch wants to see in the static config in order to allow us to
2309 * change it through the dynamic interface later.
2310 */
2311 for (i = 0; i < ds->num_ports; i++) {
2312 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
2313 mac[i].speed);
2314 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2315
2316 if (priv->xpcs[i])
2317 bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i,
2318 MDIO_MMD_VEND2, MDIO_CTRL1);
2319 }
2320
2321 /* No PTP operations can run right now */
2322 mutex_lock(&priv->ptp_data.lock);
2323
2324 rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2325 if (rc < 0) {
2326 mutex_unlock(&priv->ptp_data.lock);
2327 goto out;
2328 }
2329
2330 /* Reset switch and send updated static configuration */
2331 rc = sja1105_static_config_upload(priv);
2332 if (rc < 0) {
2333 mutex_unlock(&priv->ptp_data.lock);
2334 goto out;
2335 }
2336
2337 rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2338 if (rc < 0) {
2339 mutex_unlock(&priv->ptp_data.lock);
2340 goto out;
2341 }
2342
2343 t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2344 t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2345 t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2346 t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2347 /* Mid point, corresponds to pre-reset PTPCLKVAL */
2348 t12 = t1 + (t2 - t1) / 2;
2349 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2350 t34 = t3 + (t4 - t3) / 2;
2351 /* Advance PTPCLKVAL by the time it took since its readout */
2352 now += (t34 - t12);
2353
2354 __sja1105_ptp_adjtime(ds, now);
2355
2356 mutex_unlock(&priv->ptp_data.lock);
2357
2358 dev_info(priv->ds->dev,
2359 "Reset switch and programmed static config. Reason: %s\n",
2360 sja1105_reset_reasons[reason]);
2361
2362 /* Configure the CGU (PLLs) for MII and RMII PHYs.
2363 * For these interfaces there is no dynamic configuration
2364 * needed, since PLLs have same settings at all speeds.
2365 */
2366 if (priv->info->clocking_setup) {
2367 rc = priv->info->clocking_setup(priv);
2368 if (rc < 0)
2369 goto out;
2370 }
2371
2372 for (i = 0; i < ds->num_ports; i++) {
2373 struct dw_xpcs *xpcs = priv->xpcs[i];
2374 unsigned int neg_mode;
2375
2376 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
2377 if (rc < 0)
2378 goto out;
2379
2380 if (!xpcs)
2381 continue;
2382
2383 if (bmcr[i] & BMCR_ANENABLE)
2384 neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
2385 else
2386 neg_mode = PHYLINK_PCS_NEG_OUTBAND;
2387
2388 rc = xpcs_do_config(xpcs, priv->phy_mode[i], NULL, neg_mode);
2389 if (rc < 0)
2390 goto out;
2391
2392 if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) {
2393 int speed = SPEED_UNKNOWN;
2394
2395 if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2396 speed = SPEED_2500;
2397 else if (bmcr[i] & BMCR_SPEED1000)
2398 speed = SPEED_1000;
2399 else if (bmcr[i] & BMCR_SPEED100)
2400 speed = SPEED_100;
2401 else
2402 speed = SPEED_10;
2403
2404 xpcs_link_up(&xpcs->pcs, neg_mode, priv->phy_mode[i],
2405 speed, DUPLEX_FULL);
2406 }
2407 }
2408
2409 rc = sja1105_reload_cbs(priv);
2410 if (rc < 0)
2411 goto out;
2412out:
2413 mutex_unlock(&priv->mgmt_lock);
2414 mutex_unlock(&priv->fdb_lock);
2415
2416 return rc;
2417}
2418
2419static enum dsa_tag_protocol
2420sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2421 enum dsa_tag_protocol mp)
2422{
2423 struct sja1105_private *priv = ds->priv;
2424
2425 return priv->info->tag_proto;
2426}
2427
2428/* The TPID setting belongs to the General Parameters table,
2429 * which can only be partially reconfigured at runtime (and not the TPID).
2430 * So a switch reset is required.
2431 */
2432int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2433 struct netlink_ext_ack *extack)
2434{
2435 struct sja1105_general_params_entry *general_params;
2436 struct sja1105_private *priv = ds->priv;
2437 struct sja1105_table *table;
2438 struct sja1105_rule *rule;
2439 u16 tpid, tpid2;
2440 int rc;
2441
2442 list_for_each_entry(rule, &priv->flow_block.rules, list) {
2443 if (rule->type == SJA1105_RULE_VL) {
2444 NL_SET_ERR_MSG_MOD(extack,
2445 "Cannot change VLAN filtering with active VL rules");
2446 return -EBUSY;
2447 }
2448 }
2449
2450 if (enabled) {
2451 /* Enable VLAN filtering. */
2452 tpid = ETH_P_8021Q;
2453 tpid2 = ETH_P_8021AD;
2454 } else {
2455 /* Disable VLAN filtering. */
2456 tpid = ETH_P_SJA1105;
2457 tpid2 = ETH_P_SJA1105;
2458 }
2459
2460 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2461 general_params = table->entries;
2462 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2463 general_params->tpid = tpid;
2464 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2465 general_params->tpid2 = tpid2;
2466
2467 for (port = 0; port < ds->num_ports; port++) {
2468 if (dsa_is_unused_port(ds, port))
2469 continue;
2470
2471 rc = sja1105_commit_pvid(ds, port);
2472 if (rc)
2473 return rc;
2474 }
2475
2476 rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2477 if (rc)
2478 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2479
2480 return rc;
2481}
2482
2483static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2484 u16 flags, bool allowed_ingress)
2485{
2486 struct sja1105_vlan_lookup_entry *vlan;
2487 struct sja1105_table *table;
2488 int match, rc;
2489
2490 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2491
2492 match = sja1105_is_vlan_configured(priv, vid);
2493 if (match < 0) {
2494 rc = sja1105_table_resize(table, table->entry_count + 1);
2495 if (rc)
2496 return rc;
2497 match = table->entry_count - 1;
2498 }
2499
2500 /* Assign pointer after the resize (it's new memory) */
2501 vlan = table->entries;
2502
2503 vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2504 vlan[match].vlanid = vid;
2505 vlan[match].vlan_bc |= BIT(port);
2506
2507 if (allowed_ingress)
2508 vlan[match].vmemb_port |= BIT(port);
2509 else
2510 vlan[match].vmemb_port &= ~BIT(port);
2511
2512 if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2513 vlan[match].tag_port &= ~BIT(port);
2514 else
2515 vlan[match].tag_port |= BIT(port);
2516
2517 return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2518 &vlan[match], true);
2519}
2520
2521static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2522{
2523 struct sja1105_vlan_lookup_entry *vlan;
2524 struct sja1105_table *table;
2525 bool keep = true;
2526 int match, rc;
2527
2528 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2529
2530 match = sja1105_is_vlan_configured(priv, vid);
2531 /* Can't delete a missing entry. */
2532 if (match < 0)
2533 return 0;
2534
2535 /* Assign pointer after the resize (it's new memory) */
2536 vlan = table->entries;
2537
2538 vlan[match].vlanid = vid;
2539 vlan[match].vlan_bc &= ~BIT(port);
2540 vlan[match].vmemb_port &= ~BIT(port);
2541 /* Also unset tag_port, just so we don't have a confusing bitmap
2542 * (no practical purpose).
2543 */
2544 vlan[match].tag_port &= ~BIT(port);
2545
2546 /* If there's no port left as member of this VLAN,
2547 * it's time for it to go.
2548 */
2549 if (!vlan[match].vmemb_port)
2550 keep = false;
2551
2552 rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2553 &vlan[match], keep);
2554 if (rc < 0)
2555 return rc;
2556
2557 if (!keep)
2558 return sja1105_table_delete_entry(table, match);
2559
2560 return 0;
2561}
2562
2563static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2564 const struct switchdev_obj_port_vlan *vlan,
2565 struct netlink_ext_ack *extack)
2566{
2567 struct sja1105_private *priv = ds->priv;
2568 u16 flags = vlan->flags;
2569 int rc;
2570
2571 /* Be sure to deny alterations to the configuration done by tag_8021q.
2572 */
2573 if (vid_is_dsa_8021q(vlan->vid)) {
2574 NL_SET_ERR_MSG_MOD(extack,
2575 "Range 3072-4095 reserved for dsa_8021q operation");
2576 return -EBUSY;
2577 }
2578
2579 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2580 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2581 flags = 0;
2582
2583 rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2584 if (rc)
2585 return rc;
2586
2587 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2588 priv->bridge_pvid[port] = vlan->vid;
2589
2590 return sja1105_commit_pvid(ds, port);
2591}
2592
2593static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2594 const struct switchdev_obj_port_vlan *vlan)
2595{
2596 struct sja1105_private *priv = ds->priv;
2597 int rc;
2598
2599 rc = sja1105_vlan_del(priv, port, vlan->vid);
2600 if (rc)
2601 return rc;
2602
2603 /* In case the pvid was deleted, make sure that untagged packets will
2604 * be dropped.
2605 */
2606 return sja1105_commit_pvid(ds, port);
2607}
2608
2609static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2610 u16 flags)
2611{
2612 struct sja1105_private *priv = ds->priv;
2613 bool allowed_ingress = true;
2614 int rc;
2615
2616 /* Prevent attackers from trying to inject a DSA tag from
2617 * the outside world.
2618 */
2619 if (dsa_is_user_port(ds, port))
2620 allowed_ingress = false;
2621
2622 rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2623 if (rc)
2624 return rc;
2625
2626 if (flags & BRIDGE_VLAN_INFO_PVID)
2627 priv->tag_8021q_pvid[port] = vid;
2628
2629 return sja1105_commit_pvid(ds, port);
2630}
2631
2632static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2633{
2634 struct sja1105_private *priv = ds->priv;
2635
2636 return sja1105_vlan_del(priv, port, vid);
2637}
2638
2639static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2640 struct netdev_notifier_changeupper_info *info)
2641{
2642 struct netlink_ext_ack *extack = info->info.extack;
2643 struct net_device *upper = info->upper_dev;
2644 struct dsa_switch_tree *dst = ds->dst;
2645 struct dsa_port *dp;
2646
2647 if (is_vlan_dev(upper)) {
2648 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2649 return -EBUSY;
2650 }
2651
2652 if (netif_is_bridge_master(upper)) {
2653 list_for_each_entry(dp, &dst->ports, list) {
2654 struct net_device *br = dsa_port_bridge_dev_get(dp);
2655
2656 if (br && br != upper && br_vlan_enabled(br)) {
2657 NL_SET_ERR_MSG_MOD(extack,
2658 "Only one VLAN-aware bridge is supported");
2659 return -EBUSY;
2660 }
2661 }
2662 }
2663
2664 return 0;
2665}
2666
2667static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2668 struct sk_buff *skb, bool takets)
2669{
2670 struct sja1105_mgmt_entry mgmt_route = {0};
2671 struct sja1105_private *priv = ds->priv;
2672 struct ethhdr *hdr;
2673 int timeout = 10;
2674 int rc;
2675
2676 hdr = eth_hdr(skb);
2677
2678 mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2679 mgmt_route.destports = BIT(port);
2680 mgmt_route.enfport = 1;
2681 mgmt_route.tsreg = 0;
2682 mgmt_route.takets = takets;
2683
2684 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2685 slot, &mgmt_route, true);
2686 if (rc < 0) {
2687 kfree_skb(skb);
2688 return rc;
2689 }
2690
2691 /* Transfer skb to the host port. */
2692 dsa_enqueue_skb(skb, dsa_to_port(ds, port)->user);
2693
2694 /* Wait until the switch has processed the frame */
2695 do {
2696 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2697 slot, &mgmt_route);
2698 if (rc < 0) {
2699 dev_err_ratelimited(priv->ds->dev,
2700 "failed to poll for mgmt route\n");
2701 continue;
2702 }
2703
2704 /* UM10944: The ENFPORT flag of the respective entry is
2705 * cleared when a match is found. The host can use this
2706 * flag as an acknowledgment.
2707 */
2708 cpu_relax();
2709 } while (mgmt_route.enfport && --timeout);
2710
2711 if (!timeout) {
2712 /* Clean up the management route so that a follow-up
2713 * frame may not match on it by mistake.
2714 * This is only hardware supported on P/Q/R/S - on E/T it is
2715 * a no-op and we are silently discarding the -EOPNOTSUPP.
2716 */
2717 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2718 slot, &mgmt_route, false);
2719 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2720 }
2721
2722 return NETDEV_TX_OK;
2723}
2724
2725#define work_to_xmit_work(w) \
2726 container_of((w), struct sja1105_deferred_xmit_work, work)
2727
2728/* Deferred work is unfortunately necessary because setting up the management
2729 * route cannot be done from atomit context (SPI transfer takes a sleepable
2730 * lock on the bus)
2731 */
2732static void sja1105_port_deferred_xmit(struct kthread_work *work)
2733{
2734 struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
2735 struct sk_buff *clone, *skb = xmit_work->skb;
2736 struct dsa_switch *ds = xmit_work->dp->ds;
2737 struct sja1105_private *priv = ds->priv;
2738 int port = xmit_work->dp->index;
2739
2740 clone = SJA1105_SKB_CB(skb)->clone;
2741
2742 mutex_lock(&priv->mgmt_lock);
2743
2744 sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);
2745
2746 /* The clone, if there, was made by dsa_skb_tx_timestamp */
2747 if (clone)
2748 sja1105_ptp_txtstamp_skb(ds, port, clone);
2749
2750 mutex_unlock(&priv->mgmt_lock);
2751
2752 kfree(xmit_work);
2753}
2754
2755static int sja1105_connect_tag_protocol(struct dsa_switch *ds,
2756 enum dsa_tag_protocol proto)
2757{
2758 struct sja1105_private *priv = ds->priv;
2759 struct sja1105_tagger_data *tagger_data;
2760
2761 if (proto != priv->info->tag_proto)
2762 return -EPROTONOSUPPORT;
2763
2764 tagger_data = sja1105_tagger_data(ds);
2765 tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;
2766 tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;
2767
2768 return 0;
2769}
2770
2771/* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2772 * which cannot be reconfigured at runtime. So a switch reset is required.
2773 */
2774static int sja1105_set_ageing_time(struct dsa_switch *ds,
2775 unsigned int ageing_time)
2776{
2777 struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2778 struct sja1105_private *priv = ds->priv;
2779 struct sja1105_table *table;
2780 unsigned int maxage;
2781
2782 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2783 l2_lookup_params = table->entries;
2784
2785 maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2786
2787 if (l2_lookup_params->maxage == maxage)
2788 return 0;
2789
2790 l2_lookup_params->maxage = maxage;
2791
2792 return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2793}
2794
2795static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2796{
2797 struct sja1105_l2_policing_entry *policing;
2798 struct sja1105_private *priv = ds->priv;
2799
2800 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2801
2802 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2803 new_mtu += VLAN_HLEN;
2804
2805 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2806
2807 if (policing[port].maxlen == new_mtu)
2808 return 0;
2809
2810 policing[port].maxlen = new_mtu;
2811
2812 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2813}
2814
2815static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2816{
2817 return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2818}
2819
2820static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2821 enum tc_setup_type type,
2822 void *type_data)
2823{
2824 switch (type) {
2825 case TC_SETUP_QDISC_TAPRIO:
2826 return sja1105_setup_tc_taprio(ds, port, type_data);
2827 case TC_SETUP_QDISC_CBS:
2828 return sja1105_setup_tc_cbs(ds, port, type_data);
2829 default:
2830 return -EOPNOTSUPP;
2831 }
2832}
2833
2834/* We have a single mirror (@to) port, but can configure ingress and egress
2835 * mirroring on all other (@from) ports.
2836 * We need to allow mirroring rules only as long as the @to port is always the
2837 * same, and we need to unset the @to port from mirr_port only when there is no
2838 * mirroring rule that references it.
2839 */
2840static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2841 bool ingress, bool enabled)
2842{
2843 struct sja1105_general_params_entry *general_params;
2844 struct sja1105_mac_config_entry *mac;
2845 struct dsa_switch *ds = priv->ds;
2846 struct sja1105_table *table;
2847 bool already_enabled;
2848 u64 new_mirr_port;
2849 int rc;
2850
2851 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2852 general_params = table->entries;
2853
2854 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2855
2856 already_enabled = (general_params->mirr_port != ds->num_ports);
2857 if (already_enabled && enabled && general_params->mirr_port != to) {
2858 dev_err(priv->ds->dev,
2859 "Delete mirroring rules towards port %llu first\n",
2860 general_params->mirr_port);
2861 return -EBUSY;
2862 }
2863
2864 new_mirr_port = to;
2865 if (!enabled) {
2866 bool keep = false;
2867 int port;
2868
2869 /* Anybody still referencing mirr_port? */
2870 for (port = 0; port < ds->num_ports; port++) {
2871 if (mac[port].ing_mirr || mac[port].egr_mirr) {
2872 keep = true;
2873 break;
2874 }
2875 }
2876 /* Unset already_enabled for next time */
2877 if (!keep)
2878 new_mirr_port = ds->num_ports;
2879 }
2880 if (new_mirr_port != general_params->mirr_port) {
2881 general_params->mirr_port = new_mirr_port;
2882
2883 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2884 0, general_params, true);
2885 if (rc < 0)
2886 return rc;
2887 }
2888
2889 if (ingress)
2890 mac[from].ing_mirr = enabled;
2891 else
2892 mac[from].egr_mirr = enabled;
2893
2894 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2895 &mac[from], true);
2896}
2897
2898static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2899 struct dsa_mall_mirror_tc_entry *mirror,
2900 bool ingress, struct netlink_ext_ack *extack)
2901{
2902 return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2903 ingress, true);
2904}
2905
2906static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2907 struct dsa_mall_mirror_tc_entry *mirror)
2908{
2909 sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2910 mirror->ingress, false);
2911}
2912
2913static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2914 struct dsa_mall_policer_tc_entry *policer)
2915{
2916 struct sja1105_l2_policing_entry *policing;
2917 struct sja1105_private *priv = ds->priv;
2918
2919 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2920
2921 /* In hardware, every 8 microseconds the credit level is incremented by
2922 * the value of RATE bytes divided by 64, up to a maximum of SMAX
2923 * bytes.
2924 */
2925 policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2926 1000000);
2927 policing[port].smax = policer->burst;
2928
2929 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2930}
2931
2932static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2933{
2934 struct sja1105_l2_policing_entry *policing;
2935 struct sja1105_private *priv = ds->priv;
2936
2937 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2938
2939 policing[port].rate = SJA1105_RATE_MBPS(1000);
2940 policing[port].smax = 65535;
2941
2942 sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2943}
2944
2945static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2946 bool enabled)
2947{
2948 struct sja1105_mac_config_entry *mac;
2949
2950 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2951
2952 mac[port].dyn_learn = enabled;
2953
2954 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2955 &mac[port], true);
2956}
2957
2958static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2959 struct switchdev_brport_flags flags)
2960{
2961 if (flags.mask & BR_FLOOD) {
2962 if (flags.val & BR_FLOOD)
2963 priv->ucast_egress_floods |= BIT(to);
2964 else
2965 priv->ucast_egress_floods &= ~BIT(to);
2966 }
2967
2968 if (flags.mask & BR_BCAST_FLOOD) {
2969 if (flags.val & BR_BCAST_FLOOD)
2970 priv->bcast_egress_floods |= BIT(to);
2971 else
2972 priv->bcast_egress_floods &= ~BIT(to);
2973 }
2974
2975 return sja1105_manage_flood_domains(priv);
2976}
2977
2978static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2979 struct switchdev_brport_flags flags,
2980 struct netlink_ext_ack *extack)
2981{
2982 struct sja1105_l2_lookup_entry *l2_lookup;
2983 struct sja1105_table *table;
2984 int match, rc;
2985
2986 mutex_lock(&priv->fdb_lock);
2987
2988 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2989 l2_lookup = table->entries;
2990
2991 for (match = 0; match < table->entry_count; match++)
2992 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2993 l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2994 break;
2995
2996 if (match == table->entry_count) {
2997 NL_SET_ERR_MSG_MOD(extack,
2998 "Could not find FDB entry for unknown multicast");
2999 rc = -ENOSPC;
3000 goto out;
3001 }
3002
3003 if (flags.val & BR_MCAST_FLOOD)
3004 l2_lookup[match].destports |= BIT(to);
3005 else
3006 l2_lookup[match].destports &= ~BIT(to);
3007
3008 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
3009 l2_lookup[match].index,
3010 &l2_lookup[match], true);
3011out:
3012 mutex_unlock(&priv->fdb_lock);
3013
3014 return rc;
3015}
3016
3017static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3018 struct switchdev_brport_flags flags,
3019 struct netlink_ext_ack *extack)
3020{
3021 struct sja1105_private *priv = ds->priv;
3022
3023 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
3024 BR_BCAST_FLOOD))
3025 return -EINVAL;
3026
3027 if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
3028 !priv->info->can_limit_mcast_flood) {
3029 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
3030 bool unicast = !!(flags.val & BR_FLOOD);
3031
3032 if (unicast != multicast) {
3033 NL_SET_ERR_MSG_MOD(extack,
3034 "This chip cannot configure multicast flooding independently of unicast");
3035 return -EINVAL;
3036 }
3037 }
3038
3039 return 0;
3040}
3041
3042static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
3043 struct switchdev_brport_flags flags,
3044 struct netlink_ext_ack *extack)
3045{
3046 struct sja1105_private *priv = ds->priv;
3047 int rc;
3048
3049 if (flags.mask & BR_LEARNING) {
3050 bool learn_ena = !!(flags.val & BR_LEARNING);
3051
3052 rc = sja1105_port_set_learning(priv, port, learn_ena);
3053 if (rc)
3054 return rc;
3055 }
3056
3057 if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
3058 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
3059 if (rc)
3060 return rc;
3061 }
3062
3063 /* For chips that can't offload BR_MCAST_FLOOD independently, there
3064 * is nothing to do here, we ensured the configuration is in sync by
3065 * offloading BR_FLOOD.
3066 */
3067 if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
3068 rc = sja1105_port_mcast_flood(priv, port, flags,
3069 extack);
3070 if (rc)
3071 return rc;
3072 }
3073
3074 return 0;
3075}
3076
3077/* The programming model for the SJA1105 switch is "all-at-once" via static
3078 * configuration tables. Some of these can be dynamically modified at runtime,
3079 * but not the xMII mode parameters table.
3080 * Furthermode, some PHYs may not have crystals for generating their clocks
3081 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3082 * ref_clk pin. So port clocking needs to be initialized early, before
3083 * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3084 * Setting correct PHY link speed does not matter now.
3085 * But dsa_user_phy_setup is called later than sja1105_setup, so the PHY
3086 * bindings are not yet parsed by DSA core. We need to parse early so that we
3087 * can populate the xMII mode parameters table.
3088 */
3089static int sja1105_setup(struct dsa_switch *ds)
3090{
3091 struct sja1105_private *priv = ds->priv;
3092 int rc;
3093
3094 if (priv->info->disable_microcontroller) {
3095 rc = priv->info->disable_microcontroller(priv);
3096 if (rc < 0) {
3097 dev_err(ds->dev,
3098 "Failed to disable microcontroller: %pe\n",
3099 ERR_PTR(rc));
3100 return rc;
3101 }
3102 }
3103
3104 /* Create and send configuration down to device */
3105 rc = sja1105_static_config_load(priv);
3106 if (rc < 0) {
3107 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3108 return rc;
3109 }
3110
3111 /* Configure the CGU (PHY link modes and speeds) */
3112 if (priv->info->clocking_setup) {
3113 rc = priv->info->clocking_setup(priv);
3114 if (rc < 0) {
3115 dev_err(ds->dev,
3116 "Failed to configure MII clocking: %pe\n",
3117 ERR_PTR(rc));
3118 goto out_static_config_free;
3119 }
3120 }
3121
3122 sja1105_tas_setup(ds);
3123 sja1105_flower_setup(ds);
3124
3125 rc = sja1105_ptp_clock_register(ds);
3126 if (rc < 0) {
3127 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3128 goto out_flower_teardown;
3129 }
3130
3131 rc = sja1105_mdiobus_register(ds);
3132 if (rc < 0) {
3133 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3134 ERR_PTR(rc));
3135 goto out_ptp_clock_unregister;
3136 }
3137
3138 rc = sja1105_devlink_setup(ds);
3139 if (rc < 0)
3140 goto out_mdiobus_unregister;
3141
3142 rtnl_lock();
3143 rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3144 rtnl_unlock();
3145 if (rc)
3146 goto out_devlink_teardown;
3147
3148 /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3149 * The only thing we can do to disable it is lie about what the 802.1Q
3150 * EtherType is.
3151 * So it will still try to apply VLAN filtering, but all ingress
3152 * traffic (except frames received with EtherType of ETH_P_SJA1105)
3153 * will be internally tagged with a distorted VLAN header where the
3154 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3155 */
3156 ds->vlan_filtering_is_global = true;
3157 ds->untag_bridge_pvid = true;
3158 ds->fdb_isolation = true;
3159 /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3160 ds->max_num_bridges = 7;
3161
3162 /* Advertise the 8 egress queues */
3163 ds->num_tx_queues = SJA1105_NUM_TC;
3164
3165 ds->mtu_enforcement_ingress = true;
3166 ds->assisted_learning_on_cpu_port = true;
3167
3168 return 0;
3169
3170out_devlink_teardown:
3171 sja1105_devlink_teardown(ds);
3172out_mdiobus_unregister:
3173 sja1105_mdiobus_unregister(ds);
3174out_ptp_clock_unregister:
3175 sja1105_ptp_clock_unregister(ds);
3176out_flower_teardown:
3177 sja1105_flower_teardown(ds);
3178 sja1105_tas_teardown(ds);
3179out_static_config_free:
3180 sja1105_static_config_free(&priv->static_config);
3181
3182 return rc;
3183}
3184
3185static void sja1105_teardown(struct dsa_switch *ds)
3186{
3187 struct sja1105_private *priv = ds->priv;
3188
3189 rtnl_lock();
3190 dsa_tag_8021q_unregister(ds);
3191 rtnl_unlock();
3192
3193 sja1105_devlink_teardown(ds);
3194 sja1105_mdiobus_unregister(ds);
3195 sja1105_ptp_clock_unregister(ds);
3196 sja1105_flower_teardown(ds);
3197 sja1105_tas_teardown(ds);
3198 sja1105_static_config_free(&priv->static_config);
3199}
3200
3201static const struct dsa_switch_ops sja1105_switch_ops = {
3202 .get_tag_protocol = sja1105_get_tag_protocol,
3203 .connect_tag_protocol = sja1105_connect_tag_protocol,
3204 .setup = sja1105_setup,
3205 .teardown = sja1105_teardown,
3206 .set_ageing_time = sja1105_set_ageing_time,
3207 .port_change_mtu = sja1105_change_mtu,
3208 .port_max_mtu = sja1105_get_max_mtu,
3209 .phylink_get_caps = sja1105_phylink_get_caps,
3210 .phylink_mac_select_pcs = sja1105_mac_select_pcs,
3211 .phylink_mac_link_up = sja1105_mac_link_up,
3212 .phylink_mac_link_down = sja1105_mac_link_down,
3213 .get_strings = sja1105_get_strings,
3214 .get_ethtool_stats = sja1105_get_ethtool_stats,
3215 .get_sset_count = sja1105_get_sset_count,
3216 .get_ts_info = sja1105_get_ts_info,
3217 .port_fdb_dump = sja1105_fdb_dump,
3218 .port_fdb_add = sja1105_fdb_add,
3219 .port_fdb_del = sja1105_fdb_del,
3220 .port_fast_age = sja1105_fast_age,
3221 .port_bridge_join = sja1105_bridge_join,
3222 .port_bridge_leave = sja1105_bridge_leave,
3223 .port_pre_bridge_flags = sja1105_port_pre_bridge_flags,
3224 .port_bridge_flags = sja1105_port_bridge_flags,
3225 .port_stp_state_set = sja1105_bridge_stp_state_set,
3226 .port_vlan_filtering = sja1105_vlan_filtering,
3227 .port_vlan_add = sja1105_bridge_vlan_add,
3228 .port_vlan_del = sja1105_bridge_vlan_del,
3229 .port_mdb_add = sja1105_mdb_add,
3230 .port_mdb_del = sja1105_mdb_del,
3231 .port_hwtstamp_get = sja1105_hwtstamp_get,
3232 .port_hwtstamp_set = sja1105_hwtstamp_set,
3233 .port_rxtstamp = sja1105_port_rxtstamp,
3234 .port_txtstamp = sja1105_port_txtstamp,
3235 .port_setup_tc = sja1105_port_setup_tc,
3236 .port_mirror_add = sja1105_mirror_add,
3237 .port_mirror_del = sja1105_mirror_del,
3238 .port_policer_add = sja1105_port_policer_add,
3239 .port_policer_del = sja1105_port_policer_del,
3240 .cls_flower_add = sja1105_cls_flower_add,
3241 .cls_flower_del = sja1105_cls_flower_del,
3242 .cls_flower_stats = sja1105_cls_flower_stats,
3243 .devlink_info_get = sja1105_devlink_info_get,
3244 .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add,
3245 .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del,
3246 .port_prechangeupper = sja1105_prechangeupper,
3247};
3248
3249static const struct of_device_id sja1105_dt_ids[];
3250
3251static int sja1105_check_device_id(struct sja1105_private *priv)
3252{
3253 const struct sja1105_regs *regs = priv->info->regs;
3254 u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3255 struct device *dev = &priv->spidev->dev;
3256 const struct of_device_id *match;
3257 u32 device_id;
3258 u64 part_no;
3259 int rc;
3260
3261 rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3262 NULL);
3263 if (rc < 0)
3264 return rc;
3265
3266 rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3267 SJA1105_SIZE_DEVICE_ID);
3268 if (rc < 0)
3269 return rc;
3270
3271 sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3272
3273 for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3274 const struct sja1105_info *info = match->data;
3275
3276 /* Is what's been probed in our match table at all? */
3277 if (info->device_id != device_id || info->part_no != part_no)
3278 continue;
3279
3280 /* But is it what's in the device tree? */
3281 if (priv->info->device_id != device_id ||
3282 priv->info->part_no != part_no) {
3283 dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3284 priv->info->name, info->name);
3285 /* It isn't. No problem, pick that up. */
3286 priv->info = info;
3287 }
3288
3289 return 0;
3290 }
3291
3292 dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3293 device_id, part_no);
3294
3295 return -ENODEV;
3296}
3297
3298static int sja1105_probe(struct spi_device *spi)
3299{
3300 struct device *dev = &spi->dev;
3301 struct sja1105_private *priv;
3302 size_t max_xfer, max_msg;
3303 struct dsa_switch *ds;
3304 int rc;
3305
3306 if (!dev->of_node) {
3307 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3308 return -EINVAL;
3309 }
3310
3311 rc = sja1105_hw_reset(dev, 1, 1);
3312 if (rc)
3313 return rc;
3314
3315 priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3316 if (!priv)
3317 return -ENOMEM;
3318
3319 /* Populate our driver private structure (priv) based on
3320 * the device tree node that was probed (spi)
3321 */
3322 priv->spidev = spi;
3323 spi_set_drvdata(spi, priv);
3324
3325 /* Configure the SPI bus */
3326 spi->bits_per_word = 8;
3327 rc = spi_setup(spi);
3328 if (rc < 0) {
3329 dev_err(dev, "Could not init SPI\n");
3330 return rc;
3331 }
3332
3333 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3334 * a small one for the message header and another one for the current
3335 * chunk of the packed buffer.
3336 * Check that the restrictions imposed by the SPI controller are
3337 * respected: the chunk buffer is smaller than the max transfer size,
3338 * and the total length of the chunk plus its message header is smaller
3339 * than the max message size.
3340 * We do that during probe time since the maximum transfer size is a
3341 * runtime invariant.
3342 */
3343 max_xfer = spi_max_transfer_size(spi);
3344 max_msg = spi_max_message_size(spi);
3345
3346 /* We need to send at least one 64-bit word of SPI payload per message
3347 * in order to be able to make useful progress.
3348 */
3349 if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3350 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3351 return -EINVAL;
3352 }
3353
3354 priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3355 if (priv->max_xfer_len > max_xfer)
3356 priv->max_xfer_len = max_xfer;
3357 if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3358 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3359
3360 priv->info = of_device_get_match_data(dev);
3361
3362 /* Detect hardware device */
3363 rc = sja1105_check_device_id(priv);
3364 if (rc < 0) {
3365 dev_err(dev, "Device ID check failed: %d\n", rc);
3366 return rc;
3367 }
3368
3369 dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3370
3371 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3372 if (!ds)
3373 return -ENOMEM;
3374
3375 ds->dev = dev;
3376 ds->num_ports = priv->info->num_ports;
3377 ds->ops = &sja1105_switch_ops;
3378 ds->priv = priv;
3379 priv->ds = ds;
3380
3381 mutex_init(&priv->ptp_data.lock);
3382 mutex_init(&priv->dynamic_config_lock);
3383 mutex_init(&priv->mgmt_lock);
3384 mutex_init(&priv->fdb_lock);
3385 spin_lock_init(&priv->ts_id_lock);
3386
3387 rc = sja1105_parse_dt(priv);
3388 if (rc < 0) {
3389 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3390 return rc;
3391 }
3392
3393 if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3394 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3395 sizeof(struct sja1105_cbs_entry),
3396 GFP_KERNEL);
3397 if (!priv->cbs)
3398 return -ENOMEM;
3399 }
3400
3401 return dsa_register_switch(priv->ds);
3402}
3403
3404static void sja1105_remove(struct spi_device *spi)
3405{
3406 struct sja1105_private *priv = spi_get_drvdata(spi);
3407
3408 if (!priv)
3409 return;
3410
3411 dsa_unregister_switch(priv->ds);
3412}
3413
3414static void sja1105_shutdown(struct spi_device *spi)
3415{
3416 struct sja1105_private *priv = spi_get_drvdata(spi);
3417
3418 if (!priv)
3419 return;
3420
3421 dsa_switch_shutdown(priv->ds);
3422
3423 spi_set_drvdata(spi, NULL);
3424}
3425
3426static const struct of_device_id sja1105_dt_ids[] = {
3427 { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3428 { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3429 { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3430 { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3431 { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3432 { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3433 { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3434 { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3435 { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3436 { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3437 { /* sentinel */ },
3438};
3439MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3440
3441static const struct spi_device_id sja1105_spi_ids[] = {
3442 { "sja1105e" },
3443 { "sja1105t" },
3444 { "sja1105p" },
3445 { "sja1105q" },
3446 { "sja1105r" },
3447 { "sja1105s" },
3448 { "sja1110a" },
3449 { "sja1110b" },
3450 { "sja1110c" },
3451 { "sja1110d" },
3452 { },
3453};
3454MODULE_DEVICE_TABLE(spi, sja1105_spi_ids);
3455
3456static struct spi_driver sja1105_driver = {
3457 .driver = {
3458 .name = "sja1105",
3459 .owner = THIS_MODULE,
3460 .of_match_table = of_match_ptr(sja1105_dt_ids),
3461 },
3462 .id_table = sja1105_spi_ids,
3463 .probe = sja1105_probe,
3464 .remove = sja1105_remove,
3465 .shutdown = sja1105_shutdown,
3466};
3467
3468module_spi_driver(sja1105_driver);
3469
3470MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3471MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3472MODULE_DESCRIPTION("SJA1105 Driver");
3473MODULE_LICENSE("GPL v2");