1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * perf.h - performance monitor header
 4 *
 5 * Copyright (C) 2021 Intel Corporation
 6 *
 7 * Author: Lu Baolu <baolu.lu@linux.intel.com>
 8 */
 9
10enum latency_type {
11	DMAR_LATENCY_INV_IOTLB = 0,
12	DMAR_LATENCY_INV_DEVTLB,
13	DMAR_LATENCY_INV_IEC,
 
14	DMAR_LATENCY_NUM
15};
16
17enum latency_count {
18	COUNTS_10e2 = 0,	/* < 0.1us	*/
19	COUNTS_10e3,		/* 0.1us ~ 1us	*/
20	COUNTS_10e4,		/* 1us ~ 10us	*/
21	COUNTS_10e5,		/* 10us ~ 100us	*/
22	COUNTS_10e6,		/* 100us ~ 1ms	*/
23	COUNTS_10e7,		/* 1ms ~ 10ms	*/
24	COUNTS_10e8_plus,	/* 10ms and plus*/
25	COUNTS_MIN,
26	COUNTS_MAX,
27	COUNTS_SUM,
28	COUNTS_NUM
29};
30
31struct latency_statistic {
32	bool enabled;
33	u64 counter[COUNTS_NUM];
34	u64 samples;
35};
36
37#ifdef CONFIG_DMAR_PERF
38int dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type);
39void dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type);
40bool dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type);
41void dmar_latency_update(struct intel_iommu *iommu, enum latency_type type,
42			 u64 latency);
43int dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size);
44#else
45static inline int
46dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type)
47{
48	return -EINVAL;
49}
50
51static inline void
52dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type)
53{
54}
55
56static inline bool
57dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type)
58{
59	return false;
60}
61
62static inline void
63dmar_latency_update(struct intel_iommu *iommu, enum latency_type type, u64 latency)
64{
65}
66
67static inline int
68dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size)
69{
70	return 0;
71}
72#endif /* CONFIG_DMAR_PERF */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * perf.h - performance monitor header
 4 *
 5 * Copyright (C) 2021 Intel Corporation
 6 *
 7 * Author: Lu Baolu <baolu.lu@linux.intel.com>
 8 */
 9
10enum latency_type {
11	DMAR_LATENCY_INV_IOTLB = 0,
12	DMAR_LATENCY_INV_DEVTLB,
13	DMAR_LATENCY_INV_IEC,
14	DMAR_LATENCY_PRQ,
15	DMAR_LATENCY_NUM
16};
17
18enum latency_count {
19	COUNTS_10e2 = 0,	/* < 0.1us	*/
20	COUNTS_10e3,		/* 0.1us ~ 1us	*/
21	COUNTS_10e4,		/* 1us ~ 10us	*/
22	COUNTS_10e5,		/* 10us ~ 100us	*/
23	COUNTS_10e6,		/* 100us ~ 1ms	*/
24	COUNTS_10e7,		/* 1ms ~ 10ms	*/
25	COUNTS_10e8_plus,	/* 10ms and plus*/
26	COUNTS_MIN,
27	COUNTS_MAX,
28	COUNTS_SUM,
29	COUNTS_NUM
30};
31
32struct latency_statistic {
33	bool enabled;
34	u64 counter[COUNTS_NUM];
35	u64 samples;
36};
37
38#ifdef CONFIG_DMAR_PERF
39int dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type);
40void dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type);
41bool dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type);
42void dmar_latency_update(struct intel_iommu *iommu, enum latency_type type,
43			 u64 latency);
44int dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size);
45#else
46static inline int
47dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type)
48{
49	return -EINVAL;
50}
51
52static inline void
53dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type)
54{
55}
56
57static inline bool
58dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type)
59{
60	return false;
61}
62
63static inline void
64dmar_latency_update(struct intel_iommu *iommu, enum latency_type type, u64 latency)
65{
66}
67
68static inline int
69dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size)
70{
71	return 0;
72}
73#endif /* CONFIG_DMAR_PERF */