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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <linux/component.h>
9#include <linux/iopoll.h>
10#include <linux/irq.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/phy/phy.h>
14#include <linux/platform_device.h>
15#include <linux/reset.h>
16#include <linux/units.h>
17
18#include <video/mipi_display.h>
19#include <video/videomode.h>
20
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_bridge.h>
23#include <drm/drm_bridge_connector.h>
24#include <drm/drm_mipi_dsi.h>
25#include <drm/drm_of.h>
26#include <drm/drm_panel.h>
27#include <drm/drm_print.h>
28#include <drm/drm_probe_helper.h>
29#include <drm/drm_simple_kms_helper.h>
30
31#include "mtk_ddp_comp.h"
32#include "mtk_disp_drv.h"
33#include "mtk_drm_drv.h"
34
35#define DSI_START 0x00
36
37#define DSI_INTEN 0x08
38
39#define DSI_INTSTA 0x0c
40#define LPRX_RD_RDY_INT_FLAG BIT(0)
41#define CMD_DONE_INT_FLAG BIT(1)
42#define TE_RDY_INT_FLAG BIT(2)
43#define VM_DONE_INT_FLAG BIT(3)
44#define EXT_TE_RDY_INT_FLAG BIT(4)
45#define DSI_BUSY BIT(31)
46
47#define DSI_CON_CTRL 0x10
48#define DSI_RESET BIT(0)
49#define DSI_EN BIT(1)
50#define DPHY_RESET BIT(2)
51
52#define DSI_MODE_CTRL 0x14
53#define MODE (3)
54#define CMD_MODE 0
55#define SYNC_PULSE_MODE 1
56#define SYNC_EVENT_MODE 2
57#define BURST_MODE 3
58#define FRM_MODE BIT(16)
59#define MIX_MODE BIT(17)
60
61#define DSI_TXRX_CTRL 0x18
62#define VC_NUM BIT(1)
63#define LANE_NUM GENMASK(5, 2)
64#define DIS_EOT BIT(6)
65#define NULL_EN BIT(7)
66#define TE_FREERUN BIT(8)
67#define EXT_TE_EN BIT(9)
68#define EXT_TE_EDGE BIT(10)
69#define MAX_RTN_SIZE GENMASK(15, 12)
70#define HSTX_CKLP_EN BIT(16)
71
72#define DSI_PSCTRL 0x1c
73#define DSI_PS_WC GENMASK(13, 0)
74#define DSI_PS_SEL GENMASK(17, 16)
75#define PACKED_PS_16BIT_RGB565 0
76#define PACKED_PS_18BIT_RGB666 1
77#define LOOSELY_PS_24BIT_RGB666 2
78#define PACKED_PS_24BIT_RGB888 3
79
80#define DSI_VSA_NL 0x20
81#define DSI_VBP_NL 0x24
82#define DSI_VFP_NL 0x28
83#define DSI_VACT_NL 0x2C
84#define VACT_NL GENMASK(14, 0)
85#define DSI_SIZE_CON 0x38
86#define DSI_HEIGHT GENMASK(30, 16)
87#define DSI_WIDTH GENMASK(14, 0)
88#define DSI_HSA_WC 0x50
89#define DSI_HBP_WC 0x54
90#define DSI_HFP_WC 0x58
91#define HFP_HS_VB_PS_WC GENMASK(30, 16)
92#define HFP_HS_EN BIT(31)
93
94#define DSI_CMDQ_SIZE 0x60
95#define CMDQ_SIZE 0x3f
96#define CMDQ_SIZE_SEL BIT(15)
97
98#define DSI_HSTX_CKL_WC 0x64
99#define HSTX_CKL_WC GENMASK(15, 2)
100
101#define DSI_RX_DATA0 0x74
102#define DSI_RX_DATA1 0x78
103#define DSI_RX_DATA2 0x7c
104#define DSI_RX_DATA3 0x80
105
106#define DSI_RACK 0x84
107#define RACK BIT(0)
108
109#define DSI_PHY_LCCON 0x104
110#define LC_HS_TX_EN BIT(0)
111#define LC_ULPM_EN BIT(1)
112#define LC_WAKEUP_EN BIT(2)
113
114#define DSI_PHY_LD0CON 0x108
115#define LD0_HS_TX_EN BIT(0)
116#define LD0_ULPM_EN BIT(1)
117#define LD0_WAKEUP_EN BIT(2)
118
119#define DSI_PHY_TIMECON0 0x110
120#define LPX GENMASK(7, 0)
121#define HS_PREP GENMASK(15, 8)
122#define HS_ZERO GENMASK(23, 16)
123#define HS_TRAIL GENMASK(31, 24)
124
125#define DSI_PHY_TIMECON1 0x114
126#define TA_GO GENMASK(7, 0)
127#define TA_SURE GENMASK(15, 8)
128#define TA_GET GENMASK(23, 16)
129#define DA_HS_EXIT GENMASK(31, 24)
130
131#define DSI_PHY_TIMECON2 0x118
132#define CONT_DET GENMASK(7, 0)
133#define DA_HS_SYNC GENMASK(15, 8)
134#define CLK_ZERO GENMASK(23, 16)
135#define CLK_TRAIL GENMASK(31, 24)
136
137#define DSI_PHY_TIMECON3 0x11c
138#define CLK_HS_PREP GENMASK(7, 0)
139#define CLK_HS_POST GENMASK(15, 8)
140#define CLK_HS_EXIT GENMASK(23, 16)
141
142/* DSI_VM_CMD_CON */
143#define VM_CMD_EN BIT(0)
144#define TS_VFP_EN BIT(5)
145
146/* DSI_SHADOW_DEBUG */
147#define FORCE_COMMIT BIT(0)
148#define BYPASS_SHADOW BIT(1)
149
150/* CMDQ related bits */
151#define CONFIG GENMASK(7, 0)
152#define SHORT_PACKET 0
153#define LONG_PACKET 2
154#define BTA BIT(2)
155#define DATA_ID GENMASK(15, 8)
156#define DATA_0 GENMASK(23, 16)
157#define DATA_1 GENMASK(31, 24)
158
159#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
160
161#define MTK_DSI_HOST_IS_READ(type) \
162 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
163 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
164 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
165 (type == MIPI_DSI_DCS_READ))
166
167struct mtk_phy_timing {
168 u32 lpx;
169 u32 da_hs_prepare;
170 u32 da_hs_zero;
171 u32 da_hs_trail;
172
173 u32 ta_go;
174 u32 ta_sure;
175 u32 ta_get;
176 u32 da_hs_exit;
177
178 u32 clk_hs_zero;
179 u32 clk_hs_trail;
180
181 u32 clk_hs_prepare;
182 u32 clk_hs_post;
183 u32 clk_hs_exit;
184};
185
186struct phy;
187
188struct mtk_dsi_driver_data {
189 const u32 reg_cmdq_off;
190 const u32 reg_vm_cmd_off;
191 const u32 reg_shadow_dbg_off;
192 bool has_shadow_ctl;
193 bool has_size_ctl;
194 bool cmdq_long_packet_ctl;
195 bool support_per_frame_lp;
196};
197
198struct mtk_dsi {
199 struct device *dev;
200 struct mipi_dsi_host host;
201 struct drm_encoder encoder;
202 struct drm_bridge bridge;
203 struct drm_bridge *next_bridge;
204 struct drm_connector *connector;
205 struct phy *phy;
206
207 void __iomem *regs;
208
209 struct clk *engine_clk;
210 struct clk *digital_clk;
211 struct clk *hs_clk;
212
213 u32 data_rate;
214
215 unsigned long mode_flags;
216 enum mipi_dsi_pixel_format format;
217 unsigned int lanes;
218 struct videomode vm;
219 struct mtk_phy_timing phy_timing;
220 int refcount;
221 bool enabled;
222 bool lanes_ready;
223 u32 irq_data;
224 wait_queue_head_t irq_wait_queue;
225 const struct mtk_dsi_driver_data *driver_data;
226};
227
228static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)
229{
230 return container_of(b, struct mtk_dsi, bridge);
231}
232
233static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
234{
235 return container_of(h, struct mtk_dsi, host);
236}
237
238static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
239{
240 u32 temp = readl(dsi->regs + offset);
241
242 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
243}
244
245static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
246{
247 u32 timcon0, timcon1, timcon2, timcon3;
248 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);
249 struct mtk_phy_timing *timing = &dsi->phy_timing;
250
251 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
252 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
253 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
254 timing->da_hs_prepare;
255 timing->da_hs_trail = timing->da_hs_prepare + 1;
256
257 timing->ta_go = 4 * timing->lpx - 2;
258 timing->ta_sure = timing->lpx + 2;
259 timing->ta_get = 4 * timing->lpx;
260 timing->da_hs_exit = 2 * timing->lpx + 1;
261
262 timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
263 timing->clk_hs_post = timing->clk_hs_prepare + 8;
264 timing->clk_hs_trail = timing->clk_hs_prepare;
265 timing->clk_hs_zero = timing->clk_hs_trail * 4;
266 timing->clk_hs_exit = 2 * timing->clk_hs_trail;
267
268 timcon0 = FIELD_PREP(LPX, timing->lpx) |
269 FIELD_PREP(HS_PREP, timing->da_hs_prepare) |
270 FIELD_PREP(HS_ZERO, timing->da_hs_zero) |
271 FIELD_PREP(HS_TRAIL, timing->da_hs_trail);
272
273 timcon1 = FIELD_PREP(TA_GO, timing->ta_go) |
274 FIELD_PREP(TA_SURE, timing->ta_sure) |
275 FIELD_PREP(TA_GET, timing->ta_get) |
276 FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit);
277
278 timcon2 = FIELD_PREP(DA_HS_SYNC, 1) |
279 FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) |
280 FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail);
281
282 timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) |
283 FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) |
284 FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit);
285
286 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
287 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
288 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
289 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
290}
291
292static void mtk_dsi_enable(struct mtk_dsi *dsi)
293{
294 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
295}
296
297static void mtk_dsi_disable(struct mtk_dsi *dsi)
298{
299 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
300}
301
302static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
303{
304 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
305 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
306}
307
308static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
309{
310 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
311 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
312}
313
314static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
315{
316 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
317 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
318}
319
320static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
321{
322 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
323 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
324 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
325}
326
327static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
328{
329 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
330 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
331}
332
333static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
334{
335 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
336 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
337 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
338}
339
340static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
341{
342 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
343}
344
345static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
346{
347 if (enter && !mtk_dsi_clk_hs_state(dsi))
348 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
349 else if (!enter && mtk_dsi_clk_hs_state(dsi))
350 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
351}
352
353static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
354{
355 u32 vid_mode = CMD_MODE;
356
357 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
358 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
359 vid_mode = BURST_MODE;
360 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
361 vid_mode = SYNC_PULSE_MODE;
362 else
363 vid_mode = SYNC_EVENT_MODE;
364 }
365
366 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
367}
368
369static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
370{
371 mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN);
372 mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN);
373}
374
375static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
376{
377 u32 regval, tmp_reg = 0;
378 u8 i;
379
380 /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */
381 for (i = 0; i < dsi->lanes; i++)
382 tmp_reg |= BIT(i);
383
384 regval = FIELD_PREP(LANE_NUM, tmp_reg);
385
386 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
387 regval |= HSTX_CKLP_EN;
388
389 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
390 regval |= DIS_EOT;
391
392 writel(regval, dsi->regs + DSI_TXRX_CTRL);
393}
394
395static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact)
396{
397 u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl;
398
399 if (dsi->format == MIPI_DSI_FMT_RGB565)
400 dsi_buf_bpp = 2;
401 else
402 dsi_buf_bpp = 3;
403
404 /* Word count */
405 ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp);
406 ps_val = ps_wc;
407
408 /* Pixel Stream type */
409 switch (dsi->format) {
410 default:
411 fallthrough;
412 case MIPI_DSI_FMT_RGB888:
413 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888);
414 break;
415 case MIPI_DSI_FMT_RGB666:
416 ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666);
417 break;
418 case MIPI_DSI_FMT_RGB666_PACKED:
419 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666);
420 break;
421 case MIPI_DSI_FMT_RGB565:
422 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565);
423 break;
424 }
425
426 if (config_vact) {
427 vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive);
428 writel(vact_nl, dsi->regs + DSI_VACT_NL);
429 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
430 }
431 writel(ps_val, dsi->regs + DSI_PSCTRL);
432}
433
434static void mtk_dsi_config_vdo_timing_per_frame_lp(struct mtk_dsi *dsi)
435{
436 u32 horizontal_sync_active_byte;
437 u32 horizontal_backporch_byte;
438 u32 horizontal_frontporch_byte;
439 u32 hfp_byte_adjust, v_active_adjust;
440 u32 cklp_wc_min_adjust, cklp_wc_max_adjust;
441 u32 dsi_tmp_buf_bpp;
442 unsigned int da_hs_trail;
443 unsigned int ps_wc, hs_vb_ps_wc;
444 u32 v_active_roundup, hstx_cklp_wc;
445 u32 hstx_cklp_wc_max, hstx_cklp_wc_min;
446 struct videomode *vm = &dsi->vm;
447
448 if (dsi->format == MIPI_DSI_FMT_RGB565)
449 dsi_tmp_buf_bpp = 2;
450 else
451 dsi_tmp_buf_bpp = 3;
452
453 da_hs_trail = dsi->phy_timing.da_hs_trail;
454 ps_wc = vm->hactive * dsi_tmp_buf_bpp;
455
456 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
457 horizontal_sync_active_byte =
458 vm->hsync_len * dsi_tmp_buf_bpp - 10;
459 horizontal_backporch_byte =
460 vm->hback_porch * dsi_tmp_buf_bpp - 10;
461 hfp_byte_adjust = 12;
462 v_active_adjust = 32 + horizontal_sync_active_byte;
463 cklp_wc_min_adjust = 12 + 2 + 4 + horizontal_sync_active_byte;
464 cklp_wc_max_adjust = 20 + 6 + 4 + horizontal_sync_active_byte;
465 } else {
466 horizontal_sync_active_byte = vm->hsync_len * dsi_tmp_buf_bpp - 4;
467 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
468 dsi_tmp_buf_bpp - 10;
469 cklp_wc_min_adjust = 4;
470 cklp_wc_max_adjust = 12 + 4 + 4;
471 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
472 hfp_byte_adjust = 18;
473 v_active_adjust = 28;
474 } else {
475 hfp_byte_adjust = 12;
476 v_active_adjust = 22;
477 }
478 }
479 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp - hfp_byte_adjust;
480 v_active_roundup = (v_active_adjust + horizontal_backporch_byte + ps_wc +
481 horizontal_frontporch_byte) % dsi->lanes;
482 if (v_active_roundup)
483 horizontal_backporch_byte += dsi->lanes - v_active_roundup;
484 hstx_cklp_wc_min = (DIV_ROUND_UP(cklp_wc_min_adjust, dsi->lanes) + da_hs_trail + 1)
485 * dsi->lanes / 6 - 1;
486 hstx_cklp_wc_max = (DIV_ROUND_UP((cklp_wc_max_adjust + horizontal_backporch_byte +
487 ps_wc), dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1;
488
489 hstx_cklp_wc = FIELD_PREP(HSTX_CKL_WC, (hstx_cklp_wc_min + hstx_cklp_wc_max) / 2);
490 writel(hstx_cklp_wc, dsi->regs + DSI_HSTX_CKL_WC);
491
492 hs_vb_ps_wc = ps_wc - (dsi->phy_timing.lpx + dsi->phy_timing.da_hs_exit +
493 dsi->phy_timing.da_hs_prepare + dsi->phy_timing.da_hs_zero + 2) * dsi->lanes;
494 horizontal_frontporch_byte |= FIELD_PREP(HFP_HS_EN, 1) |
495 FIELD_PREP(HFP_HS_VB_PS_WC, hs_vb_ps_wc);
496
497 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
498 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
499 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
500}
501
502static void mtk_dsi_config_vdo_timing_per_line_lp(struct mtk_dsi *dsi)
503{
504 u32 horizontal_sync_active_byte;
505 u32 horizontal_backporch_byte;
506 u32 horizontal_frontporch_byte;
507 u32 horizontal_front_back_byte;
508 u32 data_phy_cycles_byte;
509 u32 dsi_tmp_buf_bpp, data_phy_cycles;
510 u32 delta;
511 struct mtk_phy_timing *timing = &dsi->phy_timing;
512 struct videomode *vm = &dsi->vm;
513
514 if (dsi->format == MIPI_DSI_FMT_RGB565)
515 dsi_tmp_buf_bpp = 2;
516 else
517 dsi_tmp_buf_bpp = 3;
518
519 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
520
521 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
522 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10;
523 else
524 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
525 dsi_tmp_buf_bpp - 10;
526
527 data_phy_cycles = timing->lpx + timing->da_hs_prepare +
528 timing->da_hs_zero + timing->da_hs_exit + 3;
529
530 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
531 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2;
532
533 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
534 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte;
535 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
536
537 if (horizontal_front_back_byte > data_phy_cycles_byte) {
538 horizontal_frontporch_byte -= data_phy_cycles_byte *
539 horizontal_frontporch_byte /
540 horizontal_front_back_byte;
541
542 horizontal_backporch_byte -= data_phy_cycles_byte *
543 horizontal_backporch_byte /
544 horizontal_front_back_byte;
545 } else {
546 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
547 }
548
549 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
550 (dsi->lanes == 4)) {
551 horizontal_sync_active_byte =
552 roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
553 horizontal_frontporch_byte =
554 roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
555 horizontal_backporch_byte =
556 roundup(horizontal_backporch_byte, dsi->lanes) - 2;
557 horizontal_backporch_byte -=
558 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
559 }
560
561 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
562 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
563 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
564}
565
566static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
567{
568 struct videomode *vm = &dsi->vm;
569
570 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
571 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
572 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
573 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
574
575 if (dsi->driver_data->has_size_ctl)
576 writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) |
577 FIELD_PREP(DSI_WIDTH, vm->hactive),
578 dsi->regs + DSI_SIZE_CON);
579
580 if (dsi->driver_data->support_per_frame_lp)
581 mtk_dsi_config_vdo_timing_per_frame_lp(dsi);
582 else
583 mtk_dsi_config_vdo_timing_per_line_lp(dsi);
584
585 mtk_dsi_ps_control(dsi, false);
586}
587
588static void mtk_dsi_start(struct mtk_dsi *dsi)
589{
590 writel(0, dsi->regs + DSI_START);
591 writel(1, dsi->regs + DSI_START);
592}
593
594static void mtk_dsi_stop(struct mtk_dsi *dsi)
595{
596 writel(0, dsi->regs + DSI_START);
597}
598
599static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
600{
601 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
602}
603
604static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
605{
606 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
607
608 writel(inten, dsi->regs + DSI_INTEN);
609}
610
611static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
612{
613 dsi->irq_data |= irq_bit;
614}
615
616static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
617{
618 dsi->irq_data &= ~irq_bit;
619}
620
621static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
622 unsigned int timeout)
623{
624 s32 ret = 0;
625 unsigned long jiffies = msecs_to_jiffies(timeout);
626
627 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
628 dsi->irq_data & irq_flag,
629 jiffies);
630 if (ret == 0) {
631 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
632
633 mtk_dsi_enable(dsi);
634 mtk_dsi_reset_engine(dsi);
635 }
636
637 return ret;
638}
639
640static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
641{
642 struct mtk_dsi *dsi = dev_id;
643 u32 status, tmp;
644 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
645
646 status = readl(dsi->regs + DSI_INTSTA) & flag;
647
648 if (status) {
649 do {
650 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
651 tmp = readl(dsi->regs + DSI_INTSTA);
652 } while (tmp & DSI_BUSY);
653
654 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
655 mtk_dsi_irq_data_set(dsi, status);
656 wake_up_interruptible(&dsi->irq_wait_queue);
657 }
658
659 return IRQ_HANDLED;
660}
661
662static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
663{
664 mtk_dsi_irq_data_clear(dsi, irq_flag);
665 mtk_dsi_set_cmd_mode(dsi);
666
667 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
668 DRM_ERROR("failed to switch cmd mode\n");
669 return -ETIME;
670 } else {
671 return 0;
672 }
673}
674
675static int mtk_dsi_poweron(struct mtk_dsi *dsi)
676{
677 struct device *dev = dsi->host.dev;
678 int ret;
679 u32 bit_per_pixel;
680
681 if (++dsi->refcount != 1)
682 return 0;
683
684 ret = mipi_dsi_pixel_format_to_bpp(dsi->format);
685 if (ret < 0) {
686 dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format);
687 return ret;
688 }
689 bit_per_pixel = ret;
690
691 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
692 dsi->lanes);
693
694 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
695 if (ret < 0) {
696 dev_err(dev, "Failed to set data rate: %d\n", ret);
697 goto err_refcount;
698 }
699
700 phy_power_on(dsi->phy);
701
702 ret = clk_prepare_enable(dsi->engine_clk);
703 if (ret < 0) {
704 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
705 goto err_phy_power_off;
706 }
707
708 ret = clk_prepare_enable(dsi->digital_clk);
709 if (ret < 0) {
710 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
711 goto err_disable_engine_clk;
712 }
713
714 mtk_dsi_enable(dsi);
715
716 if (dsi->driver_data->has_shadow_ctl)
717 writel(FORCE_COMMIT | BYPASS_SHADOW,
718 dsi->regs + dsi->driver_data->reg_shadow_dbg_off);
719
720 mtk_dsi_reset_engine(dsi);
721 mtk_dsi_phy_timconfig(dsi);
722
723 mtk_dsi_ps_control(dsi, true);
724 mtk_dsi_set_vm_cmd(dsi);
725 mtk_dsi_config_vdo_timing(dsi);
726 mtk_dsi_set_interrupt_enable(dsi);
727
728 return 0;
729err_disable_engine_clk:
730 clk_disable_unprepare(dsi->engine_clk);
731err_phy_power_off:
732 phy_power_off(dsi->phy);
733err_refcount:
734 dsi->refcount--;
735 return ret;
736}
737
738static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
739{
740 if (WARN_ON(dsi->refcount == 0))
741 return;
742
743 if (--dsi->refcount != 0)
744 return;
745
746 /*
747 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
748 * mtk_dsi_stop() should be called after mtk_crtc_atomic_disable(),
749 * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
750 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
751 * after dsi is fully set.
752 */
753 mtk_dsi_stop(dsi);
754
755 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
756 mtk_dsi_reset_engine(dsi);
757 mtk_dsi_lane0_ulp_mode_enter(dsi);
758 mtk_dsi_clk_ulp_mode_enter(dsi);
759 /* set the lane number as 0 to pull down mipi */
760 writel(0, dsi->regs + DSI_TXRX_CTRL);
761
762 mtk_dsi_disable(dsi);
763
764 clk_disable_unprepare(dsi->engine_clk);
765 clk_disable_unprepare(dsi->digital_clk);
766
767 phy_power_off(dsi->phy);
768
769 dsi->lanes_ready = false;
770}
771
772static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
773{
774 if (!dsi->lanes_ready) {
775 dsi->lanes_ready = true;
776 mtk_dsi_rxtx_control(dsi);
777 usleep_range(30, 100);
778 mtk_dsi_reset_dphy(dsi);
779 mtk_dsi_clk_ulp_mode_leave(dsi);
780 mtk_dsi_lane0_ulp_mode_leave(dsi);
781 mtk_dsi_clk_hs_mode(dsi, 0);
782 usleep_range(1000, 3000);
783 /* The reaction time after pulling up the mipi signal for dsi_rx */
784 }
785}
786
787static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
788{
789 if (dsi->enabled)
790 return;
791
792 mtk_dsi_lane_ready(dsi);
793 mtk_dsi_set_mode(dsi);
794 mtk_dsi_clk_hs_mode(dsi, 1);
795
796 mtk_dsi_start(dsi);
797
798 dsi->enabled = true;
799}
800
801static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
802{
803 if (!dsi->enabled)
804 return;
805
806 dsi->enabled = false;
807}
808
809static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
810 enum drm_bridge_attach_flags flags)
811{
812 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
813
814 /* Attach the panel or bridge to the dsi bridge */
815 return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
816 &dsi->bridge, flags);
817}
818
819static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
820 const struct drm_display_mode *mode,
821 const struct drm_display_mode *adjusted)
822{
823 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
824
825 drm_display_mode_to_videomode(adjusted, &dsi->vm);
826}
827
828static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
829 struct drm_bridge_state *old_bridge_state)
830{
831 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
832
833 mtk_output_dsi_disable(dsi);
834}
835
836static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
837 struct drm_bridge_state *old_bridge_state)
838{
839 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
840
841 if (dsi->refcount == 0)
842 return;
843
844 mtk_output_dsi_enable(dsi);
845}
846
847static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
848 struct drm_bridge_state *old_bridge_state)
849{
850 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
851 int ret;
852
853 ret = mtk_dsi_poweron(dsi);
854 if (ret < 0)
855 DRM_ERROR("failed to power on dsi\n");
856}
857
858static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
859 struct drm_bridge_state *old_bridge_state)
860{
861 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
862
863 mtk_dsi_poweroff(dsi);
864}
865
866static enum drm_mode_status
867mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,
868 const struct drm_display_info *info,
869 const struct drm_display_mode *mode)
870{
871 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
872 int bpp;
873
874 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
875 if (bpp < 0)
876 return MODE_ERROR;
877
878 if (mode->clock * bpp / dsi->lanes > 1500000)
879 return MODE_CLOCK_HIGH;
880
881 return MODE_OK;
882}
883
884static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
885 .attach = mtk_dsi_bridge_attach,
886 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
887 .atomic_disable = mtk_dsi_bridge_atomic_disable,
888 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
889 .atomic_enable = mtk_dsi_bridge_atomic_enable,
890 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
891 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
892 .atomic_reset = drm_atomic_helper_bridge_reset,
893 .mode_valid = mtk_dsi_bridge_mode_valid,
894 .mode_set = mtk_dsi_bridge_mode_set,
895};
896
897void mtk_dsi_ddp_start(struct device *dev)
898{
899 struct mtk_dsi *dsi = dev_get_drvdata(dev);
900
901 mtk_dsi_poweron(dsi);
902}
903
904void mtk_dsi_ddp_stop(struct device *dev)
905{
906 struct mtk_dsi *dsi = dev_get_drvdata(dev);
907
908 mtk_dsi_poweroff(dsi);
909}
910
911static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
912{
913 int ret;
914
915 ret = drm_simple_encoder_init(drm, &dsi->encoder,
916 DRM_MODE_ENCODER_DSI);
917 if (ret) {
918 DRM_ERROR("Failed to encoder init to drm\n");
919 return ret;
920 }
921
922 ret = mtk_find_possible_crtcs(drm, dsi->host.dev);
923 if (ret < 0)
924 goto err_cleanup_encoder;
925 dsi->encoder.possible_crtcs = ret;
926
927 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
928 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
929 if (ret)
930 goto err_cleanup_encoder;
931
932 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
933 if (IS_ERR(dsi->connector)) {
934 DRM_ERROR("Unable to create bridge connector\n");
935 ret = PTR_ERR(dsi->connector);
936 goto err_cleanup_encoder;
937 }
938 drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
939
940 return 0;
941
942err_cleanup_encoder:
943 drm_encoder_cleanup(&dsi->encoder);
944 return ret;
945}
946
947unsigned int mtk_dsi_encoder_index(struct device *dev)
948{
949 struct mtk_dsi *dsi = dev_get_drvdata(dev);
950 unsigned int encoder_index = drm_encoder_index(&dsi->encoder);
951
952 dev_dbg(dev, "encoder index:%d\n", encoder_index);
953 return encoder_index;
954}
955
956static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
957{
958 int ret;
959 struct drm_device *drm = data;
960 struct mtk_dsi *dsi = dev_get_drvdata(dev);
961
962 ret = mtk_dsi_encoder_init(drm, dsi);
963 if (ret)
964 return ret;
965
966 return device_reset_optional(dev);
967}
968
969static void mtk_dsi_unbind(struct device *dev, struct device *master,
970 void *data)
971{
972 struct mtk_dsi *dsi = dev_get_drvdata(dev);
973
974 drm_encoder_cleanup(&dsi->encoder);
975}
976
977static const struct component_ops mtk_dsi_component_ops = {
978 .bind = mtk_dsi_bind,
979 .unbind = mtk_dsi_unbind,
980};
981
982static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
983 struct mipi_dsi_device *device)
984{
985 struct mtk_dsi *dsi = host_to_dsi(host);
986 struct device *dev = host->dev;
987 int ret;
988
989 dsi->lanes = device->lanes;
990 dsi->format = device->format;
991 dsi->mode_flags = device->mode_flags;
992 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
993 if (IS_ERR(dsi->next_bridge)) {
994 ret = PTR_ERR(dsi->next_bridge);
995 if (ret == -EPROBE_DEFER)
996 return ret;
997
998 /* Old devicetree has only one endpoint */
999 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
1000 if (IS_ERR(dsi->next_bridge))
1001 return PTR_ERR(dsi->next_bridge);
1002 }
1003
1004 drm_bridge_add(&dsi->bridge);
1005
1006 ret = component_add(host->dev, &mtk_dsi_component_ops);
1007 if (ret) {
1008 DRM_ERROR("failed to add dsi_host component: %d\n", ret);
1009 drm_bridge_remove(&dsi->bridge);
1010 return ret;
1011 }
1012
1013 return 0;
1014}
1015
1016static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
1017 struct mipi_dsi_device *device)
1018{
1019 struct mtk_dsi *dsi = host_to_dsi(host);
1020
1021 component_del(host->dev, &mtk_dsi_component_ops);
1022 drm_bridge_remove(&dsi->bridge);
1023 return 0;
1024}
1025
1026static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
1027{
1028 int ret;
1029 u32 val;
1030
1031 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
1032 4, 2000000);
1033 if (ret) {
1034 DRM_WARN("polling dsi wait not busy timeout!\n");
1035
1036 mtk_dsi_enable(dsi);
1037 mtk_dsi_reset_engine(dsi);
1038 }
1039}
1040
1041static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
1042{
1043 switch (type) {
1044 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1045 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1046 return 1;
1047 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1048 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1049 return 2;
1050 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1051 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1052 return read_data[1] + read_data[2] * 16;
1053 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1054 DRM_INFO("type is 0x02, try again\n");
1055 break;
1056 default:
1057 DRM_INFO("type(0x%x) not recognized\n", type);
1058 break;
1059 }
1060
1061 return 0;
1062}
1063
1064static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
1065{
1066 const char *tx_buf = msg->tx_buf;
1067 u8 config, cmdq_size, cmdq_off, type = msg->type;
1068 u32 reg_val, cmdq_mask, i;
1069 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
1070
1071 if (MTK_DSI_HOST_IS_READ(type))
1072 config = BTA;
1073 else
1074 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
1075
1076 if (msg->tx_len > 2) {
1077 cmdq_size = 1 + (msg->tx_len + 3) / 4;
1078 cmdq_off = 4;
1079 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
1080 reg_val = (msg->tx_len << 16) | (type << 8) | config;
1081 } else {
1082 cmdq_size = 1;
1083 cmdq_off = 2;
1084 cmdq_mask = CONFIG | DATA_ID;
1085 reg_val = (type << 8) | config;
1086 }
1087
1088 for (i = 0; i < msg->tx_len; i++)
1089 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
1090 (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
1091 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
1092
1093 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
1094 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
1095 if (dsi->driver_data->cmdq_long_packet_ctl) {
1096 /* Disable setting cmdq_size automatically for long packets */
1097 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
1098 }
1099}
1100
1101static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
1102 const struct mipi_dsi_msg *msg, u8 flag)
1103{
1104 mtk_dsi_wait_for_idle(dsi);
1105 mtk_dsi_irq_data_clear(dsi, flag);
1106 mtk_dsi_cmdq(dsi, msg);
1107 mtk_dsi_start(dsi);
1108
1109 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
1110 return -ETIME;
1111 else
1112 return 0;
1113}
1114
1115static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
1116 const struct mipi_dsi_msg *msg)
1117{
1118 struct mtk_dsi *dsi = host_to_dsi(host);
1119 u32 recv_cnt, i;
1120 u8 read_data[16];
1121 void *src_addr;
1122 u8 irq_flag = CMD_DONE_INT_FLAG;
1123 u32 dsi_mode;
1124 int ret;
1125
1126 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);
1127 if (dsi_mode & MODE) {
1128 mtk_dsi_stop(dsi);
1129 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
1130 if (ret)
1131 goto restore_dsi_mode;
1132 }
1133
1134 if (MTK_DSI_HOST_IS_READ(msg->type))
1135 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1136
1137 mtk_dsi_lane_ready(dsi);
1138
1139 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
1140 if (ret)
1141 goto restore_dsi_mode;
1142
1143 if (!MTK_DSI_HOST_IS_READ(msg->type)) {
1144 recv_cnt = 0;
1145 goto restore_dsi_mode;
1146 }
1147
1148 if (!msg->rx_buf) {
1149 DRM_ERROR("dsi receive buffer size may be NULL\n");
1150 ret = -EINVAL;
1151 goto restore_dsi_mode;
1152 }
1153
1154 for (i = 0; i < 16; i++)
1155 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1156
1157 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1158
1159 if (recv_cnt > 2)
1160 src_addr = &read_data[4];
1161 else
1162 src_addr = &read_data[1];
1163
1164 if (recv_cnt > 10)
1165 recv_cnt = 10;
1166
1167 if (recv_cnt > msg->rx_len)
1168 recv_cnt = msg->rx_len;
1169
1170 if (recv_cnt)
1171 memcpy(msg->rx_buf, src_addr, recv_cnt);
1172
1173 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1174 recv_cnt, *((u8 *)(msg->tx_buf)));
1175
1176restore_dsi_mode:
1177 if (dsi_mode & MODE) {
1178 mtk_dsi_set_mode(dsi);
1179 mtk_dsi_start(dsi);
1180 }
1181
1182 return ret < 0 ? ret : recv_cnt;
1183}
1184
1185static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1186 .attach = mtk_dsi_host_attach,
1187 .detach = mtk_dsi_host_detach,
1188 .transfer = mtk_dsi_host_transfer,
1189};
1190
1191static int mtk_dsi_probe(struct platform_device *pdev)
1192{
1193 struct mtk_dsi *dsi;
1194 struct device *dev = &pdev->dev;
1195 struct resource *regs;
1196 int irq_num;
1197 int ret;
1198
1199 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1200 if (!dsi)
1201 return -ENOMEM;
1202
1203 dsi->driver_data = of_device_get_match_data(dev);
1204
1205 dsi->engine_clk = devm_clk_get(dev, "engine");
1206 if (IS_ERR(dsi->engine_clk))
1207 return dev_err_probe(dev, PTR_ERR(dsi->engine_clk),
1208 "Failed to get engine clock\n");
1209
1210
1211 dsi->digital_clk = devm_clk_get(dev, "digital");
1212 if (IS_ERR(dsi->digital_clk))
1213 return dev_err_probe(dev, PTR_ERR(dsi->digital_clk),
1214 "Failed to get digital clock\n");
1215
1216 dsi->hs_clk = devm_clk_get(dev, "hs");
1217 if (IS_ERR(dsi->hs_clk))
1218 return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n");
1219
1220 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1221 dsi->regs = devm_ioremap_resource(dev, regs);
1222 if (IS_ERR(dsi->regs))
1223 return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n");
1224
1225 dsi->phy = devm_phy_get(dev, "dphy");
1226 if (IS_ERR(dsi->phy))
1227 return dev_err_probe(dev, PTR_ERR(dsi->phy), "Failed to get MIPI-DPHY\n");
1228
1229 irq_num = platform_get_irq(pdev, 0);
1230 if (irq_num < 0)
1231 return irq_num;
1232
1233 dsi->host.ops = &mtk_dsi_ops;
1234 dsi->host.dev = dev;
1235 ret = mipi_dsi_host_register(&dsi->host);
1236 if (ret < 0)
1237 return dev_err_probe(dev, ret, "Failed to register DSI host\n");
1238
1239 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1240 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);
1241 if (ret) {
1242 mipi_dsi_host_unregister(&dsi->host);
1243 return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n");
1244 }
1245
1246 init_waitqueue_head(&dsi->irq_wait_queue);
1247
1248 platform_set_drvdata(pdev, dsi);
1249
1250 dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
1251 dsi->bridge.of_node = dev->of_node;
1252 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1253
1254 return 0;
1255}
1256
1257static void mtk_dsi_remove(struct platform_device *pdev)
1258{
1259 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1260
1261 mtk_output_dsi_disable(dsi);
1262 mipi_dsi_host_unregister(&dsi->host);
1263}
1264
1265static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1266 .reg_cmdq_off = 0x200,
1267 .reg_vm_cmd_off = 0x130,
1268 .reg_shadow_dbg_off = 0x190
1269};
1270
1271static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1272 .reg_cmdq_off = 0x180,
1273 .reg_vm_cmd_off = 0x130,
1274 .reg_shadow_dbg_off = 0x190
1275};
1276
1277static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1278 .reg_cmdq_off = 0x200,
1279 .reg_vm_cmd_off = 0x130,
1280 .reg_shadow_dbg_off = 0x190,
1281 .has_shadow_ctl = true,
1282 .has_size_ctl = true,
1283};
1284
1285static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
1286 .reg_cmdq_off = 0xd00,
1287 .reg_vm_cmd_off = 0x200,
1288 .reg_shadow_dbg_off = 0xc00,
1289 .has_shadow_ctl = true,
1290 .has_size_ctl = true,
1291};
1292
1293static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
1294 .reg_cmdq_off = 0xd00,
1295 .reg_vm_cmd_off = 0x200,
1296 .reg_shadow_dbg_off = 0xc00,
1297 .has_shadow_ctl = true,
1298 .has_size_ctl = true,
1299 .cmdq_long_packet_ctl = true,
1300 .support_per_frame_lp = true,
1301};
1302
1303static const struct of_device_id mtk_dsi_of_match[] = {
1304 { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data },
1305 { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data },
1306 { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data },
1307 { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data },
1308 { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data },
1309 { /* sentinel */ }
1310};
1311MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
1312
1313struct platform_driver mtk_dsi_driver = {
1314 .probe = mtk_dsi_probe,
1315 .remove = mtk_dsi_remove,
1316 .driver = {
1317 .name = "mtk-dsi",
1318 .of_match_table = mtk_dsi_of_match,
1319 },
1320};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/component.h>
8#include <linux/iopoll.h>
9#include <linux/irq.h>
10#include <linux/of.h>
11#include <linux/of_platform.h>
12#include <linux/phy/phy.h>
13#include <linux/platform_device.h>
14#include <linux/reset.h>
15
16#include <video/mipi_display.h>
17#include <video/videomode.h>
18
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_bridge.h>
21#include <drm/drm_bridge_connector.h>
22#include <drm/drm_mipi_dsi.h>
23#include <drm/drm_of.h>
24#include <drm/drm_panel.h>
25#include <drm/drm_print.h>
26#include <drm/drm_probe_helper.h>
27#include <drm/drm_simple_kms_helper.h>
28
29#include "mtk_disp_drv.h"
30#include "mtk_drm_ddp_comp.h"
31#include "mtk_drm_drv.h"
32
33#define DSI_START 0x00
34
35#define DSI_INTEN 0x08
36
37#define DSI_INTSTA 0x0c
38#define LPRX_RD_RDY_INT_FLAG BIT(0)
39#define CMD_DONE_INT_FLAG BIT(1)
40#define TE_RDY_INT_FLAG BIT(2)
41#define VM_DONE_INT_FLAG BIT(3)
42#define EXT_TE_RDY_INT_FLAG BIT(4)
43#define DSI_BUSY BIT(31)
44
45#define DSI_CON_CTRL 0x10
46#define DSI_RESET BIT(0)
47#define DSI_EN BIT(1)
48#define DPHY_RESET BIT(2)
49
50#define DSI_MODE_CTRL 0x14
51#define MODE (3)
52#define CMD_MODE 0
53#define SYNC_PULSE_MODE 1
54#define SYNC_EVENT_MODE 2
55#define BURST_MODE 3
56#define FRM_MODE BIT(16)
57#define MIX_MODE BIT(17)
58
59#define DSI_TXRX_CTRL 0x18
60#define VC_NUM BIT(1)
61#define LANE_NUM (0xf << 2)
62#define DIS_EOT BIT(6)
63#define NULL_EN BIT(7)
64#define TE_FREERUN BIT(8)
65#define EXT_TE_EN BIT(9)
66#define EXT_TE_EDGE BIT(10)
67#define MAX_RTN_SIZE (0xf << 12)
68#define HSTX_CKLP_EN BIT(16)
69
70#define DSI_PSCTRL 0x1c
71#define DSI_PS_WC 0x3fff
72#define DSI_PS_SEL (3 << 16)
73#define PACKED_PS_16BIT_RGB565 (0 << 16)
74#define LOOSELY_PS_18BIT_RGB666 (1 << 16)
75#define PACKED_PS_18BIT_RGB666 (2 << 16)
76#define PACKED_PS_24BIT_RGB888 (3 << 16)
77
78#define DSI_VSA_NL 0x20
79#define DSI_VBP_NL 0x24
80#define DSI_VFP_NL 0x28
81#define DSI_VACT_NL 0x2C
82#define DSI_SIZE_CON 0x38
83#define DSI_HSA_WC 0x50
84#define DSI_HBP_WC 0x54
85#define DSI_HFP_WC 0x58
86
87#define DSI_CMDQ_SIZE 0x60
88#define CMDQ_SIZE 0x3f
89#define CMDQ_SIZE_SEL BIT(15)
90
91#define DSI_HSTX_CKL_WC 0x64
92
93#define DSI_RX_DATA0 0x74
94#define DSI_RX_DATA1 0x78
95#define DSI_RX_DATA2 0x7c
96#define DSI_RX_DATA3 0x80
97
98#define DSI_RACK 0x84
99#define RACK BIT(0)
100
101#define DSI_PHY_LCCON 0x104
102#define LC_HS_TX_EN BIT(0)
103#define LC_ULPM_EN BIT(1)
104#define LC_WAKEUP_EN BIT(2)
105
106#define DSI_PHY_LD0CON 0x108
107#define LD0_HS_TX_EN BIT(0)
108#define LD0_ULPM_EN BIT(1)
109#define LD0_WAKEUP_EN BIT(2)
110
111#define DSI_PHY_TIMECON0 0x110
112#define LPX (0xff << 0)
113#define HS_PREP (0xff << 8)
114#define HS_ZERO (0xff << 16)
115#define HS_TRAIL (0xff << 24)
116
117#define DSI_PHY_TIMECON1 0x114
118#define TA_GO (0xff << 0)
119#define TA_SURE (0xff << 8)
120#define TA_GET (0xff << 16)
121#define DA_HS_EXIT (0xff << 24)
122
123#define DSI_PHY_TIMECON2 0x118
124#define CONT_DET (0xff << 0)
125#define CLK_ZERO (0xff << 16)
126#define CLK_TRAIL (0xff << 24)
127
128#define DSI_PHY_TIMECON3 0x11c
129#define CLK_HS_PREP (0xff << 0)
130#define CLK_HS_POST (0xff << 8)
131#define CLK_HS_EXIT (0xff << 16)
132
133#define DSI_VM_CMD_CON 0x130
134#define VM_CMD_EN BIT(0)
135#define TS_VFP_EN BIT(5)
136
137#define DSI_SHADOW_DEBUG 0x190U
138#define FORCE_COMMIT BIT(0)
139#define BYPASS_SHADOW BIT(1)
140
141#define CONFIG (0xff << 0)
142#define SHORT_PACKET 0
143#define LONG_PACKET 2
144#define BTA BIT(2)
145#define DATA_ID (0xff << 8)
146#define DATA_0 (0xff << 16)
147#define DATA_1 (0xff << 24)
148
149#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
150
151#define MTK_DSI_HOST_IS_READ(type) \
152 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
153 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
154 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
155 (type == MIPI_DSI_DCS_READ))
156
157struct mtk_phy_timing {
158 u32 lpx;
159 u32 da_hs_prepare;
160 u32 da_hs_zero;
161 u32 da_hs_trail;
162
163 u32 ta_go;
164 u32 ta_sure;
165 u32 ta_get;
166 u32 da_hs_exit;
167
168 u32 clk_hs_zero;
169 u32 clk_hs_trail;
170
171 u32 clk_hs_prepare;
172 u32 clk_hs_post;
173 u32 clk_hs_exit;
174};
175
176struct phy;
177
178struct mtk_dsi_driver_data {
179 const u32 reg_cmdq_off;
180 bool has_shadow_ctl;
181 bool has_size_ctl;
182 bool cmdq_long_packet_ctl;
183};
184
185struct mtk_dsi {
186 struct device *dev;
187 struct mipi_dsi_host host;
188 struct drm_encoder encoder;
189 struct drm_bridge bridge;
190 struct drm_bridge *next_bridge;
191 struct drm_connector *connector;
192 struct phy *phy;
193
194 void __iomem *regs;
195
196 struct clk *engine_clk;
197 struct clk *digital_clk;
198 struct clk *hs_clk;
199
200 u32 data_rate;
201
202 unsigned long mode_flags;
203 enum mipi_dsi_pixel_format format;
204 unsigned int lanes;
205 struct videomode vm;
206 struct mtk_phy_timing phy_timing;
207 int refcount;
208 bool enabled;
209 bool lanes_ready;
210 u32 irq_data;
211 wait_queue_head_t irq_wait_queue;
212 const struct mtk_dsi_driver_data *driver_data;
213};
214
215static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)
216{
217 return container_of(b, struct mtk_dsi, bridge);
218}
219
220static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
221{
222 return container_of(h, struct mtk_dsi, host);
223}
224
225static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
226{
227 u32 temp = readl(dsi->regs + offset);
228
229 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
230}
231
232static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
233{
234 u32 timcon0, timcon1, timcon2, timcon3;
235 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
236 struct mtk_phy_timing *timing = &dsi->phy_timing;
237
238 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
239 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
240 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
241 timing->da_hs_prepare;
242 timing->da_hs_trail = timing->da_hs_prepare + 1;
243
244 timing->ta_go = 4 * timing->lpx - 2;
245 timing->ta_sure = timing->lpx + 2;
246 timing->ta_get = 4 * timing->lpx;
247 timing->da_hs_exit = 2 * timing->lpx + 1;
248
249 timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
250 timing->clk_hs_post = timing->clk_hs_prepare + 8;
251 timing->clk_hs_trail = timing->clk_hs_prepare;
252 timing->clk_hs_zero = timing->clk_hs_trail * 4;
253 timing->clk_hs_exit = 2 * timing->clk_hs_trail;
254
255 timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
256 timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
257 timcon1 = timing->ta_go | timing->ta_sure << 8 |
258 timing->ta_get << 16 | timing->da_hs_exit << 24;
259 timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
260 timing->clk_hs_trail << 24;
261 timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
262 timing->clk_hs_exit << 16;
263
264 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
265 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
266 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
267 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
268}
269
270static void mtk_dsi_enable(struct mtk_dsi *dsi)
271{
272 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
273}
274
275static void mtk_dsi_disable(struct mtk_dsi *dsi)
276{
277 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
278}
279
280static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
281{
282 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
283 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
284}
285
286static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
287{
288 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
289 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
290}
291
292static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
293{
294 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
295 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
296}
297
298static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
299{
300 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
301 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
302 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
303}
304
305static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
306{
307 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
308 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
309}
310
311static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
312{
313 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
314 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
315 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
316}
317
318static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
319{
320 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
321}
322
323static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
324{
325 if (enter && !mtk_dsi_clk_hs_state(dsi))
326 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
327 else if (!enter && mtk_dsi_clk_hs_state(dsi))
328 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
329}
330
331static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
332{
333 u32 vid_mode = CMD_MODE;
334
335 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
336 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
337 vid_mode = BURST_MODE;
338 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
339 vid_mode = SYNC_PULSE_MODE;
340 else
341 vid_mode = SYNC_EVENT_MODE;
342 }
343
344 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
345}
346
347static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
348{
349 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
350 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
351}
352
353static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
354{
355 struct videomode *vm = &dsi->vm;
356 u32 dsi_buf_bpp, ps_wc;
357 u32 ps_bpp_mode;
358
359 if (dsi->format == MIPI_DSI_FMT_RGB565)
360 dsi_buf_bpp = 2;
361 else
362 dsi_buf_bpp = 3;
363
364 ps_wc = vm->hactive * dsi_buf_bpp;
365 ps_bpp_mode = ps_wc;
366
367 switch (dsi->format) {
368 case MIPI_DSI_FMT_RGB888:
369 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
370 break;
371 case MIPI_DSI_FMT_RGB666:
372 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
373 break;
374 case MIPI_DSI_FMT_RGB666_PACKED:
375 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
376 break;
377 case MIPI_DSI_FMT_RGB565:
378 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
379 break;
380 }
381
382 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
383 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
384 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
385}
386
387static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
388{
389 u32 tmp_reg;
390
391 switch (dsi->lanes) {
392 case 1:
393 tmp_reg = 1 << 2;
394 break;
395 case 2:
396 tmp_reg = 3 << 2;
397 break;
398 case 3:
399 tmp_reg = 7 << 2;
400 break;
401 case 4:
402 tmp_reg = 0xf << 2;
403 break;
404 default:
405 tmp_reg = 0xf << 2;
406 break;
407 }
408
409 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
410 tmp_reg |= HSTX_CKLP_EN;
411
412 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
413 tmp_reg |= DIS_EOT;
414
415 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
416}
417
418static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
419{
420 u32 dsi_tmp_buf_bpp;
421 u32 tmp_reg;
422
423 switch (dsi->format) {
424 case MIPI_DSI_FMT_RGB888:
425 tmp_reg = PACKED_PS_24BIT_RGB888;
426 dsi_tmp_buf_bpp = 3;
427 break;
428 case MIPI_DSI_FMT_RGB666:
429 tmp_reg = LOOSELY_PS_18BIT_RGB666;
430 dsi_tmp_buf_bpp = 3;
431 break;
432 case MIPI_DSI_FMT_RGB666_PACKED:
433 tmp_reg = PACKED_PS_18BIT_RGB666;
434 dsi_tmp_buf_bpp = 3;
435 break;
436 case MIPI_DSI_FMT_RGB565:
437 tmp_reg = PACKED_PS_16BIT_RGB565;
438 dsi_tmp_buf_bpp = 2;
439 break;
440 default:
441 tmp_reg = PACKED_PS_24BIT_RGB888;
442 dsi_tmp_buf_bpp = 3;
443 break;
444 }
445
446 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
447 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
448}
449
450static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
451{
452 u32 horizontal_sync_active_byte;
453 u32 horizontal_backporch_byte;
454 u32 horizontal_frontporch_byte;
455 u32 horizontal_front_back_byte;
456 u32 data_phy_cycles_byte;
457 u32 dsi_tmp_buf_bpp, data_phy_cycles;
458 u32 delta;
459 struct mtk_phy_timing *timing = &dsi->phy_timing;
460
461 struct videomode *vm = &dsi->vm;
462
463 if (dsi->format == MIPI_DSI_FMT_RGB565)
464 dsi_tmp_buf_bpp = 2;
465 else
466 dsi_tmp_buf_bpp = 3;
467
468 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
469 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
470 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
471 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
472
473 if (dsi->driver_data->has_size_ctl)
474 writel(vm->vactive << 16 | vm->hactive,
475 dsi->regs + DSI_SIZE_CON);
476
477 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
478
479 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
480 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10;
481 else
482 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
483 dsi_tmp_buf_bpp - 10;
484
485 data_phy_cycles = timing->lpx + timing->da_hs_prepare +
486 timing->da_hs_zero + timing->da_hs_exit + 3;
487
488 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
489 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2;
490
491 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
492 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte;
493 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
494
495 if (horizontal_front_back_byte > data_phy_cycles_byte) {
496 horizontal_frontporch_byte -= data_phy_cycles_byte *
497 horizontal_frontporch_byte /
498 horizontal_front_back_byte;
499
500 horizontal_backporch_byte -= data_phy_cycles_byte *
501 horizontal_backporch_byte /
502 horizontal_front_back_byte;
503 } else {
504 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
505 }
506
507 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
508 (dsi->lanes == 4)) {
509 horizontal_sync_active_byte =
510 roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
511 horizontal_frontporch_byte =
512 roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
513 horizontal_backporch_byte =
514 roundup(horizontal_backporch_byte, dsi->lanes) - 2;
515 horizontal_backporch_byte -=
516 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
517 }
518
519 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
520 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
521 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
522
523 mtk_dsi_ps_control(dsi);
524}
525
526static void mtk_dsi_start(struct mtk_dsi *dsi)
527{
528 writel(0, dsi->regs + DSI_START);
529 writel(1, dsi->regs + DSI_START);
530}
531
532static void mtk_dsi_stop(struct mtk_dsi *dsi)
533{
534 writel(0, dsi->regs + DSI_START);
535}
536
537static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
538{
539 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
540}
541
542static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
543{
544 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
545
546 writel(inten, dsi->regs + DSI_INTEN);
547}
548
549static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
550{
551 dsi->irq_data |= irq_bit;
552}
553
554static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
555{
556 dsi->irq_data &= ~irq_bit;
557}
558
559static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
560 unsigned int timeout)
561{
562 s32 ret = 0;
563 unsigned long jiffies = msecs_to_jiffies(timeout);
564
565 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
566 dsi->irq_data & irq_flag,
567 jiffies);
568 if (ret == 0) {
569 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
570
571 mtk_dsi_enable(dsi);
572 mtk_dsi_reset_engine(dsi);
573 }
574
575 return ret;
576}
577
578static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
579{
580 struct mtk_dsi *dsi = dev_id;
581 u32 status, tmp;
582 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
583
584 status = readl(dsi->regs + DSI_INTSTA) & flag;
585
586 if (status) {
587 do {
588 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
589 tmp = readl(dsi->regs + DSI_INTSTA);
590 } while (tmp & DSI_BUSY);
591
592 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
593 mtk_dsi_irq_data_set(dsi, status);
594 wake_up_interruptible(&dsi->irq_wait_queue);
595 }
596
597 return IRQ_HANDLED;
598}
599
600static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
601{
602 mtk_dsi_irq_data_clear(dsi, irq_flag);
603 mtk_dsi_set_cmd_mode(dsi);
604
605 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
606 DRM_ERROR("failed to switch cmd mode\n");
607 return -ETIME;
608 } else {
609 return 0;
610 }
611}
612
613static int mtk_dsi_poweron(struct mtk_dsi *dsi)
614{
615 struct device *dev = dsi->host.dev;
616 int ret;
617 u32 bit_per_pixel;
618
619 if (++dsi->refcount != 1)
620 return 0;
621
622 switch (dsi->format) {
623 case MIPI_DSI_FMT_RGB565:
624 bit_per_pixel = 16;
625 break;
626 case MIPI_DSI_FMT_RGB666_PACKED:
627 bit_per_pixel = 18;
628 break;
629 case MIPI_DSI_FMT_RGB666:
630 case MIPI_DSI_FMT_RGB888:
631 default:
632 bit_per_pixel = 24;
633 break;
634 }
635
636 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
637 dsi->lanes);
638
639 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
640 if (ret < 0) {
641 dev_err(dev, "Failed to set data rate: %d\n", ret);
642 goto err_refcount;
643 }
644
645 phy_power_on(dsi->phy);
646
647 ret = clk_prepare_enable(dsi->engine_clk);
648 if (ret < 0) {
649 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
650 goto err_phy_power_off;
651 }
652
653 ret = clk_prepare_enable(dsi->digital_clk);
654 if (ret < 0) {
655 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
656 goto err_disable_engine_clk;
657 }
658
659 mtk_dsi_enable(dsi);
660
661 if (dsi->driver_data->has_shadow_ctl)
662 writel(FORCE_COMMIT | BYPASS_SHADOW,
663 dsi->regs + DSI_SHADOW_DEBUG);
664
665 mtk_dsi_reset_engine(dsi);
666 mtk_dsi_phy_timconfig(dsi);
667
668 mtk_dsi_ps_control_vact(dsi);
669 mtk_dsi_set_vm_cmd(dsi);
670 mtk_dsi_config_vdo_timing(dsi);
671 mtk_dsi_set_interrupt_enable(dsi);
672
673 return 0;
674err_disable_engine_clk:
675 clk_disable_unprepare(dsi->engine_clk);
676err_phy_power_off:
677 phy_power_off(dsi->phy);
678err_refcount:
679 dsi->refcount--;
680 return ret;
681}
682
683static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
684{
685 if (WARN_ON(dsi->refcount == 0))
686 return;
687
688 if (--dsi->refcount != 0)
689 return;
690
691 /*
692 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
693 * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
694 * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
695 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
696 * after dsi is fully set.
697 */
698 mtk_dsi_stop(dsi);
699
700 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
701 mtk_dsi_reset_engine(dsi);
702 mtk_dsi_lane0_ulp_mode_enter(dsi);
703 mtk_dsi_clk_ulp_mode_enter(dsi);
704 /* set the lane number as 0 to pull down mipi */
705 writel(0, dsi->regs + DSI_TXRX_CTRL);
706
707 mtk_dsi_disable(dsi);
708
709 clk_disable_unprepare(dsi->engine_clk);
710 clk_disable_unprepare(dsi->digital_clk);
711
712 phy_power_off(dsi->phy);
713
714 dsi->lanes_ready = false;
715}
716
717static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
718{
719 if (!dsi->lanes_ready) {
720 dsi->lanes_ready = true;
721 mtk_dsi_rxtx_control(dsi);
722 usleep_range(30, 100);
723 mtk_dsi_reset_dphy(dsi);
724 mtk_dsi_clk_ulp_mode_leave(dsi);
725 mtk_dsi_lane0_ulp_mode_leave(dsi);
726 mtk_dsi_clk_hs_mode(dsi, 0);
727 usleep_range(1000, 3000);
728 /* The reaction time after pulling up the mipi signal for dsi_rx */
729 }
730}
731
732static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
733{
734 if (dsi->enabled)
735 return;
736
737 mtk_dsi_lane_ready(dsi);
738 mtk_dsi_set_mode(dsi);
739 mtk_dsi_clk_hs_mode(dsi, 1);
740
741 mtk_dsi_start(dsi);
742
743 dsi->enabled = true;
744}
745
746static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
747{
748 if (!dsi->enabled)
749 return;
750
751 dsi->enabled = false;
752}
753
754static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
755 enum drm_bridge_attach_flags flags)
756{
757 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
758
759 /* Attach the panel or bridge to the dsi bridge */
760 return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
761 &dsi->bridge, flags);
762}
763
764static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
765 const struct drm_display_mode *mode,
766 const struct drm_display_mode *adjusted)
767{
768 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
769
770 drm_display_mode_to_videomode(adjusted, &dsi->vm);
771}
772
773static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
774 struct drm_bridge_state *old_bridge_state)
775{
776 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
777
778 mtk_output_dsi_disable(dsi);
779}
780
781static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
782 struct drm_bridge_state *old_bridge_state)
783{
784 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
785
786 if (dsi->refcount == 0)
787 return;
788
789 mtk_output_dsi_enable(dsi);
790}
791
792static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
793 struct drm_bridge_state *old_bridge_state)
794{
795 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
796 int ret;
797
798 ret = mtk_dsi_poweron(dsi);
799 if (ret < 0)
800 DRM_ERROR("failed to power on dsi\n");
801}
802
803static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
804 struct drm_bridge_state *old_bridge_state)
805{
806 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
807
808 mtk_dsi_poweroff(dsi);
809}
810
811static enum drm_mode_status
812mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,
813 const struct drm_display_info *info,
814 const struct drm_display_mode *mode)
815{
816 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
817 u32 bpp;
818
819 if (dsi->format == MIPI_DSI_FMT_RGB565)
820 bpp = 16;
821 else
822 bpp = 24;
823
824 if (mode->clock * bpp / dsi->lanes > 1500000)
825 return MODE_CLOCK_HIGH;
826
827 return MODE_OK;
828}
829
830static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
831 .attach = mtk_dsi_bridge_attach,
832 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
833 .atomic_disable = mtk_dsi_bridge_atomic_disable,
834 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
835 .atomic_enable = mtk_dsi_bridge_atomic_enable,
836 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
837 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
838 .atomic_reset = drm_atomic_helper_bridge_reset,
839 .mode_valid = mtk_dsi_bridge_mode_valid,
840 .mode_set = mtk_dsi_bridge_mode_set,
841};
842
843void mtk_dsi_ddp_start(struct device *dev)
844{
845 struct mtk_dsi *dsi = dev_get_drvdata(dev);
846
847 mtk_dsi_poweron(dsi);
848}
849
850void mtk_dsi_ddp_stop(struct device *dev)
851{
852 struct mtk_dsi *dsi = dev_get_drvdata(dev);
853
854 mtk_dsi_poweroff(dsi);
855}
856
857static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
858{
859 int ret;
860
861 ret = drm_simple_encoder_init(drm, &dsi->encoder,
862 DRM_MODE_ENCODER_DSI);
863 if (ret) {
864 DRM_ERROR("Failed to encoder init to drm\n");
865 return ret;
866 }
867
868 dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev);
869
870 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
871 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
872 if (ret)
873 goto err_cleanup_encoder;
874
875 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
876 if (IS_ERR(dsi->connector)) {
877 DRM_ERROR("Unable to create bridge connector\n");
878 ret = PTR_ERR(dsi->connector);
879 goto err_cleanup_encoder;
880 }
881 drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
882
883 return 0;
884
885err_cleanup_encoder:
886 drm_encoder_cleanup(&dsi->encoder);
887 return ret;
888}
889
890unsigned int mtk_dsi_encoder_index(struct device *dev)
891{
892 struct mtk_dsi *dsi = dev_get_drvdata(dev);
893 unsigned int encoder_index = drm_encoder_index(&dsi->encoder);
894
895 dev_dbg(dev, "encoder index:%d\n", encoder_index);
896 return encoder_index;
897}
898
899static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
900{
901 int ret;
902 struct drm_device *drm = data;
903 struct mtk_dsi *dsi = dev_get_drvdata(dev);
904
905 ret = mtk_dsi_encoder_init(drm, dsi);
906 if (ret)
907 return ret;
908
909 return device_reset_optional(dev);
910}
911
912static void mtk_dsi_unbind(struct device *dev, struct device *master,
913 void *data)
914{
915 struct mtk_dsi *dsi = dev_get_drvdata(dev);
916
917 drm_encoder_cleanup(&dsi->encoder);
918}
919
920static const struct component_ops mtk_dsi_component_ops = {
921 .bind = mtk_dsi_bind,
922 .unbind = mtk_dsi_unbind,
923};
924
925static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
926 struct mipi_dsi_device *device)
927{
928 struct mtk_dsi *dsi = host_to_dsi(host);
929 struct device *dev = host->dev;
930 int ret;
931
932 dsi->lanes = device->lanes;
933 dsi->format = device->format;
934 dsi->mode_flags = device->mode_flags;
935 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
936 if (IS_ERR(dsi->next_bridge))
937 return PTR_ERR(dsi->next_bridge);
938
939 drm_bridge_add(&dsi->bridge);
940
941 ret = component_add(host->dev, &mtk_dsi_component_ops);
942 if (ret) {
943 DRM_ERROR("failed to add dsi_host component: %d\n", ret);
944 drm_bridge_remove(&dsi->bridge);
945 return ret;
946 }
947
948 return 0;
949}
950
951static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
952 struct mipi_dsi_device *device)
953{
954 struct mtk_dsi *dsi = host_to_dsi(host);
955
956 component_del(host->dev, &mtk_dsi_component_ops);
957 drm_bridge_remove(&dsi->bridge);
958 return 0;
959}
960
961static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
962{
963 int ret;
964 u32 val;
965
966 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
967 4, 2000000);
968 if (ret) {
969 DRM_WARN("polling dsi wait not busy timeout!\n");
970
971 mtk_dsi_enable(dsi);
972 mtk_dsi_reset_engine(dsi);
973 }
974}
975
976static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
977{
978 switch (type) {
979 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
980 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
981 return 1;
982 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
983 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
984 return 2;
985 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
986 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
987 return read_data[1] + read_data[2] * 16;
988 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
989 DRM_INFO("type is 0x02, try again\n");
990 break;
991 default:
992 DRM_INFO("type(0x%x) not recognized\n", type);
993 break;
994 }
995
996 return 0;
997}
998
999static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
1000{
1001 const char *tx_buf = msg->tx_buf;
1002 u8 config, cmdq_size, cmdq_off, type = msg->type;
1003 u32 reg_val, cmdq_mask, i;
1004 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
1005
1006 if (MTK_DSI_HOST_IS_READ(type))
1007 config = BTA;
1008 else
1009 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
1010
1011 if (msg->tx_len > 2) {
1012 cmdq_size = 1 + (msg->tx_len + 3) / 4;
1013 cmdq_off = 4;
1014 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
1015 reg_val = (msg->tx_len << 16) | (type << 8) | config;
1016 } else {
1017 cmdq_size = 1;
1018 cmdq_off = 2;
1019 cmdq_mask = CONFIG | DATA_ID;
1020 reg_val = (type << 8) | config;
1021 }
1022
1023 for (i = 0; i < msg->tx_len; i++)
1024 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
1025 (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
1026 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
1027
1028 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
1029 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
1030 if (dsi->driver_data->cmdq_long_packet_ctl) {
1031 /* Disable setting cmdq_size automatically for long packets */
1032 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
1033 }
1034}
1035
1036static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
1037 const struct mipi_dsi_msg *msg, u8 flag)
1038{
1039 mtk_dsi_wait_for_idle(dsi);
1040 mtk_dsi_irq_data_clear(dsi, flag);
1041 mtk_dsi_cmdq(dsi, msg);
1042 mtk_dsi_start(dsi);
1043
1044 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
1045 return -ETIME;
1046 else
1047 return 0;
1048}
1049
1050static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
1051 const struct mipi_dsi_msg *msg)
1052{
1053 struct mtk_dsi *dsi = host_to_dsi(host);
1054 u32 recv_cnt, i;
1055 u8 read_data[16];
1056 void *src_addr;
1057 u8 irq_flag = CMD_DONE_INT_FLAG;
1058 u32 dsi_mode;
1059 int ret;
1060
1061 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);
1062 if (dsi_mode & MODE) {
1063 mtk_dsi_stop(dsi);
1064 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
1065 if (ret)
1066 goto restore_dsi_mode;
1067 }
1068
1069 if (MTK_DSI_HOST_IS_READ(msg->type))
1070 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1071
1072 mtk_dsi_lane_ready(dsi);
1073
1074 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
1075 if (ret)
1076 goto restore_dsi_mode;
1077
1078 if (!MTK_DSI_HOST_IS_READ(msg->type)) {
1079 recv_cnt = 0;
1080 goto restore_dsi_mode;
1081 }
1082
1083 if (!msg->rx_buf) {
1084 DRM_ERROR("dsi receive buffer size may be NULL\n");
1085 ret = -EINVAL;
1086 goto restore_dsi_mode;
1087 }
1088
1089 for (i = 0; i < 16; i++)
1090 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1091
1092 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1093
1094 if (recv_cnt > 2)
1095 src_addr = &read_data[4];
1096 else
1097 src_addr = &read_data[1];
1098
1099 if (recv_cnt > 10)
1100 recv_cnt = 10;
1101
1102 if (recv_cnt > msg->rx_len)
1103 recv_cnt = msg->rx_len;
1104
1105 if (recv_cnt)
1106 memcpy(msg->rx_buf, src_addr, recv_cnt);
1107
1108 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1109 recv_cnt, *((u8 *)(msg->tx_buf)));
1110
1111restore_dsi_mode:
1112 if (dsi_mode & MODE) {
1113 mtk_dsi_set_mode(dsi);
1114 mtk_dsi_start(dsi);
1115 }
1116
1117 return ret < 0 ? ret : recv_cnt;
1118}
1119
1120static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1121 .attach = mtk_dsi_host_attach,
1122 .detach = mtk_dsi_host_detach,
1123 .transfer = mtk_dsi_host_transfer,
1124};
1125
1126static int mtk_dsi_probe(struct platform_device *pdev)
1127{
1128 struct mtk_dsi *dsi;
1129 struct device *dev = &pdev->dev;
1130 struct resource *regs;
1131 int irq_num;
1132 int ret;
1133
1134 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1135 if (!dsi)
1136 return -ENOMEM;
1137
1138 dsi->host.ops = &mtk_dsi_ops;
1139 dsi->host.dev = dev;
1140 ret = mipi_dsi_host_register(&dsi->host);
1141 if (ret < 0) {
1142 dev_err(dev, "failed to register DSI host: %d\n", ret);
1143 return ret;
1144 }
1145
1146 dsi->driver_data = of_device_get_match_data(dev);
1147
1148 dsi->engine_clk = devm_clk_get(dev, "engine");
1149 if (IS_ERR(dsi->engine_clk)) {
1150 ret = PTR_ERR(dsi->engine_clk);
1151
1152 if (ret != -EPROBE_DEFER)
1153 dev_err(dev, "Failed to get engine clock: %d\n", ret);
1154 goto err_unregister_host;
1155 }
1156
1157 dsi->digital_clk = devm_clk_get(dev, "digital");
1158 if (IS_ERR(dsi->digital_clk)) {
1159 ret = PTR_ERR(dsi->digital_clk);
1160
1161 if (ret != -EPROBE_DEFER)
1162 dev_err(dev, "Failed to get digital clock: %d\n", ret);
1163 goto err_unregister_host;
1164 }
1165
1166 dsi->hs_clk = devm_clk_get(dev, "hs");
1167 if (IS_ERR(dsi->hs_clk)) {
1168 ret = PTR_ERR(dsi->hs_clk);
1169 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1170 goto err_unregister_host;
1171 }
1172
1173 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1174 dsi->regs = devm_ioremap_resource(dev, regs);
1175 if (IS_ERR(dsi->regs)) {
1176 ret = PTR_ERR(dsi->regs);
1177 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1178 goto err_unregister_host;
1179 }
1180
1181 dsi->phy = devm_phy_get(dev, "dphy");
1182 if (IS_ERR(dsi->phy)) {
1183 ret = PTR_ERR(dsi->phy);
1184 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1185 goto err_unregister_host;
1186 }
1187
1188 irq_num = platform_get_irq(pdev, 0);
1189 if (irq_num < 0) {
1190 ret = irq_num;
1191 goto err_unregister_host;
1192 }
1193
1194 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1195 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);
1196 if (ret) {
1197 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1198 goto err_unregister_host;
1199 }
1200
1201 init_waitqueue_head(&dsi->irq_wait_queue);
1202
1203 platform_set_drvdata(pdev, dsi);
1204
1205 dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
1206 dsi->bridge.of_node = dev->of_node;
1207 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1208
1209 return 0;
1210
1211err_unregister_host:
1212 mipi_dsi_host_unregister(&dsi->host);
1213 return ret;
1214}
1215
1216static void mtk_dsi_remove(struct platform_device *pdev)
1217{
1218 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1219
1220 mtk_output_dsi_disable(dsi);
1221 mipi_dsi_host_unregister(&dsi->host);
1222}
1223
1224static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1225 .reg_cmdq_off = 0x200,
1226};
1227
1228static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1229 .reg_cmdq_off = 0x180,
1230};
1231
1232static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1233 .reg_cmdq_off = 0x200,
1234 .has_shadow_ctl = true,
1235 .has_size_ctl = true,
1236};
1237
1238static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
1239 .reg_cmdq_off = 0xd00,
1240 .has_shadow_ctl = true,
1241 .has_size_ctl = true,
1242};
1243
1244static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
1245 .reg_cmdq_off = 0xd00,
1246 .has_shadow_ctl = true,
1247 .has_size_ctl = true,
1248 .cmdq_long_packet_ctl = true,
1249};
1250
1251static const struct of_device_id mtk_dsi_of_match[] = {
1252 { .compatible = "mediatek,mt2701-dsi",
1253 .data = &mt2701_dsi_driver_data },
1254 { .compatible = "mediatek,mt8173-dsi",
1255 .data = &mt8173_dsi_driver_data },
1256 { .compatible = "mediatek,mt8183-dsi",
1257 .data = &mt8183_dsi_driver_data },
1258 { .compatible = "mediatek,mt8186-dsi",
1259 .data = &mt8186_dsi_driver_data },
1260 { .compatible = "mediatek,mt8188-dsi",
1261 .data = &mt8188_dsi_driver_data },
1262 { },
1263};
1264MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
1265
1266struct platform_driver mtk_dsi_driver = {
1267 .probe = mtk_dsi_probe,
1268 .remove_new = mtk_dsi_remove,
1269 .driver = {
1270 .name = "mtk-dsi",
1271 .of_match_table = mtk_dsi_of_match,
1272 },
1273};