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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "i915_reg.h"
8#include "intel_de.h"
9#include "intel_display_irq.h"
10#include "intel_display_types.h"
11#include "intel_dp_aux.h"
12#include "intel_gmbus.h"
13#include "intel_hotplug.h"
14#include "intel_hotplug_irq.h"
15
16typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
17typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder);
18typedef u32 (*hotplug_mask_func)(enum hpd_pin pin);
19
20static const u32 hpd_ilk[HPD_NUM_PINS] = {
21 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
22};
23
24static const u32 hpd_ivb[HPD_NUM_PINS] = {
25 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
26};
27
28static const u32 hpd_bdw[HPD_NUM_PINS] = {
29 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
30};
31
32static const u32 hpd_ibx[HPD_NUM_PINS] = {
33 [HPD_CRT] = SDE_CRT_HOTPLUG,
34 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
35 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
36 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
37 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
38};
39
40static const u32 hpd_cpt[HPD_NUM_PINS] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
46};
47
48static const u32 hpd_spt[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
53 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
54};
55
56static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
63};
64
65static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
72};
73
74static const u32 hpd_status_i915[HPD_NUM_PINS] = {
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
81};
82
83static const u32 hpd_bxt[HPD_NUM_PINS] = {
84 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
85 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
86 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
87};
88
89static const u32 hpd_gen11[HPD_NUM_PINS] = {
90 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
91 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
92 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
93 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
94 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
95 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
96};
97
98static const u32 hpd_xelpdp[HPD_NUM_PINS] = {
99 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1),
100 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2),
101 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3),
102 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4),
103};
104
105static const u32 hpd_icp[HPD_NUM_PINS] = {
106 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
107 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
108 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
109 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
110 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
111 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
112 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
113 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
114 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
115};
116
117static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
118 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
119 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
120 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
121 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
122 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
123};
124
125static const u32 hpd_mtp[HPD_NUM_PINS] = {
126 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
127 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
128 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
129 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
130 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
131 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
132};
133
134static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
135{
136 struct intel_hotplug *hpd = &dev_priv->display.hotplug;
137
138 if (HAS_GMCH(dev_priv)) {
139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
140 IS_CHERRYVIEW(dev_priv))
141 hpd->hpd = hpd_status_g4x;
142 else
143 hpd->hpd = hpd_status_i915;
144 return;
145 }
146
147 if (DISPLAY_VER(dev_priv) >= 14)
148 hpd->hpd = hpd_xelpdp;
149 else if (DISPLAY_VER(dev_priv) >= 11)
150 hpd->hpd = hpd_gen11;
151 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
152 hpd->hpd = hpd_bxt;
153 else if (DISPLAY_VER(dev_priv) == 9)
154 hpd->hpd = NULL; /* no north HPD on SKL */
155 else if (DISPLAY_VER(dev_priv) >= 8)
156 hpd->hpd = hpd_bdw;
157 else if (DISPLAY_VER(dev_priv) >= 7)
158 hpd->hpd = hpd_ivb;
159 else
160 hpd->hpd = hpd_ilk;
161
162 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
164 return;
165
166 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
167 hpd->pch_hpd = hpd_mtp;
168 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
169 hpd->pch_hpd = hpd_sde_dg1;
170 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
171 hpd->pch_hpd = hpd_icp;
172 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
173 hpd->pch_hpd = hpd_spt;
174 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
175 hpd->pch_hpd = hpd_cpt;
176 else if (HAS_PCH_IBX(dev_priv))
177 hpd->pch_hpd = hpd_ibx;
178 else
179 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
180}
181
182/* For display hotplug interrupt */
183void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
184 u32 mask, u32 bits)
185{
186 lockdep_assert_held(&dev_priv->irq_lock);
187 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
188
189 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN(dev_priv), mask,
190 bits);
191}
192
193/**
194 * i915_hotplug_interrupt_update - update hotplug interrupt enable
195 * @dev_priv: driver private
196 * @mask: bits to update
197 * @bits: bits to enable
198 * NOTE: the HPD enable bits are modified both inside and outside
199 * of an interrupt context. To avoid that read-modify-write cycles
200 * interfer, these bits are protected by a spinlock. Since this
201 * function is usually not called from a context where the lock is
202 * held already, this function acquires the lock itself. A non-locking
203 * version is also available.
204 */
205void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
206 u32 mask,
207 u32 bits)
208{
209 spin_lock_irq(&dev_priv->irq_lock);
210 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
211 spin_unlock_irq(&dev_priv->irq_lock);
212}
213
214static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
215{
216 switch (pin) {
217 case HPD_PORT_TC1:
218 case HPD_PORT_TC2:
219 case HPD_PORT_TC3:
220 case HPD_PORT_TC4:
221 case HPD_PORT_TC5:
222 case HPD_PORT_TC6:
223 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
224 default:
225 return false;
226 }
227}
228
229static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
230{
231 switch (pin) {
232 case HPD_PORT_A:
233 return val & PORTA_HOTPLUG_LONG_DETECT;
234 case HPD_PORT_B:
235 return val & PORTB_HOTPLUG_LONG_DETECT;
236 case HPD_PORT_C:
237 return val & PORTC_HOTPLUG_LONG_DETECT;
238 default:
239 return false;
240 }
241}
242
243static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
244{
245 switch (pin) {
246 case HPD_PORT_A:
247 case HPD_PORT_B:
248 case HPD_PORT_C:
249 case HPD_PORT_D:
250 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
251 default:
252 return false;
253 }
254}
255
256static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
257{
258 switch (pin) {
259 case HPD_PORT_TC1:
260 case HPD_PORT_TC2:
261 case HPD_PORT_TC3:
262 case HPD_PORT_TC4:
263 case HPD_PORT_TC5:
264 case HPD_PORT_TC6:
265 return val & ICP_TC_HPD_LONG_DETECT(pin);
266 default:
267 return false;
268 }
269}
270
271static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
272{
273 switch (pin) {
274 case HPD_PORT_E:
275 return val & PORTE_HOTPLUG_LONG_DETECT;
276 default:
277 return false;
278 }
279}
280
281static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
282{
283 switch (pin) {
284 case HPD_PORT_A:
285 return val & PORTA_HOTPLUG_LONG_DETECT;
286 case HPD_PORT_B:
287 return val & PORTB_HOTPLUG_LONG_DETECT;
288 case HPD_PORT_C:
289 return val & PORTC_HOTPLUG_LONG_DETECT;
290 case HPD_PORT_D:
291 return val & PORTD_HOTPLUG_LONG_DETECT;
292 default:
293 return false;
294 }
295}
296
297static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
298{
299 switch (pin) {
300 case HPD_PORT_A:
301 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
302 default:
303 return false;
304 }
305}
306
307static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
308{
309 switch (pin) {
310 case HPD_PORT_B:
311 return val & PORTB_HOTPLUG_LONG_DETECT;
312 case HPD_PORT_C:
313 return val & PORTC_HOTPLUG_LONG_DETECT;
314 case HPD_PORT_D:
315 return val & PORTD_HOTPLUG_LONG_DETECT;
316 default:
317 return false;
318 }
319}
320
321static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
322{
323 switch (pin) {
324 case HPD_PORT_B:
325 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
326 case HPD_PORT_C:
327 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
328 case HPD_PORT_D:
329 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
330 default:
331 return false;
332 }
333}
334
335/*
336 * Get a bit mask of pins that have triggered, and which ones may be long.
337 * This can be called multiple times with the same masks to accumulate
338 * hotplug detection results from several registers.
339 *
340 * Note that the caller is expected to zero out the masks initially.
341 */
342static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
343 u32 *pin_mask, u32 *long_mask,
344 u32 hotplug_trigger, u32 dig_hotplug_reg,
345 const u32 hpd[HPD_NUM_PINS],
346 bool long_pulse_detect(enum hpd_pin pin, u32 val))
347{
348 enum hpd_pin pin;
349
350 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
351
352 for_each_hpd_pin(pin) {
353 if ((hpd[pin] & hotplug_trigger) == 0)
354 continue;
355
356 *pin_mask |= BIT(pin);
357
358 if (long_pulse_detect(pin, dig_hotplug_reg))
359 *long_mask |= BIT(pin);
360 }
361
362 drm_dbg(&dev_priv->drm,
363 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
364 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
365}
366
367static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
368 const u32 hpd[HPD_NUM_PINS])
369{
370 struct intel_encoder *encoder;
371 u32 enabled_irqs = 0;
372
373 for_each_intel_encoder(&dev_priv->drm, encoder)
374 if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
375 enabled_irqs |= hpd[encoder->hpd_pin];
376
377 return enabled_irqs;
378}
379
380static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
381 const u32 hpd[HPD_NUM_PINS])
382{
383 struct intel_encoder *encoder;
384 u32 hotplug_irqs = 0;
385
386 for_each_intel_encoder(&dev_priv->drm, encoder)
387 hotplug_irqs |= hpd[encoder->hpd_pin];
388
389 return hotplug_irqs;
390}
391
392static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915,
393 hotplug_mask_func hotplug_mask)
394{
395 enum hpd_pin pin;
396 u32 hotplug = 0;
397
398 for_each_hpd_pin(pin)
399 hotplug |= hotplug_mask(pin);
400
401 return hotplug;
402}
403
404static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
405 hotplug_enables_func hotplug_enables)
406{
407 struct intel_encoder *encoder;
408 u32 hotplug = 0;
409
410 for_each_intel_encoder(&i915->drm, encoder)
411 hotplug |= hotplug_enables(encoder);
412
413 return hotplug;
414}
415
416u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
417{
418 u32 hotplug_status = 0, hotplug_status_mask;
419 int i;
420
421 if (IS_G4X(dev_priv) ||
422 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
423 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
424 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
425 else
426 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
427
428 /*
429 * We absolutely have to clear all the pending interrupt
430 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
431 * interrupt bit won't have an edge, and the i965/g4x
432 * edge triggered IIR will not notice that an interrupt
433 * is still pending. We can't use PORT_HOTPLUG_EN to
434 * guarantee the edge as the act of toggling the enable
435 * bits can itself generate a new hotplug interrupt :(
436 */
437 for (i = 0; i < 10; i++) {
438 u32 tmp = intel_uncore_read(&dev_priv->uncore,
439 PORT_HOTPLUG_STAT(dev_priv)) & hotplug_status_mask;
440
441 if (tmp == 0)
442 return hotplug_status;
443
444 hotplug_status |= tmp;
445 intel_uncore_write(&dev_priv->uncore,
446 PORT_HOTPLUG_STAT(dev_priv),
447 hotplug_status);
448 }
449
450 drm_WARN_ONCE(&dev_priv->drm, 1,
451 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
452 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT(dev_priv)));
453
454 return hotplug_status;
455}
456
457void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status)
458{
459 struct intel_display *display = &dev_priv->display;
460 u32 pin_mask = 0, long_mask = 0;
461 u32 hotplug_trigger;
462
463 if (IS_G4X(dev_priv) ||
464 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
465 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
466 else
467 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
468
469 if (hotplug_trigger) {
470 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
471 hotplug_trigger, hotplug_trigger,
472 dev_priv->display.hotplug.hpd,
473 i9xx_port_hotplug_long_detect);
474
475 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
476 }
477
478 if ((IS_G4X(dev_priv) ||
479 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
480 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
481 intel_dp_aux_irq_handler(display);
482}
483
484void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
485{
486 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
487
488 /*
489 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
490 * unless we touch the hotplug register, even if hotplug_trigger is
491 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
492 * errors.
493 */
494 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
495 if (!hotplug_trigger) {
496 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
497 PORTD_HOTPLUG_STATUS_MASK |
498 PORTC_HOTPLUG_STATUS_MASK |
499 PORTB_HOTPLUG_STATUS_MASK;
500 dig_hotplug_reg &= ~mask;
501 }
502
503 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
504 if (!hotplug_trigger)
505 return;
506
507 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
508 hotplug_trigger, dig_hotplug_reg,
509 dev_priv->display.hotplug.pch_hpd,
510 pch_port_hotplug_long_detect);
511
512 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
513}
514
515void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
516{
517 struct intel_display *display = &i915->display;
518 enum hpd_pin pin;
519 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK);
520 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
521 u32 pin_mask = 0, long_mask = 0;
522
523 if (DISPLAY_VER(i915) >= 20)
524 trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
525
526 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
527 u32 val;
528
529 if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger))
530 continue;
531
532 pin_mask |= BIT(pin);
533
534 val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin));
535 intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val);
536
537 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT))
538 long_mask |= BIT(pin);
539 }
540
541 if (pin_mask) {
542 drm_dbg(&i915->drm,
543 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
544 hotplug_trigger, pin_mask, long_mask);
545
546 intel_hpd_irq_handler(i915, pin_mask, long_mask);
547 }
548
549 if (trigger_aux)
550 intel_dp_aux_irq_handler(display);
551
552 if (!pin_mask && !trigger_aux)
553 drm_err(&i915->drm,
554 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
555}
556
557void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
558{
559 struct intel_display *display = &dev_priv->display;
560 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
561 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
562 u32 pin_mask = 0, long_mask = 0;
563
564 if (ddi_hotplug_trigger) {
565 u32 dig_hotplug_reg;
566
567 /* Locking due to DSI native GPIO sequences */
568 spin_lock(&dev_priv->irq_lock);
569 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI, 0, 0);
570 spin_unlock(&dev_priv->irq_lock);
571
572 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
573 ddi_hotplug_trigger, dig_hotplug_reg,
574 dev_priv->display.hotplug.pch_hpd,
575 icp_ddi_port_hotplug_long_detect);
576 }
577
578 if (tc_hotplug_trigger) {
579 u32 dig_hotplug_reg;
580
581 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC, 0, 0);
582
583 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
584 tc_hotplug_trigger, dig_hotplug_reg,
585 dev_priv->display.hotplug.pch_hpd,
586 icp_tc_port_hotplug_long_detect);
587 }
588
589 if (pin_mask)
590 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
591
592 if (pch_iir & SDE_GMBUS_ICP)
593 intel_gmbus_irq_handler(display);
594}
595
596void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
597{
598 struct intel_display *display = &dev_priv->display;
599 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
600 ~SDE_PORTE_HOTPLUG_SPT;
601 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
602 u32 pin_mask = 0, long_mask = 0;
603
604 if (hotplug_trigger) {
605 u32 dig_hotplug_reg;
606
607 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
608
609 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
610 hotplug_trigger, dig_hotplug_reg,
611 dev_priv->display.hotplug.pch_hpd,
612 spt_port_hotplug_long_detect);
613 }
614
615 if (hotplug2_trigger) {
616 u32 dig_hotplug_reg;
617
618 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2, 0, 0);
619
620 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
621 hotplug2_trigger, dig_hotplug_reg,
622 dev_priv->display.hotplug.pch_hpd,
623 spt_port_hotplug2_long_detect);
624 }
625
626 if (pin_mask)
627 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
628
629 if (pch_iir & SDE_GMBUS_CPT)
630 intel_gmbus_irq_handler(display);
631}
632
633void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
634{
635 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
636
637 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
638
639 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
640 hotplug_trigger, dig_hotplug_reg,
641 dev_priv->display.hotplug.hpd,
642 ilk_port_hotplug_long_detect);
643
644 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
645}
646
647void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
648{
649 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
650
651 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
652
653 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
654 hotplug_trigger, dig_hotplug_reg,
655 dev_priv->display.hotplug.hpd,
656 bxt_port_hotplug_long_detect);
657
658 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
659}
660
661void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
662{
663 u32 pin_mask = 0, long_mask = 0;
664 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
665 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
666
667 if (trigger_tc) {
668 u32 dig_hotplug_reg;
669
670 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, 0, 0);
671
672 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
673 trigger_tc, dig_hotplug_reg,
674 dev_priv->display.hotplug.hpd,
675 gen11_port_hotplug_long_detect);
676 }
677
678 if (trigger_tbt) {
679 u32 dig_hotplug_reg;
680
681 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, 0, 0);
682
683 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
684 trigger_tbt, dig_hotplug_reg,
685 dev_priv->display.hotplug.hpd,
686 gen11_port_hotplug_long_detect);
687 }
688
689 if (pin_mask)
690 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
691 else
692 drm_err(&dev_priv->drm,
693 "Unexpected DE HPD interrupt 0x%08x\n", iir);
694}
695
696static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin)
697{
698 switch (hpd_pin) {
699 case HPD_PORT_A:
700 return PORTA_HOTPLUG_ENABLE;
701 case HPD_PORT_B:
702 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK;
703 case HPD_PORT_C:
704 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK;
705 case HPD_PORT_D:
706 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK;
707 default:
708 return 0;
709 }
710}
711
712static u32 ibx_hotplug_enables(struct intel_encoder *encoder)
713{
714 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
715
716 switch (encoder->hpd_pin) {
717 case HPD_PORT_A:
718 /*
719 * When CPU and PCH are on the same package, port A
720 * HPD must be enabled in both north and south.
721 */
722 return HAS_PCH_LPT_LP(i915) ?
723 PORTA_HOTPLUG_ENABLE : 0;
724 case HPD_PORT_B:
725 return PORTB_HOTPLUG_ENABLE |
726 PORTB_PULSE_DURATION_2ms;
727 case HPD_PORT_C:
728 return PORTC_HOTPLUG_ENABLE |
729 PORTC_PULSE_DURATION_2ms;
730 case HPD_PORT_D:
731 return PORTD_HOTPLUG_ENABLE |
732 PORTD_PULSE_DURATION_2ms;
733 default:
734 return 0;
735 }
736}
737
738static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
739{
740 /*
741 * Enable digital hotplug on the PCH, and configure the DP short pulse
742 * duration to 2ms (which is the minimum in the Display Port spec).
743 * The pulse duration bits are reserved on LPT+.
744 */
745 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
746 intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
747 intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
748}
749
750static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
751{
752 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
753
754 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
755 ibx_hotplug_mask(encoder->hpd_pin),
756 ibx_hotplug_enables(encoder));
757}
758
759static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
760{
761 u32 hotplug_irqs, enabled_irqs;
762
763 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
764 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
765
766 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
767
768 ibx_hpd_detection_setup(dev_priv);
769}
770
771static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
772{
773 switch (hpd_pin) {
774 case HPD_PORT_A:
775 case HPD_PORT_B:
776 case HPD_PORT_C:
777 case HPD_PORT_D:
778 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
779 default:
780 return 0;
781 }
782}
783
784static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder)
785{
786 return icp_ddi_hotplug_mask(encoder->hpd_pin);
787}
788
789static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin)
790{
791 switch (hpd_pin) {
792 case HPD_PORT_TC1:
793 case HPD_PORT_TC2:
794 case HPD_PORT_TC3:
795 case HPD_PORT_TC4:
796 case HPD_PORT_TC5:
797 case HPD_PORT_TC6:
798 return ICP_TC_HPD_ENABLE(hpd_pin);
799 default:
800 return 0;
801 }
802}
803
804static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
805{
806 return icp_tc_hotplug_mask(encoder->hpd_pin);
807}
808
809static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
810{
811 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI,
812 intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
813 intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables));
814}
815
816static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
817{
818 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
819
820 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_DDI,
821 icp_ddi_hotplug_mask(encoder->hpd_pin),
822 icp_ddi_hotplug_enables(encoder));
823}
824
825static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
826{
827 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC,
828 intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
829 intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables));
830}
831
832static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
833{
834 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
835
836 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_TC,
837 icp_tc_hotplug_mask(encoder->hpd_pin),
838 icp_tc_hotplug_enables(encoder));
839}
840
841static void icp_hpd_enable_detection(struct intel_encoder *encoder)
842{
843 icp_ddi_hpd_enable_detection(encoder);
844 icp_tc_hpd_enable_detection(encoder);
845}
846
847static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
848{
849 u32 hotplug_irqs, enabled_irqs;
850
851 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
852 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
853
854 /*
855 * We reduce the value to 250us to be able to detect SHPD when an external display
856 * is connected. This is also expected of us as stated in DP1.4a Table 3-4.
857 */
858 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
859
860 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
861
862 icp_ddi_hpd_detection_setup(dev_priv);
863 icp_tc_hpd_detection_setup(dev_priv);
864}
865
866static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)
867{
868 switch (hpd_pin) {
869 case HPD_PORT_TC1:
870 case HPD_PORT_TC2:
871 case HPD_PORT_TC3:
872 case HPD_PORT_TC4:
873 case HPD_PORT_TC5:
874 case HPD_PORT_TC6:
875 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin);
876 default:
877 return 0;
878 }
879}
880
881static u32 gen11_hotplug_enables(struct intel_encoder *encoder)
882{
883 return gen11_hotplug_mask(encoder->hpd_pin);
884}
885
886static void dg1_hpd_invert(struct drm_i915_private *i915)
887{
888 u32 val = (INVERT_DDIA_HPD |
889 INVERT_DDIB_HPD |
890 INVERT_DDIC_HPD |
891 INVERT_DDID_HPD);
892 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val);
893}
894
895static void dg1_hpd_enable_detection(struct intel_encoder *encoder)
896{
897 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
898
899 dg1_hpd_invert(i915);
900 icp_hpd_enable_detection(encoder);
901}
902
903static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
904{
905 dg1_hpd_invert(dev_priv);
906 icp_hpd_irq_setup(dev_priv);
907}
908
909static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
910{
911 intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL,
912 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
913 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
914}
915
916static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
917{
918 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
919
920 intel_uncore_rmw(&i915->uncore, GEN11_TC_HOTPLUG_CTL,
921 gen11_hotplug_mask(encoder->hpd_pin),
922 gen11_hotplug_enables(encoder));
923}
924
925static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
926{
927 intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL,
928 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
929 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
930}
931
932static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder)
933{
934 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
935
936 intel_uncore_rmw(&i915->uncore, GEN11_TBT_HOTPLUG_CTL,
937 gen11_hotplug_mask(encoder->hpd_pin),
938 gen11_hotplug_enables(encoder));
939}
940
941static void gen11_hpd_enable_detection(struct intel_encoder *encoder)
942{
943 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
944
945 gen11_tc_hpd_enable_detection(encoder);
946 gen11_tbt_hpd_enable_detection(encoder);
947
948 if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
949 icp_hpd_enable_detection(encoder);
950}
951
952static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
953{
954 u32 hotplug_irqs, enabled_irqs;
955
956 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
957 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
958
959 intel_uncore_rmw(&dev_priv->uncore, GEN11_DE_HPD_IMR, hotplug_irqs,
960 ~enabled_irqs & hotplug_irqs);
961 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
962
963 gen11_tc_hpd_detection_setup(dev_priv);
964 gen11_tbt_hpd_detection_setup(dev_priv);
965
966 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
967 icp_hpd_irq_setup(dev_priv);
968}
969
970static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
971{
972 switch (hpd_pin) {
973 case HPD_PORT_A:
974 case HPD_PORT_B:
975 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
976 default:
977 return 0;
978 }
979}
980
981static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder)
982{
983 return mtp_ddi_hotplug_mask(encoder->hpd_pin);
984}
985
986static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)
987{
988 switch (hpd_pin) {
989 case HPD_PORT_TC1:
990 case HPD_PORT_TC2:
991 case HPD_PORT_TC3:
992 case HPD_PORT_TC4:
993 return ICP_TC_HPD_ENABLE(hpd_pin);
994 default:
995 return 0;
996 }
997}
998
999static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder)
1000{
1001 return mtp_tc_hotplug_mask(encoder->hpd_pin);
1002}
1003
1004static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *i915)
1005{
1006 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1007 intel_hpd_hotplug_mask(i915, mtp_ddi_hotplug_mask),
1008 intel_hpd_hotplug_enables(i915, mtp_ddi_hotplug_enables));
1009}
1010
1011static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
1012{
1013 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1014
1015 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1016 mtp_ddi_hotplug_mask(encoder->hpd_pin),
1017 mtp_ddi_hotplug_enables(encoder));
1018}
1019
1020static void mtp_tc_hpd_detection_setup(struct drm_i915_private *i915)
1021{
1022 intel_de_rmw(i915, SHOTPLUG_CTL_TC,
1023 intel_hpd_hotplug_mask(i915, mtp_tc_hotplug_mask),
1024 intel_hpd_hotplug_enables(i915, mtp_tc_hotplug_enables));
1025}
1026
1027static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder)
1028{
1029 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1030
1031 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1032 mtp_tc_hotplug_mask(encoder->hpd_pin),
1033 mtp_tc_hotplug_enables(encoder));
1034}
1035
1036static void mtp_hpd_invert(struct drm_i915_private *i915)
1037{
1038 u32 val = (INVERT_DDIA_HPD |
1039 INVERT_DDIB_HPD |
1040 INVERT_DDIC_HPD |
1041 INVERT_TC1_HPD |
1042 INVERT_TC2_HPD |
1043 INVERT_TC3_HPD |
1044 INVERT_TC4_HPD |
1045 INVERT_DDID_HPD_MTP |
1046 INVERT_DDIE_HPD);
1047 intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val);
1048}
1049
1050static void mtp_hpd_enable_detection(struct intel_encoder *encoder)
1051{
1052 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1053
1054 mtp_hpd_invert(i915);
1055 mtp_ddi_hpd_enable_detection(encoder);
1056 mtp_tc_hpd_enable_detection(encoder);
1057}
1058
1059static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
1060{
1061 u32 hotplug_irqs, enabled_irqs;
1062
1063 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
1064 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
1065
1066 /*
1067 * Use 250us here to align with the DP1.4a(Table 3-4) spec as to what the
1068 * SHPD_FILTER_CNT value should be.
1069 */
1070 intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
1071
1072 mtp_hpd_invert(i915);
1073 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
1074
1075 mtp_ddi_hpd_detection_setup(i915);
1076 mtp_tc_hpd_detection_setup(i915);
1077}
1078
1079static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
1080{
1081 u32 hotplug_irqs, enabled_irqs;
1082
1083 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
1084 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
1085
1086 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
1087
1088 mtp_ddi_hpd_detection_setup(i915);
1089 mtp_tc_hpd_detection_setup(i915);
1090}
1091
1092static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
1093{
1094 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
1095}
1096
1097static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915,
1098 enum hpd_pin hpd_pin, bool enable)
1099{
1100 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |
1101 XELPDP_DP_ALT_HOTPLUG_ENABLE;
1102
1103 if (!is_xelpdp_pica_hpd_pin(hpd_pin))
1104 return;
1105
1106 intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
1107 mask, enable ? mask : 0);
1108}
1109
1110static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder)
1111{
1112 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1113
1114 _xelpdp_pica_hpd_detection_setup(i915, encoder->hpd_pin, true);
1115}
1116
1117static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915)
1118{
1119 struct intel_encoder *encoder;
1120 u32 available_pins = 0;
1121 enum hpd_pin pin;
1122
1123 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS);
1124
1125 for_each_intel_encoder(&i915->drm, encoder)
1126 available_pins |= BIT(encoder->hpd_pin);
1127
1128 for_each_hpd_pin(pin)
1129 _xelpdp_pica_hpd_detection_setup(i915, pin, available_pins & BIT(pin));
1130}
1131
1132static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
1133{
1134 xelpdp_pica_hpd_enable_detection(encoder);
1135 mtp_hpd_enable_detection(encoder);
1136}
1137
1138static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
1139{
1140 u32 hotplug_irqs, enabled_irqs;
1141
1142 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd);
1143 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd);
1144
1145 intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs,
1146 ~enabled_irqs & hotplug_irqs);
1147 intel_uncore_posting_read(&i915->uncore, PICAINTERRUPT_IMR);
1148
1149 xelpdp_pica_hpd_detection_setup(i915);
1150
1151 if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
1152 xe2lpd_sde_hpd_irq_setup(i915);
1153 else if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
1154 mtp_hpd_irq_setup(i915);
1155}
1156
1157static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)
1158{
1159 switch (hpd_pin) {
1160 case HPD_PORT_A:
1161 return PORTA_HOTPLUG_ENABLE;
1162 case HPD_PORT_B:
1163 return PORTB_HOTPLUG_ENABLE;
1164 case HPD_PORT_C:
1165 return PORTC_HOTPLUG_ENABLE;
1166 case HPD_PORT_D:
1167 return PORTD_HOTPLUG_ENABLE;
1168 default:
1169 return 0;
1170 }
1171}
1172
1173static u32 spt_hotplug_enables(struct intel_encoder *encoder)
1174{
1175 return spt_hotplug_mask(encoder->hpd_pin);
1176}
1177
1178static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin)
1179{
1180 switch (hpd_pin) {
1181 case HPD_PORT_E:
1182 return PORTE_HOTPLUG_ENABLE;
1183 default:
1184 return 0;
1185 }
1186}
1187
1188static u32 spt_hotplug2_enables(struct intel_encoder *encoder)
1189{
1190 return spt_hotplug2_mask(encoder->hpd_pin);
1191}
1192
1193static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
1194{
1195 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1196 if (HAS_PCH_CNP(dev_priv)) {
1197 intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
1198 CHASSIS_CLK_REQ_DURATION(0xf));
1199 }
1200
1201 /* Enable digital hotplug on the PCH */
1202 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
1203 intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
1204 intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
1205
1206 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2,
1207 intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
1208 intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
1209}
1210
1211static void spt_hpd_enable_detection(struct intel_encoder *encoder)
1212{
1213 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1214
1215 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1216 if (HAS_PCH_CNP(i915)) {
1217 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1,
1218 CHASSIS_CLK_REQ_DURATION_MASK,
1219 CHASSIS_CLK_REQ_DURATION(0xf));
1220 }
1221
1222 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
1223 spt_hotplug_mask(encoder->hpd_pin),
1224 spt_hotplug_enables(encoder));
1225
1226 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG2,
1227 spt_hotplug2_mask(encoder->hpd_pin),
1228 spt_hotplug2_enables(encoder));
1229}
1230
1231static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
1232{
1233 u32 hotplug_irqs, enabled_irqs;
1234
1235 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1236 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
1237
1238 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
1239 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
1240
1241 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
1242
1243 spt_hpd_detection_setup(dev_priv);
1244}
1245
1246static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)
1247{
1248 switch (hpd_pin) {
1249 case HPD_PORT_A:
1250 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1251 DIGITAL_PORTA_PULSE_DURATION_MASK;
1252 default:
1253 return 0;
1254 }
1255}
1256
1257static u32 ilk_hotplug_enables(struct intel_encoder *encoder)
1258{
1259 switch (encoder->hpd_pin) {
1260 case HPD_PORT_A:
1261 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1262 DIGITAL_PORTA_PULSE_DURATION_2ms;
1263 default:
1264 return 0;
1265 }
1266}
1267
1268static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
1269{
1270 /*
1271 * Enable digital hotplug on the CPU, and configure the DP short pulse
1272 * duration to 2ms (which is the minimum in the Display Port spec)
1273 * The pulse duration bits are reserved on HSW+.
1274 */
1275 intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
1276 intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
1277 intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
1278}
1279
1280static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
1281{
1282 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1283
1284 intel_uncore_rmw(&i915->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
1285 ilk_hotplug_mask(encoder->hpd_pin),
1286 ilk_hotplug_enables(encoder));
1287
1288 ibx_hpd_enable_detection(encoder);
1289}
1290
1291static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
1292{
1293 u32 hotplug_irqs, enabled_irqs;
1294
1295 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1296 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1297
1298 if (DISPLAY_VER(dev_priv) >= 8)
1299 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
1300 else
1301 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
1302
1303 ilk_hpd_detection_setup(dev_priv);
1304
1305 ibx_hpd_irq_setup(dev_priv);
1306}
1307
1308static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)
1309{
1310 switch (hpd_pin) {
1311 case HPD_PORT_A:
1312 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT;
1313 case HPD_PORT_B:
1314 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT;
1315 case HPD_PORT_C:
1316 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT;
1317 default:
1318 return 0;
1319 }
1320}
1321
1322static u32 bxt_hotplug_enables(struct intel_encoder *encoder)
1323{
1324 u32 hotplug;
1325
1326 switch (encoder->hpd_pin) {
1327 case HPD_PORT_A:
1328 hotplug = PORTA_HOTPLUG_ENABLE;
1329 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1330 hotplug |= BXT_DDIA_HPD_INVERT;
1331 return hotplug;
1332 case HPD_PORT_B:
1333 hotplug = PORTB_HOTPLUG_ENABLE;
1334 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1335 hotplug |= BXT_DDIB_HPD_INVERT;
1336 return hotplug;
1337 case HPD_PORT_C:
1338 hotplug = PORTC_HOTPLUG_ENABLE;
1339 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1340 hotplug |= BXT_DDIC_HPD_INVERT;
1341 return hotplug;
1342 default:
1343 return 0;
1344 }
1345}
1346
1347static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
1348{
1349 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
1350 intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
1351 intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
1352}
1353
1354static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
1355{
1356 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1357
1358 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
1359 bxt_hotplug_mask(encoder->hpd_pin),
1360 bxt_hotplug_enables(encoder));
1361}
1362
1363static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
1364{
1365 u32 hotplug_irqs, enabled_irqs;
1366
1367 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1368 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1369
1370 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
1371
1372 bxt_hpd_detection_setup(dev_priv);
1373}
1374
1375static void g45_hpd_peg_band_gap_wa(struct drm_i915_private *i915)
1376{
1377 /*
1378 * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1379 * 0xd. Failure to do so will result in spurious interrupts being
1380 * generated on the port when a cable is not attached.
1381 */
1382 intel_de_rmw(i915, PEG_BAND_GAP_DATA, 0xf, 0xd);
1383}
1384
1385static void i915_hpd_enable_detection(struct intel_encoder *encoder)
1386{
1387 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1388 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];
1389
1390 if (IS_G45(i915))
1391 g45_hpd_peg_band_gap_wa(i915);
1392
1393 /* HPD sense and interrupt enable are one and the same */
1394 i915_hotplug_interrupt_update(i915, hotplug_en, hotplug_en);
1395}
1396
1397static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
1398{
1399 u32 hotplug_en;
1400
1401 lockdep_assert_held(&dev_priv->irq_lock);
1402
1403 /*
1404 * Note HDMI and DP share hotplug bits. Enable bits are the same for all
1405 * generations.
1406 */
1407 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
1408 /*
1409 * Programming the CRT detection parameters tends to generate a spurious
1410 * hotplug event about three seconds later. So just do it once.
1411 */
1412 if (IS_G4X(dev_priv))
1413 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1414 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1415
1416 if (IS_G45(dev_priv))
1417 g45_hpd_peg_band_gap_wa(dev_priv);
1418
1419 /* Ignore TV since it's buggy */
1420 i915_hotplug_interrupt_update_locked(dev_priv,
1421 HOTPLUG_INT_EN_MASK |
1422 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
1423 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
1424 hotplug_en);
1425}
1426
1427struct intel_hotplug_funcs {
1428 /* Enable HPD sense and interrupts for all present encoders */
1429 void (*hpd_irq_setup)(struct drm_i915_private *i915);
1430 /* Enable HPD sense for a single encoder */
1431 void (*hpd_enable_detection)(struct intel_encoder *encoder);
1432};
1433
1434#define HPD_FUNCS(platform) \
1435static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
1436 .hpd_irq_setup = platform##_hpd_irq_setup, \
1437 .hpd_enable_detection = platform##_hpd_enable_detection, \
1438}
1439
1440HPD_FUNCS(i915);
1441HPD_FUNCS(xelpdp);
1442HPD_FUNCS(dg1);
1443HPD_FUNCS(gen11);
1444HPD_FUNCS(bxt);
1445HPD_FUNCS(icp);
1446HPD_FUNCS(spt);
1447HPD_FUNCS(ilk);
1448#undef HPD_FUNCS
1449
1450void intel_hpd_enable_detection(struct intel_encoder *encoder)
1451{
1452 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1453
1454 if (i915->display.funcs.hotplug)
1455 i915->display.funcs.hotplug->hpd_enable_detection(encoder);
1456}
1457
1458void intel_hpd_irq_setup(struct drm_i915_private *i915)
1459{
1460 if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug)
1461 i915->display.funcs.hotplug->hpd_irq_setup(i915);
1462}
1463
1464void intel_hotplug_irq_init(struct drm_i915_private *i915)
1465{
1466 intel_hpd_init_pins(i915);
1467
1468 intel_hpd_init_early(i915);
1469
1470 if (HAS_GMCH(i915)) {
1471 if (I915_HAS_HOTPLUG(i915))
1472 i915->display.funcs.hotplug = &i915_hpd_funcs;
1473 } else {
1474 if (HAS_PCH_DG2(i915))
1475 i915->display.funcs.hotplug = &icp_hpd_funcs;
1476 else if (HAS_PCH_DG1(i915))
1477 i915->display.funcs.hotplug = &dg1_hpd_funcs;
1478 else if (DISPLAY_VER(i915) >= 14)
1479 i915->display.funcs.hotplug = &xelpdp_hpd_funcs;
1480 else if (DISPLAY_VER(i915) >= 11)
1481 i915->display.funcs.hotplug = &gen11_hpd_funcs;
1482 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1483 i915->display.funcs.hotplug = &bxt_hpd_funcs;
1484 else if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
1485 i915->display.funcs.hotplug = &icp_hpd_funcs;
1486 else if (INTEL_PCH_TYPE(i915) >= PCH_SPT)
1487 i915->display.funcs.hotplug = &spt_hpd_funcs;
1488 else
1489 i915->display.funcs.hotplug = &ilk_hpd_funcs;
1490 }
1491}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "i915_reg.h"
8#include "intel_de.h"
9#include "intel_display_irq.h"
10#include "intel_display_types.h"
11#include "intel_dp_aux.h"
12#include "intel_gmbus.h"
13#include "intel_hotplug.h"
14#include "intel_hotplug_irq.h"
15
16typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
17typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder);
18typedef u32 (*hotplug_mask_func)(enum hpd_pin pin);
19
20static const u32 hpd_ilk[HPD_NUM_PINS] = {
21 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
22};
23
24static const u32 hpd_ivb[HPD_NUM_PINS] = {
25 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
26};
27
28static const u32 hpd_bdw[HPD_NUM_PINS] = {
29 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
30};
31
32static const u32 hpd_ibx[HPD_NUM_PINS] = {
33 [HPD_CRT] = SDE_CRT_HOTPLUG,
34 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
35 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
36 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
37 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
38};
39
40static const u32 hpd_cpt[HPD_NUM_PINS] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
46};
47
48static const u32 hpd_spt[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
53 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
54};
55
56static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
63};
64
65static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
72};
73
74static const u32 hpd_status_i915[HPD_NUM_PINS] = {
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
81};
82
83static const u32 hpd_bxt[HPD_NUM_PINS] = {
84 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
85 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
86 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
87};
88
89static const u32 hpd_gen11[HPD_NUM_PINS] = {
90 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
91 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
92 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
93 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
94 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
95 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
96};
97
98static const u32 hpd_xelpdp[HPD_NUM_PINS] = {
99 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1),
100 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2),
101 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3),
102 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4),
103};
104
105static const u32 hpd_icp[HPD_NUM_PINS] = {
106 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
107 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
108 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
109 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
110 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
111 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
112 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
113 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
114 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
115};
116
117static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
118 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
119 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
120 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
121 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
122 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
123};
124
125static const u32 hpd_mtp[HPD_NUM_PINS] = {
126 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
127 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
128 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
129 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
130 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
131 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
132};
133
134static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
135{
136 struct intel_hotplug *hpd = &dev_priv->display.hotplug;
137
138 if (HAS_GMCH(dev_priv)) {
139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
140 IS_CHERRYVIEW(dev_priv))
141 hpd->hpd = hpd_status_g4x;
142 else
143 hpd->hpd = hpd_status_i915;
144 return;
145 }
146
147 if (DISPLAY_VER(dev_priv) >= 14)
148 hpd->hpd = hpd_xelpdp;
149 else if (DISPLAY_VER(dev_priv) >= 11)
150 hpd->hpd = hpd_gen11;
151 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
152 hpd->hpd = hpd_bxt;
153 else if (DISPLAY_VER(dev_priv) == 9)
154 hpd->hpd = NULL; /* no north HPD on SKL */
155 else if (DISPLAY_VER(dev_priv) >= 8)
156 hpd->hpd = hpd_bdw;
157 else if (DISPLAY_VER(dev_priv) >= 7)
158 hpd->hpd = hpd_ivb;
159 else
160 hpd->hpd = hpd_ilk;
161
162 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
164 return;
165
166 if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
167 hpd->pch_hpd = hpd_mtp;
168 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
169 hpd->pch_hpd = hpd_sde_dg1;
170 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
171 hpd->pch_hpd = hpd_mtp;
172 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
173 hpd->pch_hpd = hpd_icp;
174 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
175 hpd->pch_hpd = hpd_spt;
176 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
177 hpd->pch_hpd = hpd_cpt;
178 else if (HAS_PCH_IBX(dev_priv))
179 hpd->pch_hpd = hpd_ibx;
180 else
181 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
182}
183
184/* For display hotplug interrupt */
185void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
186 u32 mask, u32 bits)
187{
188 lockdep_assert_held(&dev_priv->irq_lock);
189 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
190
191 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN, mask, bits);
192}
193
194/**
195 * i915_hotplug_interrupt_update - update hotplug interrupt enable
196 * @dev_priv: driver private
197 * @mask: bits to update
198 * @bits: bits to enable
199 * NOTE: the HPD enable bits are modified both inside and outside
200 * of an interrupt context. To avoid that read-modify-write cycles
201 * interfer, these bits are protected by a spinlock. Since this
202 * function is usually not called from a context where the lock is
203 * held already, this function acquires the lock itself. A non-locking
204 * version is also available.
205 */
206void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
207 u32 mask,
208 u32 bits)
209{
210 spin_lock_irq(&dev_priv->irq_lock);
211 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
212 spin_unlock_irq(&dev_priv->irq_lock);
213}
214
215static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
216{
217 switch (pin) {
218 case HPD_PORT_TC1:
219 case HPD_PORT_TC2:
220 case HPD_PORT_TC3:
221 case HPD_PORT_TC4:
222 case HPD_PORT_TC5:
223 case HPD_PORT_TC6:
224 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
225 default:
226 return false;
227 }
228}
229
230static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
231{
232 switch (pin) {
233 case HPD_PORT_A:
234 return val & PORTA_HOTPLUG_LONG_DETECT;
235 case HPD_PORT_B:
236 return val & PORTB_HOTPLUG_LONG_DETECT;
237 case HPD_PORT_C:
238 return val & PORTC_HOTPLUG_LONG_DETECT;
239 default:
240 return false;
241 }
242}
243
244static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
245{
246 switch (pin) {
247 case HPD_PORT_A:
248 case HPD_PORT_B:
249 case HPD_PORT_C:
250 case HPD_PORT_D:
251 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
252 default:
253 return false;
254 }
255}
256
257static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
258{
259 switch (pin) {
260 case HPD_PORT_TC1:
261 case HPD_PORT_TC2:
262 case HPD_PORT_TC3:
263 case HPD_PORT_TC4:
264 case HPD_PORT_TC5:
265 case HPD_PORT_TC6:
266 return val & ICP_TC_HPD_LONG_DETECT(pin);
267 default:
268 return false;
269 }
270}
271
272static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
273{
274 switch (pin) {
275 case HPD_PORT_E:
276 return val & PORTE_HOTPLUG_LONG_DETECT;
277 default:
278 return false;
279 }
280}
281
282static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
283{
284 switch (pin) {
285 case HPD_PORT_A:
286 return val & PORTA_HOTPLUG_LONG_DETECT;
287 case HPD_PORT_B:
288 return val & PORTB_HOTPLUG_LONG_DETECT;
289 case HPD_PORT_C:
290 return val & PORTC_HOTPLUG_LONG_DETECT;
291 case HPD_PORT_D:
292 return val & PORTD_HOTPLUG_LONG_DETECT;
293 default:
294 return false;
295 }
296}
297
298static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
299{
300 switch (pin) {
301 case HPD_PORT_A:
302 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
303 default:
304 return false;
305 }
306}
307
308static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
309{
310 switch (pin) {
311 case HPD_PORT_B:
312 return val & PORTB_HOTPLUG_LONG_DETECT;
313 case HPD_PORT_C:
314 return val & PORTC_HOTPLUG_LONG_DETECT;
315 case HPD_PORT_D:
316 return val & PORTD_HOTPLUG_LONG_DETECT;
317 default:
318 return false;
319 }
320}
321
322static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
323{
324 switch (pin) {
325 case HPD_PORT_B:
326 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
327 case HPD_PORT_C:
328 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
329 case HPD_PORT_D:
330 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
331 default:
332 return false;
333 }
334}
335
336/*
337 * Get a bit mask of pins that have triggered, and which ones may be long.
338 * This can be called multiple times with the same masks to accumulate
339 * hotplug detection results from several registers.
340 *
341 * Note that the caller is expected to zero out the masks initially.
342 */
343static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
344 u32 *pin_mask, u32 *long_mask,
345 u32 hotplug_trigger, u32 dig_hotplug_reg,
346 const u32 hpd[HPD_NUM_PINS],
347 bool long_pulse_detect(enum hpd_pin pin, u32 val))
348{
349 enum hpd_pin pin;
350
351 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
352
353 for_each_hpd_pin(pin) {
354 if ((hpd[pin] & hotplug_trigger) == 0)
355 continue;
356
357 *pin_mask |= BIT(pin);
358
359 if (long_pulse_detect(pin, dig_hotplug_reg))
360 *long_mask |= BIT(pin);
361 }
362
363 drm_dbg(&dev_priv->drm,
364 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
365 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
366}
367
368static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
369 const u32 hpd[HPD_NUM_PINS])
370{
371 struct intel_encoder *encoder;
372 u32 enabled_irqs = 0;
373
374 for_each_intel_encoder(&dev_priv->drm, encoder)
375 if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
376 enabled_irqs |= hpd[encoder->hpd_pin];
377
378 return enabled_irqs;
379}
380
381static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
382 const u32 hpd[HPD_NUM_PINS])
383{
384 struct intel_encoder *encoder;
385 u32 hotplug_irqs = 0;
386
387 for_each_intel_encoder(&dev_priv->drm, encoder)
388 hotplug_irqs |= hpd[encoder->hpd_pin];
389
390 return hotplug_irqs;
391}
392
393static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915,
394 hotplug_mask_func hotplug_mask)
395{
396 enum hpd_pin pin;
397 u32 hotplug = 0;
398
399 for_each_hpd_pin(pin)
400 hotplug |= hotplug_mask(pin);
401
402 return hotplug;
403}
404
405static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
406 hotplug_enables_func hotplug_enables)
407{
408 struct intel_encoder *encoder;
409 u32 hotplug = 0;
410
411 for_each_intel_encoder(&i915->drm, encoder)
412 hotplug |= hotplug_enables(encoder);
413
414 return hotplug;
415}
416
417u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
418{
419 u32 hotplug_status = 0, hotplug_status_mask;
420 int i;
421
422 if (IS_G4X(dev_priv) ||
423 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
424 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
425 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
426 else
427 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
428
429 /*
430 * We absolutely have to clear all the pending interrupt
431 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
432 * interrupt bit won't have an edge, and the i965/g4x
433 * edge triggered IIR will not notice that an interrupt
434 * is still pending. We can't use PORT_HOTPLUG_EN to
435 * guarantee the edge as the act of toggling the enable
436 * bits can itself generate a new hotplug interrupt :(
437 */
438 for (i = 0; i < 10; i++) {
439 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
440
441 if (tmp == 0)
442 return hotplug_status;
443
444 hotplug_status |= tmp;
445 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
446 }
447
448 drm_WARN_ONCE(&dev_priv->drm, 1,
449 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
450 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
451
452 return hotplug_status;
453}
454
455void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status)
456{
457 u32 pin_mask = 0, long_mask = 0;
458 u32 hotplug_trigger;
459
460 if (IS_G4X(dev_priv) ||
461 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
462 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
463 else
464 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
465
466 if (hotplug_trigger) {
467 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
468 hotplug_trigger, hotplug_trigger,
469 dev_priv->display.hotplug.hpd,
470 i9xx_port_hotplug_long_detect);
471
472 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
473 }
474
475 if ((IS_G4X(dev_priv) ||
476 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
477 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
478 intel_dp_aux_irq_handler(dev_priv);
479}
480
481void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
482{
483 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
484
485 /*
486 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
487 * unless we touch the hotplug register, even if hotplug_trigger is
488 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
489 * errors.
490 */
491 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
492 if (!hotplug_trigger) {
493 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
494 PORTD_HOTPLUG_STATUS_MASK |
495 PORTC_HOTPLUG_STATUS_MASK |
496 PORTB_HOTPLUG_STATUS_MASK;
497 dig_hotplug_reg &= ~mask;
498 }
499
500 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
501 if (!hotplug_trigger)
502 return;
503
504 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
505 hotplug_trigger, dig_hotplug_reg,
506 dev_priv->display.hotplug.pch_hpd,
507 pch_port_hotplug_long_detect);
508
509 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
510}
511
512void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
513{
514 enum hpd_pin pin;
515 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK);
516 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
517 u32 pin_mask = 0, long_mask = 0;
518
519 if (DISPLAY_VER(i915) >= 20)
520 trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
521
522 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
523 u32 val;
524
525 if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger))
526 continue;
527
528 pin_mask |= BIT(pin);
529
530 val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin));
531 intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val);
532
533 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT))
534 long_mask |= BIT(pin);
535 }
536
537 if (pin_mask) {
538 drm_dbg(&i915->drm,
539 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
540 hotplug_trigger, pin_mask, long_mask);
541
542 intel_hpd_irq_handler(i915, pin_mask, long_mask);
543 }
544
545 if (trigger_aux)
546 intel_dp_aux_irq_handler(i915);
547
548 if (!pin_mask && !trigger_aux)
549 drm_err(&i915->drm,
550 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
551}
552
553void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
554{
555 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
556 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
557 u32 pin_mask = 0, long_mask = 0;
558
559 if (ddi_hotplug_trigger) {
560 u32 dig_hotplug_reg;
561
562 /* Locking due to DSI native GPIO sequences */
563 spin_lock(&dev_priv->irq_lock);
564 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI, 0, 0);
565 spin_unlock(&dev_priv->irq_lock);
566
567 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
568 ddi_hotplug_trigger, dig_hotplug_reg,
569 dev_priv->display.hotplug.pch_hpd,
570 icp_ddi_port_hotplug_long_detect);
571 }
572
573 if (tc_hotplug_trigger) {
574 u32 dig_hotplug_reg;
575
576 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC, 0, 0);
577
578 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
579 tc_hotplug_trigger, dig_hotplug_reg,
580 dev_priv->display.hotplug.pch_hpd,
581 icp_tc_port_hotplug_long_detect);
582 }
583
584 if (pin_mask)
585 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
586
587 if (pch_iir & SDE_GMBUS_ICP)
588 intel_gmbus_irq_handler(dev_priv);
589}
590
591void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
592{
593 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
594 ~SDE_PORTE_HOTPLUG_SPT;
595 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
596 u32 pin_mask = 0, long_mask = 0;
597
598 if (hotplug_trigger) {
599 u32 dig_hotplug_reg;
600
601 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
602
603 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
604 hotplug_trigger, dig_hotplug_reg,
605 dev_priv->display.hotplug.pch_hpd,
606 spt_port_hotplug_long_detect);
607 }
608
609 if (hotplug2_trigger) {
610 u32 dig_hotplug_reg;
611
612 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2, 0, 0);
613
614 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
615 hotplug2_trigger, dig_hotplug_reg,
616 dev_priv->display.hotplug.pch_hpd,
617 spt_port_hotplug2_long_detect);
618 }
619
620 if (pin_mask)
621 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
622
623 if (pch_iir & SDE_GMBUS_CPT)
624 intel_gmbus_irq_handler(dev_priv);
625}
626
627void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
628{
629 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
630
631 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
632
633 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
634 hotplug_trigger, dig_hotplug_reg,
635 dev_priv->display.hotplug.hpd,
636 ilk_port_hotplug_long_detect);
637
638 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
639}
640
641void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
642{
643 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
644
645 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
646
647 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
648 hotplug_trigger, dig_hotplug_reg,
649 dev_priv->display.hotplug.hpd,
650 bxt_port_hotplug_long_detect);
651
652 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
653}
654
655void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
656{
657 u32 pin_mask = 0, long_mask = 0;
658 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
659 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
660
661 if (trigger_tc) {
662 u32 dig_hotplug_reg;
663
664 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, 0, 0);
665
666 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
667 trigger_tc, dig_hotplug_reg,
668 dev_priv->display.hotplug.hpd,
669 gen11_port_hotplug_long_detect);
670 }
671
672 if (trigger_tbt) {
673 u32 dig_hotplug_reg;
674
675 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, 0, 0);
676
677 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
678 trigger_tbt, dig_hotplug_reg,
679 dev_priv->display.hotplug.hpd,
680 gen11_port_hotplug_long_detect);
681 }
682
683 if (pin_mask)
684 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
685 else
686 drm_err(&dev_priv->drm,
687 "Unexpected DE HPD interrupt 0x%08x\n", iir);
688}
689
690static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin)
691{
692 switch (hpd_pin) {
693 case HPD_PORT_A:
694 return PORTA_HOTPLUG_ENABLE;
695 case HPD_PORT_B:
696 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK;
697 case HPD_PORT_C:
698 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK;
699 case HPD_PORT_D:
700 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK;
701 default:
702 return 0;
703 }
704}
705
706static u32 ibx_hotplug_enables(struct intel_encoder *encoder)
707{
708 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
709
710 switch (encoder->hpd_pin) {
711 case HPD_PORT_A:
712 /*
713 * When CPU and PCH are on the same package, port A
714 * HPD must be enabled in both north and south.
715 */
716 return HAS_PCH_LPT_LP(i915) ?
717 PORTA_HOTPLUG_ENABLE : 0;
718 case HPD_PORT_B:
719 return PORTB_HOTPLUG_ENABLE |
720 PORTB_PULSE_DURATION_2ms;
721 case HPD_PORT_C:
722 return PORTC_HOTPLUG_ENABLE |
723 PORTC_PULSE_DURATION_2ms;
724 case HPD_PORT_D:
725 return PORTD_HOTPLUG_ENABLE |
726 PORTD_PULSE_DURATION_2ms;
727 default:
728 return 0;
729 }
730}
731
732static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
733{
734 /*
735 * Enable digital hotplug on the PCH, and configure the DP short pulse
736 * duration to 2ms (which is the minimum in the Display Port spec).
737 * The pulse duration bits are reserved on LPT+.
738 */
739 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
740 intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
741 intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
742}
743
744static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
745{
746 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
747
748 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
749 ibx_hotplug_mask(encoder->hpd_pin),
750 ibx_hotplug_enables(encoder));
751}
752
753static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
754{
755 u32 hotplug_irqs, enabled_irqs;
756
757 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
758 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
759
760 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
761
762 ibx_hpd_detection_setup(dev_priv);
763}
764
765static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
766{
767 switch (hpd_pin) {
768 case HPD_PORT_A:
769 case HPD_PORT_B:
770 case HPD_PORT_C:
771 case HPD_PORT_D:
772 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
773 default:
774 return 0;
775 }
776}
777
778static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder)
779{
780 return icp_ddi_hotplug_mask(encoder->hpd_pin);
781}
782
783static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin)
784{
785 switch (hpd_pin) {
786 case HPD_PORT_TC1:
787 case HPD_PORT_TC2:
788 case HPD_PORT_TC3:
789 case HPD_PORT_TC4:
790 case HPD_PORT_TC5:
791 case HPD_PORT_TC6:
792 return ICP_TC_HPD_ENABLE(hpd_pin);
793 default:
794 return 0;
795 }
796}
797
798static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
799{
800 return icp_tc_hotplug_mask(encoder->hpd_pin);
801}
802
803static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
804{
805 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI,
806 intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
807 intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables));
808}
809
810static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
811{
812 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
813
814 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_DDI,
815 icp_ddi_hotplug_mask(encoder->hpd_pin),
816 icp_ddi_hotplug_enables(encoder));
817}
818
819static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
820{
821 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC,
822 intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
823 intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables));
824}
825
826static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
827{
828 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
829
830 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_TC,
831 icp_tc_hotplug_mask(encoder->hpd_pin),
832 icp_tc_hotplug_enables(encoder));
833}
834
835static void icp_hpd_enable_detection(struct intel_encoder *encoder)
836{
837 icp_ddi_hpd_enable_detection(encoder);
838 icp_tc_hpd_enable_detection(encoder);
839}
840
841static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
842{
843 u32 hotplug_irqs, enabled_irqs;
844
845 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
846 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
847
848 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
849 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
850 else
851 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
852
853 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
854
855 icp_ddi_hpd_detection_setup(dev_priv);
856 icp_tc_hpd_detection_setup(dev_priv);
857}
858
859static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)
860{
861 switch (hpd_pin) {
862 case HPD_PORT_TC1:
863 case HPD_PORT_TC2:
864 case HPD_PORT_TC3:
865 case HPD_PORT_TC4:
866 case HPD_PORT_TC5:
867 case HPD_PORT_TC6:
868 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin);
869 default:
870 return 0;
871 }
872}
873
874static u32 gen11_hotplug_enables(struct intel_encoder *encoder)
875{
876 return gen11_hotplug_mask(encoder->hpd_pin);
877}
878
879static void dg1_hpd_invert(struct drm_i915_private *i915)
880{
881 u32 val = (INVERT_DDIA_HPD |
882 INVERT_DDIB_HPD |
883 INVERT_DDIC_HPD |
884 INVERT_DDID_HPD);
885 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val);
886}
887
888static void dg1_hpd_enable_detection(struct intel_encoder *encoder)
889{
890 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
891
892 dg1_hpd_invert(i915);
893 icp_hpd_enable_detection(encoder);
894}
895
896static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
897{
898 dg1_hpd_invert(dev_priv);
899 icp_hpd_irq_setup(dev_priv);
900}
901
902static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
903{
904 intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL,
905 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
906 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
907}
908
909static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
910{
911 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
912
913 intel_uncore_rmw(&i915->uncore, GEN11_TC_HOTPLUG_CTL,
914 gen11_hotplug_mask(encoder->hpd_pin),
915 gen11_hotplug_enables(encoder));
916}
917
918static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
919{
920 intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL,
921 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
922 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
923}
924
925static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder)
926{
927 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
928
929 intel_uncore_rmw(&i915->uncore, GEN11_TBT_HOTPLUG_CTL,
930 gen11_hotplug_mask(encoder->hpd_pin),
931 gen11_hotplug_enables(encoder));
932}
933
934static void gen11_hpd_enable_detection(struct intel_encoder *encoder)
935{
936 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
937
938 gen11_tc_hpd_enable_detection(encoder);
939 gen11_tbt_hpd_enable_detection(encoder);
940
941 if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
942 icp_hpd_enable_detection(encoder);
943}
944
945static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
946{
947 u32 hotplug_irqs, enabled_irqs;
948
949 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
950 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
951
952 intel_uncore_rmw(&dev_priv->uncore, GEN11_DE_HPD_IMR, hotplug_irqs,
953 ~enabled_irqs & hotplug_irqs);
954 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
955
956 gen11_tc_hpd_detection_setup(dev_priv);
957 gen11_tbt_hpd_detection_setup(dev_priv);
958
959 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
960 icp_hpd_irq_setup(dev_priv);
961}
962
963static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
964{
965 switch (hpd_pin) {
966 case HPD_PORT_A:
967 case HPD_PORT_B:
968 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
969 default:
970 return 0;
971 }
972}
973
974static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder)
975{
976 return mtp_ddi_hotplug_mask(encoder->hpd_pin);
977}
978
979static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)
980{
981 switch (hpd_pin) {
982 case HPD_PORT_TC1:
983 case HPD_PORT_TC2:
984 case HPD_PORT_TC3:
985 case HPD_PORT_TC4:
986 return ICP_TC_HPD_ENABLE(hpd_pin);
987 default:
988 return 0;
989 }
990}
991
992static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder)
993{
994 return mtp_tc_hotplug_mask(encoder->hpd_pin);
995}
996
997static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *i915)
998{
999 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1000 intel_hpd_hotplug_mask(i915, mtp_ddi_hotplug_mask),
1001 intel_hpd_hotplug_enables(i915, mtp_ddi_hotplug_enables));
1002}
1003
1004static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
1005{
1006 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1007
1008 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1009 mtp_ddi_hotplug_mask(encoder->hpd_pin),
1010 mtp_ddi_hotplug_enables(encoder));
1011}
1012
1013static void mtp_tc_hpd_detection_setup(struct drm_i915_private *i915)
1014{
1015 intel_de_rmw(i915, SHOTPLUG_CTL_TC,
1016 intel_hpd_hotplug_mask(i915, mtp_tc_hotplug_mask),
1017 intel_hpd_hotplug_enables(i915, mtp_tc_hotplug_enables));
1018}
1019
1020static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder)
1021{
1022 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1023
1024 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1025 mtp_tc_hotplug_mask(encoder->hpd_pin),
1026 mtp_tc_hotplug_enables(encoder));
1027}
1028
1029static void mtp_hpd_invert(struct drm_i915_private *i915)
1030{
1031 u32 val = (INVERT_DDIA_HPD |
1032 INVERT_DDIB_HPD |
1033 INVERT_DDIC_HPD |
1034 INVERT_TC1_HPD |
1035 INVERT_TC2_HPD |
1036 INVERT_TC3_HPD |
1037 INVERT_TC4_HPD |
1038 INVERT_DDID_HPD_MTP |
1039 INVERT_DDIE_HPD);
1040 intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val);
1041}
1042
1043static void mtp_hpd_enable_detection(struct intel_encoder *encoder)
1044{
1045 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1046
1047 mtp_hpd_invert(i915);
1048 mtp_ddi_hpd_enable_detection(encoder);
1049 mtp_tc_hpd_enable_detection(encoder);
1050}
1051
1052static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
1053{
1054 u32 hotplug_irqs, enabled_irqs;
1055
1056 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
1057 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
1058
1059 intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
1060
1061 mtp_hpd_invert(i915);
1062 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
1063
1064 mtp_ddi_hpd_detection_setup(i915);
1065 mtp_tc_hpd_detection_setup(i915);
1066}
1067
1068static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
1069{
1070 u32 hotplug_irqs, enabled_irqs;
1071
1072 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
1073 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
1074
1075 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
1076
1077 mtp_ddi_hpd_detection_setup(i915);
1078 mtp_tc_hpd_detection_setup(i915);
1079}
1080
1081static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
1082{
1083 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
1084}
1085
1086static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915,
1087 enum hpd_pin hpd_pin, bool enable)
1088{
1089 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |
1090 XELPDP_DP_ALT_HOTPLUG_ENABLE;
1091
1092 if (!is_xelpdp_pica_hpd_pin(hpd_pin))
1093 return;
1094
1095 intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
1096 mask, enable ? mask : 0);
1097}
1098
1099static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder)
1100{
1101 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1102
1103 _xelpdp_pica_hpd_detection_setup(i915, encoder->hpd_pin, true);
1104}
1105
1106static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915)
1107{
1108 struct intel_encoder *encoder;
1109 u32 available_pins = 0;
1110 enum hpd_pin pin;
1111
1112 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS);
1113
1114 for_each_intel_encoder(&i915->drm, encoder)
1115 available_pins |= BIT(encoder->hpd_pin);
1116
1117 for_each_hpd_pin(pin)
1118 _xelpdp_pica_hpd_detection_setup(i915, pin, available_pins & BIT(pin));
1119}
1120
1121static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
1122{
1123 xelpdp_pica_hpd_enable_detection(encoder);
1124 mtp_hpd_enable_detection(encoder);
1125}
1126
1127static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
1128{
1129 u32 hotplug_irqs, enabled_irqs;
1130
1131 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd);
1132 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd);
1133
1134 intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs,
1135 ~enabled_irqs & hotplug_irqs);
1136 intel_uncore_posting_read(&i915->uncore, PICAINTERRUPT_IMR);
1137
1138 xelpdp_pica_hpd_detection_setup(i915);
1139
1140 if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
1141 xe2lpd_sde_hpd_irq_setup(i915);
1142 else if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
1143 mtp_hpd_irq_setup(i915);
1144}
1145
1146static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)
1147{
1148 switch (hpd_pin) {
1149 case HPD_PORT_A:
1150 return PORTA_HOTPLUG_ENABLE;
1151 case HPD_PORT_B:
1152 return PORTB_HOTPLUG_ENABLE;
1153 case HPD_PORT_C:
1154 return PORTC_HOTPLUG_ENABLE;
1155 case HPD_PORT_D:
1156 return PORTD_HOTPLUG_ENABLE;
1157 default:
1158 return 0;
1159 }
1160}
1161
1162static u32 spt_hotplug_enables(struct intel_encoder *encoder)
1163{
1164 return spt_hotplug_mask(encoder->hpd_pin);
1165}
1166
1167static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin)
1168{
1169 switch (hpd_pin) {
1170 case HPD_PORT_E:
1171 return PORTE_HOTPLUG_ENABLE;
1172 default:
1173 return 0;
1174 }
1175}
1176
1177static u32 spt_hotplug2_enables(struct intel_encoder *encoder)
1178{
1179 return spt_hotplug2_mask(encoder->hpd_pin);
1180}
1181
1182static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
1183{
1184 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1185 if (HAS_PCH_CNP(dev_priv)) {
1186 intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
1187 CHASSIS_CLK_REQ_DURATION(0xf));
1188 }
1189
1190 /* Enable digital hotplug on the PCH */
1191 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
1192 intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
1193 intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
1194
1195 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2,
1196 intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
1197 intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
1198}
1199
1200static void spt_hpd_enable_detection(struct intel_encoder *encoder)
1201{
1202 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1203
1204 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1205 if (HAS_PCH_CNP(i915)) {
1206 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1,
1207 CHASSIS_CLK_REQ_DURATION_MASK,
1208 CHASSIS_CLK_REQ_DURATION(0xf));
1209 }
1210
1211 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
1212 spt_hotplug_mask(encoder->hpd_pin),
1213 spt_hotplug_enables(encoder));
1214
1215 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG2,
1216 spt_hotplug2_mask(encoder->hpd_pin),
1217 spt_hotplug2_enables(encoder));
1218}
1219
1220static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
1221{
1222 u32 hotplug_irqs, enabled_irqs;
1223
1224 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1225 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
1226
1227 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
1228 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
1229
1230 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
1231
1232 spt_hpd_detection_setup(dev_priv);
1233}
1234
1235static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)
1236{
1237 switch (hpd_pin) {
1238 case HPD_PORT_A:
1239 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1240 DIGITAL_PORTA_PULSE_DURATION_MASK;
1241 default:
1242 return 0;
1243 }
1244}
1245
1246static u32 ilk_hotplug_enables(struct intel_encoder *encoder)
1247{
1248 switch (encoder->hpd_pin) {
1249 case HPD_PORT_A:
1250 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1251 DIGITAL_PORTA_PULSE_DURATION_2ms;
1252 default:
1253 return 0;
1254 }
1255}
1256
1257static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
1258{
1259 /*
1260 * Enable digital hotplug on the CPU, and configure the DP short pulse
1261 * duration to 2ms (which is the minimum in the Display Port spec)
1262 * The pulse duration bits are reserved on HSW+.
1263 */
1264 intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
1265 intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
1266 intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
1267}
1268
1269static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
1270{
1271 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1272
1273 intel_uncore_rmw(&i915->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
1274 ilk_hotplug_mask(encoder->hpd_pin),
1275 ilk_hotplug_enables(encoder));
1276
1277 ibx_hpd_enable_detection(encoder);
1278}
1279
1280static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
1281{
1282 u32 hotplug_irqs, enabled_irqs;
1283
1284 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1285 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1286
1287 if (DISPLAY_VER(dev_priv) >= 8)
1288 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
1289 else
1290 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
1291
1292 ilk_hpd_detection_setup(dev_priv);
1293
1294 ibx_hpd_irq_setup(dev_priv);
1295}
1296
1297static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)
1298{
1299 switch (hpd_pin) {
1300 case HPD_PORT_A:
1301 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT;
1302 case HPD_PORT_B:
1303 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT;
1304 case HPD_PORT_C:
1305 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT;
1306 default:
1307 return 0;
1308 }
1309}
1310
1311static u32 bxt_hotplug_enables(struct intel_encoder *encoder)
1312{
1313 u32 hotplug;
1314
1315 switch (encoder->hpd_pin) {
1316 case HPD_PORT_A:
1317 hotplug = PORTA_HOTPLUG_ENABLE;
1318 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1319 hotplug |= BXT_DDIA_HPD_INVERT;
1320 return hotplug;
1321 case HPD_PORT_B:
1322 hotplug = PORTB_HOTPLUG_ENABLE;
1323 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1324 hotplug |= BXT_DDIB_HPD_INVERT;
1325 return hotplug;
1326 case HPD_PORT_C:
1327 hotplug = PORTC_HOTPLUG_ENABLE;
1328 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1329 hotplug |= BXT_DDIC_HPD_INVERT;
1330 return hotplug;
1331 default:
1332 return 0;
1333 }
1334}
1335
1336static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
1337{
1338 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
1339 intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
1340 intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
1341}
1342
1343static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
1344{
1345 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1346
1347 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
1348 bxt_hotplug_mask(encoder->hpd_pin),
1349 bxt_hotplug_enables(encoder));
1350}
1351
1352static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
1353{
1354 u32 hotplug_irqs, enabled_irqs;
1355
1356 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1357 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1358
1359 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
1360
1361 bxt_hpd_detection_setup(dev_priv);
1362}
1363
1364static void g45_hpd_peg_band_gap_wa(struct drm_i915_private *i915)
1365{
1366 /*
1367 * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1368 * 0xd. Failure to do so will result in spurious interrupts being
1369 * generated on the port when a cable is not attached.
1370 */
1371 intel_de_rmw(i915, PEG_BAND_GAP_DATA, 0xf, 0xd);
1372}
1373
1374static void i915_hpd_enable_detection(struct intel_encoder *encoder)
1375{
1376 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1377 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];
1378
1379 if (IS_G45(i915))
1380 g45_hpd_peg_band_gap_wa(i915);
1381
1382 /* HPD sense and interrupt enable are one and the same */
1383 i915_hotplug_interrupt_update(i915, hotplug_en, hotplug_en);
1384}
1385
1386static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
1387{
1388 u32 hotplug_en;
1389
1390 lockdep_assert_held(&dev_priv->irq_lock);
1391
1392 /*
1393 * Note HDMI and DP share hotplug bits. Enable bits are the same for all
1394 * generations.
1395 */
1396 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
1397 /*
1398 * Programming the CRT detection parameters tends to generate a spurious
1399 * hotplug event about three seconds later. So just do it once.
1400 */
1401 if (IS_G4X(dev_priv))
1402 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1403 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1404
1405 if (IS_G45(dev_priv))
1406 g45_hpd_peg_band_gap_wa(dev_priv);
1407
1408 /* Ignore TV since it's buggy */
1409 i915_hotplug_interrupt_update_locked(dev_priv,
1410 HOTPLUG_INT_EN_MASK |
1411 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
1412 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
1413 hotplug_en);
1414}
1415
1416struct intel_hotplug_funcs {
1417 /* Enable HPD sense and interrupts for all present encoders */
1418 void (*hpd_irq_setup)(struct drm_i915_private *i915);
1419 /* Enable HPD sense for a single encoder */
1420 void (*hpd_enable_detection)(struct intel_encoder *encoder);
1421};
1422
1423#define HPD_FUNCS(platform) \
1424static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
1425 .hpd_irq_setup = platform##_hpd_irq_setup, \
1426 .hpd_enable_detection = platform##_hpd_enable_detection, \
1427}
1428
1429HPD_FUNCS(i915);
1430HPD_FUNCS(xelpdp);
1431HPD_FUNCS(dg1);
1432HPD_FUNCS(gen11);
1433HPD_FUNCS(bxt);
1434HPD_FUNCS(icp);
1435HPD_FUNCS(spt);
1436HPD_FUNCS(ilk);
1437#undef HPD_FUNCS
1438
1439void intel_hpd_enable_detection(struct intel_encoder *encoder)
1440{
1441 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1442
1443 if (i915->display.funcs.hotplug)
1444 i915->display.funcs.hotplug->hpd_enable_detection(encoder);
1445}
1446
1447void intel_hpd_irq_setup(struct drm_i915_private *i915)
1448{
1449 if (i915->display_irqs_enabled && i915->display.funcs.hotplug)
1450 i915->display.funcs.hotplug->hpd_irq_setup(i915);
1451}
1452
1453void intel_hotplug_irq_init(struct drm_i915_private *i915)
1454{
1455 intel_hpd_init_pins(i915);
1456
1457 intel_hpd_init_early(i915);
1458
1459 if (HAS_GMCH(i915)) {
1460 if (I915_HAS_HOTPLUG(i915))
1461 i915->display.funcs.hotplug = &i915_hpd_funcs;
1462 } else {
1463 if (HAS_PCH_DG2(i915))
1464 i915->display.funcs.hotplug = &icp_hpd_funcs;
1465 else if (HAS_PCH_DG1(i915))
1466 i915->display.funcs.hotplug = &dg1_hpd_funcs;
1467 else if (DISPLAY_VER(i915) >= 14)
1468 i915->display.funcs.hotplug = &xelpdp_hpd_funcs;
1469 else if (DISPLAY_VER(i915) >= 11)
1470 i915->display.funcs.hotplug = &gen11_hpd_funcs;
1471 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1472 i915->display.funcs.hotplug = &bxt_hpd_funcs;
1473 else if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
1474 i915->display.funcs.hotplug = &icp_hpd_funcs;
1475 else if (INTEL_PCH_TYPE(i915) >= PCH_SPT)
1476 i915->display.funcs.hotplug = &spt_hpd_funcs;
1477 else
1478 i915->display.funcs.hotplug = &ilk_hpd_funcs;
1479 }
1480}