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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 *
4 * This file defines the common audio settings for the child boards
5 * using rt5682 codec.
6 *
7 * Copyright 2022 Google LLC.
8 */
9
10/ {
11 /* BOARD-SPECIFIC TOP LEVEL NODES */
12 sound: sound {
13 compatible = "google,sc7280-herobrine";
14 model = "sc7280-rt5682-max98360a-1mic";
15
16 audio-routing = "Headphone Jack", "HPOL",
17 "Headphone Jack", "HPOR";
18
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 dai-link@0 {
23 link-name = "MAX98360";
24 reg = <0>;
25
26 cpu {
27 sound-dai = <&lpass_cpu MI2S_SECONDARY>;
28 };
29
30 codec {
31 sound-dai = <&max98360a>;
32 };
33 };
34
35 dai-link@1 {
36 link-name = "DisplayPort";
37 reg = <1>;
38
39 cpu {
40 sound-dai = <&lpass_cpu LPASS_DP_RX>;
41 };
42
43 codec {
44 sound-dai = <&mdss_dp>;
45 };
46 };
47
48 dai-link@2 {
49 link-name = "ALC5682";
50 reg = <2>;
51
52 cpu {
53 sound-dai = <&lpass_cpu MI2S_PRIMARY>;
54 };
55
56 codec {
57 sound-dai = <&alc5682 0 /* aif1 */>;
58 };
59 };
60 };
61};
62
63hp_i2c: &i2c2 {
64 clock-frequency = <400000>;
65 status = "okay";
66
67 alc5682: codec@1a {
68 compatible = "realtek,rt5682s";
69 reg = <0x1a>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&hp_irq>;
72
73 #sound-dai-cells = <1>;
74
75 interrupt-parent = <&tlmm>;
76 interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
77
78 AVDD-supply = <&pp1800_alc5682>;
79 DBVDD-supply = <&pp1800_alc5682>;
80 LDO1-IN-supply = <&pp1800_alc5682>;
81 MICVDD-supply = <&pp3300_codec>;
82
83 realtek,dmic1-data-pin = <1>;
84 realtek,dmic1-clk-pin = <2>;
85 realtek,jd-src = <1>;
86 realtek,dmic-clk-rate-hz = <2048000>;
87 };
88};
89
90&lpass_cpu {
91 pinctrl-names = "default";
92 pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
93 <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
94
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 status = "okay";
99
100 dai-link@0 {
101 reg = <MI2S_PRIMARY>;
102 qcom,playback-sd-lines = <1>;
103 qcom,capture-sd-lines = <0>;
104 };
105
106 dai-link@1 {
107 reg = <MI2S_SECONDARY>;
108 qcom,playback-sd-lines = <0>;
109 };
110
111 dai-link@5 {
112 reg = <LPASS_DP_RX>;
113 };
114};
115
116/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
117
118&mi2s0_data0 {
119 drive-strength = <6>;
120 bias-disable;
121};
122
123&mi2s0_data1 {
124 drive-strength = <6>;
125 bias-disable;
126};
127
128&mi2s0_mclk {
129 drive-strength = <6>;
130 bias-disable;
131};
132
133&mi2s0_sclk {
134 drive-strength = <6>;
135 bias-disable;
136};
137
138&mi2s0_ws {
139 drive-strength = <6>;
140 bias-disable;
141};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 *
4 * This file defines the common audio settings for the child boards
5 * using rt5682 codec.
6 *
7 * Copyright 2022 Google LLC.
8 */
9
10/ {
11 /* BOARD-SPECIFIC TOP LEVEL NODES */
12 sound: sound {
13 compatible = "google,sc7280-herobrine";
14 model = "sc7280-rt5682-max98360a-1mic";
15
16 audio-routing = "Headphone Jack", "HPOL",
17 "Headphone Jack", "HPOR";
18
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 dai-link@0 {
23 link-name = "MAX98360";
24 reg = <0>;
25
26 cpu {
27 sound-dai = <&lpass_cpu MI2S_SECONDARY>;
28 };
29
30 codec {
31 sound-dai = <&max98360a>;
32 };
33 };
34
35 dai-link@1 {
36 link-name = "DisplayPort";
37 reg = <1>;
38
39 cpu {
40 sound-dai = <&lpass_cpu LPASS_DP_RX>;
41 };
42
43 codec {
44 sound-dai = <&mdss_dp>;
45 };
46 };
47
48 dai-link@2 {
49 link-name = "ALC5682";
50 reg = <2>;
51
52 cpu {
53 sound-dai = <&lpass_cpu MI2S_PRIMARY>;
54 };
55
56 codec {
57 sound-dai = <&alc5682 0 /* aif1 */>;
58 };
59 };
60 };
61};
62
63hp_i2c: &i2c2 {
64 clock-frequency = <400000>;
65 status = "okay";
66
67 alc5682: codec@1a {
68 compatible = "realtek,rt5682s";
69 reg = <0x1a>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&hp_irq>;
72
73 #sound-dai-cells = <1>;
74
75 interrupt-parent = <&tlmm>;
76 interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
77
78 AVDD-supply = <&pp1800_alc5682>;
79 DBVDD-supply = <&pp1800_alc5682>;
80 LDO1-IN-supply = <&pp1800_alc5682>;
81 MICVDD-supply = <&pp3300_codec>;
82
83 realtek,dmic1-data-pin = <1>;
84 realtek,dmic1-clk-pin = <2>;
85 realtek,jd-src = <1>;
86 realtek,dmic-clk-rate-hz = <2048000>;
87 };
88};
89
90&lpass_cpu {
91 pinctrl-names = "default";
92 pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
93 <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
94
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 status = "okay";
99
100 dai-link@0 {
101 reg = <MI2S_PRIMARY>;
102 qcom,playback-sd-lines = <1>;
103 qcom,capture-sd-lines = <0>;
104 };
105
106 dai-link@1 {
107 reg = <MI2S_SECONDARY>;
108 qcom,playback-sd-lines = <0>;
109 };
110
111 dai-link@5 {
112 reg = <LPASS_DP_RX>;
113 };
114};
115
116/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
117
118&mi2s0_data0 {
119 drive-strength = <6>;
120 bias-disable;
121};
122
123&mi2s0_data1 {
124 drive-strength = <6>;
125 bias-disable;
126};
127
128&mi2s0_mclk {
129 drive-strength = <6>;
130 bias-disable;
131};
132
133&mi2s0_sclk {
134 drive-strength = <6>;
135 bias-disable;
136};
137
138&mi2s0_ws {
139 drive-strength = <6>;
140 bias-disable;
141};