1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 *  linux/arch/arm/mm/tlbv4wb.S
 4 *
 5 *  Copyright (C) 1997-2002 Russell King
 6 *
 7 *  ARM architecture version 4 TLB handling functions.
 8 *  These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
 9 *
10 *  Processors: SA110 SA1100 SA1110
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <linux/cfi_types.h>
15#include <asm/assembler.h>
16#include <asm/asm-offsets.h>
17#include <asm/tlbflush.h>
18#include "proc-macros.S"
19
20	.align	5
21/*
22 *	v4wb_flush_user_tlb_range(start, end, mm)
23 *
24 *	Invalidate a range of TLB entries in the specified address space.
25 *
26 *	- start - range start address
27 *	- end   - range end address
28 *	- mm    - mm_struct describing address space
29 */
30	.align	5
31SYM_TYPED_FUNC_START(v4wb_flush_user_tlb_range)
32	vma_vm_mm ip, r2
33	act_mm	r3				@ get current->active_mm
34	eors	r3, ip, r3				@ == mm ?
35	retne	lr				@ no, we dont do anything
36	vma_vm_flags r2, r2
37	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
38	tst	r2, #VM_EXEC
39	mcrne	p15, 0, r3, c8, c5, 0		@ invalidate I TLB
40	bic	r0, r0, #0x0ff
41	bic	r0, r0, #0xf00
421:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
43	add	r0, r0, #PAGE_SZ
44	cmp	r0, r1
45	blo	1b
46	ret	lr
47SYM_FUNC_END(v4wb_flush_user_tlb_range)
48
49/*
50 *	v4_flush_kern_tlb_range(start, end)
51 *
52 *	Invalidate a range of TLB entries in the specified kernel
53 *	address range.
54 *
55 *	- start - virtual address (may not be aligned)
56 *	- end   - virtual address (may not be aligned)
57 */
58SYM_TYPED_FUNC_START(v4wb_flush_kern_tlb_range)
59	mov	r3, #0
60	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
61	bic	r0, r0, #0x0ff
62	bic	r0, r0, #0xf00
63	mcr	p15, 0, r3, c8, c5, 0		@ invalidate I TLB
641:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
65	add	r0, r0, #PAGE_SZ
66	cmp	r0, r1
67	blo	1b
68	ret	lr
69SYM_FUNC_END(v4wb_flush_kern_tlb_range)
 
 
 
 

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 *  linux/arch/arm/mm/tlbv4wb.S
 4 *
 5 *  Copyright (C) 1997-2002 Russell King
 6 *
 7 *  ARM architecture version 4 TLB handling functions.
 8 *  These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
 9 *
10 *  Processors: SA110 SA1100 SA1110
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
 
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/tlbflush.h>
17#include "proc-macros.S"
18
19	.align	5
20/*
21 *	v4wb_flush_user_tlb_range(start, end, mm)
22 *
23 *	Invalidate a range of TLB entries in the specified address space.
24 *
25 *	- start - range start address
26 *	- end   - range end address
27 *	- mm    - mm_struct describing address space
28 */
29	.align	5
30ENTRY(v4wb_flush_user_tlb_range)
31	vma_vm_mm ip, r2
32	act_mm	r3				@ get current->active_mm
33	eors	r3, ip, r3				@ == mm ?
34	retne	lr				@ no, we dont do anything
35	vma_vm_flags r2, r2
36	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
37	tst	r2, #VM_EXEC
38	mcrne	p15, 0, r3, c8, c5, 0		@ invalidate I TLB
39	bic	r0, r0, #0x0ff
40	bic	r0, r0, #0xf00
411:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
42	add	r0, r0, #PAGE_SZ
43	cmp	r0, r1
44	blo	1b
45	ret	lr
 
46
47/*
48 *	v4_flush_kern_tlb_range(start, end)
49 *
50 *	Invalidate a range of TLB entries in the specified kernel
51 *	address range.
52 *
53 *	- start - virtual address (may not be aligned)
54 *	- end   - virtual address (may not be aligned)
55 */
56ENTRY(v4wb_flush_kern_tlb_range)
57	mov	r3, #0
58	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
59	bic	r0, r0, #0x0ff
60	bic	r0, r0, #0xf00
61	mcr	p15, 0, r3, c8, c5, 0		@ invalidate I TLB
621:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
63	add	r0, r0, #PAGE_SZ
64	cmp	r0, r1
65	blo	1b
66	ret	lr
67
68	__INITDATA
69
70	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
71	define_tlb_functions v4wb, v4wb_tlb_flags