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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
4 *
5 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
6 * Rob Scott (rscott@mtrob.fdns.net)
7 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
8 * hacked for non-paged-MM by Hyok S. Choi, 2004.
9 *
10 * These are the low level assembler for performing cache and TLB
11 * functions on the ARM720T. The ARM720T has a writethrough IDC
12 * cache, so we don't need to clean it.
13 *
14 * Changelog:
15 * 05-09-2000 SJH Created by moving 720 specific functions
16 * out of 'proc-arm6,7.S' per RMK discussion
17 * 07-25-2000 SJH Added idle function.
18 * 08-25-2000 DBS Updated for integration of ARM Ltd version.
19 * 04-20-2004 HSC modified for non-paged memory management mode.
20 */
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <linux/cfi_types.h>
24#include <linux/pgtable.h>
25#include <asm/assembler.h>
26#include <asm/asm-offsets.h>
27#include <asm/hwcap.h>
28#include <asm/pgtable-hwdef.h>
29#include <asm/ptrace.h>
30
31#include "proc-macros.S"
32
33/*
34 * Function: arm720_proc_init (void)
35 * : arm720_proc_fin (void)
36 *
37 * Notes : This processor does not require these
38 */
39SYM_TYPED_FUNC_START(cpu_arm720_dcache_clean_area)
40 ret lr
41SYM_FUNC_END(cpu_arm720_dcache_clean_area)
42
43SYM_TYPED_FUNC_START(cpu_arm720_proc_init)
44 ret lr
45SYM_FUNC_END(cpu_arm720_proc_init)
46
47SYM_TYPED_FUNC_START(cpu_arm720_proc_fin)
48 mrc p15, 0, r0, c1, c0, 0
49 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x000e @ ............wca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 ret lr
53SYM_FUNC_END(cpu_arm720_proc_fin)
54
55/*
56 * Function: arm720_proc_do_idle(void)
57 * Params : r0 = unused
58 * Purpose : put the processor in proper idle mode
59 */
60SYM_TYPED_FUNC_START(cpu_arm720_do_idle)
61 ret lr
62SYM_FUNC_END(cpu_arm720_do_idle)
63
64/*
65 * Function: arm720_switch_mm(unsigned long pgd_phys)
66 * Params : pgd_phys Physical address of page table
67 * Purpose : Perform a task switch, saving the old process' state and restoring
68 * the new.
69 */
70SYM_TYPED_FUNC_START(cpu_arm720_switch_mm)
71#ifdef CONFIG_MMU
72 mov r1, #0
73 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
74 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
75 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
76#endif
77 ret lr
78SYM_FUNC_END(cpu_arm720_switch_mm)
79
80/*
81 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
82 * Params : r0 = Address to set
83 * : r1 = value to set
84 * Purpose : Set a PTE and flush it out of any WB cache
85 */
86 .align 5
87SYM_TYPED_FUNC_START(cpu_arm720_set_pte_ext)
88#ifdef CONFIG_MMU
89 armv3_set_pte_ext wc_disable=0
90#endif
91 ret lr
92SYM_FUNC_END(cpu_arm720_set_pte_ext)
93
94/*
95 * Function: arm720_reset
96 * Params : r0 = address to jump to
97 * Notes : This sets up everything for a reset
98 */
99 .pushsection .idmap.text, "ax"
100SYM_TYPED_FUNC_START(cpu_arm720_reset)
101 mov ip, #0
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
103#ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
105#endif
106 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
107 bic ip, ip, #0x000f @ ............wcam
108 bic ip, ip, #0x2100 @ ..v....s........
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
110 ret r0
111SYM_FUNC_END(cpu_arm720_reset)
112 .popsection
113
114 .type __arm710_setup, #function
115__arm710_setup:
116 mov r0, #0
117 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
118#ifdef CONFIG_MMU
119 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
120#endif
121 mrc p15, 0, r0, c1, c0 @ get control register
122 ldr r5, arm710_cr1_clear
123 bic r0, r0, r5
124 ldr r5, arm710_cr1_set
125 orr r0, r0, r5
126 ret lr @ __ret (head.S)
127 .size __arm710_setup, . - __arm710_setup
128
129 /*
130 * R
131 * .RVI ZFRS BLDP WCAM
132 * .... 0001 ..11 1101
133 *
134 */
135 .type arm710_cr1_clear, #object
136 .type arm710_cr1_set, #object
137arm710_cr1_clear:
138 .word 0x0f3f
139arm710_cr1_set:
140 .word 0x013d
141
142 .type __arm720_setup, #function
143__arm720_setup:
144 mov r0, #0
145 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
146#ifdef CONFIG_MMU
147 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
148#endif
149 adr r5, arm720_crval
150 ldmia r5, {r5, r6}
151 mrc p15, 0, r0, c1, c0 @ get control register
152 bic r0, r0, r5
153 orr r0, r0, r6
154 ret lr @ __ret (head.S)
155 .size __arm720_setup, . - __arm720_setup
156
157 /*
158 * R
159 * .RVI ZFRS BLDP WCAM
160 * ..1. 1001 ..11 1101
161 *
162 */
163 .type arm720_crval, #object
164arm720_crval:
165 crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
166
167 __INITDATA
168 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
169 define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort
170
171 .section ".rodata"
172
173 string cpu_arch_name, "armv4t"
174 string cpu_elf_name, "v4"
175 string cpu_arm710_name, "ARM710T"
176 string cpu_arm720_name, "ARM720T"
177
178 .align
179
180/*
181 * See <asm/procinfo.h> for a definition of this structure.
182 */
183
184 .section ".proc.info.init", "a"
185
186.macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
187 .type __\name\()_proc_info,#object
188__\name\()_proc_info:
189 .long \cpu_val
190 .long \cpu_mask
191 .long PMD_TYPE_SECT | \
192 PMD_SECT_BUFFERABLE | \
193 PMD_SECT_CACHEABLE | \
194 PMD_BIT4 | \
195 PMD_SECT_AP_WRITE | \
196 PMD_SECT_AP_READ
197 .long PMD_TYPE_SECT | \
198 PMD_BIT4 | \
199 PMD_SECT_AP_WRITE | \
200 PMD_SECT_AP_READ
201 initfn \cpu_flush, __\name\()_proc_info @ cpu_flush
202 .long cpu_arch_name @ arch_name
203 .long cpu_elf_name @ elf_name
204 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap
205 .long \cpu_name
206 .long arm720_processor_functions
207 .long v4_tlb_fns
208 .long v4wt_user_fns
209 .long v4_cache_fns
210 .size __\name\()_proc_info, . - __\name\()_proc_info
211.endm
212
213 arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
214 arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
4 *
5 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
6 * Rob Scott (rscott@mtrob.fdns.net)
7 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
8 * hacked for non-paged-MM by Hyok S. Choi, 2004.
9 *
10 * These are the low level assembler for performing cache and TLB
11 * functions on the ARM720T. The ARM720T has a writethrough IDC
12 * cache, so we don't need to clean it.
13 *
14 * Changelog:
15 * 05-09-2000 SJH Created by moving 720 specific functions
16 * out of 'proc-arm6,7.S' per RMK discussion
17 * 07-25-2000 SJH Added idle function.
18 * 08-25-2000 DBS Updated for integration of ARM Ltd version.
19 * 04-20-2004 HSC modified for non-paged memory management mode.
20 */
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <linux/pgtable.h>
24#include <asm/assembler.h>
25#include <asm/asm-offsets.h>
26#include <asm/hwcap.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/ptrace.h>
29
30#include "proc-macros.S"
31
32/*
33 * Function: arm720_proc_init (void)
34 * : arm720_proc_fin (void)
35 *
36 * Notes : This processor does not require these
37 */
38ENTRY(cpu_arm720_dcache_clean_area)
39ENTRY(cpu_arm720_proc_init)
40 ret lr
41
42ENTRY(cpu_arm720_proc_fin)
43 mrc p15, 0, r0, c1, c0, 0
44 bic r0, r0, #0x1000 @ ...i............
45 bic r0, r0, #0x000e @ ............wca.
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
47 ret lr
48
49/*
50 * Function: arm720_proc_do_idle(void)
51 * Params : r0 = unused
52 * Purpose : put the processor in proper idle mode
53 */
54ENTRY(cpu_arm720_do_idle)
55 ret lr
56
57/*
58 * Function: arm720_switch_mm(unsigned long pgd_phys)
59 * Params : pgd_phys Physical address of page table
60 * Purpose : Perform a task switch, saving the old process' state and restoring
61 * the new.
62 */
63ENTRY(cpu_arm720_switch_mm)
64#ifdef CONFIG_MMU
65 mov r1, #0
66 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
67 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
68 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
69#endif
70 ret lr
71
72/*
73 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
74 * Params : r0 = Address to set
75 * : r1 = value to set
76 * Purpose : Set a PTE and flush it out of any WB cache
77 */
78 .align 5
79ENTRY(cpu_arm720_set_pte_ext)
80#ifdef CONFIG_MMU
81 armv3_set_pte_ext wc_disable=0
82#endif
83 ret lr
84
85/*
86 * Function: arm720_reset
87 * Params : r0 = address to jump to
88 * Notes : This sets up everything for a reset
89 */
90 .pushsection .idmap.text, "ax"
91ENTRY(cpu_arm720_reset)
92 mov ip, #0
93 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
94#ifdef CONFIG_MMU
95 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
96#endif
97 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
98 bic ip, ip, #0x000f @ ............wcam
99 bic ip, ip, #0x2100 @ ..v....s........
100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
101 ret r0
102ENDPROC(cpu_arm720_reset)
103 .popsection
104
105 .type __arm710_setup, #function
106__arm710_setup:
107 mov r0, #0
108 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
109#ifdef CONFIG_MMU
110 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
111#endif
112 mrc p15, 0, r0, c1, c0 @ get control register
113 ldr r5, arm710_cr1_clear
114 bic r0, r0, r5
115 ldr r5, arm710_cr1_set
116 orr r0, r0, r5
117 ret lr @ __ret (head.S)
118 .size __arm710_setup, . - __arm710_setup
119
120 /*
121 * R
122 * .RVI ZFRS BLDP WCAM
123 * .... 0001 ..11 1101
124 *
125 */
126 .type arm710_cr1_clear, #object
127 .type arm710_cr1_set, #object
128arm710_cr1_clear:
129 .word 0x0f3f
130arm710_cr1_set:
131 .word 0x013d
132
133 .type __arm720_setup, #function
134__arm720_setup:
135 mov r0, #0
136 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
137#ifdef CONFIG_MMU
138 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
139#endif
140 adr r5, arm720_crval
141 ldmia r5, {r5, r6}
142 mrc p15, 0, r0, c1, c0 @ get control register
143 bic r0, r0, r5
144 orr r0, r0, r6
145 ret lr @ __ret (head.S)
146 .size __arm720_setup, . - __arm720_setup
147
148 /*
149 * R
150 * .RVI ZFRS BLDP WCAM
151 * ..1. 1001 ..11 1101
152 *
153 */
154 .type arm720_crval, #object
155arm720_crval:
156 crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
157
158 __INITDATA
159 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
160 define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort
161
162 .section ".rodata"
163
164 string cpu_arch_name, "armv4t"
165 string cpu_elf_name, "v4"
166 string cpu_arm710_name, "ARM710T"
167 string cpu_arm720_name, "ARM720T"
168
169 .align
170
171/*
172 * See <asm/procinfo.h> for a definition of this structure.
173 */
174
175 .section ".proc.info.init", "a"
176
177.macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
178 .type __\name\()_proc_info,#object
179__\name\()_proc_info:
180 .long \cpu_val
181 .long \cpu_mask
182 .long PMD_TYPE_SECT | \
183 PMD_SECT_BUFFERABLE | \
184 PMD_SECT_CACHEABLE | \
185 PMD_BIT4 | \
186 PMD_SECT_AP_WRITE | \
187 PMD_SECT_AP_READ
188 .long PMD_TYPE_SECT | \
189 PMD_BIT4 | \
190 PMD_SECT_AP_WRITE | \
191 PMD_SECT_AP_READ
192 initfn \cpu_flush, __\name\()_proc_info @ cpu_flush
193 .long cpu_arch_name @ arch_name
194 .long cpu_elf_name @ elf_name
195 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap
196 .long \cpu_name
197 .long arm720_processor_functions
198 .long v4_tlb_fns
199 .long v4wt_user_fns
200 .long v4_cache_fns
201 .size __\name\()_proc_info, . - __\name\()_proc_info
202.endm
203
204 arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
205 arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup