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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
4 *
5 * Copyright (C) 2000 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 *
9 * These are the low level assembler for performing cache and TLB
10 * functions on the arm1020.
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <linux/cfi_types.h>
15#include <linux/pgtable.h>
16#include <asm/assembler.h>
17#include <asm/asm-offsets.h>
18#include <asm/hwcap.h>
19#include <asm/pgtable-hwdef.h>
20#include <asm/ptrace.h>
21
22#include "proc-macros.S"
23
24/*
25 * This is the maximum size of an area which will be invalidated
26 * using the single invalidate entry instructions. Anything larger
27 * than this, and we go for the whole cache.
28 *
29 * This value should be chosen such that we choose the cheapest
30 * alternative.
31 */
32#define MAX_AREA_SIZE 32768
33
34/*
35 * The size of one data cache line.
36 */
37#define CACHE_DLINESIZE 32
38
39/*
40 * The number of data cache segments.
41 */
42#define CACHE_DSEGMENTS 16
43
44/*
45 * The number of lines in a cache segment.
46 */
47#define CACHE_DENTRIES 64
48
49/*
50 * This is the size at which it becomes more efficient to
51 * clean the whole cache, rather than using the individual
52 * cache line maintenance instructions.
53 */
54#define CACHE_DLIMIT 32768
55
56 .text
57/*
58 * cpu_arm1020_proc_init()
59 */
60SYM_TYPED_FUNC_START(cpu_arm1020_proc_init)
61 ret lr
62SYM_FUNC_END(cpu_arm1020_proc_init)
63
64/*
65 * cpu_arm1020_proc_fin()
66 */
67SYM_TYPED_FUNC_START(cpu_arm1020_proc_fin)
68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 bic r0, r0, #0x1000 @ ...i............
70 bic r0, r0, #0x000e @ ............wca.
71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 ret lr
73SYM_FUNC_END(cpu_arm1020_proc_fin)
74
75/*
76 * cpu_arm1020_reset(loc)
77 *
78 * Perform a soft reset of the system. Put the CPU into the
79 * same state as it would be if it had been reset, and branch
80 * to what would be the reset vector.
81 *
82 * loc: location to jump to for soft reset
83 */
84 .align 5
85 .pushsection .idmap.text, "ax"
86SYM_TYPED_FUNC_START(cpu_arm1020_reset)
87 mov ip, #0
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
90#ifdef CONFIG_MMU
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
92#endif
93 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
94 bic ip, ip, #0x000f @ ............wcam
95 bic ip, ip, #0x1100 @ ...i...s........
96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
97 ret r0
98SYM_FUNC_END(cpu_arm1020_reset)
99 .popsection
100
101/*
102 * cpu_arm1020_do_idle()
103 */
104 .align 5
105SYM_TYPED_FUNC_START(cpu_arm1020_do_idle)
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
107 ret lr
108SYM_FUNC_END(cpu_arm1020_do_idle)
109
110/* ================================= CACHE ================================ */
111
112 .align 5
113
114/*
115 * flush_icache_all()
116 *
117 * Unconditionally clean and invalidate the entire icache.
118 */
119SYM_TYPED_FUNC_START(arm1020_flush_icache_all)
120#ifndef CONFIG_CPU_ICACHE_DISABLE
121 mov r0, #0
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
123#endif
124 ret lr
125SYM_FUNC_END(arm1020_flush_icache_all)
126
127/*
128 * flush_user_cache_all()
129 *
130 * Invalidate all cache entries in a particular address
131 * space.
132 */
133SYM_FUNC_ALIAS(arm1020_flush_user_cache_all, arm1020_flush_kern_cache_all)
134
135/*
136 * flush_kern_cache_all()
137 *
138 * Clean and invalidate the entire cache.
139 */
140SYM_TYPED_FUNC_START(arm1020_flush_kern_cache_all)
141 mov r2, #VM_EXEC
142 mov ip, #0
143__flush_whole_cache:
144#ifndef CONFIG_CPU_DCACHE_DISABLE
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
146 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
1471: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1482: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
149 mcr p15, 0, ip, c7, c10, 4 @ drain WB
150 subs r3, r3, #1 << 26
151 bcs 2b @ entries 63 to 0
152 subs r1, r1, #1 << 5
153 bcs 1b @ segments 15 to 0
154#endif
155 tst r2, #VM_EXEC
156#ifndef CONFIG_CPU_ICACHE_DISABLE
157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
158#endif
159 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
160 ret lr
161SYM_FUNC_END(arm1020_flush_kern_cache_all)
162
163/*
164 * flush_user_cache_range(start, end, flags)
165 *
166 * Invalidate a range of cache entries in the specified
167 * address space.
168 *
169 * - start - start address (inclusive)
170 * - end - end address (exclusive)
171 * - flags - vm_flags for this space
172 */
173SYM_TYPED_FUNC_START(arm1020_flush_user_cache_range)
174 mov ip, #0
175 sub r3, r1, r0 @ calculate total size
176 cmp r3, #CACHE_DLIMIT
177 bhs __flush_whole_cache
178
179#ifndef CONFIG_CPU_DCACHE_DISABLE
180 mcr p15, 0, ip, c7, c10, 4
1811: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
182 mcr p15, 0, ip, c7, c10, 4 @ drain WB
183 add r0, r0, #CACHE_DLINESIZE
184 cmp r0, r1
185 blo 1b
186#endif
187 tst r2, #VM_EXEC
188#ifndef CONFIG_CPU_ICACHE_DISABLE
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190#endif
191 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
192 ret lr
193SYM_FUNC_END(arm1020_flush_user_cache_range)
194
195/*
196 * coherent_kern_range(start, end)
197 *
198 * Ensure coherency between the Icache and the Dcache in the
199 * region described by start. If you have non-snooping
200 * Harvard caches, you need to implement this function.
201 *
202 * - start - virtual start address
203 * - end - virtual end address
204 */
205SYM_TYPED_FUNC_START(arm1020_coherent_kern_range)
206#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
207 b arm1020_coherent_user_range
208#endif
209SYM_FUNC_END(arm1020_coherent_kern_range)
210
211/*
212 * coherent_user_range(start, end)
213 *
214 * Ensure coherency between the Icache and the Dcache in the
215 * region described by start. If you have non-snooping
216 * Harvard caches, you need to implement this function.
217 *
218 * - start - virtual start address
219 * - end - virtual end address
220 */
221SYM_TYPED_FUNC_START(arm1020_coherent_user_range)
222 mov ip, #0
223 bic r0, r0, #CACHE_DLINESIZE - 1
224 mcr p15, 0, ip, c7, c10, 4
2251:
226#ifndef CONFIG_CPU_DCACHE_DISABLE
227 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
228 mcr p15, 0, ip, c7, c10, 4 @ drain WB
229#endif
230#ifndef CONFIG_CPU_ICACHE_DISABLE
231 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
232#endif
233 add r0, r0, #CACHE_DLINESIZE
234 cmp r0, r1
235 blo 1b
236 mcr p15, 0, ip, c7, c10, 4 @ drain WB
237 mov r0, #0
238 ret lr
239SYM_FUNC_END(arm1020_coherent_user_range)
240
241/*
242 * flush_kern_dcache_area(void *addr, size_t size)
243 *
244 * Ensure no D cache aliasing occurs, either with itself or
245 * the I cache
246 *
247 * - addr - kernel address
248 * - size - region size
249 */
250SYM_TYPED_FUNC_START(arm1020_flush_kern_dcache_area)
251 mov ip, #0
252#ifndef CONFIG_CPU_DCACHE_DISABLE
253 add r1, r0, r1
2541: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
255 mcr p15, 0, ip, c7, c10, 4 @ drain WB
256 add r0, r0, #CACHE_DLINESIZE
257 cmp r0, r1
258 blo 1b
259#endif
260 mcr p15, 0, ip, c7, c10, 4 @ drain WB
261 ret lr
262SYM_FUNC_END(arm1020_flush_kern_dcache_area)
263
264/*
265 * dma_inv_range(start, end)
266 *
267 * Invalidate (discard) the specified virtual address range.
268 * May not write back any entries. If 'start' or 'end'
269 * are not cache line aligned, those lines must be written
270 * back.
271 *
272 * - start - virtual start address
273 * - end - virtual end address
274 *
275 * (same as v4wb)
276 */
277arm1020_dma_inv_range:
278 mov ip, #0
279#ifndef CONFIG_CPU_DCACHE_DISABLE
280 tst r0, #CACHE_DLINESIZE - 1
281 bic r0, r0, #CACHE_DLINESIZE - 1
282 mcrne p15, 0, ip, c7, c10, 4
283 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
284 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
285 tst r1, #CACHE_DLINESIZE - 1
286 mcrne p15, 0, ip, c7, c10, 4
287 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
288 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
2891: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
290 add r0, r0, #CACHE_DLINESIZE
291 cmp r0, r1
292 blo 1b
293#endif
294 mcr p15, 0, ip, c7, c10, 4 @ drain WB
295 ret lr
296
297/*
298 * dma_clean_range(start, end)
299 *
300 * Clean the specified virtual address range.
301 *
302 * - start - virtual start address
303 * - end - virtual end address
304 *
305 * (same as v4wb)
306 */
307arm1020_dma_clean_range:
308 mov ip, #0
309#ifndef CONFIG_CPU_DCACHE_DISABLE
310 bic r0, r0, #CACHE_DLINESIZE - 1
3111: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
312 mcr p15, 0, ip, c7, c10, 4 @ drain WB
313 add r0, r0, #CACHE_DLINESIZE
314 cmp r0, r1
315 blo 1b
316#endif
317 mcr p15, 0, ip, c7, c10, 4 @ drain WB
318 ret lr
319
320/*
321 * dma_flush_range(start, end)
322 *
323 * Clean and invalidate the specified virtual address range.
324 *
325 * - start - virtual start address
326 * - end - virtual end address
327 */
328SYM_TYPED_FUNC_START(arm1020_dma_flush_range)
329 mov ip, #0
330#ifndef CONFIG_CPU_DCACHE_DISABLE
331 bic r0, r0, #CACHE_DLINESIZE - 1
332 mcr p15, 0, ip, c7, c10, 4
3331: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
334 mcr p15, 0, ip, c7, c10, 4 @ drain WB
335 add r0, r0, #CACHE_DLINESIZE
336 cmp r0, r1
337 blo 1b
338#endif
339 mcr p15, 0, ip, c7, c10, 4 @ drain WB
340 ret lr
341SYM_FUNC_END(arm1020_dma_flush_range)
342
343/*
344 * dma_map_area(start, size, dir)
345 * - start - kernel virtual start address
346 * - size - size of region
347 * - dir - DMA direction
348 */
349SYM_TYPED_FUNC_START(arm1020_dma_map_area)
350 add r1, r1, r0
351 cmp r2, #DMA_TO_DEVICE
352 beq arm1020_dma_clean_range
353 bcs arm1020_dma_inv_range
354 b arm1020_dma_flush_range
355SYM_FUNC_END(arm1020_dma_map_area)
356
357/*
358 * dma_unmap_area(start, size, dir)
359 * - start - kernel virtual start address
360 * - size - size of region
361 * - dir - DMA direction
362 */
363SYM_TYPED_FUNC_START(arm1020_dma_unmap_area)
364 ret lr
365SYM_FUNC_END(arm1020_dma_unmap_area)
366
367 .align 5
368SYM_TYPED_FUNC_START(cpu_arm1020_dcache_clean_area)
369#ifndef CONFIG_CPU_DCACHE_DISABLE
370 mov ip, #0
3711: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
372 mcr p15, 0, ip, c7, c10, 4 @ drain WB
373 add r0, r0, #CACHE_DLINESIZE
374 subs r1, r1, #CACHE_DLINESIZE
375 bhi 1b
376#endif
377 ret lr
378SYM_FUNC_END(cpu_arm1020_dcache_clean_area)
379
380/* =============================== PageTable ============================== */
381
382/*
383 * cpu_arm1020_switch_mm(pgd)
384 *
385 * Set the translation base pointer to be as described by pgd.
386 *
387 * pgd: new page tables
388 */
389 .align 5
390SYM_TYPED_FUNC_START(cpu_arm1020_switch_mm)
391#ifdef CONFIG_MMU
392#ifndef CONFIG_CPU_DCACHE_DISABLE
393 mcr p15, 0, r3, c7, c10, 4
394 mov r1, #0xF @ 16 segments
3951: mov r3, #0x3F @ 64 entries
3962: mov ip, r3, LSL #26 @ shift up entry
397 orr ip, ip, r1, LSL #5 @ shift in/up index
398 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
399 mov ip, #0
400 mcr p15, 0, ip, c7, c10, 4
401 subs r3, r3, #1
402 cmp r3, #0
403 bge 2b @ entries 3F to 0
404 subs r1, r1, #1
405 cmp r1, #0
406 bge 1b @ segments 15 to 0
407
408#endif
409 mov r1, #0
410#ifndef CONFIG_CPU_ICACHE_DISABLE
411 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
412#endif
413 mcr p15, 0, r1, c7, c10, 4 @ drain WB
414 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
415 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
416#endif /* CONFIG_MMU */
417 ret lr
418SYM_FUNC_END(cpu_arm1020_switch_mm)
419
420/*
421 * cpu_arm1020_set_pte(ptep, pte)
422 *
423 * Set a PTE and flush it out
424 */
425 .align 5
426SYM_TYPED_FUNC_START(cpu_arm1020_set_pte_ext)
427#ifdef CONFIG_MMU
428 armv3_set_pte_ext
429 mov r0, r0
430#ifndef CONFIG_CPU_DCACHE_DISABLE
431 mcr p15, 0, r0, c7, c10, 4
432 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
433#endif
434 mcr p15, 0, r0, c7, c10, 4 @ drain WB
435#endif /* CONFIG_MMU */
436 ret lr
437SYM_FUNC_END(cpu_arm1020_set_pte_ext)
438
439 .type __arm1020_setup, #function
440__arm1020_setup:
441 mov r0, #0
442 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
443 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
444#ifdef CONFIG_MMU
445 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
446#endif
447
448 adr r5, arm1020_crval
449 ldmia r5, {r5, r6}
450 mrc p15, 0, r0, c1, c0 @ get control register v4
451 bic r0, r0, r5
452 orr r0, r0, r6
453#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
454 orr r0, r0, #0x4000 @ .R.. .... .... ....
455#endif
456 ret lr
457 .size __arm1020_setup, . - __arm1020_setup
458
459 /*
460 * R
461 * .RVI ZFRS BLDP WCAM
462 * .011 1001 ..11 0101
463 */
464 .type arm1020_crval, #object
465arm1020_crval:
466 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
467
468 __INITDATA
469 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
470 define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
471
472
473 .section ".rodata"
474
475 string cpu_arch_name, "armv5t"
476 string cpu_elf_name, "v5"
477
478 .type cpu_arm1020_name, #object
479cpu_arm1020_name:
480 .ascii "ARM1020"
481#ifndef CONFIG_CPU_ICACHE_DISABLE
482 .ascii "i"
483#endif
484#ifndef CONFIG_CPU_DCACHE_DISABLE
485 .ascii "d"
486#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
487 .ascii "(wt)"
488#else
489 .ascii "(wb)"
490#endif
491#endif
492#ifndef CONFIG_CPU_BPREDICT_DISABLE
493 .ascii "B"
494#endif
495#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
496 .ascii "RR"
497#endif
498 .ascii "\0"
499 .size cpu_arm1020_name, . - cpu_arm1020_name
500
501 .align
502
503 .section ".proc.info.init", "a"
504
505 .type __arm1020_proc_info,#object
506__arm1020_proc_info:
507 .long 0x4104a200 @ ARM 1020T (Architecture v5T)
508 .long 0xff0ffff0
509 .long PMD_TYPE_SECT | \
510 PMD_SECT_AP_WRITE | \
511 PMD_SECT_AP_READ
512 .long PMD_TYPE_SECT | \
513 PMD_SECT_AP_WRITE | \
514 PMD_SECT_AP_READ
515 initfn __arm1020_setup, __arm1020_proc_info
516 .long cpu_arch_name
517 .long cpu_elf_name
518 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
519 .long cpu_arm1020_name
520 .long arm1020_processor_functions
521 .long v4wbi_tlb_fns
522 .long v4wb_user_fns
523 .long arm1020_cache_fns
524 .size __arm1020_proc_info, . - __arm1020_proc_info
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
4 *
5 * Copyright (C) 2000 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 *
9 * These are the low level assembler for performing cache and TLB
10 * functions on the arm1020.
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <linux/pgtable.h>
15#include <asm/assembler.h>
16#include <asm/asm-offsets.h>
17#include <asm/hwcap.h>
18#include <asm/pgtable-hwdef.h>
19#include <asm/ptrace.h>
20
21#include "proc-macros.S"
22
23/*
24 * This is the maximum size of an area which will be invalidated
25 * using the single invalidate entry instructions. Anything larger
26 * than this, and we go for the whole cache.
27 *
28 * This value should be chosen such that we choose the cheapest
29 * alternative.
30 */
31#define MAX_AREA_SIZE 32768
32
33/*
34 * The size of one data cache line.
35 */
36#define CACHE_DLINESIZE 32
37
38/*
39 * The number of data cache segments.
40 */
41#define CACHE_DSEGMENTS 16
42
43/*
44 * The number of lines in a cache segment.
45 */
46#define CACHE_DENTRIES 64
47
48/*
49 * This is the size at which it becomes more efficient to
50 * clean the whole cache, rather than using the individual
51 * cache line maintenance instructions.
52 */
53#define CACHE_DLIMIT 32768
54
55 .text
56/*
57 * cpu_arm1020_proc_init()
58 */
59ENTRY(cpu_arm1020_proc_init)
60 ret lr
61
62/*
63 * cpu_arm1020_proc_fin()
64 */
65ENTRY(cpu_arm1020_proc_fin)
66 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
67 bic r0, r0, #0x1000 @ ...i............
68 bic r0, r0, #0x000e @ ............wca.
69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
70 ret lr
71
72/*
73 * cpu_arm1020_reset(loc)
74 *
75 * Perform a soft reset of the system. Put the CPU into the
76 * same state as it would be if it had been reset, and branch
77 * to what would be the reset vector.
78 *
79 * loc: location to jump to for soft reset
80 */
81 .align 5
82 .pushsection .idmap.text, "ax"
83ENTRY(cpu_arm1020_reset)
84 mov ip, #0
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
87#ifdef CONFIG_MMU
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
89#endif
90 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
91 bic ip, ip, #0x000f @ ............wcam
92 bic ip, ip, #0x1100 @ ...i...s........
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
94 ret r0
95ENDPROC(cpu_arm1020_reset)
96 .popsection
97
98/*
99 * cpu_arm1020_do_idle()
100 */
101 .align 5
102ENTRY(cpu_arm1020_do_idle)
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
104 ret lr
105
106/* ================================= CACHE ================================ */
107
108 .align 5
109
110/*
111 * flush_icache_all()
112 *
113 * Unconditionally clean and invalidate the entire icache.
114 */
115ENTRY(arm1020_flush_icache_all)
116#ifndef CONFIG_CPU_ICACHE_DISABLE
117 mov r0, #0
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119#endif
120 ret lr
121ENDPROC(arm1020_flush_icache_all)
122
123/*
124 * flush_user_cache_all()
125 *
126 * Invalidate all cache entries in a particular address
127 * space.
128 */
129ENTRY(arm1020_flush_user_cache_all)
130 /* FALLTHROUGH */
131/*
132 * flush_kern_cache_all()
133 *
134 * Clean and invalidate the entire cache.
135 */
136ENTRY(arm1020_flush_kern_cache_all)
137 mov r2, #VM_EXEC
138 mov ip, #0
139__flush_whole_cache:
140#ifndef CONFIG_CPU_DCACHE_DISABLE
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
142 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
1431: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1442: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
146 subs r3, r3, #1 << 26
147 bcs 2b @ entries 63 to 0
148 subs r1, r1, #1 << 5
149 bcs 1b @ segments 15 to 0
150#endif
151 tst r2, #VM_EXEC
152#ifndef CONFIG_CPU_ICACHE_DISABLE
153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
154#endif
155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
156 ret lr
157
158/*
159 * flush_user_cache_range(start, end, flags)
160 *
161 * Invalidate a range of cache entries in the specified
162 * address space.
163 *
164 * - start - start address (inclusive)
165 * - end - end address (exclusive)
166 * - flags - vm_flags for this space
167 */
168ENTRY(arm1020_flush_user_cache_range)
169 mov ip, #0
170 sub r3, r1, r0 @ calculate total size
171 cmp r3, #CACHE_DLIMIT
172 bhs __flush_whole_cache
173
174#ifndef CONFIG_CPU_DCACHE_DISABLE
175 mcr p15, 0, ip, c7, c10, 4
1761: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
177 mcr p15, 0, ip, c7, c10, 4 @ drain WB
178 add r0, r0, #CACHE_DLINESIZE
179 cmp r0, r1
180 blo 1b
181#endif
182 tst r2, #VM_EXEC
183#ifndef CONFIG_CPU_ICACHE_DISABLE
184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
185#endif
186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
187 ret lr
188
189/*
190 * coherent_kern_range(start, end)
191 *
192 * Ensure coherency between the Icache and the Dcache in the
193 * region described by start. If you have non-snooping
194 * Harvard caches, you need to implement this function.
195 *
196 * - start - virtual start address
197 * - end - virtual end address
198 */
199ENTRY(arm1020_coherent_kern_range)
200 /* FALLTRHOUGH */
201
202/*
203 * coherent_user_range(start, end)
204 *
205 * Ensure coherency between the Icache and the Dcache in the
206 * region described by start. If you have non-snooping
207 * Harvard caches, you need to implement this function.
208 *
209 * - start - virtual start address
210 * - end - virtual end address
211 */
212ENTRY(arm1020_coherent_user_range)
213 mov ip, #0
214 bic r0, r0, #CACHE_DLINESIZE - 1
215 mcr p15, 0, ip, c7, c10, 4
2161:
217#ifndef CONFIG_CPU_DCACHE_DISABLE
218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
219 mcr p15, 0, ip, c7, c10, 4 @ drain WB
220#endif
221#ifndef CONFIG_CPU_ICACHE_DISABLE
222 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
223#endif
224 add r0, r0, #CACHE_DLINESIZE
225 cmp r0, r1
226 blo 1b
227 mcr p15, 0, ip, c7, c10, 4 @ drain WB
228 mov r0, #0
229 ret lr
230
231/*
232 * flush_kern_dcache_area(void *addr, size_t size)
233 *
234 * Ensure no D cache aliasing occurs, either with itself or
235 * the I cache
236 *
237 * - addr - kernel address
238 * - size - region size
239 */
240ENTRY(arm1020_flush_kern_dcache_area)
241 mov ip, #0
242#ifndef CONFIG_CPU_DCACHE_DISABLE
243 add r1, r0, r1
2441: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
245 mcr p15, 0, ip, c7, c10, 4 @ drain WB
246 add r0, r0, #CACHE_DLINESIZE
247 cmp r0, r1
248 blo 1b
249#endif
250 mcr p15, 0, ip, c7, c10, 4 @ drain WB
251 ret lr
252
253/*
254 * dma_inv_range(start, end)
255 *
256 * Invalidate (discard) the specified virtual address range.
257 * May not write back any entries. If 'start' or 'end'
258 * are not cache line aligned, those lines must be written
259 * back.
260 *
261 * - start - virtual start address
262 * - end - virtual end address
263 *
264 * (same as v4wb)
265 */
266arm1020_dma_inv_range:
267 mov ip, #0
268#ifndef CONFIG_CPU_DCACHE_DISABLE
269 tst r0, #CACHE_DLINESIZE - 1
270 bic r0, r0, #CACHE_DLINESIZE - 1
271 mcrne p15, 0, ip, c7, c10, 4
272 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
273 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
274 tst r1, #CACHE_DLINESIZE - 1
275 mcrne p15, 0, ip, c7, c10, 4
276 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
277 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
2781: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
279 add r0, r0, #CACHE_DLINESIZE
280 cmp r0, r1
281 blo 1b
282#endif
283 mcr p15, 0, ip, c7, c10, 4 @ drain WB
284 ret lr
285
286/*
287 * dma_clean_range(start, end)
288 *
289 * Clean the specified virtual address range.
290 *
291 * - start - virtual start address
292 * - end - virtual end address
293 *
294 * (same as v4wb)
295 */
296arm1020_dma_clean_range:
297 mov ip, #0
298#ifndef CONFIG_CPU_DCACHE_DISABLE
299 bic r0, r0, #CACHE_DLINESIZE - 1
3001: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
301 mcr p15, 0, ip, c7, c10, 4 @ drain WB
302 add r0, r0, #CACHE_DLINESIZE
303 cmp r0, r1
304 blo 1b
305#endif
306 mcr p15, 0, ip, c7, c10, 4 @ drain WB
307 ret lr
308
309/*
310 * dma_flush_range(start, end)
311 *
312 * Clean and invalidate the specified virtual address range.
313 *
314 * - start - virtual start address
315 * - end - virtual end address
316 */
317ENTRY(arm1020_dma_flush_range)
318 mov ip, #0
319#ifndef CONFIG_CPU_DCACHE_DISABLE
320 bic r0, r0, #CACHE_DLINESIZE - 1
321 mcr p15, 0, ip, c7, c10, 4
3221: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
323 mcr p15, 0, ip, c7, c10, 4 @ drain WB
324 add r0, r0, #CACHE_DLINESIZE
325 cmp r0, r1
326 blo 1b
327#endif
328 mcr p15, 0, ip, c7, c10, 4 @ drain WB
329 ret lr
330
331/*
332 * dma_map_area(start, size, dir)
333 * - start - kernel virtual start address
334 * - size - size of region
335 * - dir - DMA direction
336 */
337ENTRY(arm1020_dma_map_area)
338 add r1, r1, r0
339 cmp r2, #DMA_TO_DEVICE
340 beq arm1020_dma_clean_range
341 bcs arm1020_dma_inv_range
342 b arm1020_dma_flush_range
343ENDPROC(arm1020_dma_map_area)
344
345/*
346 * dma_unmap_area(start, size, dir)
347 * - start - kernel virtual start address
348 * - size - size of region
349 * - dir - DMA direction
350 */
351ENTRY(arm1020_dma_unmap_area)
352 ret lr
353ENDPROC(arm1020_dma_unmap_area)
354
355 .globl arm1020_flush_kern_cache_louis
356 .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all
357
358 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
359 define_cache_functions arm1020
360
361 .align 5
362ENTRY(cpu_arm1020_dcache_clean_area)
363#ifndef CONFIG_CPU_DCACHE_DISABLE
364 mov ip, #0
3651: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
366 mcr p15, 0, ip, c7, c10, 4 @ drain WB
367 add r0, r0, #CACHE_DLINESIZE
368 subs r1, r1, #CACHE_DLINESIZE
369 bhi 1b
370#endif
371 ret lr
372
373/* =============================== PageTable ============================== */
374
375/*
376 * cpu_arm1020_switch_mm(pgd)
377 *
378 * Set the translation base pointer to be as described by pgd.
379 *
380 * pgd: new page tables
381 */
382 .align 5
383ENTRY(cpu_arm1020_switch_mm)
384#ifdef CONFIG_MMU
385#ifndef CONFIG_CPU_DCACHE_DISABLE
386 mcr p15, 0, r3, c7, c10, 4
387 mov r1, #0xF @ 16 segments
3881: mov r3, #0x3F @ 64 entries
3892: mov ip, r3, LSL #26 @ shift up entry
390 orr ip, ip, r1, LSL #5 @ shift in/up index
391 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
392 mov ip, #0
393 mcr p15, 0, ip, c7, c10, 4
394 subs r3, r3, #1
395 cmp r3, #0
396 bge 2b @ entries 3F to 0
397 subs r1, r1, #1
398 cmp r1, #0
399 bge 1b @ segments 15 to 0
400
401#endif
402 mov r1, #0
403#ifndef CONFIG_CPU_ICACHE_DISABLE
404 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
405#endif
406 mcr p15, 0, r1, c7, c10, 4 @ drain WB
407 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
408 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
409#endif /* CONFIG_MMU */
410 ret lr
411
412/*
413 * cpu_arm1020_set_pte(ptep, pte)
414 *
415 * Set a PTE and flush it out
416 */
417 .align 5
418ENTRY(cpu_arm1020_set_pte_ext)
419#ifdef CONFIG_MMU
420 armv3_set_pte_ext
421 mov r0, r0
422#ifndef CONFIG_CPU_DCACHE_DISABLE
423 mcr p15, 0, r0, c7, c10, 4
424 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
425#endif
426 mcr p15, 0, r0, c7, c10, 4 @ drain WB
427#endif /* CONFIG_MMU */
428 ret lr
429
430 .type __arm1020_setup, #function
431__arm1020_setup:
432 mov r0, #0
433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
434 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
435#ifdef CONFIG_MMU
436 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
437#endif
438
439 adr r5, arm1020_crval
440 ldmia r5, {r5, r6}
441 mrc p15, 0, r0, c1, c0 @ get control register v4
442 bic r0, r0, r5
443 orr r0, r0, r6
444#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
445 orr r0, r0, #0x4000 @ .R.. .... .... ....
446#endif
447 ret lr
448 .size __arm1020_setup, . - __arm1020_setup
449
450 /*
451 * R
452 * .RVI ZFRS BLDP WCAM
453 * .011 1001 ..11 0101
454 */
455 .type arm1020_crval, #object
456arm1020_crval:
457 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
458
459 __INITDATA
460 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
461 define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
462
463
464 .section ".rodata"
465
466 string cpu_arch_name, "armv5t"
467 string cpu_elf_name, "v5"
468
469 .type cpu_arm1020_name, #object
470cpu_arm1020_name:
471 .ascii "ARM1020"
472#ifndef CONFIG_CPU_ICACHE_DISABLE
473 .ascii "i"
474#endif
475#ifndef CONFIG_CPU_DCACHE_DISABLE
476 .ascii "d"
477#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
478 .ascii "(wt)"
479#else
480 .ascii "(wb)"
481#endif
482#endif
483#ifndef CONFIG_CPU_BPREDICT_DISABLE
484 .ascii "B"
485#endif
486#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
487 .ascii "RR"
488#endif
489 .ascii "\0"
490 .size cpu_arm1020_name, . - cpu_arm1020_name
491
492 .align
493
494 .section ".proc.info.init", "a"
495
496 .type __arm1020_proc_info,#object
497__arm1020_proc_info:
498 .long 0x4104a200 @ ARM 1020T (Architecture v5T)
499 .long 0xff0ffff0
500 .long PMD_TYPE_SECT | \
501 PMD_SECT_AP_WRITE | \
502 PMD_SECT_AP_READ
503 .long PMD_TYPE_SECT | \
504 PMD_SECT_AP_WRITE | \
505 PMD_SECT_AP_READ
506 initfn __arm1020_setup, __arm1020_proc_info
507 .long cpu_arch_name
508 .long cpu_elf_name
509 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
510 .long cpu_arm1020_name
511 .long arm1020_processor_functions
512 .long v4wbi_tlb_fns
513 .long v4wb_user_fns
514 .long arm1020_cache_fns
515 .size __arm1020_proc_info, . - __arm1020_proc_info