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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mm/cache-fa.S
4 *
5 * Copyright (C) 2005 Faraday Corp.
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
7 *
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
10 *
11 * Processors: FA520 FA526 FA626
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <linux/cfi_types.h>
16#include <asm/assembler.h>
17#include <asm/page.h>
18
19#include "proc-macros.S"
20
21/*
22 * The size of one data cache line.
23 */
24#define CACHE_DLINESIZE 16
25
26/*
27 * The total size of the data cache.
28 */
29#ifdef CONFIG_ARCH_GEMINI
30#define CACHE_DSIZE 8192
31#else
32#define CACHE_DSIZE 16384
33#endif
34
35/* FIXME: put optimal value here. Current one is just estimation */
36#define CACHE_DLIMIT (CACHE_DSIZE * 2)
37
38/*
39 * flush_icache_all()
40 *
41 * Unconditionally clean and invalidate the entire icache.
42 */
43SYM_TYPED_FUNC_START(fa_flush_icache_all)
44 mov r0, #0
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
46 ret lr
47SYM_FUNC_END(fa_flush_icache_all)
48
49/*
50 * flush_user_cache_all()
51 *
52 * Clean and invalidate all cache entries in a particular address
53 * space.
54 */
55SYM_FUNC_ALIAS(fa_flush_user_cache_all, fa_flush_kern_cache_all)
56
57/*
58 * flush_kern_cache_all()
59 *
60 * Clean and invalidate the entire cache.
61 */
62SYM_TYPED_FUNC_START(fa_flush_kern_cache_all)
63 mov ip, #0
64 mov r2, #VM_EXEC
65__flush_whole_cache:
66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
67 tst r2, #VM_EXEC
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
70 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
72 ret lr
73SYM_FUNC_END(fa_flush_kern_cache_all)
74
75/*
76 * flush_user_cache_range(start, end, flags)
77 *
78 * Invalidate a range of cache entries in the specified
79 * address space.
80 *
81 * - start - start address (inclusive, page aligned)
82 * - end - end address (exclusive, page aligned)
83 * - flags - vma_area_struct flags describing address space
84 */
85SYM_TYPED_FUNC_START(fa_flush_user_cache_range)
86 mov ip, #0
87 sub r3, r1, r0 @ calculate total size
88 cmp r3, #CACHE_DLIMIT @ total size >= limit?
89 bhs __flush_whole_cache @ flush whole D cache
90
911: tst r2, #VM_EXEC
92 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
94 add r0, r0, #CACHE_DLINESIZE
95 cmp r0, r1
96 blo 1b
97 tst r2, #VM_EXEC
98 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
99 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
100 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
101 ret lr
102SYM_FUNC_END(fa_flush_user_cache_range)
103
104/*
105 * coherent_kern_range(start, end)
106 *
107 * Ensure coherency between the Icache and the Dcache in the
108 * region described by start. If you have non-snooping
109 * Harvard caches, you need to implement this function.
110 *
111 * - start - virtual start address
112 * - end - virtual end address
113 */
114SYM_TYPED_FUNC_START(fa_coherent_kern_range)
115#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
116 b fa_coherent_user_range
117#endif
118SYM_FUNC_END(fa_coherent_kern_range)
119
120/*
121 * coherent_user_range(start, end)
122 *
123 * Ensure coherency between the Icache and the Dcache in the
124 * region described by start. If you have non-snooping
125 * Harvard caches, you need to implement this function.
126 *
127 * - start - virtual start address
128 * - end - virtual end address
129 */
130SYM_TYPED_FUNC_START(fa_coherent_user_range)
131 bic r0, r0, #CACHE_DLINESIZE - 1
1321: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
133 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
134 add r0, r0, #CACHE_DLINESIZE
135 cmp r0, r1
136 blo 1b
137 mov r0, #0
138 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
139 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
140 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
141 ret lr
142SYM_FUNC_END(fa_coherent_user_range)
143
144/*
145 * flush_kern_dcache_area(void *addr, size_t size)
146 *
147 * Ensure that the data held in the page kaddr is written back
148 * to the page in question.
149 *
150 * - addr - kernel address
151 * - size - size of region
152 */
153SYM_TYPED_FUNC_START(fa_flush_kern_dcache_area)
154 add r1, r0, r1
1551: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
156 add r0, r0, #CACHE_DLINESIZE
157 cmp r0, r1
158 blo 1b
159 mov r0, #0
160 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
161 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
162 ret lr
163SYM_FUNC_END(fa_flush_kern_dcache_area)
164
165/*
166 * dma_inv_range(start, end)
167 *
168 * Invalidate (discard) the specified virtual address range.
169 * May not write back any entries. If 'start' or 'end'
170 * are not cache line aligned, those lines must be written
171 * back.
172 *
173 * - start - virtual start address
174 * - end - virtual end address
175 */
176fa_dma_inv_range:
177 tst r0, #CACHE_DLINESIZE - 1
178 bic r0, r0, #CACHE_DLINESIZE - 1
179 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
180 tst r1, #CACHE_DLINESIZE - 1
181 bic r1, r1, #CACHE_DLINESIZE - 1
182 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry
1831: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
184 add r0, r0, #CACHE_DLINESIZE
185 cmp r0, r1
186 blo 1b
187 mov r0, #0
188 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
189 ret lr
190
191/*
192 * dma_clean_range(start, end)
193 *
194 * Clean (write back) the specified virtual address range.
195 *
196 * - start - virtual start address
197 * - end - virtual end address
198 */
199fa_dma_clean_range:
200 bic r0, r0, #CACHE_DLINESIZE - 1
2011: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
202 add r0, r0, #CACHE_DLINESIZE
203 cmp r0, r1
204 blo 1b
205 mov r0, #0
206 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
207 ret lr
208
209/*
210 * dma_flush_range(start,end)
211 * - start - virtual start address of region
212 * - end - virtual end address of region
213 */
214SYM_TYPED_FUNC_START(fa_dma_flush_range)
215 bic r0, r0, #CACHE_DLINESIZE - 1
2161: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
217 add r0, r0, #CACHE_DLINESIZE
218 cmp r0, r1
219 blo 1b
220 mov r0, #0
221 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
222 ret lr
223SYM_FUNC_END(fa_dma_flush_range)
224
225/*
226 * dma_map_area(start, size, dir)
227 * - start - kernel virtual start address
228 * - size - size of region
229 * - dir - DMA direction
230 */
231SYM_TYPED_FUNC_START(fa_dma_map_area)
232 add r1, r1, r0
233 cmp r2, #DMA_TO_DEVICE
234 beq fa_dma_clean_range
235 bcs fa_dma_inv_range
236 b fa_dma_flush_range
237SYM_FUNC_END(fa_dma_map_area)
238
239/*
240 * dma_unmap_area(start, size, dir)
241 * - start - kernel virtual start address
242 * - size - size of region
243 * - dir - DMA direction
244 */
245SYM_TYPED_FUNC_START(fa_dma_unmap_area)
246 ret lr
247SYM_FUNC_END(fa_dma_unmap_area)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mm/cache-fa.S
4 *
5 * Copyright (C) 2005 Faraday Corp.
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
7 *
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
10 *
11 * Processors: FA520 FA526 FA626
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <asm/assembler.h>
16#include <asm/page.h>
17
18#include "proc-macros.S"
19
20/*
21 * The size of one data cache line.
22 */
23#define CACHE_DLINESIZE 16
24
25/*
26 * The total size of the data cache.
27 */
28#ifdef CONFIG_ARCH_GEMINI
29#define CACHE_DSIZE 8192
30#else
31#define CACHE_DSIZE 16384
32#endif
33
34/* FIXME: put optimal value here. Current one is just estimation */
35#define CACHE_DLIMIT (CACHE_DSIZE * 2)
36
37/*
38 * flush_icache_all()
39 *
40 * Unconditionally clean and invalidate the entire icache.
41 */
42ENTRY(fa_flush_icache_all)
43 mov r0, #0
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
45 ret lr
46ENDPROC(fa_flush_icache_all)
47
48/*
49 * flush_user_cache_all()
50 *
51 * Clean and invalidate all cache entries in a particular address
52 * space.
53 */
54ENTRY(fa_flush_user_cache_all)
55 /* FALLTHROUGH */
56/*
57 * flush_kern_cache_all()
58 *
59 * Clean and invalidate the entire cache.
60 */
61ENTRY(fa_flush_kern_cache_all)
62 mov ip, #0
63 mov r2, #VM_EXEC
64__flush_whole_cache:
65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
66 tst r2, #VM_EXEC
67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
69 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
71 ret lr
72
73/*
74 * flush_user_cache_range(start, end, flags)
75 *
76 * Invalidate a range of cache entries in the specified
77 * address space.
78 *
79 * - start - start address (inclusive, page aligned)
80 * - end - end address (exclusive, page aligned)
81 * - flags - vma_area_struct flags describing address space
82 */
83ENTRY(fa_flush_user_cache_range)
84 mov ip, #0
85 sub r3, r1, r0 @ calculate total size
86 cmp r3, #CACHE_DLIMIT @ total size >= limit?
87 bhs __flush_whole_cache @ flush whole D cache
88
891: tst r2, #VM_EXEC
90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
91 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
92 add r0, r0, #CACHE_DLINESIZE
93 cmp r0, r1
94 blo 1b
95 tst r2, #VM_EXEC
96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
97 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
98 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
99 ret lr
100
101/*
102 * coherent_kern_range(start, end)
103 *
104 * Ensure coherency between the Icache and the Dcache in the
105 * region described by start. If you have non-snooping
106 * Harvard caches, you need to implement this function.
107 *
108 * - start - virtual start address
109 * - end - virtual end address
110 */
111ENTRY(fa_coherent_kern_range)
112 /* fall through */
113
114/*
115 * coherent_user_range(start, end)
116 *
117 * Ensure coherency between the Icache and the Dcache in the
118 * region described by start. If you have non-snooping
119 * Harvard caches, you need to implement this function.
120 *
121 * - start - virtual start address
122 * - end - virtual end address
123 */
124ENTRY(fa_coherent_user_range)
125 bic r0, r0, #CACHE_DLINESIZE - 1
1261: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
128 add r0, r0, #CACHE_DLINESIZE
129 cmp r0, r1
130 blo 1b
131 mov r0, #0
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
133 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
134 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
135 ret lr
136
137/*
138 * flush_kern_dcache_area(void *addr, size_t size)
139 *
140 * Ensure that the data held in the page kaddr is written back
141 * to the page in question.
142 *
143 * - addr - kernel address
144 * - size - size of region
145 */
146ENTRY(fa_flush_kern_dcache_area)
147 add r1, r0, r1
1481: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
149 add r0, r0, #CACHE_DLINESIZE
150 cmp r0, r1
151 blo 1b
152 mov r0, #0
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
154 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
155 ret lr
156
157/*
158 * dma_inv_range(start, end)
159 *
160 * Invalidate (discard) the specified virtual address range.
161 * May not write back any entries. If 'start' or 'end'
162 * are not cache line aligned, those lines must be written
163 * back.
164 *
165 * - start - virtual start address
166 * - end - virtual end address
167 */
168fa_dma_inv_range:
169 tst r0, #CACHE_DLINESIZE - 1
170 bic r0, r0, #CACHE_DLINESIZE - 1
171 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
172 tst r1, #CACHE_DLINESIZE - 1
173 bic r1, r1, #CACHE_DLINESIZE - 1
174 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry
1751: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
176 add r0, r0, #CACHE_DLINESIZE
177 cmp r0, r1
178 blo 1b
179 mov r0, #0
180 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
181 ret lr
182
183/*
184 * dma_clean_range(start, end)
185 *
186 * Clean (write back) the specified virtual address range.
187 *
188 * - start - virtual start address
189 * - end - virtual end address
190 */
191fa_dma_clean_range:
192 bic r0, r0, #CACHE_DLINESIZE - 1
1931: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
194 add r0, r0, #CACHE_DLINESIZE
195 cmp r0, r1
196 blo 1b
197 mov r0, #0
198 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
199 ret lr
200
201/*
202 * dma_flush_range(start,end)
203 * - start - virtual start address of region
204 * - end - virtual end address of region
205 */
206ENTRY(fa_dma_flush_range)
207 bic r0, r0, #CACHE_DLINESIZE - 1
2081: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
209 add r0, r0, #CACHE_DLINESIZE
210 cmp r0, r1
211 blo 1b
212 mov r0, #0
213 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
214 ret lr
215
216/*
217 * dma_map_area(start, size, dir)
218 * - start - kernel virtual start address
219 * - size - size of region
220 * - dir - DMA direction
221 */
222ENTRY(fa_dma_map_area)
223 add r1, r1, r0
224 cmp r2, #DMA_TO_DEVICE
225 beq fa_dma_clean_range
226 bcs fa_dma_inv_range
227 b fa_dma_flush_range
228ENDPROC(fa_dma_map_area)
229
230/*
231 * dma_unmap_area(start, size, dir)
232 * - start - kernel virtual start address
233 * - size - size of region
234 * - dir - DMA direction
235 */
236ENTRY(fa_dma_unmap_area)
237 ret lr
238ENDPROC(fa_dma_unmap_area)
239
240 .globl fa_flush_kern_cache_louis
241 .equ fa_flush_kern_cache_louis, fa_flush_kern_cache_all
242
243 __INITDATA
244
245 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
246 define_cache_functions fa