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1# SPDX-License-Identifier: GPL-2.0
2comment "Processor Type"
3
4# Select CPU types depending on the architecture selected. This selects
5# which CPUs we support in the kernel image, and the compiler instruction
6# optimiser behaviour.
7
8# ARM7TDMI
9config CPU_ARM7TDMI
10 bool
11 depends on !MMU
12 select CPU_32v4T
13 select CPU_ABRT_LV4T
14 select CPU_CACHE_V4
15 select CPU_PABRT_LEGACY
16 help
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
19
20 Say Y if you want support for the ARM7TDMI processor.
21 Otherwise, say N.
22
23# ARM720T
24config CPU_ARM720T
25 bool
26 select CPU_32v4T
27 select CPU_ABRT_LV4T
28 select CPU_CACHE_V4
29 select CPU_CACHE_VIVT
30 select CPU_COPY_V4WT if MMU
31 select CPU_CP15_MMU
32 select CPU_PABRT_LEGACY
33 select CPU_THUMB_CAPABLE
34 select CPU_TLB_V4WT if MMU
35 help
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
37 MMU built around an ARM7TDMI core.
38
39 Say Y if you want support for the ARM720T processor.
40 Otherwise, say N.
41
42# ARM740T
43config CPU_ARM740T
44 bool
45 depends on !MMU
46 select CPU_32v4T
47 select CPU_ABRT_LV4T
48 select CPU_CACHE_V4
49 select CPU_CP15_MPU
50 select CPU_PABRT_LEGACY
51 select CPU_THUMB_CAPABLE
52 help
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
55 an ARM7TDMI core.
56
57 Say Y if you want support for the ARM740T processor.
58 Otherwise, say N.
59
60# ARM9TDMI
61config CPU_ARM9TDMI
62 bool
63 depends on !MMU
64 select CPU_32v4T
65 select CPU_ABRT_NOMMU
66 select CPU_CACHE_V4
67 select CPU_PABRT_LEGACY
68 help
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
71
72 Say Y if you want support for the ARM9TDMI processor.
73 Otherwise, say N.
74
75# ARM920T
76config CPU_ARM920T
77 bool
78 select CPU_32v4T
79 select CPU_ABRT_EV4T
80 select CPU_CACHE_V4WT
81 select CPU_CACHE_VIVT
82 select CPU_COPY_V4WB if MMU
83 select CPU_CP15_MMU
84 select CPU_PABRT_LEGACY
85 select CPU_THUMB_CAPABLE
86 select CPU_TLB_V4WBI if MMU
87 help
88 The ARM920T is licensed to be produced by numerous vendors,
89 and is used in the Cirrus EP93xx and the Samsung S3C2410.
90
91 Say Y if you want support for the ARM920T processor.
92 Otherwise, say N.
93
94# ARM922T
95config CPU_ARM922T
96 bool
97 select CPU_32v4T
98 select CPU_ABRT_EV4T
99 select CPU_CACHE_V4WT
100 select CPU_CACHE_VIVT
101 select CPU_COPY_V4WB if MMU
102 select CPU_CP15_MMU
103 select CPU_PABRT_LEGACY
104 select CPU_THUMB_CAPABLE
105 select CPU_TLB_V4WBI if MMU
106 help
107 The ARM922T is a version of the ARM920T, but with smaller
108 instruction and data caches. It is used in Altera's
109 Excalibur XA device family and the ARM Integrator.
110
111 Say Y if you want support for the ARM922T processor.
112 Otherwise, say N.
113
114# ARM925T
115config CPU_ARM925T
116 bool
117 select CPU_32v4T
118 select CPU_ABRT_EV4T
119 select CPU_CACHE_V4WT
120 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
122 select CPU_CP15_MMU
123 select CPU_PABRT_LEGACY
124 select CPU_THUMB_CAPABLE
125 select CPU_TLB_V4WBI if MMU
126 help
127 The ARM925T is a mix between the ARM920T and ARM926T, but with
128 different instruction and data caches. It is used in TI's OMAP
129 device family.
130
131 Say Y if you want support for the ARM925T processor.
132 Otherwise, say N.
133
134# ARM926T
135config CPU_ARM926T
136 bool
137 select CPU_32v5
138 select CPU_ABRT_EV5TJ
139 select CPU_CACHE_VIVT
140 select CPU_COPY_V4WB if MMU
141 select CPU_CP15_MMU
142 select CPU_PABRT_LEGACY
143 select CPU_THUMB_CAPABLE
144 select CPU_TLB_V4WBI if MMU
145 help
146 This is a variant of the ARM920. It has slightly different
147 instruction sequences for cache and TLB operations. Curiously,
148 there is no documentation on it at the ARM corporate website.
149
150 Say Y if you want support for the ARM926T processor.
151 Otherwise, say N.
152
153# FA526
154config CPU_FA526
155 bool
156 select CPU_32v4
157 select CPU_ABRT_EV4
158 select CPU_CACHE_FA
159 select CPU_CACHE_VIVT
160 select CPU_COPY_FA if MMU
161 select CPU_CP15_MMU
162 select CPU_PABRT_LEGACY
163 select CPU_TLB_FA if MMU
164 help
165 The FA526 is a version of the ARMv4 compatible processor with
166 Branch Target Buffer, Unified TLB and cache line size 16.
167
168 Say Y if you want support for the FA526 processor.
169 Otherwise, say N.
170
171# ARM940T
172config CPU_ARM940T
173 bool
174 depends on !MMU
175 select CPU_32v4T
176 select CPU_ABRT_NOMMU
177 select CPU_CACHE_VIVT
178 select CPU_CP15_MPU
179 select CPU_PABRT_LEGACY
180 select CPU_THUMB_CAPABLE
181 help
182 ARM940T is a member of the ARM9TDMI family of general-
183 purpose microprocessors with MPU and separate 4KB
184 instruction and 4KB data cases, each with a 4-word line
185 length.
186
187 Say Y if you want support for the ARM940T processor.
188 Otherwise, say N.
189
190# ARM946E-S
191config CPU_ARM946E
192 bool
193 depends on !MMU
194 select CPU_32v5
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 select CPU_PABRT_LEGACY
199 select CPU_THUMB_CAPABLE
200 help
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
204
205 Say Y if you want support for the ARM946E-S processor.
206 Otherwise, say N.
207
208# ARM1020 - needs validating
209config CPU_ARM1020
210 bool
211 select CPU_32v5
212 select CPU_ABRT_EV4T
213 select CPU_CACHE_V4WT
214 select CPU_CACHE_VIVT
215 select CPU_COPY_V4WB if MMU
216 select CPU_CP15_MMU
217 select CPU_PABRT_LEGACY
218 select CPU_THUMB_CAPABLE
219 select CPU_TLB_V4WBI if MMU
220 help
221 The ARM1020 is the 32K cached version of the ARM10 processor,
222 with an addition of a floating-point unit.
223
224 Say Y if you want support for the ARM1020 processor.
225 Otherwise, say N.
226
227# ARM1020E - needs validating
228config CPU_ARM1020E
229 bool
230 depends on n
231 select CPU_32v5
232 select CPU_ABRT_EV4T
233 select CPU_CACHE_V4WT
234 select CPU_CACHE_VIVT
235 select CPU_COPY_V4WB if MMU
236 select CPU_CP15_MMU
237 select CPU_PABRT_LEGACY
238 select CPU_THUMB_CAPABLE
239 select CPU_TLB_V4WBI if MMU
240
241# ARM1022E
242config CPU_ARM1022
243 bool
244 select CPU_32v5
245 select CPU_ABRT_EV4T
246 select CPU_CACHE_VIVT
247 select CPU_COPY_V4WB if MMU # can probably do better
248 select CPU_CP15_MMU
249 select CPU_PABRT_LEGACY
250 select CPU_THUMB_CAPABLE
251 select CPU_TLB_V4WBI if MMU
252 help
253 The ARM1022E is an implementation of the ARMv5TE architecture
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
256
257 Say Y if you want support for the ARM1022E processor.
258 Otherwise, say N.
259
260# ARM1026EJ-S
261config CPU_ARM1026
262 bool
263 select CPU_32v5
264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
265 select CPU_CACHE_VIVT
266 select CPU_COPY_V4WB if MMU # can probably do better
267 select CPU_CP15_MMU
268 select CPU_PABRT_LEGACY
269 select CPU_THUMB_CAPABLE
270 select CPU_TLB_V4WBI if MMU
271 help
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
273 based upon the ARM10 integer core.
274
275 Say Y if you want support for the ARM1026EJ-S processor.
276 Otherwise, say N.
277
278# SA110
279config CPU_SA110
280 bool
281 select CPU_32v3 if ARCH_RPC
282 select CPU_32v4 if !ARCH_RPC
283 select CPU_ABRT_EV4
284 select CPU_CACHE_V4WB
285 select CPU_CACHE_VIVT
286 select CPU_COPY_V4WB if MMU
287 select CPU_CP15_MMU
288 select CPU_PABRT_LEGACY
289 select CPU_TLB_V4WB if MMU
290 help
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
292 is available at five speeds ranging from 100 MHz to 233 MHz.
293 More information is available at
294 <http://developer.intel.com/design/strong/sa110.htm>.
295
296 Say Y if you want support for the SA-110 processor.
297 Otherwise, say N.
298
299# SA1100
300config CPU_SA1100
301 bool
302 select CPU_32v4
303 select CPU_ABRT_EV4
304 select CPU_CACHE_V4WB
305 select CPU_CACHE_VIVT
306 select CPU_CP15_MMU
307 select CPU_PABRT_LEGACY
308 select CPU_TLB_V4WB if MMU
309
310# XScale
311config CPU_XSCALE
312 bool
313 select CPU_32v5
314 select CPU_ABRT_EV5T
315 select CPU_CACHE_VIVT
316 select CPU_CP15_MMU
317 select CPU_PABRT_LEGACY
318 select CPU_THUMB_CAPABLE
319 select CPU_TLB_V4WBI if MMU
320
321# XScale Core Version 3
322config CPU_XSC3
323 bool
324 select CPU_32v5
325 select CPU_ABRT_EV5T
326 select CPU_CACHE_VIVT
327 select CPU_CP15_MMU
328 select CPU_PABRT_LEGACY
329 select CPU_THUMB_CAPABLE
330 select CPU_TLB_V4WBI if MMU
331 select IO_36
332
333# Marvell PJ1 (Mohawk)
334config CPU_MOHAWK
335 bool
336 select CPU_32v5
337 select CPU_ABRT_EV5T
338 select CPU_CACHE_VIVT
339 select CPU_COPY_V4WB if MMU
340 select CPU_CP15_MMU
341 select CPU_PABRT_LEGACY
342 select CPU_THUMB_CAPABLE
343 select CPU_TLB_V4WBI if MMU
344
345# Feroceon
346config CPU_FEROCEON
347 bool
348 select CPU_32v5
349 select CPU_ABRT_EV5T
350 select CPU_CACHE_VIVT
351 select CPU_COPY_FEROCEON if MMU
352 select CPU_CP15_MMU
353 select CPU_PABRT_LEGACY
354 select CPU_THUMB_CAPABLE
355 select CPU_TLB_FEROCEON if MMU
356
357config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
360 default y
361 help
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
365
366# Marvell PJ4
367config CPU_PJ4
368 bool
369 select ARM_THUMBEE
370 select CPU_V7
371
372config CPU_PJ4B
373 bool
374 select CPU_V7
375
376# ARMv6
377config CPU_V6
378 bool
379 select CPU_32v6
380 select CPU_ABRT_EV6
381 select CPU_CACHE_V6
382 select CPU_CACHE_VIPT
383 select CPU_COPY_V6 if MMU
384 select CPU_CP15_MMU
385 select CPU_HAS_ASID if MMU
386 select CPU_PABRT_V6
387 select CPU_THUMB_CAPABLE
388 select CPU_TLB_V6 if MMU
389 select SMP_ON_UP if SMP
390
391# ARMv6k
392config CPU_V6K
393 bool
394 select CPU_32v6
395 select CPU_32v6K
396 select CPU_ABRT_EV6
397 select CPU_CACHE_V6
398 select CPU_CACHE_VIPT
399 select CPU_COPY_V6 if MMU
400 select CPU_CP15_MMU
401 select CPU_HAS_ASID if MMU
402 select CPU_PABRT_V6
403 select CPU_THUMB_CAPABLE
404 select CPU_TLB_V6 if MMU
405
406# ARMv7 and ARMv8 architectures
407config CPU_V7
408 bool
409 select CPU_32v6K
410 select CPU_32v7
411 select CPU_ABRT_EV7
412 select CPU_CACHE_V7
413 select CPU_CACHE_VIPT
414 select CPU_COPY_V6 if MMU
415 select CPU_CP15_MMU if MMU
416 select CPU_CP15_MPU if !MMU
417 select CPU_HAS_ASID if MMU
418 select CPU_PABRT_V7
419 select CPU_SPECTRE if MMU
420 select CPU_THUMB_CAPABLE
421 select CPU_TLB_V7 if MMU
422
423# ARMv7M
424config CPU_V7M
425 bool
426 select CPU_32v7M
427 select CPU_ABRT_NOMMU
428 select CPU_CACHE_V7M
429 select CPU_CACHE_NOP
430 select CPU_PABRT_LEGACY
431 select CPU_THUMBONLY
432
433config CPU_THUMBONLY
434 bool
435 select CPU_THUMB_CAPABLE
436 # There are no CPUs available with MMU that don't implement an ARM ISA:
437 depends on !MMU
438 help
439 Select this if your CPU doesn't support the 32 bit ARM instructions.
440
441config CPU_THUMB_CAPABLE
442 bool
443 help
444 Select this if your CPU can support Thumb mode.
445
446# Figure out what processor architecture version we should be using.
447# This defines the compiler instruction set which depends on the machine type.
448config CPU_32v3
449 bool
450 select CPU_USE_DOMAINS if MMU
451 select NEED_KUSER_HELPERS
452 select TLS_REG_EMUL if SMP || !MMU
453 select CPU_NO_EFFICIENT_FFS
454
455config CPU_32v4
456 bool
457 select CPU_USE_DOMAINS if MMU
458 select NEED_KUSER_HELPERS
459 select TLS_REG_EMUL if SMP || !MMU
460 select CPU_NO_EFFICIENT_FFS
461
462config CPU_32v4T
463 bool
464 select CPU_USE_DOMAINS if MMU
465 select NEED_KUSER_HELPERS
466 select TLS_REG_EMUL if SMP || !MMU
467 select CPU_NO_EFFICIENT_FFS
468
469config CPU_32v5
470 bool
471 select CPU_USE_DOMAINS if MMU
472 select NEED_KUSER_HELPERS
473 select TLS_REG_EMUL if SMP || !MMU
474
475config CPU_32v6
476 bool
477 select TLS_REG_EMUL if !CPU_32v6K && !MMU
478
479config CPU_32v6K
480 bool
481
482config CPU_32v7
483 bool
484
485config CPU_32v7M
486 bool
487
488# The abort model
489config CPU_ABRT_NOMMU
490 bool
491
492config CPU_ABRT_EV4
493 bool
494
495config CPU_ABRT_EV4T
496 bool
497
498config CPU_ABRT_LV4T
499 bool
500
501config CPU_ABRT_EV5T
502 bool
503
504config CPU_ABRT_EV5TJ
505 bool
506
507config CPU_ABRT_EV6
508 bool
509
510config CPU_ABRT_EV7
511 bool
512
513config CPU_PABRT_LEGACY
514 bool
515
516config CPU_PABRT_V6
517 bool
518
519config CPU_PABRT_V7
520 bool
521
522# The cache model
523config CPU_CACHE_V4
524 bool
525
526config CPU_CACHE_V4WT
527 bool
528
529config CPU_CACHE_V4WB
530 bool
531
532config CPU_CACHE_V6
533 bool
534
535config CPU_CACHE_V7
536 bool
537
538config CPU_CACHE_NOP
539 bool
540
541config CPU_CACHE_VIVT
542 bool
543
544config CPU_CACHE_VIPT
545 bool
546
547config CPU_CACHE_FA
548 bool
549
550config CPU_CACHE_V7M
551 bool
552
553if MMU
554# The copy-page model
555config CPU_COPY_V4WT
556 bool
557
558config CPU_COPY_V4WB
559 bool
560
561config CPU_COPY_FEROCEON
562 bool
563
564config CPU_COPY_FA
565 bool
566
567config CPU_COPY_V6
568 bool
569
570# This selects the TLB model
571config CPU_TLB_V4WT
572 bool
573 help
574 ARM Architecture Version 4 TLB with writethrough cache.
575
576config CPU_TLB_V4WB
577 bool
578 help
579 ARM Architecture Version 4 TLB with writeback cache.
580
581config CPU_TLB_V4WBI
582 bool
583 help
584 ARM Architecture Version 4 TLB with writeback cache and invalidate
585 instruction cache entry.
586
587config CPU_TLB_FEROCEON
588 bool
589 help
590 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
591
592config CPU_TLB_FA
593 bool
594 help
595 Faraday ARM FA526 architecture, unified TLB with writeback cache
596 and invalidate instruction cache entry. Branch target buffer is
597 also supported.
598
599config CPU_TLB_V6
600 bool
601
602config CPU_TLB_V7
603 bool
604
605endif
606
607config CPU_HAS_ASID
608 bool
609 help
610 This indicates whether the CPU has the ASID register; used to
611 tag TLB and possibly cache entries.
612
613config CPU_CP15
614 bool
615 help
616 Processor has the CP15 register.
617
618config CPU_CP15_MMU
619 bool
620 select CPU_CP15
621 help
622 Processor has the CP15 register, which has MMU related registers.
623
624config CPU_CP15_MPU
625 bool
626 select CPU_CP15
627 help
628 Processor has the CP15 register, which has MPU related registers.
629
630config CPU_USE_DOMAINS
631 bool
632 help
633 This option enables or disables the use of domain switching
634 using the DACR (domain access control register) to protect memory
635 domains from each other. In Linux we use three domains: kernel, user
636 and IO. The domains are used to protect userspace from kernelspace
637 and to handle IO-space as a special type of memory by assigning
638 manager or client roles to running code (such as a process).
639
640config CPU_V7M_NUM_IRQ
641 int "Number of external interrupts connected to the NVIC"
642 depends on CPU_V7M
643 default 90 if ARCH_STM32
644 default 112 if SOC_VF610
645 default 240
646 help
647 This option indicates the number of interrupts connected to the NVIC.
648 The value can be larger than the real number of interrupts supported
649 by the system, but must not be lower.
650 The default value is 240, corresponding to the maximum number of
651 interrupts supported by the NVIC on Cortex-M family.
652
653 If unsure, keep default value.
654
655#
656# CPU supports 36-bit I/O
657#
658config IO_36
659 bool
660
661comment "Processor Features"
662
663config ARM_LPAE
664 bool "Support for the Large Physical Address Extension"
665 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
666 !CPU_32v4 && !CPU_32v3
667 select PHYS_ADDR_T_64BIT
668 select SWIOTLB
669 help
670 Say Y if you have an ARMv7 processor supporting the LPAE page
671 table format and you would like to access memory beyond the
672 4GB limit. The resulting kernel image will not run on
673 processors without the LPA extension.
674
675 If unsure, say N.
676
677config ARM_PV_FIXUP
678 def_bool y
679 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
680
681config ARM_THUMB
682 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
683 depends on CPU_THUMB_CAPABLE && !CPU_32v4
684 default y
685 help
686 Say Y if you want to include kernel support for running user space
687 Thumb binaries.
688
689 The Thumb instruction set is a compressed form of the standard ARM
690 instruction set resulting in smaller binaries at the expense of
691 slightly less efficient code.
692
693 If this option is disabled, and you run userspace that switches to
694 Thumb mode, signal handling will not work correctly, resulting in
695 segmentation faults or illegal instruction aborts.
696
697 If you don't know what this all is, saying Y is a safe choice.
698
699config ARM_THUMBEE
700 bool "Enable ThumbEE CPU extension"
701 depends on CPU_V7
702 help
703 Say Y here if you have a CPU with the ThumbEE extension and code to
704 make use of it. Say N for code that can run on CPUs without ThumbEE.
705
706config ARM_VIRT_EXT
707 bool
708 default y if CPU_V7
709 help
710 Enable the kernel to make use of the ARM Virtualization
711 Extensions to install hypervisors without run-time firmware
712 assistance.
713
714 A compliant bootloader is required in order to make maximum
715 use of this feature. Refer to Documentation/arch/arm/booting.rst for
716 details.
717
718config SWP_EMULATE
719 bool "Emulate SWP/SWPB instructions" if !SMP
720 depends on CPU_V7
721 default y if SMP
722 select HAVE_PROC_CPU if PROC_FS
723 help
724 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
725 ARMv7 multiprocessing extensions introduce the ability to disable
726 these instructions, triggering an undefined instruction exception
727 when executed. Say Y here to enable software emulation of these
728 instructions for userspace (not kernel) using LDREX/STREX.
729 Also creates /proc/cpu/swp_emulation for statistics.
730
731 In some older versions of glibc [<=2.8] SWP is used during futex
732 trylock() operations with the assumption that the code will not
733 be preempted. This invalid assumption may be more likely to fail
734 with SWP emulation enabled, leading to deadlock of the user
735 application.
736
737 NOTE: when accessing uncached shared regions, LDREX/STREX rely
738 on an external transaction monitoring block called a global
739 monitor to maintain update atomicity. If your system does not
740 implement a global monitor, this option can cause programs that
741 perform SWP operations to uncached memory to deadlock.
742
743 If unsure, say Y.
744
745choice
746 prompt "CPU Endianness"
747 default CPU_LITTLE_ENDIAN
748
749config CPU_LITTLE_ENDIAN
750 bool "Built little-endian kernel"
751 help
752 Say Y if you plan on running a kernel in little-endian mode.
753 This is the default and is used in practically all modern user
754 space builds.
755
756config CPU_BIG_ENDIAN
757 bool "Build big-endian kernel"
758 depends on !LD_IS_LLD
759 help
760 Say Y if you plan on running a kernel in big-endian mode.
761 This works on many machines using ARMv6 or newer processors
762 but requires big-endian user space.
763
764 The only ARMv5 platform with big-endian support is
765 Intel IXP4xx.
766
767endchoice
768
769config CPU_ENDIAN_BE8
770 bool
771 depends on CPU_BIG_ENDIAN
772 default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
773 help
774 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
775
776config CPU_ENDIAN_BE32
777 bool
778 depends on CPU_BIG_ENDIAN
779 default !CPU_ENDIAN_BE8
780 help
781 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
782
783config CPU_HIGH_VECTOR
784 depends on !MMU && CPU_CP15 && !CPU_ARM740T
785 bool "Select the High exception vector"
786 help
787 Say Y here to select high exception vector(0xFFFF0000~).
788 The exception vector can vary depending on the platform
789 design in nommu mode. If your platform needs to select
790 high exception vector, say Y.
791 Otherwise or if you are unsure, say N, and the low exception
792 vector (0x00000000~) will be used.
793
794config CPU_ICACHE_DISABLE
795 bool "Disable I-Cache (I-bit)"
796 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
797 help
798 Say Y here to disable the processor instruction cache. Unless
799 you have a reason not to or are unsure, say N.
800
801config CPU_ICACHE_MISMATCH_WORKAROUND
802 bool "Workaround for I-Cache line size mismatch between CPU cores"
803 depends on SMP && CPU_V7
804 help
805 Some big.LITTLE systems have I-Cache line size mismatch between
806 LITTLE and big cores. Say Y here to enable a workaround for
807 proper I-Cache support on such systems. If unsure, say N.
808
809config CPU_DCACHE_DISABLE
810 bool "Disable D-Cache (C-bit)"
811 depends on (CPU_CP15 && !SMP) || CPU_V7M
812 help
813 Say Y here to disable the processor data cache. Unless
814 you have a reason not to or are unsure, say N.
815
816config CPU_DCACHE_SIZE
817 hex
818 depends on CPU_ARM740T || CPU_ARM946E
819 default 0x00001000 if CPU_ARM740T
820 default 0x00002000 # default size for ARM946E-S
821 help
822 Some cores are synthesizable to have various sized cache. For
823 ARM946E-S case, it can vary from 0KB to 1MB.
824 To support such cache operations, it is efficient to know the size
825 before compile time.
826 If your SoC is configured to have a different size, define the value
827 here with proper conditions.
828
829config CPU_DCACHE_WRITETHROUGH
830 bool "Force write through D-cache"
831 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
832 default y if CPU_ARM925T
833 help
834 Say Y here to use the data cache in writethrough mode. Unless you
835 specifically require this or are unsure, say N.
836
837config CPU_CACHE_ROUND_ROBIN
838 bool "Round robin I and D cache replacement algorithm"
839 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
840 help
841 Say Y here to use the predictable round-robin cache replacement
842 policy. Unless you specifically require this or are unsure, say N.
843
844config CPU_BPREDICT_DISABLE
845 bool "Disable branch prediction"
846 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
847 help
848 Say Y here to disable branch prediction. If unsure, say N.
849
850config CPU_SPECTRE
851 bool
852 select GENERIC_CPU_VULNERABILITIES
853
854config HARDEN_BRANCH_PREDICTOR
855 bool "Harden the branch predictor against aliasing attacks" if EXPERT
856 depends on CPU_SPECTRE
857 default y
858 help
859 Speculation attacks against some high-performance processors rely
860 on being able to manipulate the branch predictor for a victim
861 context by executing aliasing branches in the attacker context.
862 Such attacks can be partially mitigated against by clearing
863 internal branch predictor state and limiting the prediction
864 logic in some situations.
865
866 This config option will take CPU-specific actions to harden
867 the branch predictor against aliasing attacks and may rely on
868 specific instruction sequences or control bits being set by
869 the system firmware.
870
871 If unsure, say Y.
872
873config HARDEN_BRANCH_HISTORY
874 bool "Harden Spectre style attacks against branch history" if EXPERT
875 depends on CPU_SPECTRE
876 default y
877 help
878 Speculation attacks against some high-performance processors can
879 make use of branch history to influence future speculation. When
880 taking an exception, a sequence of branches overwrites the branch
881 history, or branch history is invalidated.
882
883config TLS_REG_EMUL
884 bool
885 select NEED_KUSER_HELPERS
886 help
887 An SMP system using a pre-ARMv6 processor (there are apparently
888 a few prototypes like that in existence) and therefore access to
889 that required register must be emulated.
890
891config NEED_KUSER_HELPERS
892 bool
893
894config KUSER_HELPERS
895 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
896 depends on MMU
897 default y
898 help
899 Warning: disabling this option may break user programs.
900
901 Provide kuser helpers in the vector page. The kernel provides
902 helper code to userspace in read only form at a fixed location
903 in the high vector page to allow userspace to be independent of
904 the CPU type fitted to the system. This permits binaries to be
905 run on ARMv4 through to ARMv7 without modification.
906
907 See Documentation/arch/arm/kernel_user_helpers.rst for details.
908
909 However, the fixed address nature of these helpers can be used
910 by ROP (return orientated programming) authors when creating
911 exploits.
912
913 If all of the binaries and libraries which run on your platform
914 are built specifically for your platform, and make no use of
915 these helpers, then you can turn this option off to hinder
916 such exploits. However, in that case, if a binary or library
917 relying on those helpers is run, it will receive a SIGILL signal,
918 which will terminate the program.
919
920 Say N here only if you are absolutely certain that you do not
921 need these helpers; otherwise, the safe option is to say Y.
922
923config VDSO
924 bool "Enable VDSO for acceleration of some system calls"
925 depends on AEABI && MMU && CPU_V7
926 default y if ARM_ARCH_TIMER
927 select HAVE_GENERIC_VDSO
928 select GENERIC_TIME_VSYSCALL
929 select GENERIC_VDSO_32
930 select GENERIC_GETTIMEOFDAY
931 help
932 Place in the process address space an ELF shared object
933 providing fast implementations of gettimeofday and
934 clock_gettime. Systems that implement the ARM architected
935 timer will receive maximum benefit.
936
937 You must have glibc 2.22 or later for programs to seamlessly
938 take advantage of this.
939
940
941config OUTER_CACHE
942 bool
943
944config OUTER_CACHE_SYNC
945 bool
946 select ARM_HEAVY_MB
947 help
948 The outer cache has a outer_cache_fns.sync function pointer
949 that can be used to drain the write buffer of the outer cache.
950
951config CACHE_B15_RAC
952 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
953 depends on ARCH_BRCMSTB
954 default y
955 help
956 This option enables the Broadcom Brahma-B15 read-ahead cache
957 controller. If disabled, the read-ahead cache remains off.
958
959config CACHE_FEROCEON_L2
960 bool "Enable the Feroceon L2 cache controller"
961 depends on ARCH_MV78XX0 || ARCH_MVEBU
962 default y
963 select OUTER_CACHE
964 help
965 This option enables the Feroceon L2 cache controller.
966
967config CACHE_FEROCEON_L2_WRITETHROUGH
968 bool "Force Feroceon L2 cache write through"
969 depends on CACHE_FEROCEON_L2
970 help
971 Say Y here to use the Feroceon L2 cache in writethrough mode.
972 Unless you specifically require this, say N for writeback mode.
973
974config MIGHT_HAVE_CACHE_L2X0
975 bool
976 help
977 This option should be selected by machines which have a L2x0
978 or PL310 cache controller, but where its use is optional.
979
980 The only effect of this option is to make CACHE_L2X0 and
981 related options available to the user for configuration.
982
983 Boards or SoCs which always require the cache controller
984 support to be present should select CACHE_L2X0 directly
985 instead of this option, thus preventing the user from
986 inadvertently configuring a broken kernel.
987
988config CACHE_L2X0
989 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
990 default MIGHT_HAVE_CACHE_L2X0
991 select OUTER_CACHE
992 select OUTER_CACHE_SYNC
993 help
994 This option enables the L2x0 PrimeCell.
995
996config CACHE_L2X0_PMU
997 bool "L2x0 performance monitor support" if CACHE_L2X0
998 depends on PERF_EVENTS
999 help
1000 This option enables support for the performance monitoring features
1001 of the L220 and PL310 outer cache controllers.
1002
1003if CACHE_L2X0
1004
1005config PL310_ERRATA_588369
1006 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1007 help
1008 The PL310 L2 cache controller implements three types of Clean &
1009 Invalidate maintenance operations: by Physical Address
1010 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1011 They are architecturally defined to behave as the execution of a
1012 clean operation followed immediately by an invalidate operation,
1013 both performing to the same memory location. This functionality
1014 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1015 as clean lines are not invalidated as a result of these operations.
1016
1017config PL310_ERRATA_727915
1018 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1019 help
1020 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1021 operation (offset 0x7FC). This operation runs in background so that
1022 PL310 can handle normal accesses while it is in progress. Under very
1023 rare circumstances, due to this erratum, write data can be lost when
1024 PL310 treats a cacheable write transaction during a Clean &
1025 Invalidate by Way operation. Revisions prior to r3p1 are affected by
1026 this errata (fixed in r3p1).
1027
1028config PL310_ERRATA_753970
1029 bool "PL310 errata: cache sync operation may be faulty"
1030 help
1031 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1032
1033 Under some condition the effect of cache sync operation on
1034 the store buffer still remains when the operation completes.
1035 This means that the store buffer is always asked to drain and
1036 this prevents it from merging any further writes. The workaround
1037 is to replace the normal offset of cache sync operation (0x730)
1038 by another offset targeting an unmapped PL310 register 0x740.
1039 This has the same effect as the cache sync operation: store buffer
1040 drain and waiting for all buffers empty.
1041
1042config PL310_ERRATA_769419
1043 bool "PL310 errata: no automatic Store Buffer drain"
1044 help
1045 On revisions of the PL310 prior to r3p2, the Store Buffer does
1046 not automatically drain. This can cause normal, non-cacheable
1047 writes to be retained when the memory system is idle, leading
1048 to suboptimal I/O performance for drivers using coherent DMA.
1049 This option adds a write barrier to the cpu_idle loop so that,
1050 on systems with an outer cache, the store buffer is drained
1051 explicitly.
1052
1053endif
1054
1055config CACHE_TAUROS2
1056 bool "Enable the Tauros2 L2 cache controller"
1057 depends on (CPU_MOHAWK || CPU_PJ4)
1058 default y
1059 select OUTER_CACHE
1060 help
1061 This option enables the Tauros2 L2 cache controller (as
1062 found on PJ1/PJ4).
1063
1064config CACHE_UNIPHIER
1065 bool "Enable the UniPhier outer cache controller"
1066 depends on ARCH_UNIPHIER
1067 select ARM_L1_CACHE_SHIFT_7
1068 select OUTER_CACHE
1069 select OUTER_CACHE_SYNC
1070 help
1071 This option enables the UniPhier outer cache (system cache)
1072 controller.
1073
1074config CACHE_XSC3L2
1075 bool "Enable the L2 cache on XScale3"
1076 depends on CPU_XSC3
1077 default y
1078 select OUTER_CACHE
1079 help
1080 This option enables the L2 cache on XScale3.
1081
1082config ARM_L1_CACHE_SHIFT_6
1083 bool
1084 default y if CPU_V7
1085 help
1086 Setting ARM L1 cache line size to 64 Bytes.
1087
1088config ARM_L1_CACHE_SHIFT_7
1089 bool
1090 help
1091 Setting ARM L1 cache line size to 128 Bytes.
1092
1093config ARM_L1_CACHE_SHIFT
1094 int
1095 default 7 if ARM_L1_CACHE_SHIFT_7
1096 default 6 if ARM_L1_CACHE_SHIFT_6
1097 default 5
1098
1099config ARM_DMA_MEM_BUFFERABLE
1100 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1101 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1102 help
1103 Historically, the kernel has used strongly ordered mappings to
1104 provide DMA coherent memory. With the advent of ARMv7, mapping
1105 memory with differing types results in unpredictable behaviour,
1106 so on these CPUs, this option is forced on.
1107
1108 Multiple mappings with differing attributes is also unpredictable
1109 on ARMv6 CPUs, but since they do not have aggressive speculative
1110 prefetch, no harm appears to occur.
1111
1112 However, drivers may be missing the necessary barriers for ARMv6,
1113 and therefore turning this on may result in unpredictable driver
1114 behaviour. Therefore, we offer this as an option.
1115
1116 On some of the beefier ARMv7-M machines (with DMA and write
1117 buffers) you likely want this enabled, while those that
1118 didn't need it until now also won't need it in the future.
1119
1120 You are recommended say 'Y' here and debug any affected drivers.
1121
1122config ARM_HEAVY_MB
1123 bool
1124
1125config DEBUG_ALIGN_RODATA
1126 bool "Make rodata strictly non-executable"
1127 depends on STRICT_KERNEL_RWX
1128 default y
1129 help
1130 If this is set, rodata will be made explicitly non-executable. This
1131 provides protection on the rare chance that attackers might find and
1132 use ROP gadgets that exist in the rodata section. This adds an
1133 additional section-aligned split of rodata from kernel text so it
1134 can be made explicitly non-executable. This padding may waste memory
1135 space to gain the additional protection.
1# SPDX-License-Identifier: GPL-2.0
2comment "Processor Type"
3
4# Select CPU types depending on the architecture selected. This selects
5# which CPUs we support in the kernel image, and the compiler instruction
6# optimiser behaviour.
7
8# ARM7TDMI
9config CPU_ARM7TDMI
10 bool
11 depends on !MMU
12 select CPU_32v4T
13 select CPU_ABRT_LV4T
14 select CPU_CACHE_V4
15 select CPU_PABRT_LEGACY
16 help
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
19
20 Say Y if you want support for the ARM7TDMI processor.
21 Otherwise, say N.
22
23# ARM720T
24config CPU_ARM720T
25 bool
26 select CPU_32v4T
27 select CPU_ABRT_LV4T
28 select CPU_CACHE_V4
29 select CPU_CACHE_VIVT
30 select CPU_COPY_V4WT if MMU
31 select CPU_CP15_MMU
32 select CPU_PABRT_LEGACY
33 select CPU_THUMB_CAPABLE
34 select CPU_TLB_V4WT if MMU
35 help
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
37 MMU built around an ARM7TDMI core.
38
39 Say Y if you want support for the ARM720T processor.
40 Otherwise, say N.
41
42# ARM740T
43config CPU_ARM740T
44 bool
45 depends on !MMU
46 select CPU_32v4T
47 select CPU_ABRT_LV4T
48 select CPU_CACHE_V4
49 select CPU_CP15_MPU
50 select CPU_PABRT_LEGACY
51 select CPU_THUMB_CAPABLE
52 help
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
55 an ARM7TDMI core.
56
57 Say Y if you want support for the ARM740T processor.
58 Otherwise, say N.
59
60# ARM9TDMI
61config CPU_ARM9TDMI
62 bool
63 depends on !MMU
64 select CPU_32v4T
65 select CPU_ABRT_NOMMU
66 select CPU_CACHE_V4
67 select CPU_PABRT_LEGACY
68 help
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
71
72 Say Y if you want support for the ARM9TDMI processor.
73 Otherwise, say N.
74
75# ARM920T
76config CPU_ARM920T
77 bool
78 select CPU_32v4T
79 select CPU_ABRT_EV4T
80 select CPU_CACHE_V4WT
81 select CPU_CACHE_VIVT
82 select CPU_COPY_V4WB if MMU
83 select CPU_CP15_MMU
84 select CPU_PABRT_LEGACY
85 select CPU_THUMB_CAPABLE
86 select CPU_TLB_V4WBI if MMU
87 help
88 The ARM920T is licensed to be produced by numerous vendors,
89 and is used in the Cirrus EP93xx and the Samsung S3C2410.
90
91 Say Y if you want support for the ARM920T processor.
92 Otherwise, say N.
93
94# ARM922T
95config CPU_ARM922T
96 bool
97 select CPU_32v4T
98 select CPU_ABRT_EV4T
99 select CPU_CACHE_V4WT
100 select CPU_CACHE_VIVT
101 select CPU_COPY_V4WB if MMU
102 select CPU_CP15_MMU
103 select CPU_PABRT_LEGACY
104 select CPU_THUMB_CAPABLE
105 select CPU_TLB_V4WBI if MMU
106 help
107 The ARM922T is a version of the ARM920T, but with smaller
108 instruction and data caches. It is used in Altera's
109 Excalibur XA device family and the ARM Integrator.
110
111 Say Y if you want support for the ARM922T processor.
112 Otherwise, say N.
113
114# ARM925T
115config CPU_ARM925T
116 bool
117 select CPU_32v4T
118 select CPU_ABRT_EV4T
119 select CPU_CACHE_V4WT
120 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
122 select CPU_CP15_MMU
123 select CPU_PABRT_LEGACY
124 select CPU_THUMB_CAPABLE
125 select CPU_TLB_V4WBI if MMU
126 help
127 The ARM925T is a mix between the ARM920T and ARM926T, but with
128 different instruction and data caches. It is used in TI's OMAP
129 device family.
130
131 Say Y if you want support for the ARM925T processor.
132 Otherwise, say N.
133
134# ARM926T
135config CPU_ARM926T
136 bool
137 select CPU_32v5
138 select CPU_ABRT_EV5TJ
139 select CPU_CACHE_VIVT
140 select CPU_COPY_V4WB if MMU
141 select CPU_CP15_MMU
142 select CPU_PABRT_LEGACY
143 select CPU_THUMB_CAPABLE
144 select CPU_TLB_V4WBI if MMU
145 help
146 This is a variant of the ARM920. It has slightly different
147 instruction sequences for cache and TLB operations. Curiously,
148 there is no documentation on it at the ARM corporate website.
149
150 Say Y if you want support for the ARM926T processor.
151 Otherwise, say N.
152
153# FA526
154config CPU_FA526
155 bool
156 select CPU_32v4
157 select CPU_ABRT_EV4
158 select CPU_CACHE_FA
159 select CPU_CACHE_VIVT
160 select CPU_COPY_FA if MMU
161 select CPU_CP15_MMU
162 select CPU_PABRT_LEGACY
163 select CPU_TLB_FA if MMU
164 help
165 The FA526 is a version of the ARMv4 compatible processor with
166 Branch Target Buffer, Unified TLB and cache line size 16.
167
168 Say Y if you want support for the FA526 processor.
169 Otherwise, say N.
170
171# ARM940T
172config CPU_ARM940T
173 bool
174 depends on !MMU
175 select CPU_32v4T
176 select CPU_ABRT_NOMMU
177 select CPU_CACHE_VIVT
178 select CPU_CP15_MPU
179 select CPU_PABRT_LEGACY
180 select CPU_THUMB_CAPABLE
181 help
182 ARM940T is a member of the ARM9TDMI family of general-
183 purpose microprocessors with MPU and separate 4KB
184 instruction and 4KB data cases, each with a 4-word line
185 length.
186
187 Say Y if you want support for the ARM940T processor.
188 Otherwise, say N.
189
190# ARM946E-S
191config CPU_ARM946E
192 bool
193 depends on !MMU
194 select CPU_32v5
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 select CPU_PABRT_LEGACY
199 select CPU_THUMB_CAPABLE
200 help
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
204
205 Say Y if you want support for the ARM946E-S processor.
206 Otherwise, say N.
207
208# ARM1020 - needs validating
209config CPU_ARM1020
210 bool
211 select CPU_32v5
212 select CPU_ABRT_EV4T
213 select CPU_CACHE_V4WT
214 select CPU_CACHE_VIVT
215 select CPU_COPY_V4WB if MMU
216 select CPU_CP15_MMU
217 select CPU_PABRT_LEGACY
218 select CPU_THUMB_CAPABLE
219 select CPU_TLB_V4WBI if MMU
220 help
221 The ARM1020 is the 32K cached version of the ARM10 processor,
222 with an addition of a floating-point unit.
223
224 Say Y if you want support for the ARM1020 processor.
225 Otherwise, say N.
226
227# ARM1020E - needs validating
228config CPU_ARM1020E
229 bool
230 depends on n
231 select CPU_32v5
232 select CPU_ABRT_EV4T
233 select CPU_CACHE_V4WT
234 select CPU_CACHE_VIVT
235 select CPU_COPY_V4WB if MMU
236 select CPU_CP15_MMU
237 select CPU_PABRT_LEGACY
238 select CPU_THUMB_CAPABLE
239 select CPU_TLB_V4WBI if MMU
240
241# ARM1022E
242config CPU_ARM1022
243 bool
244 select CPU_32v5
245 select CPU_ABRT_EV4T
246 select CPU_CACHE_VIVT
247 select CPU_COPY_V4WB if MMU # can probably do better
248 select CPU_CP15_MMU
249 select CPU_PABRT_LEGACY
250 select CPU_THUMB_CAPABLE
251 select CPU_TLB_V4WBI if MMU
252 help
253 The ARM1022E is an implementation of the ARMv5TE architecture
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
256
257 Say Y if you want support for the ARM1022E processor.
258 Otherwise, say N.
259
260# ARM1026EJ-S
261config CPU_ARM1026
262 bool
263 select CPU_32v5
264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
265 select CPU_CACHE_VIVT
266 select CPU_COPY_V4WB if MMU # can probably do better
267 select CPU_CP15_MMU
268 select CPU_PABRT_LEGACY
269 select CPU_THUMB_CAPABLE
270 select CPU_TLB_V4WBI if MMU
271 help
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
273 based upon the ARM10 integer core.
274
275 Say Y if you want support for the ARM1026EJ-S processor.
276 Otherwise, say N.
277
278# SA110
279config CPU_SA110
280 bool
281 select CPU_32v3 if ARCH_RPC
282 select CPU_32v4 if !ARCH_RPC
283 select CPU_ABRT_EV4
284 select CPU_CACHE_V4WB
285 select CPU_CACHE_VIVT
286 select CPU_COPY_V4WB if MMU
287 select CPU_CP15_MMU
288 select CPU_PABRT_LEGACY
289 select CPU_TLB_V4WB if MMU
290 help
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
292 is available at five speeds ranging from 100 MHz to 233 MHz.
293 More information is available at
294 <http://developer.intel.com/design/strong/sa110.htm>.
295
296 Say Y if you want support for the SA-110 processor.
297 Otherwise, say N.
298
299# SA1100
300config CPU_SA1100
301 bool
302 select CPU_32v4
303 select CPU_ABRT_EV4
304 select CPU_CACHE_V4WB
305 select CPU_CACHE_VIVT
306 select CPU_CP15_MMU
307 select CPU_PABRT_LEGACY
308 select CPU_TLB_V4WB if MMU
309
310# XScale
311config CPU_XSCALE
312 bool
313 select CPU_32v5
314 select CPU_ABRT_EV5T
315 select CPU_CACHE_VIVT
316 select CPU_CP15_MMU
317 select CPU_PABRT_LEGACY
318 select CPU_THUMB_CAPABLE
319 select CPU_TLB_V4WBI if MMU
320
321# XScale Core Version 3
322config CPU_XSC3
323 bool
324 select CPU_32v5
325 select CPU_ABRT_EV5T
326 select CPU_CACHE_VIVT
327 select CPU_CP15_MMU
328 select CPU_PABRT_LEGACY
329 select CPU_THUMB_CAPABLE
330 select CPU_TLB_V4WBI if MMU
331 select IO_36
332
333# Marvell PJ1 (Mohawk)
334config CPU_MOHAWK
335 bool
336 select CPU_32v5
337 select CPU_ABRT_EV5T
338 select CPU_CACHE_VIVT
339 select CPU_COPY_V4WB if MMU
340 select CPU_CP15_MMU
341 select CPU_PABRT_LEGACY
342 select CPU_THUMB_CAPABLE
343 select CPU_TLB_V4WBI if MMU
344
345# Feroceon
346config CPU_FEROCEON
347 bool
348 select CPU_32v5
349 select CPU_ABRT_EV5T
350 select CPU_CACHE_VIVT
351 select CPU_COPY_FEROCEON if MMU
352 select CPU_CP15_MMU
353 select CPU_PABRT_LEGACY
354 select CPU_THUMB_CAPABLE
355 select CPU_TLB_FEROCEON if MMU
356
357config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
360 default y
361 help
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
365
366# Marvell PJ4
367config CPU_PJ4
368 bool
369 select ARM_THUMBEE
370 select CPU_V7
371
372config CPU_PJ4B
373 bool
374 select CPU_V7
375
376# ARMv6
377config CPU_V6
378 bool
379 select CPU_32v6
380 select CPU_ABRT_EV6
381 select CPU_CACHE_V6
382 select CPU_CACHE_VIPT
383 select CPU_COPY_V6 if MMU
384 select CPU_CP15_MMU
385 select CPU_HAS_ASID if MMU
386 select CPU_PABRT_V6
387 select CPU_THUMB_CAPABLE
388 select CPU_TLB_V6 if MMU
389 select SMP_ON_UP if SMP
390
391# ARMv6k
392config CPU_V6K
393 bool
394 select CPU_32v6
395 select CPU_32v6K
396 select CPU_ABRT_EV6
397 select CPU_CACHE_V6
398 select CPU_CACHE_VIPT
399 select CPU_COPY_V6 if MMU
400 select CPU_CP15_MMU
401 select CPU_HAS_ASID if MMU
402 select CPU_PABRT_V6
403 select CPU_THUMB_CAPABLE
404 select CPU_TLB_V6 if MMU
405
406# ARMv7 and ARMv8 architectures
407config CPU_V7
408 bool
409 select CPU_32v6K
410 select CPU_32v7
411 select CPU_ABRT_EV7
412 select CPU_CACHE_V7
413 select CPU_CACHE_VIPT
414 select CPU_COPY_V6 if MMU
415 select CPU_CP15_MMU if MMU
416 select CPU_CP15_MPU if !MMU
417 select CPU_HAS_ASID if MMU
418 select CPU_PABRT_V7
419 select CPU_SPECTRE if MMU
420 select CPU_THUMB_CAPABLE
421 select CPU_TLB_V7 if MMU
422
423# ARMv7M
424config CPU_V7M
425 bool
426 select CPU_32v7M
427 select CPU_ABRT_NOMMU
428 select CPU_CACHE_V7M
429 select CPU_CACHE_NOP
430 select CPU_PABRT_LEGACY
431 select CPU_THUMBONLY
432
433config CPU_THUMBONLY
434 bool
435 select CPU_THUMB_CAPABLE
436 # There are no CPUs available with MMU that don't implement an ARM ISA:
437 depends on !MMU
438 help
439 Select this if your CPU doesn't support the 32 bit ARM instructions.
440
441config CPU_THUMB_CAPABLE
442 bool
443 help
444 Select this if your CPU can support Thumb mode.
445
446# Figure out what processor architecture version we should be using.
447# This defines the compiler instruction set which depends on the machine type.
448config CPU_32v3
449 bool
450 select CPU_USE_DOMAINS if MMU
451 select NEED_KUSER_HELPERS
452 select TLS_REG_EMUL if SMP || !MMU
453 select CPU_NO_EFFICIENT_FFS
454
455config CPU_32v4
456 bool
457 select CPU_USE_DOMAINS if MMU
458 select NEED_KUSER_HELPERS
459 select TLS_REG_EMUL if SMP || !MMU
460 select CPU_NO_EFFICIENT_FFS
461
462config CPU_32v4T
463 bool
464 select CPU_USE_DOMAINS if MMU
465 select NEED_KUSER_HELPERS
466 select TLS_REG_EMUL if SMP || !MMU
467 select CPU_NO_EFFICIENT_FFS
468
469config CPU_32v5
470 bool
471 select CPU_USE_DOMAINS if MMU
472 select NEED_KUSER_HELPERS
473 select TLS_REG_EMUL if SMP || !MMU
474
475config CPU_32v6
476 bool
477 select TLS_REG_EMUL if !CPU_32v6K && !MMU
478
479config CPU_32v6K
480 bool
481
482config CPU_32v7
483 bool
484
485config CPU_32v7M
486 bool
487
488# The abort model
489config CPU_ABRT_NOMMU
490 bool
491
492config CPU_ABRT_EV4
493 bool
494
495config CPU_ABRT_EV4T
496 bool
497
498config CPU_ABRT_LV4T
499 bool
500
501config CPU_ABRT_EV5T
502 bool
503
504config CPU_ABRT_EV5TJ
505 bool
506
507config CPU_ABRT_EV6
508 bool
509
510config CPU_ABRT_EV7
511 bool
512
513config CPU_PABRT_LEGACY
514 bool
515
516config CPU_PABRT_V6
517 bool
518
519config CPU_PABRT_V7
520 bool
521
522# The cache model
523config CPU_CACHE_V4
524 bool
525
526config CPU_CACHE_V4WT
527 bool
528
529config CPU_CACHE_V4WB
530 bool
531
532config CPU_CACHE_V6
533 bool
534
535config CPU_CACHE_V7
536 bool
537
538config CPU_CACHE_NOP
539 bool
540
541config CPU_CACHE_VIVT
542 bool
543
544config CPU_CACHE_VIPT
545 bool
546
547config CPU_CACHE_FA
548 bool
549
550config CPU_CACHE_V7M
551 bool
552
553if MMU
554# The copy-page model
555config CPU_COPY_V4WT
556 bool
557
558config CPU_COPY_V4WB
559 bool
560
561config CPU_COPY_FEROCEON
562 bool
563
564config CPU_COPY_FA
565 bool
566
567config CPU_COPY_V6
568 bool
569
570# This selects the TLB model
571config CPU_TLB_V4WT
572 bool
573 help
574 ARM Architecture Version 4 TLB with writethrough cache.
575
576config CPU_TLB_V4WB
577 bool
578 help
579 ARM Architecture Version 4 TLB with writeback cache.
580
581config CPU_TLB_V4WBI
582 bool
583 help
584 ARM Architecture Version 4 TLB with writeback cache and invalidate
585 instruction cache entry.
586
587config CPU_TLB_FEROCEON
588 bool
589 help
590 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
591
592config CPU_TLB_FA
593 bool
594 help
595 Faraday ARM FA526 architecture, unified TLB with writeback cache
596 and invalidate instruction cache entry. Branch target buffer is
597 also supported.
598
599config CPU_TLB_V6
600 bool
601
602config CPU_TLB_V7
603 bool
604
605endif
606
607config CPU_HAS_ASID
608 bool
609 help
610 This indicates whether the CPU has the ASID register; used to
611 tag TLB and possibly cache entries.
612
613config CPU_CP15
614 bool
615 help
616 Processor has the CP15 register.
617
618config CPU_CP15_MMU
619 bool
620 select CPU_CP15
621 help
622 Processor has the CP15 register, which has MMU related registers.
623
624config CPU_CP15_MPU
625 bool
626 select CPU_CP15
627 help
628 Processor has the CP15 register, which has MPU related registers.
629
630config CPU_USE_DOMAINS
631 bool
632 help
633 This option enables or disables the use of domain switching
634 using the DACR (domain access control register) to protect memory
635 domains from each other. In Linux we use three domains: kernel, user
636 and IO. The domains are used to protect userspace from kernelspace
637 and to handle IO-space as a special type of memory by assigning
638 manager or client roles to running code (such as a process).
639
640config CPU_V7M_NUM_IRQ
641 int "Number of external interrupts connected to the NVIC"
642 depends on CPU_V7M
643 default 90 if ARCH_STM32
644 default 112 if SOC_VF610
645 default 240
646 help
647 This option indicates the number of interrupts connected to the NVIC.
648 The value can be larger than the real number of interrupts supported
649 by the system, but must not be lower.
650 The default value is 240, corresponding to the maximum number of
651 interrupts supported by the NVIC on Cortex-M family.
652
653 If unsure, keep default value.
654
655#
656# CPU supports 36-bit I/O
657#
658config IO_36
659 bool
660
661comment "Processor Features"
662
663config ARM_LPAE
664 bool "Support for the Large Physical Address Extension"
665 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
666 !CPU_32v4 && !CPU_32v3
667 select PHYS_ADDR_T_64BIT
668 select SWIOTLB
669 help
670 Say Y if you have an ARMv7 processor supporting the LPAE page
671 table format and you would like to access memory beyond the
672 4GB limit. The resulting kernel image will not run on
673 processors without the LPA extension.
674
675 If unsure, say N.
676
677config ARM_PV_FIXUP
678 def_bool y
679 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
680
681config ARM_THUMB
682 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
683 depends on CPU_THUMB_CAPABLE && !CPU_32v4
684 default y
685 help
686 Say Y if you want to include kernel support for running user space
687 Thumb binaries.
688
689 The Thumb instruction set is a compressed form of the standard ARM
690 instruction set resulting in smaller binaries at the expense of
691 slightly less efficient code.
692
693 If this option is disabled, and you run userspace that switches to
694 Thumb mode, signal handling will not work correctly, resulting in
695 segmentation faults or illegal instruction aborts.
696
697 If you don't know what this all is, saying Y is a safe choice.
698
699config ARM_THUMBEE
700 bool "Enable ThumbEE CPU extension"
701 depends on CPU_V7
702 help
703 Say Y here if you have a CPU with the ThumbEE extension and code to
704 make use of it. Say N for code that can run on CPUs without ThumbEE.
705
706config ARM_VIRT_EXT
707 bool
708 default y if CPU_V7
709 help
710 Enable the kernel to make use of the ARM Virtualization
711 Extensions to install hypervisors without run-time firmware
712 assistance.
713
714 A compliant bootloader is required in order to make maximum
715 use of this feature. Refer to Documentation/arch/arm/booting.rst for
716 details.
717
718config SWP_EMULATE
719 bool "Emulate SWP/SWPB instructions" if !SMP
720 depends on CPU_V7
721 default y if SMP
722 select HAVE_PROC_CPU if PROC_FS
723 help
724 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
725 ARMv7 multiprocessing extensions introduce the ability to disable
726 these instructions, triggering an undefined instruction exception
727 when executed. Say Y here to enable software emulation of these
728 instructions for userspace (not kernel) using LDREX/STREX.
729 Also creates /proc/cpu/swp_emulation for statistics.
730
731 In some older versions of glibc [<=2.8] SWP is used during futex
732 trylock() operations with the assumption that the code will not
733 be preempted. This invalid assumption may be more likely to fail
734 with SWP emulation enabled, leading to deadlock of the user
735 application.
736
737 NOTE: when accessing uncached shared regions, LDREX/STREX rely
738 on an external transaction monitoring block called a global
739 monitor to maintain update atomicity. If your system does not
740 implement a global monitor, this option can cause programs that
741 perform SWP operations to uncached memory to deadlock.
742
743 If unsure, say Y.
744
745choice
746 prompt "CPU Endianness"
747 default CPU_LITTLE_ENDIAN
748
749config CPU_LITTLE_ENDIAN
750 bool "Built little-endian kernel"
751 help
752 Say Y if you plan on running a kernel in little-endian mode.
753 This is the default and is used in practically all modern user
754 space builds.
755
756config CPU_BIG_ENDIAN
757 bool "Build big-endian kernel"
758 depends on !LD_IS_LLD
759 help
760 Say Y if you plan on running a kernel in big-endian mode.
761 This works on many machines using ARMv6 or newer processors
762 but requires big-endian user space.
763
764 The only ARMv5 platform with big-endian support is
765 Intel IXP4xx.
766
767endchoice
768
769config CPU_ENDIAN_BE8
770 bool
771 depends on CPU_BIG_ENDIAN
772 default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
773 help
774 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
775
776config CPU_ENDIAN_BE32
777 bool
778 depends on CPU_BIG_ENDIAN
779 default !CPU_ENDIAN_BE8
780 help
781 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
782
783config CPU_HIGH_VECTOR
784 depends on !MMU && CPU_CP15 && !CPU_ARM740T
785 bool "Select the High exception vector"
786 help
787 Say Y here to select high exception vector(0xFFFF0000~).
788 The exception vector can vary depending on the platform
789 design in nommu mode. If your platform needs to select
790 high exception vector, say Y.
791 Otherwise or if you are unsure, say N, and the low exception
792 vector (0x00000000~) will be used.
793
794config CPU_ICACHE_DISABLE
795 bool "Disable I-Cache (I-bit)"
796 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
797 help
798 Say Y here to disable the processor instruction cache. Unless
799 you have a reason not to or are unsure, say N.
800
801config CPU_ICACHE_MISMATCH_WORKAROUND
802 bool "Workaround for I-Cache line size mismatch between CPU cores"
803 depends on SMP && CPU_V7
804 help
805 Some big.LITTLE systems have I-Cache line size mismatch between
806 LITTLE and big cores. Say Y here to enable a workaround for
807 proper I-Cache support on such systems. If unsure, say N.
808
809config CPU_DCACHE_DISABLE
810 bool "Disable D-Cache (C-bit)"
811 depends on (CPU_CP15 && !SMP) || CPU_V7M
812 help
813 Say Y here to disable the processor data cache. Unless
814 you have a reason not to or are unsure, say N.
815
816config CPU_DCACHE_SIZE
817 hex
818 depends on CPU_ARM740T || CPU_ARM946E
819 default 0x00001000 if CPU_ARM740T
820 default 0x00002000 # default size for ARM946E-S
821 help
822 Some cores are synthesizable to have various sized cache. For
823 ARM946E-S case, it can vary from 0KB to 1MB.
824 To support such cache operations, it is efficient to know the size
825 before compile time.
826 If your SoC is configured to have a different size, define the value
827 here with proper conditions.
828
829config CPU_DCACHE_WRITETHROUGH
830 bool "Force write through D-cache"
831 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
832 default y if CPU_ARM925T
833 help
834 Say Y here to use the data cache in writethrough mode. Unless you
835 specifically require this or are unsure, say N.
836
837config CPU_CACHE_ROUND_ROBIN
838 bool "Round robin I and D cache replacement algorithm"
839 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
840 help
841 Say Y here to use the predictable round-robin cache replacement
842 policy. Unless you specifically require this or are unsure, say N.
843
844config CPU_BPREDICT_DISABLE
845 bool "Disable branch prediction"
846 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
847 help
848 Say Y here to disable branch prediction. If unsure, say N.
849
850config CPU_SPECTRE
851 bool
852 select GENERIC_CPU_VULNERABILITIES
853
854config HARDEN_BRANCH_PREDICTOR
855 bool "Harden the branch predictor against aliasing attacks" if EXPERT
856 depends on CPU_SPECTRE
857 default y
858 help
859 Speculation attacks against some high-performance processors rely
860 on being able to manipulate the branch predictor for a victim
861 context by executing aliasing branches in the attacker context.
862 Such attacks can be partially mitigated against by clearing
863 internal branch predictor state and limiting the prediction
864 logic in some situations.
865
866 This config option will take CPU-specific actions to harden
867 the branch predictor against aliasing attacks and may rely on
868 specific instruction sequences or control bits being set by
869 the system firmware.
870
871 If unsure, say Y.
872
873config HARDEN_BRANCH_HISTORY
874 bool "Harden Spectre style attacks against branch history" if EXPERT
875 depends on CPU_SPECTRE
876 default y
877 help
878 Speculation attacks against some high-performance processors can
879 make use of branch history to influence future speculation. When
880 taking an exception, a sequence of branches overwrites the branch
881 history, or branch history is invalidated.
882
883config TLS_REG_EMUL
884 bool
885 select NEED_KUSER_HELPERS
886 help
887 An SMP system using a pre-ARMv6 processor (there are apparently
888 a few prototypes like that in existence) and therefore access to
889 that required register must be emulated.
890
891config NEED_KUSER_HELPERS
892 bool
893
894config KUSER_HELPERS
895 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
896 depends on MMU
897 default y
898 help
899 Warning: disabling this option may break user programs.
900
901 Provide kuser helpers in the vector page. The kernel provides
902 helper code to userspace in read only form at a fixed location
903 in the high vector page to allow userspace to be independent of
904 the CPU type fitted to the system. This permits binaries to be
905 run on ARMv4 through to ARMv7 without modification.
906
907 See Documentation/arch/arm/kernel_user_helpers.rst for details.
908
909 However, the fixed address nature of these helpers can be used
910 by ROP (return orientated programming) authors when creating
911 exploits.
912
913 If all of the binaries and libraries which run on your platform
914 are built specifically for your platform, and make no use of
915 these helpers, then you can turn this option off to hinder
916 such exploits. However, in that case, if a binary or library
917 relying on those helpers is run, it will receive a SIGILL signal,
918 which will terminate the program.
919
920 Say N here only if you are absolutely certain that you do not
921 need these helpers; otherwise, the safe option is to say Y.
922
923config VDSO
924 bool "Enable VDSO for acceleration of some system calls"
925 depends on AEABI && MMU && CPU_V7
926 default y if ARM_ARCH_TIMER
927 select HAVE_GENERIC_VDSO
928 select GENERIC_TIME_VSYSCALL
929 select GENERIC_VDSO_32
930 select GENERIC_GETTIMEOFDAY
931 help
932 Place in the process address space an ELF shared object
933 providing fast implementations of gettimeofday and
934 clock_gettime. Systems that implement the ARM architected
935 timer will receive maximum benefit.
936
937 You must have glibc 2.22 or later for programs to seamlessly
938 take advantage of this.
939
940
941config OUTER_CACHE
942 bool
943
944config OUTER_CACHE_SYNC
945 bool
946 select ARM_HEAVY_MB
947 help
948 The outer cache has a outer_cache_fns.sync function pointer
949 that can be used to drain the write buffer of the outer cache.
950
951config CACHE_B15_RAC
952 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
953 depends on ARCH_BRCMSTB
954 default y
955 help
956 This option enables the Broadcom Brahma-B15 read-ahead cache
957 controller. If disabled, the read-ahead cache remains off.
958
959config CACHE_FEROCEON_L2
960 bool "Enable the Feroceon L2 cache controller"
961 depends on ARCH_MV78XX0 || ARCH_MVEBU
962 default y
963 select OUTER_CACHE
964 help
965 This option enables the Feroceon L2 cache controller.
966
967config CACHE_FEROCEON_L2_WRITETHROUGH
968 bool "Force Feroceon L2 cache write through"
969 depends on CACHE_FEROCEON_L2
970 help
971 Say Y here to use the Feroceon L2 cache in writethrough mode.
972 Unless you specifically require this, say N for writeback mode.
973
974config MIGHT_HAVE_CACHE_L2X0
975 bool
976 help
977 This option should be selected by machines which have a L2x0
978 or PL310 cache controller, but where its use is optional.
979
980 The only effect of this option is to make CACHE_L2X0 and
981 related options available to the user for configuration.
982
983 Boards or SoCs which always require the cache controller
984 support to be present should select CACHE_L2X0 directly
985 instead of this option, thus preventing the user from
986 inadvertently configuring a broken kernel.
987
988config CACHE_L2X0
989 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
990 default MIGHT_HAVE_CACHE_L2X0
991 select OUTER_CACHE
992 select OUTER_CACHE_SYNC
993 help
994 This option enables the L2x0 PrimeCell.
995
996config CACHE_L2X0_PMU
997 bool "L2x0 performance monitor support" if CACHE_L2X0
998 depends on PERF_EVENTS
999 help
1000 This option enables support for the performance monitoring features
1001 of the L220 and PL310 outer cache controllers.
1002
1003if CACHE_L2X0
1004
1005config PL310_ERRATA_588369
1006 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1007 help
1008 The PL310 L2 cache controller implements three types of Clean &
1009 Invalidate maintenance operations: by Physical Address
1010 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1011 They are architecturally defined to behave as the execution of a
1012 clean operation followed immediately by an invalidate operation,
1013 both performing to the same memory location. This functionality
1014 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1015 as clean lines are not invalidated as a result of these operations.
1016
1017config PL310_ERRATA_727915
1018 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1019 help
1020 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1021 operation (offset 0x7FC). This operation runs in background so that
1022 PL310 can handle normal accesses while it is in progress. Under very
1023 rare circumstances, due to this erratum, write data can be lost when
1024 PL310 treats a cacheable write transaction during a Clean &
1025 Invalidate by Way operation. Revisions prior to r3p1 are affected by
1026 this errata (fixed in r3p1).
1027
1028config PL310_ERRATA_753970
1029 bool "PL310 errata: cache sync operation may be faulty"
1030 help
1031 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1032
1033 Under some condition the effect of cache sync operation on
1034 the store buffer still remains when the operation completes.
1035 This means that the store buffer is always asked to drain and
1036 this prevents it from merging any further writes. The workaround
1037 is to replace the normal offset of cache sync operation (0x730)
1038 by another offset targeting an unmapped PL310 register 0x740.
1039 This has the same effect as the cache sync operation: store buffer
1040 drain and waiting for all buffers empty.
1041
1042config PL310_ERRATA_769419
1043 bool "PL310 errata: no automatic Store Buffer drain"
1044 help
1045 On revisions of the PL310 prior to r3p2, the Store Buffer does
1046 not automatically drain. This can cause normal, non-cacheable
1047 writes to be retained when the memory system is idle, leading
1048 to suboptimal I/O performance for drivers using coherent DMA.
1049 This option adds a write barrier to the cpu_idle loop so that,
1050 on systems with an outer cache, the store buffer is drained
1051 explicitly.
1052
1053endif
1054
1055config CACHE_TAUROS2
1056 bool "Enable the Tauros2 L2 cache controller"
1057 depends on (CPU_MOHAWK || CPU_PJ4)
1058 default y
1059 select OUTER_CACHE
1060 help
1061 This option enables the Tauros2 L2 cache controller (as
1062 found on PJ1/PJ4).
1063
1064config CACHE_UNIPHIER
1065 bool "Enable the UniPhier outer cache controller"
1066 depends on ARCH_UNIPHIER
1067 select ARM_L1_CACHE_SHIFT_7
1068 select OUTER_CACHE
1069 select OUTER_CACHE_SYNC
1070 help
1071 This option enables the UniPhier outer cache (system cache)
1072 controller.
1073
1074config CACHE_XSC3L2
1075 bool "Enable the L2 cache on XScale3"
1076 depends on CPU_XSC3
1077 default y
1078 select OUTER_CACHE
1079 help
1080 This option enables the L2 cache on XScale3.
1081
1082config ARM_L1_CACHE_SHIFT_6
1083 bool
1084 default y if CPU_V7
1085 help
1086 Setting ARM L1 cache line size to 64 Bytes.
1087
1088config ARM_L1_CACHE_SHIFT_7
1089 bool
1090 help
1091 Setting ARM L1 cache line size to 128 Bytes.
1092
1093config ARM_L1_CACHE_SHIFT
1094 int
1095 default 7 if ARM_L1_CACHE_SHIFT_7
1096 default 6 if ARM_L1_CACHE_SHIFT_6
1097 default 5
1098
1099config ARM_DMA_MEM_BUFFERABLE
1100 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1101 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1102 help
1103 Historically, the kernel has used strongly ordered mappings to
1104 provide DMA coherent memory. With the advent of ARMv7, mapping
1105 memory with differing types results in unpredictable behaviour,
1106 so on these CPUs, this option is forced on.
1107
1108 Multiple mappings with differing attributes is also unpredictable
1109 on ARMv6 CPUs, but since they do not have aggressive speculative
1110 prefetch, no harm appears to occur.
1111
1112 However, drivers may be missing the necessary barriers for ARMv6,
1113 and therefore turning this on may result in unpredictable driver
1114 behaviour. Therefore, we offer this as an option.
1115
1116 On some of the beefier ARMv7-M machines (with DMA and write
1117 buffers) you likely want this enabled, while those that
1118 didn't need it until now also won't need it in the future.
1119
1120 You are recommended say 'Y' here and debug any affected drivers.
1121
1122config ARM_HEAVY_MB
1123 bool
1124
1125config DEBUG_ALIGN_RODATA
1126 bool "Make rodata strictly non-executable"
1127 depends on STRICT_KERNEL_RWX
1128 default y
1129 help
1130 If this is set, rodata will be made explicitly non-executable. This
1131 provides protection on the rare chance that attackers might find and
1132 use ROP gadgets that exist in the rodata section. This adds an
1133 additional section-aligned split of rodata from kernel text so it
1134 can be made explicitly non-executable. This padding may waste memory
1135 space to gain the additional protection.