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1/*
2 * arch/arm/mach-omap1/pm.h
3 *
4 * Header file for OMAP1 Power Management Routines
5 *
6 * Author: MontaVista Software, Inc.
7 * support@mvista.com
8 *
9 * Copyright 2002 MontaVista Software Inc.
10 *
11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#ifndef __ARCH_ARM_MACH_OMAP1_PM_H
35#define __ARCH_ARM_MACH_OMAP1_PM_H
36
37#include <linux/soc/ti/omap1-io.h>
38
39/*
40 * ----------------------------------------------------------------------------
41 * Register and offset definitions to be used in PM assembler code
42 * ----------------------------------------------------------------------------
43 */
44#define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
45#define ARM_IDLECT1_ASM_OFFSET 0x04
46#define ARM_IDLECT2_ASM_OFFSET 0x08
47
48#define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
49#define EMIFS_CONFIG_ASM_OFFSET 0x0c
50#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
51
52/*
53 * ----------------------------------------------------------------------------
54 * Power management bitmasks
55 * ----------------------------------------------------------------------------
56 */
57#define IDLE_WAIT_CYCLES 0x00000fff
58#define PERIPHERAL_ENABLE 0x2
59
60#define SELF_REFRESH_MODE 0x0c000001
61#define IDLE_EMIFS_REQUEST 0xc
62#define MODEM_32K_EN 0x1
63#define PER_EN 0x1
64
65#define CPU_SUSPEND_SIZE 200
66#define ULPD_LOW_PWR_EN 0x0001
67#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010
68#define ULPD_SETUP_ANALOG_CELL_3_VAL 0
69#define ULPD_POWER_CTRL_REG_VAL 0x0219
70
71#define DSP_IDLE_DELAY 10
72#define DSP_IDLE 0x0040
73#define DSP_RST 0x0004
74#define DSP_ENABLE 0x0002
75#define SUFFICIENT_DSP_RESET_TIME 1000
76#define DEFAULT_MPUI_CONFIG 0x05cf
77#define ENABLE_XORCLK 0x2
78#define DSP_CLOCK_ENABLE 0x2000
79#define DSP_IDLE_MODE 0x2
80#define TC_IDLE_REQUEST (0x0000000c)
81
82#define IRQ_LEVEL2 (1<<0)
83#define IRQ_KEYBOARD (1<<1)
84#define IRQ_UART2 (1<<15)
85
86#define PDE_BIT 0x08
87#define PWD_EN_BIT 0x04
88#define EN_PERCK_BIT 0x04
89
90#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
91#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
92#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
93#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
94
95/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
96#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7
97#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7
98#define OMAP1610_IDLECT3_VAL 0x3f
99#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c
100#define OMAP1610_IDLECT3 0xfffece24
101#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
102
103#ifndef __ASSEMBLER__
104
105#include <linux/clk.h>
106
107extern struct kset power_subsys;
108
109extern void prevent_idle_sleep(void);
110extern void allow_idle_sleep(void);
111
112extern void omap1_pm_idle(void);
113extern void omap1_pm_suspend(void);
114
115extern void omap1510_cpu_suspend(unsigned long, unsigned long);
116extern void omap1610_cpu_suspend(unsigned long, unsigned long);
117
118extern unsigned int omap1510_cpu_suspend_sz;
119extern unsigned int omap1610_cpu_suspend_sz;
120
121#ifdef CONFIG_OMAP_SERIAL_WAKE
122extern void omap_serial_wake_trigger(int enable);
123#else
124#define omap_serial_wakeup_init() {}
125#define omap_serial_wake_trigger(x) {}
126#endif /* CONFIG_OMAP_SERIAL_WAKE */
127
128#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
129#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
130#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
131
132#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
133#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
134#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
135
136#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
137#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
138#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
139
140#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
141#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
142#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
143
144#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
145#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
146#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
147
148/*
149 * List of global OMAP registers to preserve.
150 * More ones like CP and general purpose register values are preserved
151 * with the stack pointer in sleep.S.
152 */
153
154enum arm_save_state {
155 ARM_SLEEP_SAVE_START = 0,
156 /*
157 * MPU control registers 32 bits
158 */
159 ARM_SLEEP_SAVE_ARM_CKCTL,
160 ARM_SLEEP_SAVE_ARM_IDLECT1,
161 ARM_SLEEP_SAVE_ARM_IDLECT2,
162 ARM_SLEEP_SAVE_ARM_IDLECT3,
163 ARM_SLEEP_SAVE_ARM_EWUPCT,
164 ARM_SLEEP_SAVE_ARM_RSTCT1,
165 ARM_SLEEP_SAVE_ARM_RSTCT2,
166 ARM_SLEEP_SAVE_ARM_SYSST,
167 ARM_SLEEP_SAVE_SIZE
168};
169
170enum dsp_save_state {
171 DSP_SLEEP_SAVE_START = 0,
172 /*
173 * DSP registers 16 bits
174 */
175 DSP_SLEEP_SAVE_DSP_IDLECT2,
176 DSP_SLEEP_SAVE_SIZE
177};
178
179enum ulpd_save_state {
180 ULPD_SLEEP_SAVE_START = 0,
181 /*
182 * ULPD registers 16 bits
183 */
184 ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
185 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
186 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
187 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
188 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
189 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
190 ULPD_SLEEP_SAVE_SIZE
191};
192
193enum mpui1510_save_state {
194 MPUI1510_SLEEP_SAVE_START = 0,
195 /*
196 * MPUI registers 32 bits
197 */
198 MPUI1510_SLEEP_SAVE_MPUI_CTRL,
199 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
200 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
201 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
202 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
203 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
204 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
205 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
206#if defined(CONFIG_ARCH_OMAP15XX)
207 MPUI1510_SLEEP_SAVE_SIZE
208#else
209 MPUI1510_SLEEP_SAVE_SIZE = 0
210#endif
211};
212
213enum mpui1610_save_state {
214 MPUI1610_SLEEP_SAVE_START = 0,
215 /*
216 * MPUI registers 32 bits
217 */
218 MPUI1610_SLEEP_SAVE_MPUI_CTRL,
219 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
220 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
221 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
222 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
223 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
224 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
225 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
226 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
227 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
228 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
229#if defined(CONFIG_ARCH_OMAP16XX)
230 MPUI1610_SLEEP_SAVE_SIZE
231#else
232 MPUI1610_SLEEP_SAVE_SIZE = 0
233#endif
234};
235
236#endif /* ASSEMBLER */
237#endif /* __ASM_ARCH_OMAP_PM_H */
1/*
2 * arch/arm/mach-omap1/pm.h
3 *
4 * Header file for OMAP1 Power Management Routines
5 *
6 * Author: MontaVista Software, Inc.
7 * support@mvista.com
8 *
9 * Copyright 2002 MontaVista Software Inc.
10 *
11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#ifndef __ARCH_ARM_MACH_OMAP1_PM_H
35#define __ARCH_ARM_MACH_OMAP1_PM_H
36
37#include <linux/soc/ti/omap1-io.h>
38
39/*
40 * ----------------------------------------------------------------------------
41 * Register and offset definitions to be used in PM assembler code
42 * ----------------------------------------------------------------------------
43 */
44#define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
45#define ARM_IDLECT1_ASM_OFFSET 0x04
46#define ARM_IDLECT2_ASM_OFFSET 0x08
47
48#define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
49#define EMIFS_CONFIG_ASM_OFFSET 0x0c
50#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
51
52/*
53 * ----------------------------------------------------------------------------
54 * Power management bitmasks
55 * ----------------------------------------------------------------------------
56 */
57#define IDLE_WAIT_CYCLES 0x00000fff
58#define PERIPHERAL_ENABLE 0x2
59
60#define SELF_REFRESH_MODE 0x0c000001
61#define IDLE_EMIFS_REQUEST 0xc
62#define MODEM_32K_EN 0x1
63#define PER_EN 0x1
64
65#define CPU_SUSPEND_SIZE 200
66#define ULPD_LOW_PWR_EN 0x0001
67#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010
68#define ULPD_SETUP_ANALOG_CELL_3_VAL 0
69#define ULPD_POWER_CTRL_REG_VAL 0x0219
70
71#define DSP_IDLE_DELAY 10
72#define DSP_IDLE 0x0040
73#define DSP_RST 0x0004
74#define DSP_ENABLE 0x0002
75#define SUFFICIENT_DSP_RESET_TIME 1000
76#define DEFAULT_MPUI_CONFIG 0x05cf
77#define ENABLE_XORCLK 0x2
78#define DSP_CLOCK_ENABLE 0x2000
79#define DSP_IDLE_MODE 0x2
80#define TC_IDLE_REQUEST (0x0000000c)
81
82#define IRQ_LEVEL2 (1<<0)
83#define IRQ_KEYBOARD (1<<1)
84#define IRQ_UART2 (1<<15)
85
86#define PDE_BIT 0x08
87#define PWD_EN_BIT 0x04
88#define EN_PERCK_BIT 0x04
89
90#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
91#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
92#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
93#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
94
95/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
96#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7
97#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7
98#define OMAP1610_IDLECT3_VAL 0x3f
99#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c
100#define OMAP1610_IDLECT3 0xfffece24
101#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
102
103#ifndef __ASSEMBLER__
104
105#include <linux/clk.h>
106
107extern struct kset power_subsys;
108
109extern void prevent_idle_sleep(void);
110extern void allow_idle_sleep(void);
111
112extern void omap1_pm_idle(void);
113extern void omap1_pm_suspend(void);
114
115extern void omap1510_cpu_suspend(unsigned long, unsigned long);
116extern void omap1610_cpu_suspend(unsigned long, unsigned long);
117extern void omap1510_idle_loop_suspend(void);
118extern void omap1610_idle_loop_suspend(void);
119
120extern unsigned int omap1510_cpu_suspend_sz;
121extern unsigned int omap1610_cpu_suspend_sz;
122extern unsigned int omap1510_idle_loop_suspend_sz;
123extern unsigned int omap1610_idle_loop_suspend_sz;
124
125#ifdef CONFIG_OMAP_SERIAL_WAKE
126extern void omap_serial_wake_trigger(int enable);
127#else
128#define omap_serial_wakeup_init() {}
129#define omap_serial_wake_trigger(x) {}
130#endif /* CONFIG_OMAP_SERIAL_WAKE */
131
132#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
133#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
134#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
135
136#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
137#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
138#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
139
140#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
141#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
142#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
143
144#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
145#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
146#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
147
148#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
149#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
150#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
151
152/*
153 * List of global OMAP registers to preserve.
154 * More ones like CP and general purpose register values are preserved
155 * with the stack pointer in sleep.S.
156 */
157
158enum arm_save_state {
159 ARM_SLEEP_SAVE_START = 0,
160 /*
161 * MPU control registers 32 bits
162 */
163 ARM_SLEEP_SAVE_ARM_CKCTL,
164 ARM_SLEEP_SAVE_ARM_IDLECT1,
165 ARM_SLEEP_SAVE_ARM_IDLECT2,
166 ARM_SLEEP_SAVE_ARM_IDLECT3,
167 ARM_SLEEP_SAVE_ARM_EWUPCT,
168 ARM_SLEEP_SAVE_ARM_RSTCT1,
169 ARM_SLEEP_SAVE_ARM_RSTCT2,
170 ARM_SLEEP_SAVE_ARM_SYSST,
171 ARM_SLEEP_SAVE_SIZE
172};
173
174enum dsp_save_state {
175 DSP_SLEEP_SAVE_START = 0,
176 /*
177 * DSP registers 16 bits
178 */
179 DSP_SLEEP_SAVE_DSP_IDLECT2,
180 DSP_SLEEP_SAVE_SIZE
181};
182
183enum ulpd_save_state {
184 ULPD_SLEEP_SAVE_START = 0,
185 /*
186 * ULPD registers 16 bits
187 */
188 ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
189 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
190 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
191 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
192 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
193 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
194 ULPD_SLEEP_SAVE_SIZE
195};
196
197enum mpui1510_save_state {
198 MPUI1510_SLEEP_SAVE_START = 0,
199 /*
200 * MPUI registers 32 bits
201 */
202 MPUI1510_SLEEP_SAVE_MPUI_CTRL,
203 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
204 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
205 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
206 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
207 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
208 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
209 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
210#if defined(CONFIG_ARCH_OMAP15XX)
211 MPUI1510_SLEEP_SAVE_SIZE
212#else
213 MPUI1510_SLEEP_SAVE_SIZE = 0
214#endif
215};
216
217enum mpui1610_save_state {
218 MPUI1610_SLEEP_SAVE_START = 0,
219 /*
220 * MPUI registers 32 bits
221 */
222 MPUI1610_SLEEP_SAVE_MPUI_CTRL,
223 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
224 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
225 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
226 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
227 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
228 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
229 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
230 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
231 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
232 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
233#if defined(CONFIG_ARCH_OMAP16XX)
234 MPUI1610_SLEEP_SAVE_SIZE
235#else
236 MPUI1610_SLEEP_SAVE_SIZE = 0
237#endif
238};
239
240#endif /* ASSEMBLER */
241#endif /* __ASM_ARCH_OMAP_PM_H */