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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Generic definitions for Marvell MV78xx0 SoC flavors:
4 * MV781x0 and MV782x0.
5 */
6
7#ifndef __ASM_ARCH_MV78XX0_H
8#define __ASM_ARCH_MV78XX0_H
9
10#include "irqs.h"
11
12/*
13 * Marvell MV78xx0 address maps.
14 *
15 * phys
16 * c0000000 PCIe Memory space
17 * f0800000 PCIe #0 I/O space
18 * f0900000 PCIe #1 I/O space
19 * f0a00000 PCIe #2 I/O space
20 * f0b00000 PCIe #3 I/O space
21 * f0c00000 PCIe #4 I/O space
22 * f0d00000 PCIe #5 I/O space
23 * f0e00000 PCIe #6 I/O space
24 * f0f00000 PCIe #7 I/O space
25 * f1000000 on-chip peripheral registers
26 *
27 * virt phys size
28 * fe400000 f102x000 16K core-specific peripheral registers
29 * fee00000 f0800000 64K PCIe #0 I/O space
30 * fee10000 f0900000 64K PCIe #1 I/O space
31 * fee20000 f0a00000 64K PCIe #2 I/O space
32 * fee30000 f0b00000 64K PCIe #3 I/O space
33 * fee40000 f0c00000 64K PCIe #4 I/O space
34 * fee50000 f0d00000 64K PCIe #5 I/O space
35 * fee60000 f0e00000 64K PCIe #6 I/O space
36 * fee70000 f0f00000 64K PCIe #7 I/O space
37 * fec00000 f1000000 1M on-chip peripheral registers
38 */
39#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
43#define MV78XX0_CORE_REGS_SIZE SZ_16K
44
45#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
46#define MV78XX0_PCIE_IO_SIZE SZ_1M
47
48#define MV78XX0_REGS_PHYS_BASE 0xf1000000
49#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
50#define MV78XX0_REGS_SIZE SZ_1M
51
52#define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
53#define MV78XX0_SRAM_SIZE SZ_8K
54
55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
56#define MV78XX0_PCIE_MEM_SIZE 0x30000000
57
58#define MV78XX0_MBUS_SRAM_TARGET 0x09
59#define MV78XX0_MBUS_SRAM_ATTR 0x00
60
61/*
62 * Core-specific peripheral registers.
63 */
64#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
65#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
66#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE)
67#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE)
68#define BRIDGE_WINS_SZ (0xA000)
69
70/*
71 * Register Map
72 */
73#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
74#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
75#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
76#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
77#define DDR_WINDOW_CPU_SZ (0x20)
78
79#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
80#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
81#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
82#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
83#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
84#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
85#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
86#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
87#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
88#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
89#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
90#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
91#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
92#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
93#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
94
95#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
96#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
97
98#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
99#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
100#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
101#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
102
103#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
104#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
105#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
106
107#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900)
108
109#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
110#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
111
112#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
113#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
114#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
115#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
116
117#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000)
118
119#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
120
121/*
122 * Supported devices and revisions.
123 */
124#define MV78X00_Z0_DEV_ID 0x6381
125#define MV78X00_REV_Z0 1
126
127#define MV78100_DEV_ID 0x7810
128#define MV78100_REV_A0 1
129#define MV78100_REV_A1 2
130
131#define MV78200_DEV_ID 0x7820
132#define MV78200_REV_A0 1
133
134#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Generic definitions for Marvell MV78xx0 SoC flavors:
4 * MV781x0 and MV782x0.
5 */
6
7#ifndef __ASM_ARCH_MV78XX0_H
8#define __ASM_ARCH_MV78XX0_H
9
10#include "irqs.h"
11
12/*
13 * Marvell MV78xx0 address maps.
14 *
15 * phys
16 * c0000000 PCIe Memory space
17 * f0800000 PCIe #0 I/O space
18 * f0900000 PCIe #1 I/O space
19 * f0a00000 PCIe #2 I/O space
20 * f0b00000 PCIe #3 I/O space
21 * f0c00000 PCIe #4 I/O space
22 * f0d00000 PCIe #5 I/O space
23 * f0e00000 PCIe #6 I/O space
24 * f0f00000 PCIe #7 I/O space
25 * f1000000 on-chip peripheral registers
26 *
27 * virt phys size
28 * fe400000 f102x000 16K core-specific peripheral registers
29 * fee00000 f0800000 64K PCIe #0 I/O space
30 * fee10000 f0900000 64K PCIe #1 I/O space
31 * fee20000 f0a00000 64K PCIe #2 I/O space
32 * fee30000 f0b00000 64K PCIe #3 I/O space
33 * fee40000 f0c00000 64K PCIe #4 I/O space
34 * fee50000 f0d00000 64K PCIe #5 I/O space
35 * fee60000 f0e00000 64K PCIe #6 I/O space
36 * fee70000 f0f00000 64K PCIe #7 I/O space
37 * fec00000 f1000000 1M on-chip peripheral registers
38 */
39#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
43#define MV78XX0_CORE_REGS_SIZE SZ_16K
44
45#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
46#define MV78XX0_PCIE_IO_SIZE SZ_1M
47
48#define MV78XX0_REGS_PHYS_BASE 0xf1000000
49#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
50#define MV78XX0_REGS_SIZE SZ_1M
51
52#define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
53#define MV78XX0_SRAM_SIZE SZ_8K
54
55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
56#define MV78XX0_PCIE_MEM_SIZE 0x30000000
57
58#define MV78XX0_MBUS_SRAM_TARGET 0x09
59#define MV78XX0_MBUS_SRAM_ATTR 0x00
60
61/*
62 * Core-specific peripheral registers.
63 */
64#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
65#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
66#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE)
67#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE)
68#define BRIDGE_WINS_SZ (0xA000)
69
70/*
71 * Register Map
72 */
73#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
74#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
75#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
76#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
77#define DDR_WINDOW_CPU_SZ (0x20)
78
79#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
80#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
81#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
82#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
83#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
84#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
85#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
86#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
87#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
88#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
89#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
90#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
91#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
92#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
93#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
94
95#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
96#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
97
98#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
99#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
100#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
101#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
102
103#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
104#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
105#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
106
107#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900)
108
109#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
110#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
111
112#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
113#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
114#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
115#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
116
117#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000)
118
119#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
120
121/*
122 * Supported devices and revisions.
123 */
124#define MV78X00_Z0_DEV_ID 0x6381
125#define MV78X00_REV_Z0 1
126
127#define MV78100_DEV_ID 0x7810
128#define MV78100_REV_A0 1
129#define MV78100_REV_A1 2
130
131#define MV78200_DEV_ID 0x7820
132#define MV78200_REV_A0 1
133
134#endif