1// SPDX-License-Identifier: GPL-2.0+
 2/*
 3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 4 * Copyright 2017-2018 NXP
 5 *   Author: Dong Aisheng <aisheng.dong@nxp.com>
 6 */
 7
 8#include <linux/irqchip.h>
 9#include <linux/mfd/syscon.h>
10#include <linux/of_platform.h>
11#include <linux/regmap.h>
12#include <asm/mach/arch.h>
13
14#include "common.h"
15#include "cpuidle.h"
16#include "hardware.h"
17
18#define SIM_JTAG_ID_REG		0x8c
19
20static void __init imx7ulp_set_revision(void)
21{
22	struct regmap *sim;
23	u32 revision;
24
25	sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim");
26	if (IS_ERR(sim)) {
27		pr_warn("failed to find fsl,imx7ulp-sim regmap!\n");
28		return;
29	}
30
31	if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) {
32		pr_warn("failed to read sim regmap!\n");
33		return;
34	}
35
36	/*
37	 * bit[31:28] of JTAG_ID register defines revision as below from B0:
38	 * 0001        B0
39	 * 0010        B1
40	 * 0011        B2
41	 */
42	switch (revision >> 28) {
43	case 1:
44		imx_set_soc_revision(IMX_CHIP_REVISION_2_0);
45		break;
46	case 2:
47		imx_set_soc_revision(IMX_CHIP_REVISION_2_1);
48		break;
49	case 3:
50		imx_set_soc_revision(IMX_CHIP_REVISION_2_2);
51		break;
52	default:
53		imx_set_soc_revision(IMX_CHIP_REVISION_1_0);
54		break;
55	}
56}
57
58static void __init imx7ulp_init_machine(void)
59{
60	imx7ulp_pm_init();
61
62	mxc_set_cpu_type(MXC_CPU_IMX7ULP);
63	imx7ulp_set_revision();
64	of_platform_default_populate(NULL, NULL, NULL);
65}
66
67static const char *const imx7ulp_dt_compat[] __initconst = {
68	"fsl,imx7ulp",
69	NULL,
70};
71
72static void __init imx7ulp_init_late(void)
73{
74	if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
75		platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
76
77	imx7ulp_cpuidle_init();
78}
79
80DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
81	.init_machine	= imx7ulp_init_machine,
82	.dt_compat	= imx7ulp_dt_compat,
83	.init_late	= imx7ulp_init_late,
84MACHINE_END

 1// SPDX-License-Identifier: GPL-2.0+
 2/*
 3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 4 * Copyright 2017-2018 NXP
 5 *   Author: Dong Aisheng <aisheng.dong@nxp.com>
 6 */
 7
 8#include <linux/irqchip.h>
 9#include <linux/mfd/syscon.h>
10#include <linux/of_platform.h>
11#include <linux/regmap.h>
12#include <asm/mach/arch.h>
13
14#include "common.h"
15#include "cpuidle.h"
16#include "hardware.h"
17
18#define SIM_JTAG_ID_REG		0x8c
19
20static void __init imx7ulp_set_revision(void)
21{
22	struct regmap *sim;
23	u32 revision;
24
25	sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim");
26	if (IS_ERR(sim)) {
27		pr_warn("failed to find fsl,imx7ulp-sim regmap!\n");
28		return;
29	}
30
31	if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) {
32		pr_warn("failed to read sim regmap!\n");
33		return;
34	}
35
36	/*
37	 * bit[31:28] of JTAG_ID register defines revision as below from B0:
38	 * 0001        B0
39	 * 0010        B1
40	 * 0011        B2
41	 */
42	switch (revision >> 28) {
43	case 1:
44		imx_set_soc_revision(IMX_CHIP_REVISION_2_0);
45		break;
46	case 2:
47		imx_set_soc_revision(IMX_CHIP_REVISION_2_1);
48		break;
49	case 3:
50		imx_set_soc_revision(IMX_CHIP_REVISION_2_2);
51		break;
52	default:
53		imx_set_soc_revision(IMX_CHIP_REVISION_1_0);
54		break;
55	}
56}
57
58static void __init imx7ulp_init_machine(void)
59{
60	imx7ulp_pm_init();
61
62	mxc_set_cpu_type(MXC_CPU_IMX7ULP);
63	imx7ulp_set_revision();
64	of_platform_default_populate(NULL, NULL, NULL);
65}
66
67static const char *const imx7ulp_dt_compat[] __initconst = {
68	"fsl,imx7ulp",
69	NULL,
70};
71
72static void __init imx7ulp_init_late(void)
73{
74	if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
75		platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
76
77	imx7ulp_cpuidle_init();
78}
79
80DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
81	.init_machine	= imx7ulp_init_machine,
82	.dt_compat	= imx7ulp_dt_compat,
83	.init_late	= imx7ulp_init_late,
84MACHINE_END