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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2017
4 * Author: Amelie Delaunay <amelie.delaunay@st.com>
5 */
6
7#include <linux/bcd.h>
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/errno.h>
12#include <linux/iopoll.h>
13#include <linux/ioport.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinconf-generic.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/platform_device.h>
21#include <linux/pm_wakeirq.h>
22#include <linux/regmap.h>
23#include <linux/rtc.h>
24
25#define DRIVER_NAME "stm32_rtc"
26
27/* STM32_RTC_TR bit fields */
28#define STM32_RTC_TR_SEC_SHIFT 0
29#define STM32_RTC_TR_SEC GENMASK(6, 0)
30#define STM32_RTC_TR_MIN_SHIFT 8
31#define STM32_RTC_TR_MIN GENMASK(14, 8)
32#define STM32_RTC_TR_HOUR_SHIFT 16
33#define STM32_RTC_TR_HOUR GENMASK(21, 16)
34
35/* STM32_RTC_DR bit fields */
36#define STM32_RTC_DR_DATE_SHIFT 0
37#define STM32_RTC_DR_DATE GENMASK(5, 0)
38#define STM32_RTC_DR_MONTH_SHIFT 8
39#define STM32_RTC_DR_MONTH GENMASK(12, 8)
40#define STM32_RTC_DR_WDAY_SHIFT 13
41#define STM32_RTC_DR_WDAY GENMASK(15, 13)
42#define STM32_RTC_DR_YEAR_SHIFT 16
43#define STM32_RTC_DR_YEAR GENMASK(23, 16)
44
45/* STM32_RTC_CR bit fields */
46#define STM32_RTC_CR_FMT BIT(6)
47#define STM32_RTC_CR_ALRAE BIT(8)
48#define STM32_RTC_CR_ALRAIE BIT(12)
49#define STM32_RTC_CR_OSEL GENMASK(22, 21)
50#define STM32_RTC_CR_OSEL_ALARM_A FIELD_PREP(STM32_RTC_CR_OSEL, 0x01)
51#define STM32_RTC_CR_COE BIT(23)
52#define STM32_RTC_CR_TAMPOE BIT(26)
53#define STM32_RTC_CR_TAMPALRM_TYPE BIT(30)
54#define STM32_RTC_CR_OUT2EN BIT(31)
55
56/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
57#define STM32_RTC_ISR_ALRAWF BIT(0)
58#define STM32_RTC_ISR_INITS BIT(4)
59#define STM32_RTC_ISR_RSF BIT(5)
60#define STM32_RTC_ISR_INITF BIT(6)
61#define STM32_RTC_ISR_INIT BIT(7)
62#define STM32_RTC_ISR_ALRAF BIT(8)
63
64/* STM32_RTC_PRER bit fields */
65#define STM32_RTC_PRER_PRED_S_SHIFT 0
66#define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
67#define STM32_RTC_PRER_PRED_A_SHIFT 16
68#define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
69
70/* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
71#define STM32_RTC_ALRMXR_SEC_SHIFT 0
72#define STM32_RTC_ALRMXR_SEC GENMASK(6, 0)
73#define STM32_RTC_ALRMXR_SEC_MASK BIT(7)
74#define STM32_RTC_ALRMXR_MIN_SHIFT 8
75#define STM32_RTC_ALRMXR_MIN GENMASK(14, 8)
76#define STM32_RTC_ALRMXR_MIN_MASK BIT(15)
77#define STM32_RTC_ALRMXR_HOUR_SHIFT 16
78#define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16)
79#define STM32_RTC_ALRMXR_PM BIT(22)
80#define STM32_RTC_ALRMXR_HOUR_MASK BIT(23)
81#define STM32_RTC_ALRMXR_DATE_SHIFT 24
82#define STM32_RTC_ALRMXR_DATE GENMASK(29, 24)
83#define STM32_RTC_ALRMXR_WDSEL BIT(30)
84#define STM32_RTC_ALRMXR_WDAY_SHIFT 24
85#define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
86#define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
87
88/* STM32_RTC_SR/_SCR bit fields */
89#define STM32_RTC_SR_ALRA BIT(0)
90
91/* STM32_RTC_CFGR bit fields */
92#define STM32_RTC_CFGR_OUT2_RMP BIT(0)
93#define STM32_RTC_CFGR_LSCOEN GENMASK(2, 1)
94#define STM32_RTC_CFGR_LSCOEN_OUT1 1
95#define STM32_RTC_CFGR_LSCOEN_OUT2_RMP 2
96
97/* STM32_RTC_VERR bit fields */
98#define STM32_RTC_VERR_MINREV_SHIFT 0
99#define STM32_RTC_VERR_MINREV GENMASK(3, 0)
100#define STM32_RTC_VERR_MAJREV_SHIFT 4
101#define STM32_RTC_VERR_MAJREV GENMASK(7, 4)
102
103/* STM32_RTC_SECCFGR bit fields */
104#define STM32_RTC_SECCFGR 0x20
105#define STM32_RTC_SECCFGR_ALRA_SEC BIT(0)
106#define STM32_RTC_SECCFGR_INIT_SEC BIT(14)
107#define STM32_RTC_SECCFGR_SEC BIT(15)
108
109/* STM32_RTC_RXCIDCFGR bit fields */
110#define STM32_RTC_RXCIDCFGR(x) (0x80 + 0x4 * (x))
111#define STM32_RTC_RXCIDCFGR_CFEN BIT(0)
112#define STM32_RTC_RXCIDCFGR_CID GENMASK(6, 4)
113#define STM32_RTC_RXCIDCFGR_CID1 1
114
115/* STM32_RTC_WPR key constants */
116#define RTC_WPR_1ST_KEY 0xCA
117#define RTC_WPR_2ND_KEY 0x53
118#define RTC_WPR_WRONG_KEY 0xFF
119
120/* Max STM32 RTC register offset is 0x3FC */
121#define UNDEF_REG 0xFFFF
122
123/* STM32 RTC driver time helpers */
124#define SEC_PER_DAY (24 * 60 * 60)
125
126/* STM32 RTC pinctrl helpers */
127#define STM32_RTC_PINMUX(_name, _action, ...) { \
128 .name = (_name), \
129 .action = (_action), \
130 .groups = ((const char *[]){ __VA_ARGS__ }), \
131 .num_groups = ARRAY_SIZE(((const char *[]){ __VA_ARGS__ })), \
132}
133
134struct stm32_rtc;
135
136struct stm32_rtc_registers {
137 u16 tr;
138 u16 dr;
139 u16 cr;
140 u16 isr;
141 u16 prer;
142 u16 alrmar;
143 u16 wpr;
144 u16 sr;
145 u16 scr;
146 u16 cfgr;
147 u16 verr;
148};
149
150struct stm32_rtc_events {
151 u32 alra;
152};
153
154struct stm32_rtc_data {
155 const struct stm32_rtc_registers regs;
156 const struct stm32_rtc_events events;
157 void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
158 bool has_pclk;
159 bool need_dbp;
160 bool need_accuracy;
161 bool rif_protected;
162 bool has_lsco;
163 bool has_alarm_out;
164};
165
166struct stm32_rtc {
167 struct rtc_device *rtc_dev;
168 void __iomem *base;
169 struct regmap *dbp;
170 unsigned int dbp_reg;
171 unsigned int dbp_mask;
172 struct clk *pclk;
173 struct clk *rtc_ck;
174 const struct stm32_rtc_data *data;
175 int irq_alarm;
176 struct clk *clk_lsco;
177};
178
179struct stm32_rtc_rif_resource {
180 unsigned int num;
181 u32 bit;
182};
183
184static const struct stm32_rtc_rif_resource STM32_RTC_RES_ALRA = {0, STM32_RTC_SECCFGR_ALRA_SEC};
185static const struct stm32_rtc_rif_resource STM32_RTC_RES_INIT = {5, STM32_RTC_SECCFGR_INIT_SEC};
186
187static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
188{
189 const struct stm32_rtc_registers *regs = &rtc->data->regs;
190
191 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
192 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
193}
194
195static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
196{
197 const struct stm32_rtc_registers *regs = &rtc->data->regs;
198
199 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
200}
201
202enum stm32_rtc_pin_name {
203 NONE,
204 OUT1,
205 OUT2,
206 OUT2_RMP
207};
208
209static const struct pinctrl_pin_desc stm32_rtc_pinctrl_pins[] = {
210 PINCTRL_PIN(OUT1, "out1"),
211 PINCTRL_PIN(OUT2, "out2"),
212 PINCTRL_PIN(OUT2_RMP, "out2_rmp"),
213};
214
215static int stm32_rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
216{
217 return ARRAY_SIZE(stm32_rtc_pinctrl_pins);
218}
219
220static const char *stm32_rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
221 unsigned int selector)
222{
223 return stm32_rtc_pinctrl_pins[selector].name;
224}
225
226static int stm32_rtc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
227 unsigned int selector,
228 const unsigned int **pins,
229 unsigned int *num_pins)
230{
231 *pins = &stm32_rtc_pinctrl_pins[selector].number;
232 *num_pins = 1;
233 return 0;
234}
235
236static const struct pinctrl_ops stm32_rtc_pinctrl_ops = {
237 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
238 .dt_free_map = pinconf_generic_dt_free_map,
239 .get_groups_count = stm32_rtc_pinctrl_get_groups_count,
240 .get_group_name = stm32_rtc_pinctrl_get_group_name,
241 .get_group_pins = stm32_rtc_pinctrl_get_group_pins,
242};
243
244struct stm32_rtc_pinmux_func {
245 const char *name;
246 const char * const *groups;
247 const unsigned int num_groups;
248 int (*action)(struct pinctrl_dev *pctl_dev, unsigned int pin);
249};
250
251static int stm32_rtc_pinmux_action_alarm(struct pinctrl_dev *pctldev, unsigned int pin)
252{
253 struct stm32_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
254 struct stm32_rtc_registers regs = rtc->data->regs;
255 unsigned int cr = readl_relaxed(rtc->base + regs.cr);
256 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr);
257
258 if (!rtc->data->has_alarm_out)
259 return -EPERM;
260
261 cr &= ~STM32_RTC_CR_OSEL;
262 cr |= STM32_RTC_CR_OSEL_ALARM_A;
263 cr &= ~STM32_RTC_CR_TAMPOE;
264 cr &= ~STM32_RTC_CR_COE;
265 cr &= ~STM32_RTC_CR_TAMPALRM_TYPE;
266
267 switch (pin) {
268 case OUT1:
269 cr &= ~STM32_RTC_CR_OUT2EN;
270 cfgr &= ~STM32_RTC_CFGR_OUT2_RMP;
271 break;
272 case OUT2:
273 cr |= STM32_RTC_CR_OUT2EN;
274 cfgr &= ~STM32_RTC_CFGR_OUT2_RMP;
275 break;
276 case OUT2_RMP:
277 cr |= STM32_RTC_CR_OUT2EN;
278 cfgr |= STM32_RTC_CFGR_OUT2_RMP;
279 break;
280 default:
281 return -EINVAL;
282 }
283
284 stm32_rtc_wpr_unlock(rtc);
285 writel_relaxed(cr, rtc->base + regs.cr);
286 writel_relaxed(cfgr, rtc->base + regs.cfgr);
287 stm32_rtc_wpr_lock(rtc);
288
289 return 0;
290}
291
292static int stm32_rtc_pinmux_lsco_available(struct pinctrl_dev *pctldev, unsigned int pin)
293{
294 struct stm32_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
295 struct stm32_rtc_registers regs = rtc->data->regs;
296 unsigned int cr = readl_relaxed(rtc->base + regs.cr);
297 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr);
298 unsigned int calib = STM32_RTC_CR_COE;
299 unsigned int tampalrm = STM32_RTC_CR_TAMPOE | STM32_RTC_CR_OSEL;
300
301 switch (pin) {
302 case OUT1:
303 if ((!(cr & STM32_RTC_CR_OUT2EN) &&
304 ((cr & calib) || cr & tampalrm)) ||
305 ((cr & calib) && (cr & tampalrm)))
306 return -EBUSY;
307 break;
308 case OUT2_RMP:
309 if ((cr & STM32_RTC_CR_OUT2EN) &&
310 (cfgr & STM32_RTC_CFGR_OUT2_RMP) &&
311 ((cr & calib) || (cr & tampalrm)))
312 return -EBUSY;
313 break;
314 default:
315 return -EINVAL;
316 }
317
318 if (clk_get_rate(rtc->rtc_ck) != 32768)
319 return -ERANGE;
320
321 return 0;
322}
323
324static int stm32_rtc_pinmux_action_lsco(struct pinctrl_dev *pctldev, unsigned int pin)
325{
326 struct stm32_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
327 struct stm32_rtc_registers regs = rtc->data->regs;
328 struct device *dev = rtc->rtc_dev->dev.parent;
329 u8 lscoen;
330 int ret;
331
332 if (!rtc->data->has_lsco)
333 return -EPERM;
334
335 ret = stm32_rtc_pinmux_lsco_available(pctldev, pin);
336 if (ret)
337 return ret;
338
339 lscoen = (pin == OUT1) ? STM32_RTC_CFGR_LSCOEN_OUT1 : STM32_RTC_CFGR_LSCOEN_OUT2_RMP;
340
341 rtc->clk_lsco = clk_register_gate(dev, "rtc_lsco", __clk_get_name(rtc->rtc_ck),
342 CLK_IGNORE_UNUSED | CLK_IS_CRITICAL,
343 rtc->base + regs.cfgr, lscoen, 0, NULL);
344 if (IS_ERR(rtc->clk_lsco))
345 return PTR_ERR(rtc->clk_lsco);
346
347 of_clk_add_provider(dev->of_node, of_clk_src_simple_get, rtc->clk_lsco);
348
349 return 0;
350}
351
352static const struct stm32_rtc_pinmux_func stm32_rtc_pinmux_functions[] = {
353 STM32_RTC_PINMUX("lsco", &stm32_rtc_pinmux_action_lsco, "out1", "out2_rmp"),
354 STM32_RTC_PINMUX("alarm-a", &stm32_rtc_pinmux_action_alarm, "out1", "out2", "out2_rmp"),
355};
356
357static int stm32_rtc_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
358{
359 return ARRAY_SIZE(stm32_rtc_pinmux_functions);
360}
361
362static const char *stm32_rtc_pinmux_get_fname(struct pinctrl_dev *pctldev, unsigned int selector)
363{
364 return stm32_rtc_pinmux_functions[selector].name;
365}
366
367static int stm32_rtc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
368 const char * const **groups, unsigned int * const num_groups)
369{
370 *groups = stm32_rtc_pinmux_functions[selector].groups;
371 *num_groups = stm32_rtc_pinmux_functions[selector].num_groups;
372 return 0;
373}
374
375static int stm32_rtc_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
376 unsigned int group)
377{
378 struct stm32_rtc_pinmux_func selected_func = stm32_rtc_pinmux_functions[selector];
379 struct pinctrl_pin_desc pin = stm32_rtc_pinctrl_pins[group];
380
381 /* Call action */
382 if (selected_func.action)
383 return selected_func.action(pctldev, pin.number);
384
385 return -EINVAL;
386}
387
388static const struct pinmux_ops stm32_rtc_pinmux_ops = {
389 .get_functions_count = stm32_rtc_pinmux_get_functions_count,
390 .get_function_name = stm32_rtc_pinmux_get_fname,
391 .get_function_groups = stm32_rtc_pinmux_get_groups,
392 .set_mux = stm32_rtc_pinmux_set_mux,
393 .strict = true,
394};
395
396static struct pinctrl_desc stm32_rtc_pdesc = {
397 .name = DRIVER_NAME,
398 .pins = stm32_rtc_pinctrl_pins,
399 .npins = ARRAY_SIZE(stm32_rtc_pinctrl_pins),
400 .owner = THIS_MODULE,
401 .pctlops = &stm32_rtc_pinctrl_ops,
402 .pmxops = &stm32_rtc_pinmux_ops,
403};
404
405static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
406{
407 const struct stm32_rtc_registers *regs = &rtc->data->regs;
408 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
409
410 if (!(isr & STM32_RTC_ISR_INITF)) {
411 isr |= STM32_RTC_ISR_INIT;
412 writel_relaxed(isr, rtc->base + regs->isr);
413
414 /*
415 * It takes around 2 rtc_ck clock cycles to enter in
416 * initialization phase mode (and have INITF flag set). As
417 * slowest rtc_ck frequency may be 32kHz and highest should be
418 * 1MHz, we poll every 10 us with a timeout of 100ms.
419 */
420 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr,
421 (isr & STM32_RTC_ISR_INITF),
422 10, 100000);
423 }
424
425 return 0;
426}
427
428static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
429{
430 const struct stm32_rtc_registers *regs = &rtc->data->regs;
431 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
432
433 isr &= ~STM32_RTC_ISR_INIT;
434 writel_relaxed(isr, rtc->base + regs->isr);
435}
436
437static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
438{
439 const struct stm32_rtc_registers *regs = &rtc->data->regs;
440 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
441
442 isr &= ~STM32_RTC_ISR_RSF;
443 writel_relaxed(isr, rtc->base + regs->isr);
444
445 /*
446 * Wait for RSF to be set to ensure the calendar registers are
447 * synchronised, it takes around 2 rtc_ck clock cycles
448 */
449 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
450 isr,
451 (isr & STM32_RTC_ISR_RSF),
452 10, 100000);
453}
454
455static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
456 unsigned int flags)
457{
458 rtc->data->clear_events(rtc, flags);
459}
460
461static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
462{
463 struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
464 const struct stm32_rtc_registers *regs = &rtc->data->regs;
465 const struct stm32_rtc_events *evts = &rtc->data->events;
466 unsigned int status, cr;
467
468 rtc_lock(rtc->rtc_dev);
469
470 status = readl_relaxed(rtc->base + regs->sr);
471 cr = readl_relaxed(rtc->base + regs->cr);
472
473 if ((status & evts->alra) &&
474 (cr & STM32_RTC_CR_ALRAIE)) {
475 /* Alarm A flag - Alarm interrupt */
476 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
477
478 /* Pass event to the kernel */
479 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
480
481 /* Clear event flags, otherwise new events won't be received */
482 stm32_rtc_clear_event_flags(rtc, evts->alra);
483 }
484
485 rtc_unlock(rtc->rtc_dev);
486
487 return IRQ_HANDLED;
488}
489
490/* Convert rtc_time structure from bin to bcd format */
491static void tm2bcd(struct rtc_time *tm)
492{
493 tm->tm_sec = bin2bcd(tm->tm_sec);
494 tm->tm_min = bin2bcd(tm->tm_min);
495 tm->tm_hour = bin2bcd(tm->tm_hour);
496
497 tm->tm_mday = bin2bcd(tm->tm_mday);
498 tm->tm_mon = bin2bcd(tm->tm_mon + 1);
499 tm->tm_year = bin2bcd(tm->tm_year - 100);
500 /*
501 * Number of days since Sunday
502 * - on kernel side, 0=Sunday...6=Saturday
503 * - on rtc side, 0=invalid,1=Monday...7=Sunday
504 */
505 tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
506}
507
508/* Convert rtc_time structure from bcd to bin format */
509static void bcd2tm(struct rtc_time *tm)
510{
511 tm->tm_sec = bcd2bin(tm->tm_sec);
512 tm->tm_min = bcd2bin(tm->tm_min);
513 tm->tm_hour = bcd2bin(tm->tm_hour);
514
515 tm->tm_mday = bcd2bin(tm->tm_mday);
516 tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
517 tm->tm_year = bcd2bin(tm->tm_year) + 100;
518 /*
519 * Number of days since Sunday
520 * - on kernel side, 0=Sunday...6=Saturday
521 * - on rtc side, 0=invalid,1=Monday...7=Sunday
522 */
523 tm->tm_wday %= 7;
524}
525
526static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
527{
528 struct stm32_rtc *rtc = dev_get_drvdata(dev);
529 const struct stm32_rtc_registers *regs = &rtc->data->regs;
530 unsigned int tr, dr;
531
532 /* Time and Date in BCD format */
533 tr = readl_relaxed(rtc->base + regs->tr);
534 dr = readl_relaxed(rtc->base + regs->dr);
535
536 tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
537 tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
538 tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
539
540 tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
541 tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
542 tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
543 tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
544
545 /* We don't report tm_yday and tm_isdst */
546
547 bcd2tm(tm);
548
549 return 0;
550}
551
552static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
553{
554 struct stm32_rtc *rtc = dev_get_drvdata(dev);
555 const struct stm32_rtc_registers *regs = &rtc->data->regs;
556 unsigned int tr, dr;
557 int ret = 0;
558
559 tm2bcd(tm);
560
561 /* Time in BCD format */
562 tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
563 ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
564 ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
565
566 /* Date in BCD format */
567 dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
568 ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
569 ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
570 ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
571
572 stm32_rtc_wpr_unlock(rtc);
573
574 ret = stm32_rtc_enter_init_mode(rtc);
575 if (ret) {
576 dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
577 goto end;
578 }
579
580 writel_relaxed(tr, rtc->base + regs->tr);
581 writel_relaxed(dr, rtc->base + regs->dr);
582
583 stm32_rtc_exit_init_mode(rtc);
584
585 ret = stm32_rtc_wait_sync(rtc);
586end:
587 stm32_rtc_wpr_lock(rtc);
588
589 return ret;
590}
591
592static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
593{
594 struct stm32_rtc *rtc = dev_get_drvdata(dev);
595 const struct stm32_rtc_registers *regs = &rtc->data->regs;
596 const struct stm32_rtc_events *evts = &rtc->data->events;
597 struct rtc_time *tm = &alrm->time;
598 unsigned int alrmar, cr, status;
599
600 alrmar = readl_relaxed(rtc->base + regs->alrmar);
601 cr = readl_relaxed(rtc->base + regs->cr);
602 status = readl_relaxed(rtc->base + regs->sr);
603
604 if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
605 /*
606 * Date/day doesn't matter in Alarm comparison so alarm
607 * triggers every day
608 */
609 tm->tm_mday = -1;
610 tm->tm_wday = -1;
611 } else {
612 if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
613 /* Alarm is set to a day of week */
614 tm->tm_mday = -1;
615 tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
616 STM32_RTC_ALRMXR_WDAY_SHIFT;
617 tm->tm_wday %= 7;
618 } else {
619 /* Alarm is set to a day of month */
620 tm->tm_wday = -1;
621 tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
622 STM32_RTC_ALRMXR_DATE_SHIFT;
623 }
624 }
625
626 if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
627 /* Hours don't matter in Alarm comparison */
628 tm->tm_hour = -1;
629 } else {
630 tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
631 STM32_RTC_ALRMXR_HOUR_SHIFT;
632 if (alrmar & STM32_RTC_ALRMXR_PM)
633 tm->tm_hour += 12;
634 }
635
636 if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
637 /* Minutes don't matter in Alarm comparison */
638 tm->tm_min = -1;
639 } else {
640 tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
641 STM32_RTC_ALRMXR_MIN_SHIFT;
642 }
643
644 if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
645 /* Seconds don't matter in Alarm comparison */
646 tm->tm_sec = -1;
647 } else {
648 tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
649 STM32_RTC_ALRMXR_SEC_SHIFT;
650 }
651
652 bcd2tm(tm);
653
654 alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
655 alrm->pending = (status & evts->alra) ? 1 : 0;
656
657 return 0;
658}
659
660static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
661{
662 struct stm32_rtc *rtc = dev_get_drvdata(dev);
663 const struct stm32_rtc_registers *regs = &rtc->data->regs;
664 const struct stm32_rtc_events *evts = &rtc->data->events;
665 unsigned int cr;
666
667 cr = readl_relaxed(rtc->base + regs->cr);
668
669 stm32_rtc_wpr_unlock(rtc);
670
671 /* We expose Alarm A to the kernel */
672 if (enabled)
673 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
674 else
675 cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
676 writel_relaxed(cr, rtc->base + regs->cr);
677
678 /* Clear event flags, otherwise new events won't be received */
679 stm32_rtc_clear_event_flags(rtc, evts->alra);
680
681 stm32_rtc_wpr_lock(rtc);
682
683 return 0;
684}
685
686static int stm32_rtc_valid_alrm(struct device *dev, struct rtc_time *tm)
687{
688 static struct rtc_time now;
689 time64_t max_alarm_time64;
690 int max_day_forward;
691 int next_month;
692 int next_year;
693
694 /*
695 * Assuming current date is M-D-Y H:M:S.
696 * RTC alarm can't be set on a specific month and year.
697 * So the valid alarm range is:
698 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
699 */
700 stm32_rtc_read_time(dev, &now);
701
702 /*
703 * Find the next month and the year of the next month.
704 * Note: tm_mon and next_month are from 0 to 11
705 */
706 next_month = now.tm_mon + 1;
707 if (next_month == 12) {
708 next_month = 0;
709 next_year = now.tm_year + 1;
710 } else {
711 next_year = now.tm_year;
712 }
713
714 /* Find the maximum limit of alarm in days. */
715 max_day_forward = rtc_month_days(now.tm_mon, now.tm_year)
716 - now.tm_mday
717 + min(rtc_month_days(next_month, next_year), now.tm_mday);
718
719 /* Convert to timestamp and compare the alarm time and its upper limit */
720 max_alarm_time64 = rtc_tm_to_time64(&now) + max_day_forward * SEC_PER_DAY;
721 return rtc_tm_to_time64(tm) <= max_alarm_time64 ? 0 : -EINVAL;
722}
723
724static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
725{
726 struct stm32_rtc *rtc = dev_get_drvdata(dev);
727 const struct stm32_rtc_registers *regs = &rtc->data->regs;
728 struct rtc_time *tm = &alrm->time;
729 unsigned int cr, isr, alrmar;
730 int ret = 0;
731
732 /*
733 * RTC alarm can't be set on a specific date, unless this date is
734 * up to the same day of month next month.
735 */
736 if (stm32_rtc_valid_alrm(dev, tm) < 0) {
737 dev_err(dev, "Alarm can be set only on upcoming month.\n");
738 return -EINVAL;
739 }
740
741 tm2bcd(tm);
742
743 alrmar = 0;
744 /* tm_year and tm_mon are not used because not supported by RTC */
745 alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
746 STM32_RTC_ALRMXR_DATE;
747 /* 24-hour format */
748 alrmar &= ~STM32_RTC_ALRMXR_PM;
749 alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
750 STM32_RTC_ALRMXR_HOUR;
751 alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
752 STM32_RTC_ALRMXR_MIN;
753 alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
754 STM32_RTC_ALRMXR_SEC;
755
756 stm32_rtc_wpr_unlock(rtc);
757
758 /* Disable Alarm */
759 cr = readl_relaxed(rtc->base + regs->cr);
760 cr &= ~STM32_RTC_CR_ALRAE;
761 writel_relaxed(cr, rtc->base + regs->cr);
762
763 /*
764 * Poll Alarm write flag to be sure that Alarm update is allowed: it
765 * takes around 2 rtc_ck clock cycles
766 */
767 ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
768 isr,
769 (isr & STM32_RTC_ISR_ALRAWF),
770 10, 100000);
771
772 if (ret) {
773 dev_err(dev, "Alarm update not allowed\n");
774 goto end;
775 }
776
777 /* Write to Alarm register */
778 writel_relaxed(alrmar, rtc->base + regs->alrmar);
779
780 stm32_rtc_alarm_irq_enable(dev, alrm->enabled);
781end:
782 stm32_rtc_wpr_lock(rtc);
783
784 return ret;
785}
786
787static const struct rtc_class_ops stm32_rtc_ops = {
788 .read_time = stm32_rtc_read_time,
789 .set_time = stm32_rtc_set_time,
790 .read_alarm = stm32_rtc_read_alarm,
791 .set_alarm = stm32_rtc_set_alarm,
792 .alarm_irq_enable = stm32_rtc_alarm_irq_enable,
793};
794
795static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
796 unsigned int flags)
797{
798 const struct stm32_rtc_registers *regs = &rtc->data->regs;
799
800 /* Flags are cleared by writing 0 in RTC_ISR */
801 writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
802 rtc->base + regs->isr);
803}
804
805static const struct stm32_rtc_data stm32_rtc_data = {
806 .has_pclk = false,
807 .need_dbp = true,
808 .need_accuracy = false,
809 .rif_protected = false,
810 .has_lsco = false,
811 .has_alarm_out = false,
812 .regs = {
813 .tr = 0x00,
814 .dr = 0x04,
815 .cr = 0x08,
816 .isr = 0x0C,
817 .prer = 0x10,
818 .alrmar = 0x1C,
819 .wpr = 0x24,
820 .sr = 0x0C, /* set to ISR offset to ease alarm management */
821 .scr = UNDEF_REG,
822 .cfgr = UNDEF_REG,
823 .verr = UNDEF_REG,
824 },
825 .events = {
826 .alra = STM32_RTC_ISR_ALRAF,
827 },
828 .clear_events = stm32_rtc_clear_events,
829};
830
831static const struct stm32_rtc_data stm32h7_rtc_data = {
832 .has_pclk = true,
833 .need_dbp = true,
834 .need_accuracy = false,
835 .rif_protected = false,
836 .has_lsco = false,
837 .has_alarm_out = false,
838 .regs = {
839 .tr = 0x00,
840 .dr = 0x04,
841 .cr = 0x08,
842 .isr = 0x0C,
843 .prer = 0x10,
844 .alrmar = 0x1C,
845 .wpr = 0x24,
846 .sr = 0x0C, /* set to ISR offset to ease alarm management */
847 .scr = UNDEF_REG,
848 .cfgr = UNDEF_REG,
849 .verr = UNDEF_REG,
850 },
851 .events = {
852 .alra = STM32_RTC_ISR_ALRAF,
853 },
854 .clear_events = stm32_rtc_clear_events,
855};
856
857static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
858 unsigned int flags)
859{
860 struct stm32_rtc_registers regs = rtc->data->regs;
861
862 /* Flags are cleared by writing 1 in RTC_SCR */
863 writel_relaxed(flags, rtc->base + regs.scr);
864}
865
866static const struct stm32_rtc_data stm32mp1_data = {
867 .has_pclk = true,
868 .need_dbp = false,
869 .need_accuracy = true,
870 .rif_protected = false,
871 .has_lsco = true,
872 .has_alarm_out = true,
873 .regs = {
874 .tr = 0x00,
875 .dr = 0x04,
876 .cr = 0x18,
877 .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
878 .prer = 0x10,
879 .alrmar = 0x40,
880 .wpr = 0x24,
881 .sr = 0x50,
882 .scr = 0x5C,
883 .cfgr = 0x60,
884 .verr = 0x3F4,
885 },
886 .events = {
887 .alra = STM32_RTC_SR_ALRA,
888 },
889 .clear_events = stm32mp1_rtc_clear_events,
890};
891
892static const struct stm32_rtc_data stm32mp25_data = {
893 .has_pclk = true,
894 .need_dbp = false,
895 .need_accuracy = true,
896 .rif_protected = true,
897 .has_lsco = true,
898 .has_alarm_out = true,
899 .regs = {
900 .tr = 0x00,
901 .dr = 0x04,
902 .cr = 0x18,
903 .isr = 0x0C, /* named RTC_ICSR on stm32mp25 */
904 .prer = 0x10,
905 .alrmar = 0x40,
906 .wpr = 0x24,
907 .sr = 0x50,
908 .scr = 0x5C,
909 .cfgr = 0x60,
910 .verr = 0x3F4,
911 },
912 .events = {
913 .alra = STM32_RTC_SR_ALRA,
914 },
915 .clear_events = stm32mp1_rtc_clear_events,
916};
917
918static const struct of_device_id stm32_rtc_of_match[] = {
919 { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
920 { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
921 { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
922 { .compatible = "st,stm32mp25-rtc", .data = &stm32mp25_data },
923 {}
924};
925MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
926
927static void stm32_rtc_clean_outs(struct stm32_rtc *rtc)
928{
929 struct stm32_rtc_registers regs = rtc->data->regs;
930 unsigned int cr = readl_relaxed(rtc->base + regs.cr);
931
932 cr &= ~STM32_RTC_CR_OSEL;
933 cr &= ~STM32_RTC_CR_TAMPOE;
934 cr &= ~STM32_RTC_CR_COE;
935 cr &= ~STM32_RTC_CR_TAMPALRM_TYPE;
936 cr &= ~STM32_RTC_CR_OUT2EN;
937
938 stm32_rtc_wpr_unlock(rtc);
939 writel_relaxed(cr, rtc->base + regs.cr);
940 stm32_rtc_wpr_lock(rtc);
941
942 if (regs.cfgr != UNDEF_REG) {
943 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr);
944
945 cfgr &= ~STM32_RTC_CFGR_LSCOEN;
946 cfgr &= ~STM32_RTC_CFGR_OUT2_RMP;
947 writel_relaxed(cfgr, rtc->base + regs.cfgr);
948 }
949}
950
951static int stm32_rtc_check_rif(struct stm32_rtc *stm32_rtc,
952 struct stm32_rtc_rif_resource res)
953{
954 u32 rxcidcfgr = readl_relaxed(stm32_rtc->base + STM32_RTC_RXCIDCFGR(res.num));
955 u32 seccfgr;
956
957 /* Check if RTC available for our CID */
958 if ((rxcidcfgr & STM32_RTC_RXCIDCFGR_CFEN) &&
959 (FIELD_GET(STM32_RTC_RXCIDCFGR_CID, rxcidcfgr) != STM32_RTC_RXCIDCFGR_CID1))
960 return -EACCES;
961
962 /* Check if RTC available for non secure world */
963 seccfgr = readl_relaxed(stm32_rtc->base + STM32_RTC_SECCFGR);
964 if ((seccfgr & STM32_RTC_SECCFGR_SEC) | (seccfgr & res.bit))
965 return -EACCES;
966
967 return 0;
968}
969
970static int stm32_rtc_init(struct platform_device *pdev,
971 struct stm32_rtc *rtc)
972{
973 const struct stm32_rtc_registers *regs = &rtc->data->regs;
974 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
975 unsigned int rate;
976 int ret;
977
978 rate = clk_get_rate(rtc->rtc_ck);
979
980 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
981 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
982 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
983
984 if (rate > (pred_a_max + 1) * (pred_s_max + 1)) {
985 dev_err(&pdev->dev, "rtc_ck rate is too high: %dHz\n", rate);
986 return -EINVAL;
987 }
988
989 if (rtc->data->need_accuracy) {
990 for (pred_a = 0; pred_a <= pred_a_max; pred_a++) {
991 pred_s = (rate / (pred_a + 1)) - 1;
992
993 if (pred_s <= pred_s_max && ((pred_s + 1) * (pred_a + 1)) == rate)
994 break;
995 }
996 } else {
997 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
998 pred_s = (rate / (pred_a + 1)) - 1;
999
1000 if (((pred_s + 1) * (pred_a + 1)) == rate)
1001 break;
1002 }
1003 }
1004
1005 /*
1006 * Can't find a 1Hz, so give priority to RTC power consumption
1007 * by choosing the higher possible value for prediv_a
1008 */
1009 if (pred_s > pred_s_max || pred_a > pred_a_max) {
1010 pred_a = pred_a_max;
1011 pred_s = (rate / (pred_a + 1)) - 1;
1012
1013 dev_warn(&pdev->dev, "rtc_ck is %s\n",
1014 (rate < ((pred_a + 1) * (pred_s + 1))) ?
1015 "fast" : "slow");
1016 }
1017
1018 cr = readl_relaxed(rtc->base + regs->cr);
1019
1020 prer = readl_relaxed(rtc->base + regs->prer);
1021 prer &= STM32_RTC_PRER_PRED_S | STM32_RTC_PRER_PRED_A;
1022
1023 pred_s = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) &
1024 STM32_RTC_PRER_PRED_S;
1025 pred_a = (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) &
1026 STM32_RTC_PRER_PRED_A;
1027
1028 /* quit if there is nothing to initialize */
1029 if ((cr & STM32_RTC_CR_FMT) == 0 && prer == (pred_s | pred_a))
1030 return 0;
1031
1032 stm32_rtc_wpr_unlock(rtc);
1033
1034 ret = stm32_rtc_enter_init_mode(rtc);
1035 if (ret) {
1036 dev_err(&pdev->dev,
1037 "Can't enter in init mode. Prescaler config failed.\n");
1038 goto end;
1039 }
1040
1041 writel_relaxed(pred_s, rtc->base + regs->prer);
1042 writel_relaxed(pred_a | pred_s, rtc->base + regs->prer);
1043
1044 /* Force 24h time format */
1045 cr &= ~STM32_RTC_CR_FMT;
1046 writel_relaxed(cr, rtc->base + regs->cr);
1047
1048 stm32_rtc_exit_init_mode(rtc);
1049
1050 ret = stm32_rtc_wait_sync(rtc);
1051end:
1052 stm32_rtc_wpr_lock(rtc);
1053
1054 return ret;
1055}
1056
1057static int stm32_rtc_probe(struct platform_device *pdev)
1058{
1059 struct stm32_rtc *rtc;
1060 const struct stm32_rtc_registers *regs;
1061 struct pinctrl_dev *pctl;
1062 int ret;
1063
1064 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1065 if (!rtc)
1066 return -ENOMEM;
1067
1068 rtc->base = devm_platform_ioremap_resource(pdev, 0);
1069 if (IS_ERR(rtc->base))
1070 return PTR_ERR(rtc->base);
1071
1072 rtc->data = (struct stm32_rtc_data *)
1073 of_device_get_match_data(&pdev->dev);
1074 regs = &rtc->data->regs;
1075
1076 if (rtc->data->need_dbp) {
1077 rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1078 "st,syscfg");
1079 if (IS_ERR(rtc->dbp)) {
1080 dev_err(&pdev->dev, "no st,syscfg\n");
1081 return PTR_ERR(rtc->dbp);
1082 }
1083
1084 ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
1085 1, &rtc->dbp_reg);
1086 if (ret) {
1087 dev_err(&pdev->dev, "can't read DBP register offset\n");
1088 return ret;
1089 }
1090
1091 ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
1092 2, &rtc->dbp_mask);
1093 if (ret) {
1094 dev_err(&pdev->dev, "can't read DBP register mask\n");
1095 return ret;
1096 }
1097 }
1098
1099 if (!rtc->data->has_pclk) {
1100 rtc->pclk = NULL;
1101 rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
1102 } else {
1103 rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
1104 if (IS_ERR(rtc->pclk))
1105 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->pclk), "no pclk clock");
1106
1107 rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
1108 }
1109 if (IS_ERR(rtc->rtc_ck))
1110 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtc_ck), "no rtc_ck clock");
1111
1112 if (rtc->data->has_pclk) {
1113 ret = clk_prepare_enable(rtc->pclk);
1114 if (ret)
1115 return ret;
1116 }
1117
1118 ret = clk_prepare_enable(rtc->rtc_ck);
1119 if (ret)
1120 goto err_no_rtc_ck;
1121
1122 if (rtc->data->need_dbp)
1123 regmap_update_bits(rtc->dbp, rtc->dbp_reg,
1124 rtc->dbp_mask, rtc->dbp_mask);
1125
1126 if (rtc->data->rif_protected) {
1127 ret = stm32_rtc_check_rif(rtc, STM32_RTC_RES_INIT);
1128 if (!ret)
1129 ret = stm32_rtc_check_rif(rtc, STM32_RTC_RES_ALRA);
1130 if (ret) {
1131 dev_err(&pdev->dev, "Failed to probe RTC due to RIF configuration\n");
1132 goto err;
1133 }
1134 }
1135
1136 /*
1137 * After a system reset, RTC_ISR.INITS flag can be read to check if
1138 * the calendar has been initialized or not. INITS flag is reset by a
1139 * power-on reset (no vbat, no power-supply). It is not reset if
1140 * rtc_ck parent clock has changed (so RTC prescalers need to be
1141 * changed). That's why we cannot rely on this flag to know if RTC
1142 * init has to be done.
1143 */
1144 ret = stm32_rtc_init(pdev, rtc);
1145 if (ret)
1146 goto err;
1147
1148 rtc->irq_alarm = platform_get_irq(pdev, 0);
1149 if (rtc->irq_alarm <= 0) {
1150 ret = rtc->irq_alarm;
1151 goto err;
1152 }
1153
1154 ret = device_init_wakeup(&pdev->dev, true);
1155 if (ret)
1156 goto err;
1157
1158 ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq_alarm);
1159 if (ret)
1160 goto err;
1161
1162 platform_set_drvdata(pdev, rtc);
1163
1164 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
1165 &stm32_rtc_ops, THIS_MODULE);
1166 if (IS_ERR(rtc->rtc_dev)) {
1167 ret = PTR_ERR(rtc->rtc_dev);
1168 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
1169 ret);
1170 goto err;
1171 }
1172
1173 /* Handle RTC alarm interrupts */
1174 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
1175 stm32_rtc_alarm_irq, IRQF_ONESHOT,
1176 pdev->name, rtc);
1177 if (ret) {
1178 dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
1179 rtc->irq_alarm);
1180 goto err;
1181 }
1182
1183 stm32_rtc_clean_outs(rtc);
1184
1185 ret = devm_pinctrl_register_and_init(&pdev->dev, &stm32_rtc_pdesc, rtc, &pctl);
1186 if (ret)
1187 return dev_err_probe(&pdev->dev, ret, "pinctrl register failed");
1188
1189 ret = pinctrl_enable(pctl);
1190 if (ret)
1191 return dev_err_probe(&pdev->dev, ret, "pinctrl enable failed");
1192
1193 /*
1194 * If INITS flag is reset (calendar year field set to 0x00), calendar
1195 * must be initialized
1196 */
1197 if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
1198 dev_warn(&pdev->dev, "Date/Time must be initialized\n");
1199
1200 if (regs->verr != UNDEF_REG) {
1201 u32 ver = readl_relaxed(rtc->base + regs->verr);
1202
1203 dev_info(&pdev->dev, "registered rev:%d.%d\n",
1204 (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
1205 (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
1206 }
1207
1208 return 0;
1209
1210err:
1211 clk_disable_unprepare(rtc->rtc_ck);
1212err_no_rtc_ck:
1213 if (rtc->data->has_pclk)
1214 clk_disable_unprepare(rtc->pclk);
1215
1216 if (rtc->data->need_dbp)
1217 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
1218
1219 dev_pm_clear_wake_irq(&pdev->dev);
1220 device_init_wakeup(&pdev->dev, false);
1221
1222 return ret;
1223}
1224
1225static void stm32_rtc_remove(struct platform_device *pdev)
1226{
1227 struct stm32_rtc *rtc = platform_get_drvdata(pdev);
1228 const struct stm32_rtc_registers *regs = &rtc->data->regs;
1229 unsigned int cr;
1230
1231 if (!IS_ERR_OR_NULL(rtc->clk_lsco))
1232 clk_unregister_gate(rtc->clk_lsco);
1233
1234 /* Disable interrupts */
1235 stm32_rtc_wpr_unlock(rtc);
1236 cr = readl_relaxed(rtc->base + regs->cr);
1237 cr &= ~STM32_RTC_CR_ALRAIE;
1238 writel_relaxed(cr, rtc->base + regs->cr);
1239 stm32_rtc_wpr_lock(rtc);
1240
1241 clk_disable_unprepare(rtc->rtc_ck);
1242 if (rtc->data->has_pclk)
1243 clk_disable_unprepare(rtc->pclk);
1244
1245 /* Enable backup domain write protection if needed */
1246 if (rtc->data->need_dbp)
1247 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
1248
1249 dev_pm_clear_wake_irq(&pdev->dev);
1250 device_init_wakeup(&pdev->dev, false);
1251}
1252
1253static int stm32_rtc_suspend(struct device *dev)
1254{
1255 struct stm32_rtc *rtc = dev_get_drvdata(dev);
1256
1257 if (rtc->data->has_pclk)
1258 clk_disable_unprepare(rtc->pclk);
1259
1260 return 0;
1261}
1262
1263static int stm32_rtc_resume(struct device *dev)
1264{
1265 struct stm32_rtc *rtc = dev_get_drvdata(dev);
1266 int ret = 0;
1267
1268 if (rtc->data->has_pclk) {
1269 ret = clk_prepare_enable(rtc->pclk);
1270 if (ret)
1271 return ret;
1272 }
1273
1274 ret = stm32_rtc_wait_sync(rtc);
1275 if (ret < 0) {
1276 if (rtc->data->has_pclk)
1277 clk_disable_unprepare(rtc->pclk);
1278 return ret;
1279 }
1280
1281 return ret;
1282}
1283
1284static const struct dev_pm_ops stm32_rtc_pm_ops = {
1285 NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_rtc_suspend, stm32_rtc_resume)
1286};
1287
1288static struct platform_driver stm32_rtc_driver = {
1289 .probe = stm32_rtc_probe,
1290 .remove = stm32_rtc_remove,
1291 .driver = {
1292 .name = DRIVER_NAME,
1293 .pm = &stm32_rtc_pm_ops,
1294 .of_match_table = stm32_rtc_of_match,
1295 },
1296};
1297
1298module_platform_driver(stm32_rtc_driver);
1299
1300MODULE_ALIAS("platform:" DRIVER_NAME);
1301MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
1302MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
1303MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2017
4 * Author: Amelie Delaunay <amelie.delaunay@st.com>
5 */
6
7#include <linux/bcd.h>
8#include <linux/clk.h>
9#include <linux/errno.h>
10#include <linux/iopoll.h>
11#include <linux/ioport.h>
12#include <linux/mfd/syscon.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_wakeirq.h>
17#include <linux/regmap.h>
18#include <linux/rtc.h>
19
20#define DRIVER_NAME "stm32_rtc"
21
22/* STM32_RTC_TR bit fields */
23#define STM32_RTC_TR_SEC_SHIFT 0
24#define STM32_RTC_TR_SEC GENMASK(6, 0)
25#define STM32_RTC_TR_MIN_SHIFT 8
26#define STM32_RTC_TR_MIN GENMASK(14, 8)
27#define STM32_RTC_TR_HOUR_SHIFT 16
28#define STM32_RTC_TR_HOUR GENMASK(21, 16)
29
30/* STM32_RTC_DR bit fields */
31#define STM32_RTC_DR_DATE_SHIFT 0
32#define STM32_RTC_DR_DATE GENMASK(5, 0)
33#define STM32_RTC_DR_MONTH_SHIFT 8
34#define STM32_RTC_DR_MONTH GENMASK(12, 8)
35#define STM32_RTC_DR_WDAY_SHIFT 13
36#define STM32_RTC_DR_WDAY GENMASK(15, 13)
37#define STM32_RTC_DR_YEAR_SHIFT 16
38#define STM32_RTC_DR_YEAR GENMASK(23, 16)
39
40/* STM32_RTC_CR bit fields */
41#define STM32_RTC_CR_FMT BIT(6)
42#define STM32_RTC_CR_ALRAE BIT(8)
43#define STM32_RTC_CR_ALRAIE BIT(12)
44
45/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
46#define STM32_RTC_ISR_ALRAWF BIT(0)
47#define STM32_RTC_ISR_INITS BIT(4)
48#define STM32_RTC_ISR_RSF BIT(5)
49#define STM32_RTC_ISR_INITF BIT(6)
50#define STM32_RTC_ISR_INIT BIT(7)
51#define STM32_RTC_ISR_ALRAF BIT(8)
52
53/* STM32_RTC_PRER bit fields */
54#define STM32_RTC_PRER_PRED_S_SHIFT 0
55#define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
56#define STM32_RTC_PRER_PRED_A_SHIFT 16
57#define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
58
59/* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
60#define STM32_RTC_ALRMXR_SEC_SHIFT 0
61#define STM32_RTC_ALRMXR_SEC GENMASK(6, 0)
62#define STM32_RTC_ALRMXR_SEC_MASK BIT(7)
63#define STM32_RTC_ALRMXR_MIN_SHIFT 8
64#define STM32_RTC_ALRMXR_MIN GENMASK(14, 8)
65#define STM32_RTC_ALRMXR_MIN_MASK BIT(15)
66#define STM32_RTC_ALRMXR_HOUR_SHIFT 16
67#define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16)
68#define STM32_RTC_ALRMXR_PM BIT(22)
69#define STM32_RTC_ALRMXR_HOUR_MASK BIT(23)
70#define STM32_RTC_ALRMXR_DATE_SHIFT 24
71#define STM32_RTC_ALRMXR_DATE GENMASK(29, 24)
72#define STM32_RTC_ALRMXR_WDSEL BIT(30)
73#define STM32_RTC_ALRMXR_WDAY_SHIFT 24
74#define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
75#define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
76
77/* STM32_RTC_SR/_SCR bit fields */
78#define STM32_RTC_SR_ALRA BIT(0)
79
80/* STM32_RTC_VERR bit fields */
81#define STM32_RTC_VERR_MINREV_SHIFT 0
82#define STM32_RTC_VERR_MINREV GENMASK(3, 0)
83#define STM32_RTC_VERR_MAJREV_SHIFT 4
84#define STM32_RTC_VERR_MAJREV GENMASK(7, 4)
85
86/* STM32_RTC_WPR key constants */
87#define RTC_WPR_1ST_KEY 0xCA
88#define RTC_WPR_2ND_KEY 0x53
89#define RTC_WPR_WRONG_KEY 0xFF
90
91/* Max STM32 RTC register offset is 0x3FC */
92#define UNDEF_REG 0xFFFF
93
94/* STM32 RTC driver time helpers */
95#define SEC_PER_DAY (24 * 60 * 60)
96
97struct stm32_rtc;
98
99struct stm32_rtc_registers {
100 u16 tr;
101 u16 dr;
102 u16 cr;
103 u16 isr;
104 u16 prer;
105 u16 alrmar;
106 u16 wpr;
107 u16 sr;
108 u16 scr;
109 u16 verr;
110};
111
112struct stm32_rtc_events {
113 u32 alra;
114};
115
116struct stm32_rtc_data {
117 const struct stm32_rtc_registers regs;
118 const struct stm32_rtc_events events;
119 void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
120 bool has_pclk;
121 bool need_dbp;
122 bool need_accuracy;
123};
124
125struct stm32_rtc {
126 struct rtc_device *rtc_dev;
127 void __iomem *base;
128 struct regmap *dbp;
129 unsigned int dbp_reg;
130 unsigned int dbp_mask;
131 struct clk *pclk;
132 struct clk *rtc_ck;
133 const struct stm32_rtc_data *data;
134 int irq_alarm;
135};
136
137static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
138{
139 const struct stm32_rtc_registers *regs = &rtc->data->regs;
140
141 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
142 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
143}
144
145static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
146{
147 const struct stm32_rtc_registers *regs = &rtc->data->regs;
148
149 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
150}
151
152static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
153{
154 const struct stm32_rtc_registers *regs = &rtc->data->regs;
155 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
156
157 if (!(isr & STM32_RTC_ISR_INITF)) {
158 isr |= STM32_RTC_ISR_INIT;
159 writel_relaxed(isr, rtc->base + regs->isr);
160
161 /*
162 * It takes around 2 rtc_ck clock cycles to enter in
163 * initialization phase mode (and have INITF flag set). As
164 * slowest rtc_ck frequency may be 32kHz and highest should be
165 * 1MHz, we poll every 10 us with a timeout of 100ms.
166 */
167 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr,
168 (isr & STM32_RTC_ISR_INITF),
169 10, 100000);
170 }
171
172 return 0;
173}
174
175static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
176{
177 const struct stm32_rtc_registers *regs = &rtc->data->regs;
178 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
179
180 isr &= ~STM32_RTC_ISR_INIT;
181 writel_relaxed(isr, rtc->base + regs->isr);
182}
183
184static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
185{
186 const struct stm32_rtc_registers *regs = &rtc->data->regs;
187 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
188
189 isr &= ~STM32_RTC_ISR_RSF;
190 writel_relaxed(isr, rtc->base + regs->isr);
191
192 /*
193 * Wait for RSF to be set to ensure the calendar registers are
194 * synchronised, it takes around 2 rtc_ck clock cycles
195 */
196 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
197 isr,
198 (isr & STM32_RTC_ISR_RSF),
199 10, 100000);
200}
201
202static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
203 unsigned int flags)
204{
205 rtc->data->clear_events(rtc, flags);
206}
207
208static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
209{
210 struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
211 const struct stm32_rtc_registers *regs = &rtc->data->regs;
212 const struct stm32_rtc_events *evts = &rtc->data->events;
213 unsigned int status, cr;
214
215 rtc_lock(rtc->rtc_dev);
216
217 status = readl_relaxed(rtc->base + regs->sr);
218 cr = readl_relaxed(rtc->base + regs->cr);
219
220 if ((status & evts->alra) &&
221 (cr & STM32_RTC_CR_ALRAIE)) {
222 /* Alarm A flag - Alarm interrupt */
223 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
224
225 /* Pass event to the kernel */
226 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
227
228 /* Clear event flags, otherwise new events won't be received */
229 stm32_rtc_clear_event_flags(rtc, evts->alra);
230 }
231
232 rtc_unlock(rtc->rtc_dev);
233
234 return IRQ_HANDLED;
235}
236
237/* Convert rtc_time structure from bin to bcd format */
238static void tm2bcd(struct rtc_time *tm)
239{
240 tm->tm_sec = bin2bcd(tm->tm_sec);
241 tm->tm_min = bin2bcd(tm->tm_min);
242 tm->tm_hour = bin2bcd(tm->tm_hour);
243
244 tm->tm_mday = bin2bcd(tm->tm_mday);
245 tm->tm_mon = bin2bcd(tm->tm_mon + 1);
246 tm->tm_year = bin2bcd(tm->tm_year - 100);
247 /*
248 * Number of days since Sunday
249 * - on kernel side, 0=Sunday...6=Saturday
250 * - on rtc side, 0=invalid,1=Monday...7=Sunday
251 */
252 tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
253}
254
255/* Convert rtc_time structure from bcd to bin format */
256static void bcd2tm(struct rtc_time *tm)
257{
258 tm->tm_sec = bcd2bin(tm->tm_sec);
259 tm->tm_min = bcd2bin(tm->tm_min);
260 tm->tm_hour = bcd2bin(tm->tm_hour);
261
262 tm->tm_mday = bcd2bin(tm->tm_mday);
263 tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
264 tm->tm_year = bcd2bin(tm->tm_year) + 100;
265 /*
266 * Number of days since Sunday
267 * - on kernel side, 0=Sunday...6=Saturday
268 * - on rtc side, 0=invalid,1=Monday...7=Sunday
269 */
270 tm->tm_wday %= 7;
271}
272
273static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
274{
275 struct stm32_rtc *rtc = dev_get_drvdata(dev);
276 const struct stm32_rtc_registers *regs = &rtc->data->regs;
277 unsigned int tr, dr;
278
279 /* Time and Date in BCD format */
280 tr = readl_relaxed(rtc->base + regs->tr);
281 dr = readl_relaxed(rtc->base + regs->dr);
282
283 tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
284 tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
285 tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
286
287 tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
288 tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
289 tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
290 tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
291
292 /* We don't report tm_yday and tm_isdst */
293
294 bcd2tm(tm);
295
296 return 0;
297}
298
299static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
300{
301 struct stm32_rtc *rtc = dev_get_drvdata(dev);
302 const struct stm32_rtc_registers *regs = &rtc->data->regs;
303 unsigned int tr, dr;
304 int ret = 0;
305
306 tm2bcd(tm);
307
308 /* Time in BCD format */
309 tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
310 ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
311 ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
312
313 /* Date in BCD format */
314 dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
315 ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
316 ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
317 ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
318
319 stm32_rtc_wpr_unlock(rtc);
320
321 ret = stm32_rtc_enter_init_mode(rtc);
322 if (ret) {
323 dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
324 goto end;
325 }
326
327 writel_relaxed(tr, rtc->base + regs->tr);
328 writel_relaxed(dr, rtc->base + regs->dr);
329
330 stm32_rtc_exit_init_mode(rtc);
331
332 ret = stm32_rtc_wait_sync(rtc);
333end:
334 stm32_rtc_wpr_lock(rtc);
335
336 return ret;
337}
338
339static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
340{
341 struct stm32_rtc *rtc = dev_get_drvdata(dev);
342 const struct stm32_rtc_registers *regs = &rtc->data->regs;
343 const struct stm32_rtc_events *evts = &rtc->data->events;
344 struct rtc_time *tm = &alrm->time;
345 unsigned int alrmar, cr, status;
346
347 alrmar = readl_relaxed(rtc->base + regs->alrmar);
348 cr = readl_relaxed(rtc->base + regs->cr);
349 status = readl_relaxed(rtc->base + regs->sr);
350
351 if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
352 /*
353 * Date/day doesn't matter in Alarm comparison so alarm
354 * triggers every day
355 */
356 tm->tm_mday = -1;
357 tm->tm_wday = -1;
358 } else {
359 if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
360 /* Alarm is set to a day of week */
361 tm->tm_mday = -1;
362 tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
363 STM32_RTC_ALRMXR_WDAY_SHIFT;
364 tm->tm_wday %= 7;
365 } else {
366 /* Alarm is set to a day of month */
367 tm->tm_wday = -1;
368 tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
369 STM32_RTC_ALRMXR_DATE_SHIFT;
370 }
371 }
372
373 if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
374 /* Hours don't matter in Alarm comparison */
375 tm->tm_hour = -1;
376 } else {
377 tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
378 STM32_RTC_ALRMXR_HOUR_SHIFT;
379 if (alrmar & STM32_RTC_ALRMXR_PM)
380 tm->tm_hour += 12;
381 }
382
383 if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
384 /* Minutes don't matter in Alarm comparison */
385 tm->tm_min = -1;
386 } else {
387 tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
388 STM32_RTC_ALRMXR_MIN_SHIFT;
389 }
390
391 if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
392 /* Seconds don't matter in Alarm comparison */
393 tm->tm_sec = -1;
394 } else {
395 tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
396 STM32_RTC_ALRMXR_SEC_SHIFT;
397 }
398
399 bcd2tm(tm);
400
401 alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
402 alrm->pending = (status & evts->alra) ? 1 : 0;
403
404 return 0;
405}
406
407static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
408{
409 struct stm32_rtc *rtc = dev_get_drvdata(dev);
410 const struct stm32_rtc_registers *regs = &rtc->data->regs;
411 const struct stm32_rtc_events *evts = &rtc->data->events;
412 unsigned int cr;
413
414 cr = readl_relaxed(rtc->base + regs->cr);
415
416 stm32_rtc_wpr_unlock(rtc);
417
418 /* We expose Alarm A to the kernel */
419 if (enabled)
420 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
421 else
422 cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
423 writel_relaxed(cr, rtc->base + regs->cr);
424
425 /* Clear event flags, otherwise new events won't be received */
426 stm32_rtc_clear_event_flags(rtc, evts->alra);
427
428 stm32_rtc_wpr_lock(rtc);
429
430 return 0;
431}
432
433static int stm32_rtc_valid_alrm(struct device *dev, struct rtc_time *tm)
434{
435 static struct rtc_time now;
436 time64_t max_alarm_time64;
437 int max_day_forward;
438 int next_month;
439 int next_year;
440
441 /*
442 * Assuming current date is M-D-Y H:M:S.
443 * RTC alarm can't be set on a specific month and year.
444 * So the valid alarm range is:
445 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
446 */
447 stm32_rtc_read_time(dev, &now);
448
449 /*
450 * Find the next month and the year of the next month.
451 * Note: tm_mon and next_month are from 0 to 11
452 */
453 next_month = now.tm_mon + 1;
454 if (next_month == 12) {
455 next_month = 0;
456 next_year = now.tm_year + 1;
457 } else {
458 next_year = now.tm_year;
459 }
460
461 /* Find the maximum limit of alarm in days. */
462 max_day_forward = rtc_month_days(now.tm_mon, now.tm_year)
463 - now.tm_mday
464 + min(rtc_month_days(next_month, next_year), now.tm_mday);
465
466 /* Convert to timestamp and compare the alarm time and its upper limit */
467 max_alarm_time64 = rtc_tm_to_time64(&now) + max_day_forward * SEC_PER_DAY;
468 return rtc_tm_to_time64(tm) <= max_alarm_time64 ? 0 : -EINVAL;
469}
470
471static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
472{
473 struct stm32_rtc *rtc = dev_get_drvdata(dev);
474 const struct stm32_rtc_registers *regs = &rtc->data->regs;
475 struct rtc_time *tm = &alrm->time;
476 unsigned int cr, isr, alrmar;
477 int ret = 0;
478
479 /*
480 * RTC alarm can't be set on a specific date, unless this date is
481 * up to the same day of month next month.
482 */
483 if (stm32_rtc_valid_alrm(dev, tm) < 0) {
484 dev_err(dev, "Alarm can be set only on upcoming month.\n");
485 return -EINVAL;
486 }
487
488 tm2bcd(tm);
489
490 alrmar = 0;
491 /* tm_year and tm_mon are not used because not supported by RTC */
492 alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
493 STM32_RTC_ALRMXR_DATE;
494 /* 24-hour format */
495 alrmar &= ~STM32_RTC_ALRMXR_PM;
496 alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
497 STM32_RTC_ALRMXR_HOUR;
498 alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
499 STM32_RTC_ALRMXR_MIN;
500 alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
501 STM32_RTC_ALRMXR_SEC;
502
503 stm32_rtc_wpr_unlock(rtc);
504
505 /* Disable Alarm */
506 cr = readl_relaxed(rtc->base + regs->cr);
507 cr &= ~STM32_RTC_CR_ALRAE;
508 writel_relaxed(cr, rtc->base + regs->cr);
509
510 /*
511 * Poll Alarm write flag to be sure that Alarm update is allowed: it
512 * takes around 2 rtc_ck clock cycles
513 */
514 ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
515 isr,
516 (isr & STM32_RTC_ISR_ALRAWF),
517 10, 100000);
518
519 if (ret) {
520 dev_err(dev, "Alarm update not allowed\n");
521 goto end;
522 }
523
524 /* Write to Alarm register */
525 writel_relaxed(alrmar, rtc->base + regs->alrmar);
526
527 stm32_rtc_alarm_irq_enable(dev, alrm->enabled);
528end:
529 stm32_rtc_wpr_lock(rtc);
530
531 return ret;
532}
533
534static const struct rtc_class_ops stm32_rtc_ops = {
535 .read_time = stm32_rtc_read_time,
536 .set_time = stm32_rtc_set_time,
537 .read_alarm = stm32_rtc_read_alarm,
538 .set_alarm = stm32_rtc_set_alarm,
539 .alarm_irq_enable = stm32_rtc_alarm_irq_enable,
540};
541
542static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
543 unsigned int flags)
544{
545 const struct stm32_rtc_registers *regs = &rtc->data->regs;
546
547 /* Flags are cleared by writing 0 in RTC_ISR */
548 writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
549 rtc->base + regs->isr);
550}
551
552static const struct stm32_rtc_data stm32_rtc_data = {
553 .has_pclk = false,
554 .need_dbp = true,
555 .need_accuracy = false,
556 .regs = {
557 .tr = 0x00,
558 .dr = 0x04,
559 .cr = 0x08,
560 .isr = 0x0C,
561 .prer = 0x10,
562 .alrmar = 0x1C,
563 .wpr = 0x24,
564 .sr = 0x0C, /* set to ISR offset to ease alarm management */
565 .scr = UNDEF_REG,
566 .verr = UNDEF_REG,
567 },
568 .events = {
569 .alra = STM32_RTC_ISR_ALRAF,
570 },
571 .clear_events = stm32_rtc_clear_events,
572};
573
574static const struct stm32_rtc_data stm32h7_rtc_data = {
575 .has_pclk = true,
576 .need_dbp = true,
577 .need_accuracy = false,
578 .regs = {
579 .tr = 0x00,
580 .dr = 0x04,
581 .cr = 0x08,
582 .isr = 0x0C,
583 .prer = 0x10,
584 .alrmar = 0x1C,
585 .wpr = 0x24,
586 .sr = 0x0C, /* set to ISR offset to ease alarm management */
587 .scr = UNDEF_REG,
588 .verr = UNDEF_REG,
589 },
590 .events = {
591 .alra = STM32_RTC_ISR_ALRAF,
592 },
593 .clear_events = stm32_rtc_clear_events,
594};
595
596static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
597 unsigned int flags)
598{
599 struct stm32_rtc_registers regs = rtc->data->regs;
600
601 /* Flags are cleared by writing 1 in RTC_SCR */
602 writel_relaxed(flags, rtc->base + regs.scr);
603}
604
605static const struct stm32_rtc_data stm32mp1_data = {
606 .has_pclk = true,
607 .need_dbp = false,
608 .need_accuracy = true,
609 .regs = {
610 .tr = 0x00,
611 .dr = 0x04,
612 .cr = 0x18,
613 .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
614 .prer = 0x10,
615 .alrmar = 0x40,
616 .wpr = 0x24,
617 .sr = 0x50,
618 .scr = 0x5C,
619 .verr = 0x3F4,
620 },
621 .events = {
622 .alra = STM32_RTC_SR_ALRA,
623 },
624 .clear_events = stm32mp1_rtc_clear_events,
625};
626
627static const struct of_device_id stm32_rtc_of_match[] = {
628 { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
629 { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
630 { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
631 {}
632};
633MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
634
635static int stm32_rtc_init(struct platform_device *pdev,
636 struct stm32_rtc *rtc)
637{
638 const struct stm32_rtc_registers *regs = &rtc->data->regs;
639 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
640 unsigned int rate;
641 int ret;
642
643 rate = clk_get_rate(rtc->rtc_ck);
644
645 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
646 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
647 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
648
649 if (rate > (pred_a_max + 1) * (pred_s_max + 1)) {
650 dev_err(&pdev->dev, "rtc_ck rate is too high: %dHz\n", rate);
651 return -EINVAL;
652 }
653
654 if (rtc->data->need_accuracy) {
655 for (pred_a = 0; pred_a <= pred_a_max; pred_a++) {
656 pred_s = (rate / (pred_a + 1)) - 1;
657
658 if (pred_s <= pred_s_max && ((pred_s + 1) * (pred_a + 1)) == rate)
659 break;
660 }
661 } else {
662 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
663 pred_s = (rate / (pred_a + 1)) - 1;
664
665 if (((pred_s + 1) * (pred_a + 1)) == rate)
666 break;
667 }
668 }
669
670 /*
671 * Can't find a 1Hz, so give priority to RTC power consumption
672 * by choosing the higher possible value for prediv_a
673 */
674 if (pred_s > pred_s_max || pred_a > pred_a_max) {
675 pred_a = pred_a_max;
676 pred_s = (rate / (pred_a + 1)) - 1;
677
678 dev_warn(&pdev->dev, "rtc_ck is %s\n",
679 (rate < ((pred_a + 1) * (pred_s + 1))) ?
680 "fast" : "slow");
681 }
682
683 cr = readl_relaxed(rtc->base + regs->cr);
684
685 prer = readl_relaxed(rtc->base + regs->prer);
686 prer &= STM32_RTC_PRER_PRED_S | STM32_RTC_PRER_PRED_A;
687
688 pred_s = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) &
689 STM32_RTC_PRER_PRED_S;
690 pred_a = (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) &
691 STM32_RTC_PRER_PRED_A;
692
693 /* quit if there is nothing to initialize */
694 if ((cr & STM32_RTC_CR_FMT) == 0 && prer == (pred_s | pred_a))
695 return 0;
696
697 stm32_rtc_wpr_unlock(rtc);
698
699 ret = stm32_rtc_enter_init_mode(rtc);
700 if (ret) {
701 dev_err(&pdev->dev,
702 "Can't enter in init mode. Prescaler config failed.\n");
703 goto end;
704 }
705
706 writel_relaxed(pred_s, rtc->base + regs->prer);
707 writel_relaxed(pred_a | pred_s, rtc->base + regs->prer);
708
709 /* Force 24h time format */
710 cr &= ~STM32_RTC_CR_FMT;
711 writel_relaxed(cr, rtc->base + regs->cr);
712
713 stm32_rtc_exit_init_mode(rtc);
714
715 ret = stm32_rtc_wait_sync(rtc);
716end:
717 stm32_rtc_wpr_lock(rtc);
718
719 return ret;
720}
721
722static int stm32_rtc_probe(struct platform_device *pdev)
723{
724 struct stm32_rtc *rtc;
725 const struct stm32_rtc_registers *regs;
726 int ret;
727
728 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
729 if (!rtc)
730 return -ENOMEM;
731
732 rtc->base = devm_platform_ioremap_resource(pdev, 0);
733 if (IS_ERR(rtc->base))
734 return PTR_ERR(rtc->base);
735
736 rtc->data = (struct stm32_rtc_data *)
737 of_device_get_match_data(&pdev->dev);
738 regs = &rtc->data->regs;
739
740 if (rtc->data->need_dbp) {
741 rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
742 "st,syscfg");
743 if (IS_ERR(rtc->dbp)) {
744 dev_err(&pdev->dev, "no st,syscfg\n");
745 return PTR_ERR(rtc->dbp);
746 }
747
748 ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
749 1, &rtc->dbp_reg);
750 if (ret) {
751 dev_err(&pdev->dev, "can't read DBP register offset\n");
752 return ret;
753 }
754
755 ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
756 2, &rtc->dbp_mask);
757 if (ret) {
758 dev_err(&pdev->dev, "can't read DBP register mask\n");
759 return ret;
760 }
761 }
762
763 if (!rtc->data->has_pclk) {
764 rtc->pclk = NULL;
765 rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
766 } else {
767 rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
768 if (IS_ERR(rtc->pclk))
769 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->pclk), "no pclk clock");
770
771 rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
772 }
773 if (IS_ERR(rtc->rtc_ck))
774 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtc_ck), "no rtc_ck clock");
775
776 if (rtc->data->has_pclk) {
777 ret = clk_prepare_enable(rtc->pclk);
778 if (ret)
779 return ret;
780 }
781
782 ret = clk_prepare_enable(rtc->rtc_ck);
783 if (ret)
784 goto err_no_rtc_ck;
785
786 if (rtc->data->need_dbp)
787 regmap_update_bits(rtc->dbp, rtc->dbp_reg,
788 rtc->dbp_mask, rtc->dbp_mask);
789
790 /*
791 * After a system reset, RTC_ISR.INITS flag can be read to check if
792 * the calendar has been initialized or not. INITS flag is reset by a
793 * power-on reset (no vbat, no power-supply). It is not reset if
794 * rtc_ck parent clock has changed (so RTC prescalers need to be
795 * changed). That's why we cannot rely on this flag to know if RTC
796 * init has to be done.
797 */
798 ret = stm32_rtc_init(pdev, rtc);
799 if (ret)
800 goto err;
801
802 rtc->irq_alarm = platform_get_irq(pdev, 0);
803 if (rtc->irq_alarm <= 0) {
804 ret = rtc->irq_alarm;
805 goto err;
806 }
807
808 ret = device_init_wakeup(&pdev->dev, true);
809 if (ret)
810 goto err;
811
812 ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq_alarm);
813 if (ret)
814 goto err;
815
816 platform_set_drvdata(pdev, rtc);
817
818 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
819 &stm32_rtc_ops, THIS_MODULE);
820 if (IS_ERR(rtc->rtc_dev)) {
821 ret = PTR_ERR(rtc->rtc_dev);
822 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
823 ret);
824 goto err;
825 }
826
827 /* Handle RTC alarm interrupts */
828 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
829 stm32_rtc_alarm_irq, IRQF_ONESHOT,
830 pdev->name, rtc);
831 if (ret) {
832 dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
833 rtc->irq_alarm);
834 goto err;
835 }
836
837 /*
838 * If INITS flag is reset (calendar year field set to 0x00), calendar
839 * must be initialized
840 */
841 if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
842 dev_warn(&pdev->dev, "Date/Time must be initialized\n");
843
844 if (regs->verr != UNDEF_REG) {
845 u32 ver = readl_relaxed(rtc->base + regs->verr);
846
847 dev_info(&pdev->dev, "registered rev:%d.%d\n",
848 (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
849 (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
850 }
851
852 return 0;
853
854err:
855 clk_disable_unprepare(rtc->rtc_ck);
856err_no_rtc_ck:
857 if (rtc->data->has_pclk)
858 clk_disable_unprepare(rtc->pclk);
859
860 if (rtc->data->need_dbp)
861 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
862
863 dev_pm_clear_wake_irq(&pdev->dev);
864 device_init_wakeup(&pdev->dev, false);
865
866 return ret;
867}
868
869static void stm32_rtc_remove(struct platform_device *pdev)
870{
871 struct stm32_rtc *rtc = platform_get_drvdata(pdev);
872 const struct stm32_rtc_registers *regs = &rtc->data->regs;
873 unsigned int cr;
874
875 /* Disable interrupts */
876 stm32_rtc_wpr_unlock(rtc);
877 cr = readl_relaxed(rtc->base + regs->cr);
878 cr &= ~STM32_RTC_CR_ALRAIE;
879 writel_relaxed(cr, rtc->base + regs->cr);
880 stm32_rtc_wpr_lock(rtc);
881
882 clk_disable_unprepare(rtc->rtc_ck);
883 if (rtc->data->has_pclk)
884 clk_disable_unprepare(rtc->pclk);
885
886 /* Enable backup domain write protection if needed */
887 if (rtc->data->need_dbp)
888 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
889
890 dev_pm_clear_wake_irq(&pdev->dev);
891 device_init_wakeup(&pdev->dev, false);
892}
893
894static int stm32_rtc_suspend(struct device *dev)
895{
896 struct stm32_rtc *rtc = dev_get_drvdata(dev);
897
898 if (rtc->data->has_pclk)
899 clk_disable_unprepare(rtc->pclk);
900
901 return 0;
902}
903
904static int stm32_rtc_resume(struct device *dev)
905{
906 struct stm32_rtc *rtc = dev_get_drvdata(dev);
907 int ret = 0;
908
909 if (rtc->data->has_pclk) {
910 ret = clk_prepare_enable(rtc->pclk);
911 if (ret)
912 return ret;
913 }
914
915 ret = stm32_rtc_wait_sync(rtc);
916 if (ret < 0) {
917 if (rtc->data->has_pclk)
918 clk_disable_unprepare(rtc->pclk);
919 return ret;
920 }
921
922 return ret;
923}
924
925static const struct dev_pm_ops stm32_rtc_pm_ops = {
926 NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_rtc_suspend, stm32_rtc_resume)
927};
928
929static struct platform_driver stm32_rtc_driver = {
930 .probe = stm32_rtc_probe,
931 .remove_new = stm32_rtc_remove,
932 .driver = {
933 .name = DRIVER_NAME,
934 .pm = &stm32_rtc_pm_ops,
935 .of_match_table = stm32_rtc_of_match,
936 },
937};
938
939module_platform_driver(stm32_rtc_driver);
940
941MODULE_ALIAS("platform:" DRIVER_NAME);
942MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
943MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
944MODULE_LICENSE("GPL v2");