Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Allwinner sun4i Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 *
7 * Limitations:
8 * - When outputing the source clock directly, the PWM logic will be bypassed
9 * and the currently running period is not guaranteed to be completed
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/jiffies.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pwm.h>
22#include <linux/reset.h>
23#include <linux/slab.h>
24#include <linux/spinlock.h>
25#include <linux/time.h>
26
27#define PWM_CTRL_REG 0x0
28
29#define PWM_CH_PRD_BASE 0x4
30#define PWM_CH_PRD_OFFSET 0x4
31#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
32
33#define PWMCH_OFFSET 15
34#define PWM_PRESCAL_MASK GENMASK(3, 0)
35#define PWM_PRESCAL_OFF 0
36#define PWM_EN BIT(4)
37#define PWM_ACT_STATE BIT(5)
38#define PWM_CLK_GATING BIT(6)
39#define PWM_MODE BIT(7)
40#define PWM_PULSE BIT(8)
41#define PWM_BYPASS BIT(9)
42
43#define PWM_RDY_BASE 28
44#define PWM_RDY_OFFSET 1
45#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
46
47#define PWM_PRD(prd) (((prd) - 1) << 16)
48#define PWM_PRD_MASK GENMASK(15, 0)
49
50#define PWM_DTY_MASK GENMASK(15, 0)
51
52#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
53#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
54#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
55
56#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
57
58static const u32 prescaler_table[] = {
59 120,
60 180,
61 240,
62 360,
63 480,
64 0,
65 0,
66 0,
67 12000,
68 24000,
69 36000,
70 48000,
71 72000,
72 0,
73 0,
74 0, /* Actually 1 but tested separately */
75};
76
77struct sun4i_pwm_data {
78 bool has_prescaler_bypass;
79 bool has_direct_mod_clk_output;
80 unsigned int npwm;
81};
82
83struct sun4i_pwm_chip {
84 struct clk *bus_clk;
85 struct clk *clk;
86 struct reset_control *rst;
87 void __iomem *base;
88 spinlock_t ctrl_lock;
89 const struct sun4i_pwm_data *data;
90};
91
92static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
93{
94 return pwmchip_get_drvdata(chip);
95}
96
97static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *sun4ichip,
98 unsigned long offset)
99{
100 return readl(sun4ichip->base + offset);
101}
102
103static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *sun4ichip,
104 u32 val, unsigned long offset)
105{
106 writel(val, sun4ichip->base + offset);
107}
108
109static int sun4i_pwm_get_state(struct pwm_chip *chip,
110 struct pwm_device *pwm,
111 struct pwm_state *state)
112{
113 struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
114 u64 clk_rate, tmp;
115 u32 val;
116 unsigned int prescaler;
117
118 clk_rate = clk_get_rate(sun4ichip->clk);
119 if (!clk_rate)
120 return -EINVAL;
121
122 val = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
123
124 /*
125 * PWM chapter in H6 manual has a diagram which explains that if bypass
126 * bit is set, no other setting has any meaning. Even more, experiment
127 * proved that also enable bit is ignored in this case.
128 */
129 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
130 sun4ichip->data->has_direct_mod_clk_output) {
131 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
132 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
133 state->polarity = PWM_POLARITY_NORMAL;
134 state->enabled = true;
135 return 0;
136 }
137
138 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
139 sun4ichip->data->has_prescaler_bypass)
140 prescaler = 1;
141 else
142 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
143
144 if (prescaler == 0)
145 return -EINVAL;
146
147 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
148 state->polarity = PWM_POLARITY_NORMAL;
149 else
150 state->polarity = PWM_POLARITY_INVERSED;
151
152 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
153 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
154 state->enabled = true;
155 else
156 state->enabled = false;
157
158 val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm));
159
160 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
161 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
162
163 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
164 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
165
166 return 0;
167}
168
169static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4ichip,
170 const struct pwm_state *state,
171 u32 *dty, u32 *prd, unsigned int *prsclr,
172 bool *bypass)
173{
174 u64 clk_rate, div = 0;
175 unsigned int prescaler = 0;
176
177 clk_rate = clk_get_rate(sun4ichip->clk);
178
179 *bypass = sun4ichip->data->has_direct_mod_clk_output &&
180 state->enabled &&
181 (state->period * clk_rate >= NSEC_PER_SEC) &&
182 (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
183 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
184
185 /* Skip calculation of other parameters if we bypass them */
186 if (*bypass)
187 return 0;
188
189 if (sun4ichip->data->has_prescaler_bypass) {
190 /* First, test without any prescaler when available */
191 prescaler = PWM_PRESCAL_MASK;
192 /*
193 * When not using any prescaler, the clock period in nanoseconds
194 * is not an integer so round it half up instead of
195 * truncating to get less surprising values.
196 */
197 div = clk_rate * state->period + NSEC_PER_SEC / 2;
198 do_div(div, NSEC_PER_SEC);
199 if (div - 1 > PWM_PRD_MASK)
200 prescaler = 0;
201 }
202
203 if (prescaler == 0) {
204 /* Go up from the first divider */
205 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
206 unsigned int pval = prescaler_table[prescaler];
207
208 if (!pval)
209 continue;
210
211 div = clk_rate;
212 do_div(div, pval);
213 div = div * state->period;
214 do_div(div, NSEC_PER_SEC);
215 if (div - 1 <= PWM_PRD_MASK)
216 break;
217 }
218
219 if (div - 1 > PWM_PRD_MASK)
220 return -EINVAL;
221 }
222
223 *prd = div;
224 div *= state->duty_cycle;
225 do_div(div, state->period);
226 *dty = div;
227 *prsclr = prescaler;
228
229 return 0;
230}
231
232static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
233 const struct pwm_state *state)
234{
235 struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
236 struct pwm_state cstate;
237 u32 ctrl, duty = 0, period = 0, val;
238 int ret;
239 unsigned int delay_us, prescaler = 0;
240 bool bypass;
241
242 pwm_get_state(pwm, &cstate);
243
244 if (!cstate.enabled) {
245 ret = clk_prepare_enable(sun4ichip->clk);
246 if (ret) {
247 dev_err(pwmchip_parent(chip), "failed to enable PWM clock\n");
248 return ret;
249 }
250 }
251
252 ret = sun4i_pwm_calculate(sun4ichip, state, &duty, &period, &prescaler,
253 &bypass);
254 if (ret) {
255 dev_err(pwmchip_parent(chip), "period exceeds the maximum value\n");
256 if (!cstate.enabled)
257 clk_disable_unprepare(sun4ichip->clk);
258 return ret;
259 }
260
261 spin_lock(&sun4ichip->ctrl_lock);
262 ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
263
264 if (sun4ichip->data->has_direct_mod_clk_output) {
265 if (bypass) {
266 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
267 /* We can skip other parameter */
268 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
269 spin_unlock(&sun4ichip->ctrl_lock);
270 return 0;
271 }
272
273 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
274 }
275
276 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
277 /* Prescaler changed, the clock has to be gated */
278 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
279 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
280
281 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
282 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
283 }
284
285 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
286 sun4i_pwm_writel(sun4ichip, val, PWM_CH_PRD(pwm->hwpwm));
287
288 if (state->polarity != PWM_POLARITY_NORMAL)
289 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
290 else
291 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
292
293 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
294
295 if (state->enabled)
296 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
297
298 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
299
300 spin_unlock(&sun4ichip->ctrl_lock);
301
302 if (state->enabled)
303 return 0;
304
305 /* We need a full period to elapse before disabling the channel. */
306 delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
307 if ((delay_us / 500) > MAX_UDELAY_MS)
308 msleep(delay_us / 1000 + 1);
309 else
310 usleep_range(delay_us, delay_us * 2);
311
312 spin_lock(&sun4ichip->ctrl_lock);
313 ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
314 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
315 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
316 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
317 spin_unlock(&sun4ichip->ctrl_lock);
318
319 clk_disable_unprepare(sun4ichip->clk);
320
321 return 0;
322}
323
324static const struct pwm_ops sun4i_pwm_ops = {
325 .apply = sun4i_pwm_apply,
326 .get_state = sun4i_pwm_get_state,
327};
328
329static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
330 .has_prescaler_bypass = false,
331 .npwm = 2,
332};
333
334static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
335 .has_prescaler_bypass = true,
336 .npwm = 2,
337};
338
339static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
340 .has_prescaler_bypass = true,
341 .npwm = 1,
342};
343
344static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
345 .has_prescaler_bypass = true,
346 .has_direct_mod_clk_output = true,
347 .npwm = 1,
348};
349
350static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
351 .has_prescaler_bypass = true,
352 .has_direct_mod_clk_output = true,
353 .npwm = 2,
354};
355
356static const struct of_device_id sun4i_pwm_dt_ids[] = {
357 {
358 .compatible = "allwinner,sun4i-a10-pwm",
359 .data = &sun4i_pwm_dual_nobypass,
360 }, {
361 .compatible = "allwinner,sun5i-a10s-pwm",
362 .data = &sun4i_pwm_dual_bypass,
363 }, {
364 .compatible = "allwinner,sun5i-a13-pwm",
365 .data = &sun4i_pwm_single_bypass,
366 }, {
367 .compatible = "allwinner,sun7i-a20-pwm",
368 .data = &sun4i_pwm_dual_bypass,
369 }, {
370 .compatible = "allwinner,sun8i-h3-pwm",
371 .data = &sun4i_pwm_single_bypass,
372 }, {
373 .compatible = "allwinner,sun50i-a64-pwm",
374 .data = &sun50i_a64_pwm_data,
375 }, {
376 .compatible = "allwinner,sun50i-h6-pwm",
377 .data = &sun50i_h6_pwm_data,
378 }, {
379 /* sentinel */
380 },
381};
382MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
383
384static int sun4i_pwm_probe(struct platform_device *pdev)
385{
386 struct pwm_chip *chip;
387 const struct sun4i_pwm_data *data;
388 struct sun4i_pwm_chip *sun4ichip;
389 int ret;
390
391 data = of_device_get_match_data(&pdev->dev);
392 if (!data)
393 return -ENODEV;
394
395 chip = devm_pwmchip_alloc(&pdev->dev, data->npwm, sizeof(*sun4ichip));
396 if (IS_ERR(chip))
397 return PTR_ERR(chip);
398 sun4ichip = to_sun4i_pwm_chip(chip);
399
400 sun4ichip->data = data;
401 sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
402 if (IS_ERR(sun4ichip->base))
403 return PTR_ERR(sun4ichip->base);
404
405 /*
406 * All hardware variants need a source clock that is divided and
407 * then feeds the counter that defines the output wave form. In the
408 * device tree this clock is either unnamed or called "mod".
409 * Some variants (e.g. H6) need another clock to access the
410 * hardware registers; this is called "bus".
411 * So we request "mod" first (and ignore the corner case that a
412 * parent provides a "mod" clock while the right one would be the
413 * unnamed one of the PWM device) and if this is not found we fall
414 * back to the first clock of the PWM.
415 */
416 sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
417 if (IS_ERR(sun4ichip->clk))
418 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
419 "get mod clock failed\n");
420
421 if (!sun4ichip->clk) {
422 sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
423 if (IS_ERR(sun4ichip->clk))
424 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
425 "get unnamed clock failed\n");
426 }
427
428 sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
429 if (IS_ERR(sun4ichip->bus_clk))
430 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
431 "get bus clock failed\n");
432
433 sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
434 if (IS_ERR(sun4ichip->rst))
435 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
436 "get reset failed\n");
437
438 /* Deassert reset */
439 ret = reset_control_deassert(sun4ichip->rst);
440 if (ret) {
441 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
442 ERR_PTR(ret));
443 return ret;
444 }
445
446 /*
447 * We're keeping the bus clock on for the sake of simplicity.
448 * Actually it only needs to be on for hardware register accesses.
449 */
450 ret = clk_prepare_enable(sun4ichip->bus_clk);
451 if (ret) {
452 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
453 ERR_PTR(ret));
454 goto err_bus;
455 }
456
457 chip->ops = &sun4i_pwm_ops;
458
459 spin_lock_init(&sun4ichip->ctrl_lock);
460
461 ret = pwmchip_add(chip);
462 if (ret < 0) {
463 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
464 goto err_pwm_add;
465 }
466
467 platform_set_drvdata(pdev, chip);
468
469 return 0;
470
471err_pwm_add:
472 clk_disable_unprepare(sun4ichip->bus_clk);
473err_bus:
474 reset_control_assert(sun4ichip->rst);
475
476 return ret;
477}
478
479static void sun4i_pwm_remove(struct platform_device *pdev)
480{
481 struct pwm_chip *chip = platform_get_drvdata(pdev);
482 struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
483
484 pwmchip_remove(chip);
485
486 clk_disable_unprepare(sun4ichip->bus_clk);
487 reset_control_assert(sun4ichip->rst);
488}
489
490static struct platform_driver sun4i_pwm_driver = {
491 .driver = {
492 .name = "sun4i-pwm",
493 .of_match_table = sun4i_pwm_dt_ids,
494 },
495 .probe = sun4i_pwm_probe,
496 .remove = sun4i_pwm_remove,
497};
498module_platform_driver(sun4i_pwm_driver);
499
500MODULE_ALIAS("platform:sun4i-pwm");
501MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
502MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
503MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Allwinner sun4i Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 *
7 * Limitations:
8 * - When outputing the source clock directly, the PWM logic will be bypassed
9 * and the currently running period is not guaranteed to be completed
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/jiffies.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pwm.h>
22#include <linux/reset.h>
23#include <linux/slab.h>
24#include <linux/spinlock.h>
25#include <linux/time.h>
26
27#define PWM_CTRL_REG 0x0
28
29#define PWM_CH_PRD_BASE 0x4
30#define PWM_CH_PRD_OFFSET 0x4
31#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
32
33#define PWMCH_OFFSET 15
34#define PWM_PRESCAL_MASK GENMASK(3, 0)
35#define PWM_PRESCAL_OFF 0
36#define PWM_EN BIT(4)
37#define PWM_ACT_STATE BIT(5)
38#define PWM_CLK_GATING BIT(6)
39#define PWM_MODE BIT(7)
40#define PWM_PULSE BIT(8)
41#define PWM_BYPASS BIT(9)
42
43#define PWM_RDY_BASE 28
44#define PWM_RDY_OFFSET 1
45#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
46
47#define PWM_PRD(prd) (((prd) - 1) << 16)
48#define PWM_PRD_MASK GENMASK(15, 0)
49
50#define PWM_DTY_MASK GENMASK(15, 0)
51
52#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
53#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
54#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
55
56#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
57
58static const u32 prescaler_table[] = {
59 120,
60 180,
61 240,
62 360,
63 480,
64 0,
65 0,
66 0,
67 12000,
68 24000,
69 36000,
70 48000,
71 72000,
72 0,
73 0,
74 0, /* Actually 1 but tested separately */
75};
76
77struct sun4i_pwm_data {
78 bool has_prescaler_bypass;
79 bool has_direct_mod_clk_output;
80 unsigned int npwm;
81};
82
83struct sun4i_pwm_chip {
84 struct pwm_chip chip;
85 struct clk *bus_clk;
86 struct clk *clk;
87 struct reset_control *rst;
88 void __iomem *base;
89 spinlock_t ctrl_lock;
90 const struct sun4i_pwm_data *data;
91};
92
93static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
94{
95 return container_of(chip, struct sun4i_pwm_chip, chip);
96}
97
98static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
99 unsigned long offset)
100{
101 return readl(chip->base + offset);
102}
103
104static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
105 u32 val, unsigned long offset)
106{
107 writel(val, chip->base + offset);
108}
109
110static int sun4i_pwm_get_state(struct pwm_chip *chip,
111 struct pwm_device *pwm,
112 struct pwm_state *state)
113{
114 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
115 u64 clk_rate, tmp;
116 u32 val;
117 unsigned int prescaler;
118
119 clk_rate = clk_get_rate(sun4i_pwm->clk);
120 if (!clk_rate)
121 return -EINVAL;
122
123 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
124
125 /*
126 * PWM chapter in H6 manual has a diagram which explains that if bypass
127 * bit is set, no other setting has any meaning. Even more, experiment
128 * proved that also enable bit is ignored in this case.
129 */
130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
131 sun4i_pwm->data->has_direct_mod_clk_output) {
132 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
133 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
134 state->polarity = PWM_POLARITY_NORMAL;
135 state->enabled = true;
136 return 0;
137 }
138
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
140 sun4i_pwm->data->has_prescaler_bypass)
141 prescaler = 1;
142 else
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
144
145 if (prescaler == 0)
146 return -EINVAL;
147
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
149 state->polarity = PWM_POLARITY_NORMAL;
150 else
151 state->polarity = PWM_POLARITY_INVERSED;
152
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
155 state->enabled = true;
156 else
157 state->enabled = false;
158
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
160
161 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
162 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
163
164 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
165 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
166
167 return 0;
168}
169
170static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
171 const struct pwm_state *state,
172 u32 *dty, u32 *prd, unsigned int *prsclr,
173 bool *bypass)
174{
175 u64 clk_rate, div = 0;
176 unsigned int prescaler = 0;
177
178 clk_rate = clk_get_rate(sun4i_pwm->clk);
179
180 *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
181 state->enabled &&
182 (state->period * clk_rate >= NSEC_PER_SEC) &&
183 (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
184 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
185
186 /* Skip calculation of other parameters if we bypass them */
187 if (*bypass)
188 return 0;
189
190 if (sun4i_pwm->data->has_prescaler_bypass) {
191 /* First, test without any prescaler when available */
192 prescaler = PWM_PRESCAL_MASK;
193 /*
194 * When not using any prescaler, the clock period in nanoseconds
195 * is not an integer so round it half up instead of
196 * truncating to get less surprising values.
197 */
198 div = clk_rate * state->period + NSEC_PER_SEC / 2;
199 do_div(div, NSEC_PER_SEC);
200 if (div - 1 > PWM_PRD_MASK)
201 prescaler = 0;
202 }
203
204 if (prescaler == 0) {
205 /* Go up from the first divider */
206 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
207 unsigned int pval = prescaler_table[prescaler];
208
209 if (!pval)
210 continue;
211
212 div = clk_rate;
213 do_div(div, pval);
214 div = div * state->period;
215 do_div(div, NSEC_PER_SEC);
216 if (div - 1 <= PWM_PRD_MASK)
217 break;
218 }
219
220 if (div - 1 > PWM_PRD_MASK)
221 return -EINVAL;
222 }
223
224 *prd = div;
225 div *= state->duty_cycle;
226 do_div(div, state->period);
227 *dty = div;
228 *prsclr = prescaler;
229
230 return 0;
231}
232
233static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
234 const struct pwm_state *state)
235{
236 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
237 struct pwm_state cstate;
238 u32 ctrl, duty = 0, period = 0, val;
239 int ret;
240 unsigned int delay_us, prescaler = 0;
241 bool bypass;
242
243 pwm_get_state(pwm, &cstate);
244
245 if (!cstate.enabled) {
246 ret = clk_prepare_enable(sun4i_pwm->clk);
247 if (ret) {
248 dev_err(chip->dev, "failed to enable PWM clock\n");
249 return ret;
250 }
251 }
252
253 ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
254 &bypass);
255 if (ret) {
256 dev_err(chip->dev, "period exceeds the maximum value\n");
257 if (!cstate.enabled)
258 clk_disable_unprepare(sun4i_pwm->clk);
259 return ret;
260 }
261
262 spin_lock(&sun4i_pwm->ctrl_lock);
263 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
264
265 if (sun4i_pwm->data->has_direct_mod_clk_output) {
266 if (bypass) {
267 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
268 /* We can skip other parameter */
269 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
270 spin_unlock(&sun4i_pwm->ctrl_lock);
271 return 0;
272 }
273
274 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
275 }
276
277 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
278 /* Prescaler changed, the clock has to be gated */
279 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
280 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
281
282 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
283 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
284 }
285
286 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
287 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
288
289 if (state->polarity != PWM_POLARITY_NORMAL)
290 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
291 else
292 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
293
294 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
295
296 if (state->enabled)
297 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
298
299 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
300
301 spin_unlock(&sun4i_pwm->ctrl_lock);
302
303 if (state->enabled)
304 return 0;
305
306 /* We need a full period to elapse before disabling the channel. */
307 delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
308 if ((delay_us / 500) > MAX_UDELAY_MS)
309 msleep(delay_us / 1000 + 1);
310 else
311 usleep_range(delay_us, delay_us * 2);
312
313 spin_lock(&sun4i_pwm->ctrl_lock);
314 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
315 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
316 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
317 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
318 spin_unlock(&sun4i_pwm->ctrl_lock);
319
320 clk_disable_unprepare(sun4i_pwm->clk);
321
322 return 0;
323}
324
325static const struct pwm_ops sun4i_pwm_ops = {
326 .apply = sun4i_pwm_apply,
327 .get_state = sun4i_pwm_get_state,
328};
329
330static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
331 .has_prescaler_bypass = false,
332 .npwm = 2,
333};
334
335static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
336 .has_prescaler_bypass = true,
337 .npwm = 2,
338};
339
340static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
341 .has_prescaler_bypass = true,
342 .npwm = 1,
343};
344
345static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
346 .has_prescaler_bypass = true,
347 .has_direct_mod_clk_output = true,
348 .npwm = 1,
349};
350
351static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
352 .has_prescaler_bypass = true,
353 .has_direct_mod_clk_output = true,
354 .npwm = 2,
355};
356
357static const struct of_device_id sun4i_pwm_dt_ids[] = {
358 {
359 .compatible = "allwinner,sun4i-a10-pwm",
360 .data = &sun4i_pwm_dual_nobypass,
361 }, {
362 .compatible = "allwinner,sun5i-a10s-pwm",
363 .data = &sun4i_pwm_dual_bypass,
364 }, {
365 .compatible = "allwinner,sun5i-a13-pwm",
366 .data = &sun4i_pwm_single_bypass,
367 }, {
368 .compatible = "allwinner,sun7i-a20-pwm",
369 .data = &sun4i_pwm_dual_bypass,
370 }, {
371 .compatible = "allwinner,sun8i-h3-pwm",
372 .data = &sun4i_pwm_single_bypass,
373 }, {
374 .compatible = "allwinner,sun50i-a64-pwm",
375 .data = &sun50i_a64_pwm_data,
376 }, {
377 .compatible = "allwinner,sun50i-h6-pwm",
378 .data = &sun50i_h6_pwm_data,
379 }, {
380 /* sentinel */
381 },
382};
383MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
384
385static int sun4i_pwm_probe(struct platform_device *pdev)
386{
387 struct sun4i_pwm_chip *sun4ichip;
388 int ret;
389
390 sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL);
391 if (!sun4ichip)
392 return -ENOMEM;
393
394 sun4ichip->data = of_device_get_match_data(&pdev->dev);
395 if (!sun4ichip->data)
396 return -ENODEV;
397
398 sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
399 if (IS_ERR(sun4ichip->base))
400 return PTR_ERR(sun4ichip->base);
401
402 /*
403 * All hardware variants need a source clock that is divided and
404 * then feeds the counter that defines the output wave form. In the
405 * device tree this clock is either unnamed or called "mod".
406 * Some variants (e.g. H6) need another clock to access the
407 * hardware registers; this is called "bus".
408 * So we request "mod" first (and ignore the corner case that a
409 * parent provides a "mod" clock while the right one would be the
410 * unnamed one of the PWM device) and if this is not found we fall
411 * back to the first clock of the PWM.
412 */
413 sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
414 if (IS_ERR(sun4ichip->clk))
415 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
416 "get mod clock failed\n");
417
418 if (!sun4ichip->clk) {
419 sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
420 if (IS_ERR(sun4ichip->clk))
421 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
422 "get unnamed clock failed\n");
423 }
424
425 sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
426 if (IS_ERR(sun4ichip->bus_clk))
427 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
428 "get bus clock failed\n");
429
430 sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
431 if (IS_ERR(sun4ichip->rst))
432 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
433 "get reset failed\n");
434
435 /* Deassert reset */
436 ret = reset_control_deassert(sun4ichip->rst);
437 if (ret) {
438 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
439 ERR_PTR(ret));
440 return ret;
441 }
442
443 /*
444 * We're keeping the bus clock on for the sake of simplicity.
445 * Actually it only needs to be on for hardware register accesses.
446 */
447 ret = clk_prepare_enable(sun4ichip->bus_clk);
448 if (ret) {
449 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
450 ERR_PTR(ret));
451 goto err_bus;
452 }
453
454 sun4ichip->chip.dev = &pdev->dev;
455 sun4ichip->chip.ops = &sun4i_pwm_ops;
456 sun4ichip->chip.npwm = sun4ichip->data->npwm;
457
458 spin_lock_init(&sun4ichip->ctrl_lock);
459
460 ret = pwmchip_add(&sun4ichip->chip);
461 if (ret < 0) {
462 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
463 goto err_pwm_add;
464 }
465
466 platform_set_drvdata(pdev, sun4ichip);
467
468 return 0;
469
470err_pwm_add:
471 clk_disable_unprepare(sun4ichip->bus_clk);
472err_bus:
473 reset_control_assert(sun4ichip->rst);
474
475 return ret;
476}
477
478static void sun4i_pwm_remove(struct platform_device *pdev)
479{
480 struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev);
481
482 pwmchip_remove(&sun4ichip->chip);
483
484 clk_disable_unprepare(sun4ichip->bus_clk);
485 reset_control_assert(sun4ichip->rst);
486}
487
488static struct platform_driver sun4i_pwm_driver = {
489 .driver = {
490 .name = "sun4i-pwm",
491 .of_match_table = sun4i_pwm_dt_ids,
492 },
493 .probe = sun4i_pwm_probe,
494 .remove_new = sun4i_pwm_remove,
495};
496module_platform_driver(sun4i_pwm_driver);
497
498MODULE_ALIAS("platform:sun4i-pwm");
499MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
500MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
501MODULE_LICENSE("GPL v2");