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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Clock based PWM controller
4 *
5 * Copyright (c) 2021 Nikita Travkin <nikita@trvn.ru>
6 *
7 * This is an "adapter" driver that allows PWM consumers to use
8 * system clocks with duty cycle control as PWM outputs.
9 *
10 * Limitations:
11 * - Due to the fact that exact behavior depends on the underlying
12 * clock driver, various limitations are possible.
13 * - Underlying clock may not be able to give 0% or 100% duty cycle
14 * (constant off or on), exact behavior will depend on the clock.
15 * - When the PWM is disabled, the clock will be disabled as well,
16 * line state will depend on the clock.
17 * - The clk API doesn't expose the necessary calls to implement
18 * .get_state().
19 */
20
21#include <linux/kernel.h>
22#include <linux/math64.h>
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/clk.h>
28#include <linux/pwm.h>
29
30struct pwm_clk_chip {
31 struct clk *clk;
32 bool clk_enabled;
33};
34
35static inline struct pwm_clk_chip *to_pwm_clk_chip(struct pwm_chip *chip)
36{
37 return pwmchip_get_drvdata(chip);
38}
39
40static int pwm_clk_apply(struct pwm_chip *chip, struct pwm_device *pwm,
41 const struct pwm_state *state)
42{
43 struct pwm_clk_chip *pcchip = to_pwm_clk_chip(chip);
44 int ret;
45 u32 rate;
46 u64 period = state->period;
47 u64 duty_cycle = state->duty_cycle;
48
49 if (!state->enabled) {
50 if (pwm->state.enabled) {
51 clk_disable(pcchip->clk);
52 pcchip->clk_enabled = false;
53 }
54 return 0;
55 } else if (!pwm->state.enabled) {
56 ret = clk_enable(pcchip->clk);
57 if (ret)
58 return ret;
59 pcchip->clk_enabled = true;
60 }
61
62 /*
63 * We have to enable the clk before setting the rate and duty_cycle,
64 * that however results in a window where the clk is on with a
65 * (potentially) different setting. Also setting period and duty_cycle
66 * are two separate calls, so that probably isn't atomic either.
67 */
68
69 rate = DIV64_U64_ROUND_UP(NSEC_PER_SEC, period);
70 ret = clk_set_rate(pcchip->clk, rate);
71 if (ret)
72 return ret;
73
74 if (state->polarity == PWM_POLARITY_INVERSED)
75 duty_cycle = period - duty_cycle;
76
77 return clk_set_duty_cycle(pcchip->clk, duty_cycle, period);
78}
79
80static const struct pwm_ops pwm_clk_ops = {
81 .apply = pwm_clk_apply,
82};
83
84static int pwm_clk_probe(struct platform_device *pdev)
85{
86 struct pwm_chip *chip;
87 struct pwm_clk_chip *pcchip;
88 int ret;
89
90 chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*pcchip));
91 if (IS_ERR(chip))
92 return PTR_ERR(chip);
93 pcchip = to_pwm_clk_chip(chip);
94
95 pcchip->clk = devm_clk_get_prepared(&pdev->dev, NULL);
96 if (IS_ERR(pcchip->clk))
97 return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->clk),
98 "Failed to get clock\n");
99
100 chip->ops = &pwm_clk_ops;
101
102 ret = pwmchip_add(chip);
103 if (ret < 0)
104 return dev_err_probe(&pdev->dev, ret, "Failed to add pwm chip\n");
105
106 platform_set_drvdata(pdev, chip);
107 return 0;
108}
109
110static void pwm_clk_remove(struct platform_device *pdev)
111{
112 struct pwm_chip *chip = platform_get_drvdata(pdev);
113 struct pwm_clk_chip *pcchip = to_pwm_clk_chip(chip);
114
115 pwmchip_remove(chip);
116
117 if (pcchip->clk_enabled)
118 clk_disable(pcchip->clk);
119}
120
121static const struct of_device_id pwm_clk_dt_ids[] = {
122 { .compatible = "clk-pwm", },
123 { /* sentinel */ }
124};
125MODULE_DEVICE_TABLE(of, pwm_clk_dt_ids);
126
127static struct platform_driver pwm_clk_driver = {
128 .driver = {
129 .name = "pwm-clk",
130 .of_match_table = pwm_clk_dt_ids,
131 },
132 .probe = pwm_clk_probe,
133 .remove = pwm_clk_remove,
134};
135module_platform_driver(pwm_clk_driver);
136
137MODULE_ALIAS("platform:pwm-clk");
138MODULE_AUTHOR("Nikita Travkin <nikita@trvn.ru>");
139MODULE_DESCRIPTION("Clock based PWM driver");
140MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Clock based PWM controller
4 *
5 * Copyright (c) 2021 Nikita Travkin <nikita@trvn.ru>
6 *
7 * This is an "adapter" driver that allows PWM consumers to use
8 * system clocks with duty cycle control as PWM outputs.
9 *
10 * Limitations:
11 * - Due to the fact that exact behavior depends on the underlying
12 * clock driver, various limitations are possible.
13 * - Underlying clock may not be able to give 0% or 100% duty cycle
14 * (constant off or on), exact behavior will depend on the clock.
15 * - When the PWM is disabled, the clock will be disabled as well,
16 * line state will depend on the clock.
17 * - The clk API doesn't expose the necessary calls to implement
18 * .get_state().
19 */
20
21#include <linux/kernel.h>
22#include <linux/math64.h>
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/clk.h>
28#include <linux/pwm.h>
29
30struct pwm_clk_chip {
31 struct pwm_chip chip;
32 struct clk *clk;
33 bool clk_enabled;
34};
35
36#define to_pwm_clk_chip(_chip) container_of(_chip, struct pwm_clk_chip, chip)
37
38static int pwm_clk_apply(struct pwm_chip *chip, struct pwm_device *pwm,
39 const struct pwm_state *state)
40{
41 struct pwm_clk_chip *pcchip = to_pwm_clk_chip(chip);
42 int ret;
43 u32 rate;
44 u64 period = state->period;
45 u64 duty_cycle = state->duty_cycle;
46
47 if (!state->enabled) {
48 if (pwm->state.enabled) {
49 clk_disable(pcchip->clk);
50 pcchip->clk_enabled = false;
51 }
52 return 0;
53 } else if (!pwm->state.enabled) {
54 ret = clk_enable(pcchip->clk);
55 if (ret)
56 return ret;
57 pcchip->clk_enabled = true;
58 }
59
60 /*
61 * We have to enable the clk before setting the rate and duty_cycle,
62 * that however results in a window where the clk is on with a
63 * (potentially) different setting. Also setting period and duty_cycle
64 * are two separate calls, so that probably isn't atomic either.
65 */
66
67 rate = DIV64_U64_ROUND_UP(NSEC_PER_SEC, period);
68 ret = clk_set_rate(pcchip->clk, rate);
69 if (ret)
70 return ret;
71
72 if (state->polarity == PWM_POLARITY_INVERSED)
73 duty_cycle = period - duty_cycle;
74
75 return clk_set_duty_cycle(pcchip->clk, duty_cycle, period);
76}
77
78static const struct pwm_ops pwm_clk_ops = {
79 .apply = pwm_clk_apply,
80};
81
82static int pwm_clk_probe(struct platform_device *pdev)
83{
84 struct pwm_clk_chip *pcchip;
85 int ret;
86
87 pcchip = devm_kzalloc(&pdev->dev, sizeof(*pcchip), GFP_KERNEL);
88 if (!pcchip)
89 return -ENOMEM;
90
91 pcchip->clk = devm_clk_get_prepared(&pdev->dev, NULL);
92 if (IS_ERR(pcchip->clk))
93 return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->clk),
94 "Failed to get clock\n");
95
96 pcchip->chip.dev = &pdev->dev;
97 pcchip->chip.ops = &pwm_clk_ops;
98 pcchip->chip.npwm = 1;
99
100 ret = pwmchip_add(&pcchip->chip);
101 if (ret < 0)
102 return dev_err_probe(&pdev->dev, ret, "Failed to add pwm chip\n");
103
104 platform_set_drvdata(pdev, pcchip);
105 return 0;
106}
107
108static void pwm_clk_remove(struct platform_device *pdev)
109{
110 struct pwm_clk_chip *pcchip = platform_get_drvdata(pdev);
111
112 pwmchip_remove(&pcchip->chip);
113
114 if (pcchip->clk_enabled)
115 clk_disable(pcchip->clk);
116}
117
118static const struct of_device_id pwm_clk_dt_ids[] = {
119 { .compatible = "clk-pwm", },
120 { /* sentinel */ }
121};
122MODULE_DEVICE_TABLE(of, pwm_clk_dt_ids);
123
124static struct platform_driver pwm_clk_driver = {
125 .driver = {
126 .name = "pwm-clk",
127 .of_match_table = pwm_clk_dt_ids,
128 },
129 .probe = pwm_clk_probe,
130 .remove_new = pwm_clk_remove,
131};
132module_platform_driver(pwm_clk_driver);
133
134MODULE_ALIAS("platform:pwm-clk");
135MODULE_AUTHOR("Nikita Travkin <nikita@trvn.ru>");
136MODULE_DESCRIPTION("Clock based PWM driver");
137MODULE_LICENSE("GPL");