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1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2023 NXP
3
4#include <linux/bitfield.h>
5#include <linux/init.h>
6#include <linux/interrupt.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/platform_device.h>
11#include <linux/perf_event.h>
12
13/* Performance monitor configuration */
14#define PMCFG1 0x00
15#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31)
16#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30)
17#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
18#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
19
20#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31)
21#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30)
22
23#define PMCFG2 0x04
24#define MX93_PMCFG2_ID GENMASK(17, 0)
25
26#define PMCFG3 0x08
27#define PMCFG4 0x0C
28#define PMCFG5 0x10
29#define PMCFG6 0x14
30#define MX95_PMCFG_ID_MASK GENMASK(9, 0)
31#define MX95_PMCFG_ID GENMASK(25, 16)
32
33/* Global control register affects all counters and takes priority over local control registers */
34#define PMGC0 0x40
35/* Global control register bits */
36#define PMGC0_FAC BIT(31)
37#define PMGC0_PMIE BIT(30)
38#define PMGC0_FCECE BIT(29)
39
40/*
41 * 64bit counter0 exclusively dedicated to counting cycles
42 * 32bit counters monitor counter-specific events in addition to counting reference events
43 */
44#define PMLCA(n) (0x40 + 0x10 + (0x10 * n))
45#define PMLCB(n) (0x40 + 0x14 + (0x10 * n))
46#define PMC(n) (0x40 + 0x18 + (0x10 * n))
47/* Local control register bits */
48#define PMLCA_FC BIT(31)
49#define PMLCA_CE BIT(26)
50#define PMLCA_EVENT GENMASK(22, 16)
51
52#define NUM_COUNTERS 11
53#define CYCLES_COUNTER 0
54#define CYCLES_EVENT_ID 0
55
56#define CONFIG_EVENT_MASK GENMASK(7, 0)
57#define CONFIG_COUNTER_MASK GENMASK(23, 16)
58
59#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
60
61#define DDR_PERF_DEV_NAME "imx9_ddr"
62#define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu"
63
64static DEFINE_IDA(ddr_ida);
65
66/*
67 * V1 support 1 read transaction, 1 write transaction and 1 read beats
68 * event which corresponding respecitively to counter 2, 3 and 4.
69 */
70#define DDR_PERF_AXI_FILTER_V1 0x1
71
72/*
73 * V2 support 1 read beats and 3 write beats events which corresponding
74 * respecitively to counter 2-5.
75 */
76#define DDR_PERF_AXI_FILTER_V2 0x2
77
78struct imx_ddr_devtype_data {
79 const char *identifier; /* system PMU identifier for userspace */
80 unsigned int filter_ver; /* AXI filter version */
81};
82
83struct ddr_pmu {
84 struct pmu pmu;
85 void __iomem *base;
86 unsigned int cpu;
87 struct hlist_node node;
88 struct device *dev;
89 struct perf_event *events[NUM_COUNTERS];
90 int active_events;
91 enum cpuhp_state cpuhp_state;
92 const struct imx_ddr_devtype_data *devtype_data;
93 int irq;
94 int id;
95};
96
97static const struct imx_ddr_devtype_data imx91_devtype_data = {
98 .identifier = "imx91",
99 .filter_ver = DDR_PERF_AXI_FILTER_V1
100};
101
102static const struct imx_ddr_devtype_data imx93_devtype_data = {
103 .identifier = "imx93",
104 .filter_ver = DDR_PERF_AXI_FILTER_V1
105};
106
107static const struct imx_ddr_devtype_data imx95_devtype_data = {
108 .identifier = "imx95",
109 .filter_ver = DDR_PERF_AXI_FILTER_V2
110};
111
112static inline bool axi_filter_v1(struct ddr_pmu *pmu)
113{
114 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1;
115}
116
117static inline bool axi_filter_v2(struct ddr_pmu *pmu)
118{
119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2;
120}
121
122static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
123 { .compatible = "fsl,imx91-ddr-pmu", .data = &imx91_devtype_data },
124 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
125 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
126 { /* sentinel */ }
127};
128MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
129
130static ssize_t ddr_perf_identifier_show(struct device *dev,
131 struct device_attribute *attr,
132 char *page)
133{
134 struct ddr_pmu *pmu = dev_get_drvdata(dev);
135
136 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier);
137}
138
139static struct device_attribute ddr_perf_identifier_attr =
140 __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
141
142static struct attribute *ddr_perf_identifier_attrs[] = {
143 &ddr_perf_identifier_attr.attr,
144 NULL,
145};
146
147static struct attribute_group ddr_perf_identifier_attr_group = {
148 .attrs = ddr_perf_identifier_attrs,
149};
150
151static ssize_t ddr_perf_cpumask_show(struct device *dev,
152 struct device_attribute *attr, char *buf)
153{
154 struct ddr_pmu *pmu = dev_get_drvdata(dev);
155
156 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
157}
158
159static struct device_attribute ddr_perf_cpumask_attr =
160 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
161
162static struct attribute *ddr_perf_cpumask_attrs[] = {
163 &ddr_perf_cpumask_attr.attr,
164 NULL,
165};
166
167static const struct attribute_group ddr_perf_cpumask_attr_group = {
168 .attrs = ddr_perf_cpumask_attrs,
169};
170
171struct imx9_pmu_events_attr {
172 struct device_attribute attr;
173 u64 id;
174 const struct imx_ddr_devtype_data *devtype_data;
175};
176
177static ssize_t ddr_pmu_event_show(struct device *dev,
178 struct device_attribute *attr, char *page)
179{
180 struct imx9_pmu_events_attr *pmu_attr;
181
182 pmu_attr = container_of(attr, struct imx9_pmu_events_attr, attr);
183 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
184}
185
186#define COUNTER_OFFSET_IN_EVENT 8
187#define ID(counter, id) ((counter << COUNTER_OFFSET_IN_EVENT) | id)
188
189#define DDR_PMU_EVENT_ATTR_COMM(_name, _id, _data) \
190 (&((struct imx9_pmu_events_attr[]) { \
191 { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
192 .id = _id, \
193 .devtype_data = _data, } \
194 })[0].attr.attr)
195
196#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \
197 DDR_PMU_EVENT_ATTR_COMM(_name, _id, NULL)
198
199#define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \
200 DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data)
201
202#define IMX95_DDR_PMU_EVENT_ATTR(_name, _id) \
203 DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx95_devtype_data)
204
205static struct attribute *ddr_perf_events_attrs[] = {
206 /* counter0 cycles event */
207 IMX9_DDR_PMU_EVENT_ATTR(cycles, 0),
208
209 /* reference events for all normal counters, need assert DEBUG19[21] bit */
210 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ddrc1_rmw_for_ecc, 12),
211 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_rreorder, 13),
212 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_wreorder, 14),
213 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_0, 15),
214 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_1, 16),
215 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_2, 17),
216 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_3, 18),
217 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_4, 19),
218 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_5, 22),
219 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_6, 23),
220 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_7, 24),
221 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_8, 25),
222 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_9, 26),
223 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_10, 27),
224 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_11, 28),
225 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_12, 31),
226 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_13, 59),
227 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_15, 61),
228 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_29, 63),
229
230 /* counter1 specific events */
231 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, ID(1, 64)),
232 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, ID(1, 65)),
233 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, ID(1, 66)),
234 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, ID(1, 67)),
235 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, ID(1, 68)),
236 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, ID(1, 69)),
237 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, ID(1, 70)),
238 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, ID(1, 71)),
239
240 /* counter2 specific events */
241 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, ID(2, 64)),
242 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, ID(2, 65)),
243 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, ID(2, 66)),
244 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, ID(2, 67)),
245 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, ID(2, 68)),
246 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, ID(2, 69)),
247 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)),
248 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
249 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
250 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/
251 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, ID(2, 73)), /* imx95 specific*/
252
253 /* counter3 specific events */
254 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
255 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, ID(3, 65)),
256 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, ID(3, 66)),
257 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, ID(3, 67)),
258 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, ID(3, 68)),
259 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, ID(3, 69)),
260 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)),
261 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
262 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
263 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/
264 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, ID(3, 73)), /* imx95 specific*/
265
266 /* counter4 specific events */
267 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
268 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, ID(4, 65)),
269 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, ID(4, 66)),
270 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, ID(4, 67)),
271 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, ID(4, 68)),
272 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, ID(4, 69)),
273 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)),
274 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
275 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
276 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/
277 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, ID(4, 73)), /* imx95 specific*/
278
279 /* counter5 specific events */
280 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
281 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, ID(5, 65)),
282 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, ID(5, 66)),
283 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, ID(5, 67)),
284 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, ID(5, 68)),
285 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, ID(5, 69)),
286 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)),
287 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)),
288 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)),
289 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, ID(5, 73)), /* imx95 specific*/
290
291 /* counter6 specific events */
292 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)),
293 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, ID(6, 72)),
294
295 /* counter7 specific events */
296 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, ID(7, 64)),
297 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, ID(7, 65)),
298
299 /* counter8 specific events */
300 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, ID(8, 64)),
301 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, ID(8, 65)),
302
303 /* counter9 specific events */
304 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, ID(9, 65)),
305 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, ID(9, 66)),
306
307 /* counter10 specific events */
308 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, ID(10, 65)),
309 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, ID(10, 66)),
310 NULL,
311};
312
313static umode_t
314ddr_perf_events_attrs_is_visible(struct kobject *kobj,
315 struct attribute *attr, int unused)
316{
317 struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj));
318 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
319 struct imx9_pmu_events_attr *eattr;
320
321 eattr = container_of(attr, typeof(*eattr), attr.attr);
322
323 if (!eattr->devtype_data)
324 return attr->mode;
325
326 if (eattr->devtype_data != ddr_pmu->devtype_data &&
327 eattr->devtype_data->filter_ver != ddr_pmu->devtype_data->filter_ver)
328 return 0;
329
330 return attr->mode;
331}
332
333static const struct attribute_group ddr_perf_events_attr_group = {
334 .name = "events",
335 .attrs = ddr_perf_events_attrs,
336 .is_visible = ddr_perf_events_attrs_is_visible,
337};
338
339PMU_FORMAT_ATTR(event, "config:0-7,16-23");
340PMU_FORMAT_ATTR(counter, "config:8-15");
341PMU_FORMAT_ATTR(axi_id, "config1:0-17");
342PMU_FORMAT_ATTR(axi_mask, "config2:0-17");
343
344static struct attribute *ddr_perf_format_attrs[] = {
345 &format_attr_event.attr,
346 &format_attr_counter.attr,
347 &format_attr_axi_id.attr,
348 &format_attr_axi_mask.attr,
349 NULL,
350};
351
352static const struct attribute_group ddr_perf_format_attr_group = {
353 .name = "format",
354 .attrs = ddr_perf_format_attrs,
355};
356
357static const struct attribute_group *attr_groups[] = {
358 &ddr_perf_identifier_attr_group,
359 &ddr_perf_cpumask_attr_group,
360 &ddr_perf_events_attr_group,
361 &ddr_perf_format_attr_group,
362 NULL,
363};
364
365static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter)
366{
367 if (counter == CYCLES_COUNTER) {
368 writel(0, pmu->base + PMC(counter) + 0x4);
369 writel(0, pmu->base + PMC(counter));
370 } else {
371 writel(0, pmu->base + PMC(counter));
372 }
373}
374
375static u64 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
376{
377 u32 val_lower, val_upper;
378 u64 val;
379
380 if (counter != CYCLES_COUNTER) {
381 val = readl_relaxed(pmu->base + PMC(counter));
382 goto out;
383 }
384
385 /* special handling for reading 64bit cycle counter */
386 do {
387 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4);
388 val_lower = readl_relaxed(pmu->base + PMC(counter));
389 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4));
390
391 val = val_upper;
392 val = (val << 32);
393 val |= val_lower;
394out:
395 return val;
396}
397
398static void ddr_perf_counter_global_config(struct ddr_pmu *pmu, bool enable)
399{
400 u32 ctrl;
401
402 ctrl = readl_relaxed(pmu->base + PMGC0);
403
404 if (enable) {
405 /*
406 * The performance monitor must be reset before event counting
407 * sequences. The performance monitor can be reset by first freezing
408 * one or more counters and then clearing the freeze condition to
409 * allow the counters to count according to the settings in the
410 * performance monitor registers. Counters can be frozen individually
411 * by setting PMLCAn[FC] bits, or simultaneously by setting PMGC0[FAC].
412 * Simply clearing these freeze bits will then allow the performance
413 * monitor to begin counting based on the register settings.
414 */
415 ctrl |= PMGC0_FAC;
416 writel(ctrl, pmu->base + PMGC0);
417
418 /*
419 * Freeze all counters disabled, interrupt enabled, and freeze
420 * counters on condition enabled.
421 */
422 ctrl &= ~PMGC0_FAC;
423 ctrl |= PMGC0_PMIE | PMGC0_FCECE;
424 writel(ctrl, pmu->base + PMGC0);
425 } else {
426 ctrl |= PMGC0_FAC;
427 ctrl &= ~(PMGC0_PMIE | PMGC0_FCECE);
428 writel(ctrl, pmu->base + PMGC0);
429 }
430}
431
432static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
433 int counter, bool enable)
434{
435 u32 ctrl_a;
436 int event;
437
438 ctrl_a = readl_relaxed(pmu->base + PMLCA(counter));
439 event = FIELD_GET(CONFIG_EVENT_MASK, config);
440
441 if (enable) {
442 ctrl_a |= PMLCA_FC;
443 writel(ctrl_a, pmu->base + PMLCA(counter));
444
445 ddr_perf_clear_counter(pmu, counter);
446
447 /* Freeze counter disabled, condition enabled, and program event.*/
448 ctrl_a &= ~PMLCA_FC;
449 ctrl_a |= PMLCA_CE;
450 ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F);
451 ctrl_a |= FIELD_PREP(PMLCA_EVENT, event);
452 writel(ctrl_a, pmu->base + PMLCA(counter));
453 } else {
454 /* Freeze counter. */
455 ctrl_a |= PMLCA_FC;
456 writel(ctrl_a, pmu->base + PMLCA(counter));
457 }
458}
459
460static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
461 int counter, int axi_id, int axi_mask)
462{
463 u32 pmcfg1, pmcfg2;
464 u32 mask[] = { MX93_PMCFG1_RD_TRANS_FILT_EN,
465 MX93_PMCFG1_WR_TRANS_FILT_EN,
466 MX93_PMCFG1_RD_BT_FILT_EN };
467
468 pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
469
470 if (counter >= 2 && counter <= 4)
471 pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] :
472 pmcfg1 & ~mask[counter - 2];
473
474 pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
475 pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask);
476 writel_relaxed(pmcfg1, pmu->base + PMCFG1);
477
478 pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
479 pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
480 pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id);
481 writel_relaxed(pmcfg2, pmu->base + PMCFG2);
482}
483
484static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
485 int counter, int axi_id, int axi_mask)
486{
487 u32 pmcfg1, pmcfg, offset = 0;
488
489 pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
490
491 if (event == 73) {
492 switch (counter) {
493 case 2:
494 pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN;
495 offset = PMCFG3;
496 break;
497 case 3:
498 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
499 offset = PMCFG4;
500 break;
501 case 4:
502 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
503 offset = PMCFG5;
504 break;
505 case 5:
506 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
507 offset = PMCFG6;
508 break;
509 }
510 } else {
511 switch (counter) {
512 case 2:
513 pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN;
514 break;
515 case 3:
516 case 4:
517 case 5:
518 pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
519 break;
520 }
521 }
522
523 writel_relaxed(pmcfg1, pmu->base + PMCFG1);
524
525 if (offset) {
526 pmcfg = readl_relaxed(pmu->base + offset);
527 pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) |
528 FIELD_PREP(MX95_PMCFG_ID, 0x3FF));
529 pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, axi_mask) |
530 FIELD_PREP(MX95_PMCFG_ID, axi_id));
531 writel_relaxed(pmcfg, pmu->base + offset);
532 }
533}
534
535static void ddr_perf_event_update(struct perf_event *event)
536{
537 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
538 struct hw_perf_event *hwc = &event->hw;
539 int counter = hwc->idx;
540 u64 new_raw_count;
541
542 new_raw_count = ddr_perf_read_counter(pmu, counter);
543 local64_add(new_raw_count, &event->count);
544
545 /* clear counter's value every time */
546 ddr_perf_clear_counter(pmu, counter);
547}
548
549static int ddr_perf_event_init(struct perf_event *event)
550{
551 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
552 struct hw_perf_event *hwc = &event->hw;
553 struct perf_event *sibling;
554
555 if (event->attr.type != event->pmu->type)
556 return -ENOENT;
557
558 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
559 return -EOPNOTSUPP;
560
561 if (event->cpu < 0) {
562 dev_warn(pmu->dev, "Can't provide per-task data!\n");
563 return -EOPNOTSUPP;
564 }
565
566 /*
567 * We must NOT create groups containing mixed PMUs, although software
568 * events are acceptable (for example to create a CCN group
569 * periodically read when a hrtimer aka cpu-clock leader triggers).
570 */
571 if (event->group_leader->pmu != event->pmu &&
572 !is_software_event(event->group_leader))
573 return -EINVAL;
574
575 for_each_sibling_event(sibling, event->group_leader) {
576 if (sibling->pmu != event->pmu &&
577 !is_software_event(sibling))
578 return -EINVAL;
579 }
580
581 event->cpu = pmu->cpu;
582 hwc->idx = -1;
583
584 return 0;
585}
586
587static void ddr_perf_event_start(struct perf_event *event, int flags)
588{
589 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
590 struct hw_perf_event *hwc = &event->hw;
591 int counter = hwc->idx;
592
593 local64_set(&hwc->prev_count, 0);
594
595 ddr_perf_counter_local_config(pmu, event->attr.config, counter, true);
596 hwc->state = 0;
597}
598
599static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter)
600{
601 int i;
602
603 if (event == CYCLES_EVENT_ID) {
604 // Cycles counter is dedicated for cycle event.
605 if (pmu->events[CYCLES_COUNTER] == NULL)
606 return CYCLES_COUNTER;
607 } else if (counter != 0) {
608 // Counter specific event use specific counter.
609 if (pmu->events[counter] == NULL)
610 return counter;
611 } else {
612 // Auto allocate counter for referene event.
613 for (i = 1; i < NUM_COUNTERS; i++)
614 if (pmu->events[i] == NULL)
615 return i;
616 }
617
618 return -ENOENT;
619}
620
621static int ddr_perf_event_add(struct perf_event *event, int flags)
622{
623 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
624 struct hw_perf_event *hwc = &event->hw;
625 int cfg = event->attr.config;
626 int cfg1 = event->attr.config1;
627 int cfg2 = event->attr.config2;
628 int event_id, counter;
629
630 event_id = FIELD_GET(CONFIG_EVENT_MASK, cfg);
631 counter = FIELD_GET(CONFIG_COUNTER_MASK, cfg);
632
633 counter = ddr_perf_alloc_counter(pmu, event_id, counter);
634 if (counter < 0) {
635 dev_dbg(pmu->dev, "There are not enough counters\n");
636 return -EOPNOTSUPP;
637 }
638
639 pmu->events[counter] = event;
640 pmu->active_events++;
641 hwc->idx = counter;
642 hwc->state |= PERF_HES_STOPPED;
643
644 if (axi_filter_v1(pmu))
645 /* read trans, write trans, read beat */
646 imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
647
648 if (axi_filter_v2(pmu))
649 /* write beat, read beat2, read beat1, read beat */
650 imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
651
652 if (flags & PERF_EF_START)
653 ddr_perf_event_start(event, flags);
654
655 return 0;
656}
657
658static void ddr_perf_event_stop(struct perf_event *event, int flags)
659{
660 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
661 struct hw_perf_event *hwc = &event->hw;
662 int counter = hwc->idx;
663
664 ddr_perf_counter_local_config(pmu, event->attr.config, counter, false);
665 ddr_perf_event_update(event);
666
667 hwc->state |= PERF_HES_STOPPED;
668}
669
670static void ddr_perf_event_del(struct perf_event *event, int flags)
671{
672 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
673 struct hw_perf_event *hwc = &event->hw;
674 int counter = hwc->idx;
675
676 ddr_perf_event_stop(event, PERF_EF_UPDATE);
677
678 pmu->events[counter] = NULL;
679 pmu->active_events--;
680 hwc->idx = -1;
681}
682
683static void ddr_perf_pmu_enable(struct pmu *pmu)
684{
685 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
686
687 ddr_perf_counter_global_config(ddr_pmu, true);
688}
689
690static void ddr_perf_pmu_disable(struct pmu *pmu)
691{
692 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
693
694 ddr_perf_counter_global_config(ddr_pmu, false);
695}
696
697static void ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
698 struct device *dev)
699{
700 *pmu = (struct ddr_pmu) {
701 .pmu = (struct pmu) {
702 .module = THIS_MODULE,
703 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
704 .task_ctx_nr = perf_invalid_context,
705 .attr_groups = attr_groups,
706 .event_init = ddr_perf_event_init,
707 .add = ddr_perf_event_add,
708 .del = ddr_perf_event_del,
709 .start = ddr_perf_event_start,
710 .stop = ddr_perf_event_stop,
711 .read = ddr_perf_event_update,
712 .pmu_enable = ddr_perf_pmu_enable,
713 .pmu_disable = ddr_perf_pmu_disable,
714 },
715 .base = base,
716 .dev = dev,
717 };
718}
719
720static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
721{
722 struct ddr_pmu *pmu = (struct ddr_pmu *)p;
723 struct perf_event *event;
724 int i;
725
726 /*
727 * Counters can generate an interrupt on an overflow when msb of a
728 * counter changes from 0 to 1. For the interrupt to be signalled,
729 * below condition mush be satisfied:
730 * PMGC0[PMIE] = 1, PMGC0[FCECE] = 1, PMLCAn[CE] = 1
731 * When an interrupt is signalled, PMGC0[FAC] is set by hardware and
732 * all of the registers are frozen.
733 * Software can clear the interrupt condition by resetting the performance
734 * monitor and clearing the most significant bit of the counter that
735 * generate the overflow.
736 */
737 for (i = 0; i < NUM_COUNTERS; i++) {
738 if (!pmu->events[i])
739 continue;
740
741 event = pmu->events[i];
742
743 ddr_perf_event_update(event);
744 }
745
746 ddr_perf_counter_global_config(pmu, true);
747
748 return IRQ_HANDLED;
749}
750
751static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
752{
753 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
754 int target;
755
756 if (cpu != pmu->cpu)
757 return 0;
758
759 target = cpumask_any_but(cpu_online_mask, cpu);
760 if (target >= nr_cpu_ids)
761 return 0;
762
763 perf_pmu_migrate_context(&pmu->pmu, cpu, target);
764 pmu->cpu = target;
765
766 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)));
767
768 return 0;
769}
770
771static int ddr_perf_probe(struct platform_device *pdev)
772{
773 struct ddr_pmu *pmu;
774 void __iomem *base;
775 int ret, irq;
776 char *name;
777
778 base = devm_platform_ioremap_resource(pdev, 0);
779 if (IS_ERR(base))
780 return PTR_ERR(base);
781
782 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
783 if (!pmu)
784 return -ENOMEM;
785
786 ddr_perf_init(pmu, base, &pdev->dev);
787
788 pmu->devtype_data = of_device_get_match_data(&pdev->dev);
789
790 platform_set_drvdata(pdev, pmu);
791
792 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL);
793 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", pmu->id);
794 if (!name) {
795 ret = -ENOMEM;
796 goto format_string_err;
797 }
798
799 pmu->cpu = raw_smp_processor_id();
800 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DDR_CPUHP_CB_NAME,
801 NULL, ddr_perf_offline_cpu);
802 if (ret < 0) {
803 dev_err(&pdev->dev, "Failed to add callbacks for multi state\n");
804 goto cpuhp_state_err;
805 }
806 pmu->cpuhp_state = ret;
807
808 /* Register the pmu instance for cpu hotplug */
809 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
810 if (ret) {
811 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
812 goto cpuhp_instance_err;
813 }
814
815 /* Request irq */
816 irq = platform_get_irq(pdev, 0);
817 if (irq < 0) {
818 ret = irq;
819 goto ddr_perf_err;
820 }
821
822 ret = devm_request_irq(&pdev->dev, irq, ddr_perf_irq_handler,
823 IRQF_NOBALANCING | IRQF_NO_THREAD,
824 DDR_CPUHP_CB_NAME, pmu);
825 if (ret < 0) {
826 dev_err(&pdev->dev, "Request irq failed: %d", ret);
827 goto ddr_perf_err;
828 }
829
830 pmu->irq = irq;
831 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu));
832 if (ret) {
833 dev_err(pmu->dev, "Failed to set interrupt affinity\n");
834 goto ddr_perf_err;
835 }
836
837 ret = perf_pmu_register(&pmu->pmu, name, -1);
838 if (ret)
839 goto ddr_perf_err;
840
841 return 0;
842
843ddr_perf_err:
844 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
845cpuhp_instance_err:
846 cpuhp_remove_multi_state(pmu->cpuhp_state);
847cpuhp_state_err:
848format_string_err:
849 ida_free(&ddr_ida, pmu->id);
850 dev_warn(&pdev->dev, "i.MX9 DDR Perf PMU failed (%d), disabled\n", ret);
851 return ret;
852}
853
854static void ddr_perf_remove(struct platform_device *pdev)
855{
856 struct ddr_pmu *pmu = platform_get_drvdata(pdev);
857
858 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
859 cpuhp_remove_multi_state(pmu->cpuhp_state);
860
861 perf_pmu_unregister(&pmu->pmu);
862
863 ida_free(&ddr_ida, pmu->id);
864}
865
866static struct platform_driver imx_ddr_pmu_driver = {
867 .driver = {
868 .name = "imx9-ddr-pmu",
869 .of_match_table = imx_ddr_pmu_dt_ids,
870 .suppress_bind_attrs = true,
871 },
872 .probe = ddr_perf_probe,
873 .remove = ddr_perf_remove,
874};
875module_platform_driver(imx_ddr_pmu_driver);
876
877MODULE_AUTHOR("Xu Yang <xu.yang_2@nxp.com>");
878MODULE_LICENSE("GPL v2");
879MODULE_DESCRIPTION("DDRC PerfMon for i.MX9 SoCs");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2023 NXP
3
4#include <linux/bitfield.h>
5#include <linux/init.h>
6#include <linux/interrupt.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/platform_device.h>
11#include <linux/perf_event.h>
12
13/* Performance monitor configuration */
14#define PMCFG1 0x00
15#define PMCFG1_RD_TRANS_FILT_EN BIT(31)
16#define PMCFG1_WR_TRANS_FILT_EN BIT(30)
17#define PMCFG1_RD_BT_FILT_EN BIT(29)
18#define PMCFG1_ID_MASK GENMASK(17, 0)
19
20#define PMCFG2 0x04
21#define PMCFG2_ID GENMASK(17, 0)
22
23/* Global control register affects all counters and takes priority over local control registers */
24#define PMGC0 0x40
25/* Global control register bits */
26#define PMGC0_FAC BIT(31)
27#define PMGC0_PMIE BIT(30)
28#define PMGC0_FCECE BIT(29)
29
30/*
31 * 64bit counter0 exclusively dedicated to counting cycles
32 * 32bit counters monitor counter-specific events in addition to counting reference events
33 */
34#define PMLCA(n) (0x40 + 0x10 + (0x10 * n))
35#define PMLCB(n) (0x40 + 0x14 + (0x10 * n))
36#define PMC(n) (0x40 + 0x18 + (0x10 * n))
37/* Local control register bits */
38#define PMLCA_FC BIT(31)
39#define PMLCA_CE BIT(26)
40#define PMLCA_EVENT GENMASK(22, 16)
41
42#define NUM_COUNTERS 11
43#define CYCLES_COUNTER 0
44
45#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
46
47#define DDR_PERF_DEV_NAME "imx9_ddr"
48#define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu"
49
50static DEFINE_IDA(ddr_ida);
51
52struct imx_ddr_devtype_data {
53 const char *identifier; /* system PMU identifier for userspace */
54};
55
56struct ddr_pmu {
57 struct pmu pmu;
58 void __iomem *base;
59 unsigned int cpu;
60 struct hlist_node node;
61 struct device *dev;
62 struct perf_event *events[NUM_COUNTERS];
63 int active_events;
64 enum cpuhp_state cpuhp_state;
65 const struct imx_ddr_devtype_data *devtype_data;
66 int irq;
67 int id;
68};
69
70static const struct imx_ddr_devtype_data imx93_devtype_data = {
71 .identifier = "imx93",
72};
73
74static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
75 {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
76 { /* sentinel */ }
77};
78MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
79
80static ssize_t ddr_perf_identifier_show(struct device *dev,
81 struct device_attribute *attr,
82 char *page)
83{
84 struct ddr_pmu *pmu = dev_get_drvdata(dev);
85
86 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier);
87}
88
89static struct device_attribute ddr_perf_identifier_attr =
90 __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
91
92static struct attribute *ddr_perf_identifier_attrs[] = {
93 &ddr_perf_identifier_attr.attr,
94 NULL,
95};
96
97static struct attribute_group ddr_perf_identifier_attr_group = {
98 .attrs = ddr_perf_identifier_attrs,
99};
100
101static ssize_t ddr_perf_cpumask_show(struct device *dev,
102 struct device_attribute *attr, char *buf)
103{
104 struct ddr_pmu *pmu = dev_get_drvdata(dev);
105
106 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
107}
108
109static struct device_attribute ddr_perf_cpumask_attr =
110 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
111
112static struct attribute *ddr_perf_cpumask_attrs[] = {
113 &ddr_perf_cpumask_attr.attr,
114 NULL,
115};
116
117static const struct attribute_group ddr_perf_cpumask_attr_group = {
118 .attrs = ddr_perf_cpumask_attrs,
119};
120
121static ssize_t ddr_pmu_event_show(struct device *dev,
122 struct device_attribute *attr, char *page)
123{
124 struct perf_pmu_events_attr *pmu_attr;
125
126 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
127 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
128}
129
130#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \
131 (&((struct perf_pmu_events_attr[]) { \
132 { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
133 .id = _id, } \
134 })[0].attr.attr)
135
136static struct attribute *ddr_perf_events_attrs[] = {
137 /* counter0 cycles event */
138 IMX9_DDR_PMU_EVENT_ATTR(cycles, 0),
139
140 /* reference events for all normal counters, need assert DEBUG19[21] bit */
141 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ddrc1_rmw_for_ecc, 12),
142 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_rreorder, 13),
143 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_wreorder, 14),
144 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_0, 15),
145 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_1, 16),
146 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_2, 17),
147 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_3, 18),
148 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_4, 19),
149 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_5, 22),
150 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_6, 23),
151 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_7, 24),
152 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_8, 25),
153 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_9, 26),
154 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_10, 27),
155 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_11, 28),
156 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_12, 31),
157 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_13, 59),
158 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_15, 61),
159 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_29, 63),
160
161 /* counter1 specific events */
162 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, 64),
163 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, 65),
164 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, 66),
165 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, 67),
166 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, 68),
167 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, 69),
168 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, 70),
169 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, 71),
170
171 /* counter2 specific events */
172 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, 64),
173 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, 65),
174 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, 66),
175 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, 67),
176 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, 68),
177 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, 69),
178 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70),
179 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71),
180 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72),
181 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
182
183 /* counter3 specific events */
184 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64),
185 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, 65),
186 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, 66),
187 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, 67),
188 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, 68),
189 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, 69),
190 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70),
191 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71),
192 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72),
193 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
194
195 /* counter4 specific events */
196 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64),
197 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, 65),
198 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, 66),
199 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, 67),
200 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, 68),
201 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, 69),
202 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70),
203 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71),
204 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72),
205 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
206
207 /* counter5 specific events */
208 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64),
209 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, 65),
210 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, 66),
211 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, 67),
212 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, 68),
213 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, 69),
214 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, 70),
215 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, 71),
216 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, 72),
217
218 /* counter6 specific events */
219 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, 64),
220 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, 72),
221
222 /* counter7 specific events */
223 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, 64),
224 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, 65),
225
226 /* counter8 specific events */
227 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, 64),
228 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, 65),
229
230 /* counter9 specific events */
231 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, 65),
232 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, 66),
233
234 /* counter10 specific events */
235 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, 65),
236 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, 66),
237 NULL,
238};
239
240static const struct attribute_group ddr_perf_events_attr_group = {
241 .name = "events",
242 .attrs = ddr_perf_events_attrs,
243};
244
245PMU_FORMAT_ATTR(event, "config:0-7");
246PMU_FORMAT_ATTR(counter, "config:8-15");
247PMU_FORMAT_ATTR(axi_id, "config1:0-17");
248PMU_FORMAT_ATTR(axi_mask, "config2:0-17");
249
250static struct attribute *ddr_perf_format_attrs[] = {
251 &format_attr_event.attr,
252 &format_attr_counter.attr,
253 &format_attr_axi_id.attr,
254 &format_attr_axi_mask.attr,
255 NULL,
256};
257
258static const struct attribute_group ddr_perf_format_attr_group = {
259 .name = "format",
260 .attrs = ddr_perf_format_attrs,
261};
262
263static const struct attribute_group *attr_groups[] = {
264 &ddr_perf_identifier_attr_group,
265 &ddr_perf_cpumask_attr_group,
266 &ddr_perf_events_attr_group,
267 &ddr_perf_format_attr_group,
268 NULL,
269};
270
271static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter)
272{
273 if (counter == CYCLES_COUNTER) {
274 writel(0, pmu->base + PMC(counter) + 0x4);
275 writel(0, pmu->base + PMC(counter));
276 } else {
277 writel(0, pmu->base + PMC(counter));
278 }
279}
280
281static u64 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
282{
283 u32 val_lower, val_upper;
284 u64 val;
285
286 if (counter != CYCLES_COUNTER) {
287 val = readl_relaxed(pmu->base + PMC(counter));
288 goto out;
289 }
290
291 /* special handling for reading 64bit cycle counter */
292 do {
293 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4);
294 val_lower = readl_relaxed(pmu->base + PMC(counter));
295 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4));
296
297 val = val_upper;
298 val = (val << 32);
299 val |= val_lower;
300out:
301 return val;
302}
303
304static void ddr_perf_counter_global_config(struct ddr_pmu *pmu, bool enable)
305{
306 u32 ctrl;
307
308 ctrl = readl_relaxed(pmu->base + PMGC0);
309
310 if (enable) {
311 /*
312 * The performance monitor must be reset before event counting
313 * sequences. The performance monitor can be reset by first freezing
314 * one or more counters and then clearing the freeze condition to
315 * allow the counters to count according to the settings in the
316 * performance monitor registers. Counters can be frozen individually
317 * by setting PMLCAn[FC] bits, or simultaneously by setting PMGC0[FAC].
318 * Simply clearing these freeze bits will then allow the performance
319 * monitor to begin counting based on the register settings.
320 */
321 ctrl |= PMGC0_FAC;
322 writel(ctrl, pmu->base + PMGC0);
323
324 /*
325 * Freeze all counters disabled, interrupt enabled, and freeze
326 * counters on condition enabled.
327 */
328 ctrl &= ~PMGC0_FAC;
329 ctrl |= PMGC0_PMIE | PMGC0_FCECE;
330 writel(ctrl, pmu->base + PMGC0);
331 } else {
332 ctrl |= PMGC0_FAC;
333 ctrl &= ~(PMGC0_PMIE | PMGC0_FCECE);
334 writel(ctrl, pmu->base + PMGC0);
335 }
336}
337
338static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
339 int counter, bool enable)
340{
341 u32 ctrl_a;
342
343 ctrl_a = readl_relaxed(pmu->base + PMLCA(counter));
344
345 if (enable) {
346 ctrl_a |= PMLCA_FC;
347 writel(ctrl_a, pmu->base + PMLCA(counter));
348
349 ddr_perf_clear_counter(pmu, counter);
350
351 /* Freeze counter disabled, condition enabled, and program event.*/
352 ctrl_a &= ~PMLCA_FC;
353 ctrl_a |= PMLCA_CE;
354 ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F);
355 ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF));
356 writel(ctrl_a, pmu->base + PMLCA(counter));
357 } else {
358 /* Freeze counter. */
359 ctrl_a |= PMLCA_FC;
360 writel(ctrl_a, pmu->base + PMLCA(counter));
361 }
362}
363
364static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2)
365{
366 u32 pmcfg1, pmcfg2;
367 int event, counter;
368
369 event = cfg & 0x000000FF;
370 counter = (cfg & 0x0000FF00) >> 8;
371
372 pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
373
374 if (counter == 2 && event == 73)
375 pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN;
376 else if (counter == 2 && event != 73)
377 pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN;
378
379 if (counter == 3 && event == 73)
380 pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN;
381 else if (counter == 3 && event != 73)
382 pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN;
383
384 if (counter == 4 && event == 73)
385 pmcfg1 |= PMCFG1_RD_BT_FILT_EN;
386 else if (counter == 4 && event != 73)
387 pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN;
388
389 pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
390 pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2);
391 writel(pmcfg1, pmu->base + PMCFG1);
392
393 pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
394 pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
395 pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1);
396 writel(pmcfg2, pmu->base + PMCFG2);
397}
398
399static void ddr_perf_event_update(struct perf_event *event)
400{
401 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
402 struct hw_perf_event *hwc = &event->hw;
403 int counter = hwc->idx;
404 u64 new_raw_count;
405
406 new_raw_count = ddr_perf_read_counter(pmu, counter);
407 local64_add(new_raw_count, &event->count);
408
409 /* clear counter's value every time */
410 ddr_perf_clear_counter(pmu, counter);
411}
412
413static int ddr_perf_event_init(struct perf_event *event)
414{
415 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
416 struct hw_perf_event *hwc = &event->hw;
417 struct perf_event *sibling;
418
419 if (event->attr.type != event->pmu->type)
420 return -ENOENT;
421
422 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
423 return -EOPNOTSUPP;
424
425 if (event->cpu < 0) {
426 dev_warn(pmu->dev, "Can't provide per-task data!\n");
427 return -EOPNOTSUPP;
428 }
429
430 /*
431 * We must NOT create groups containing mixed PMUs, although software
432 * events are acceptable (for example to create a CCN group
433 * periodically read when a hrtimer aka cpu-clock leader triggers).
434 */
435 if (event->group_leader->pmu != event->pmu &&
436 !is_software_event(event->group_leader))
437 return -EINVAL;
438
439 for_each_sibling_event(sibling, event->group_leader) {
440 if (sibling->pmu != event->pmu &&
441 !is_software_event(sibling))
442 return -EINVAL;
443 }
444
445 event->cpu = pmu->cpu;
446 hwc->idx = -1;
447
448 return 0;
449}
450
451static void ddr_perf_event_start(struct perf_event *event, int flags)
452{
453 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
454 struct hw_perf_event *hwc = &event->hw;
455 int counter = hwc->idx;
456
457 local64_set(&hwc->prev_count, 0);
458
459 ddr_perf_counter_local_config(pmu, event->attr.config, counter, true);
460 hwc->state = 0;
461}
462
463static int ddr_perf_event_add(struct perf_event *event, int flags)
464{
465 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
466 struct hw_perf_event *hwc = &event->hw;
467 int cfg = event->attr.config;
468 int cfg1 = event->attr.config1;
469 int cfg2 = event->attr.config2;
470 int counter;
471
472 counter = (cfg & 0x0000FF00) >> 8;
473
474 pmu->events[counter] = event;
475 pmu->active_events++;
476 hwc->idx = counter;
477 hwc->state |= PERF_HES_STOPPED;
478
479 if (flags & PERF_EF_START)
480 ddr_perf_event_start(event, flags);
481
482 /* read trans, write trans, read beat */
483 ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
484
485 return 0;
486}
487
488static void ddr_perf_event_stop(struct perf_event *event, int flags)
489{
490 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
491 struct hw_perf_event *hwc = &event->hw;
492 int counter = hwc->idx;
493
494 ddr_perf_counter_local_config(pmu, event->attr.config, counter, false);
495 ddr_perf_event_update(event);
496
497 hwc->state |= PERF_HES_STOPPED;
498}
499
500static void ddr_perf_event_del(struct perf_event *event, int flags)
501{
502 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
503 struct hw_perf_event *hwc = &event->hw;
504
505 ddr_perf_event_stop(event, PERF_EF_UPDATE);
506
507 pmu->active_events--;
508 hwc->idx = -1;
509}
510
511static void ddr_perf_pmu_enable(struct pmu *pmu)
512{
513 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
514
515 ddr_perf_counter_global_config(ddr_pmu, true);
516}
517
518static void ddr_perf_pmu_disable(struct pmu *pmu)
519{
520 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
521
522 ddr_perf_counter_global_config(ddr_pmu, false);
523}
524
525static void ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
526 struct device *dev)
527{
528 *pmu = (struct ddr_pmu) {
529 .pmu = (struct pmu) {
530 .module = THIS_MODULE,
531 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
532 .task_ctx_nr = perf_invalid_context,
533 .attr_groups = attr_groups,
534 .event_init = ddr_perf_event_init,
535 .add = ddr_perf_event_add,
536 .del = ddr_perf_event_del,
537 .start = ddr_perf_event_start,
538 .stop = ddr_perf_event_stop,
539 .read = ddr_perf_event_update,
540 .pmu_enable = ddr_perf_pmu_enable,
541 .pmu_disable = ddr_perf_pmu_disable,
542 },
543 .base = base,
544 .dev = dev,
545 };
546}
547
548static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
549{
550 struct ddr_pmu *pmu = (struct ddr_pmu *)p;
551 struct perf_event *event;
552 int i;
553
554 /*
555 * Counters can generate an interrupt on an overflow when msb of a
556 * counter changes from 0 to 1. For the interrupt to be signalled,
557 * below condition mush be satisfied:
558 * PMGC0[PMIE] = 1, PMGC0[FCECE] = 1, PMLCAn[CE] = 1
559 * When an interrupt is signalled, PMGC0[FAC] is set by hardware and
560 * all of the registers are frozen.
561 * Software can clear the interrupt condition by resetting the performance
562 * monitor and clearing the most significant bit of the counter that
563 * generate the overflow.
564 */
565 for (i = 0; i < NUM_COUNTERS; i++) {
566 if (!pmu->events[i])
567 continue;
568
569 event = pmu->events[i];
570
571 ddr_perf_event_update(event);
572 }
573
574 ddr_perf_counter_global_config(pmu, true);
575
576 return IRQ_HANDLED;
577}
578
579static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
580{
581 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
582 int target;
583
584 if (cpu != pmu->cpu)
585 return 0;
586
587 target = cpumask_any_but(cpu_online_mask, cpu);
588 if (target >= nr_cpu_ids)
589 return 0;
590
591 perf_pmu_migrate_context(&pmu->pmu, cpu, target);
592 pmu->cpu = target;
593
594 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)));
595
596 return 0;
597}
598
599static int ddr_perf_probe(struct platform_device *pdev)
600{
601 struct ddr_pmu *pmu;
602 void __iomem *base;
603 int ret, irq;
604 char *name;
605
606 base = devm_platform_ioremap_resource(pdev, 0);
607 if (IS_ERR(base))
608 return PTR_ERR(base);
609
610 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
611 if (!pmu)
612 return -ENOMEM;
613
614 ddr_perf_init(pmu, base, &pdev->dev);
615
616 pmu->devtype_data = of_device_get_match_data(&pdev->dev);
617
618 platform_set_drvdata(pdev, pmu);
619
620 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL);
621 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", pmu->id);
622 if (!name) {
623 ret = -ENOMEM;
624 goto format_string_err;
625 }
626
627 pmu->cpu = raw_smp_processor_id();
628 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DDR_CPUHP_CB_NAME,
629 NULL, ddr_perf_offline_cpu);
630 if (ret < 0) {
631 dev_err(&pdev->dev, "Failed to add callbacks for multi state\n");
632 goto cpuhp_state_err;
633 }
634 pmu->cpuhp_state = ret;
635
636 /* Register the pmu instance for cpu hotplug */
637 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
638 if (ret) {
639 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
640 goto cpuhp_instance_err;
641 }
642
643 /* Request irq */
644 irq = platform_get_irq(pdev, 0);
645 if (irq < 0) {
646 ret = irq;
647 goto ddr_perf_err;
648 }
649
650 ret = devm_request_irq(&pdev->dev, irq, ddr_perf_irq_handler,
651 IRQF_NOBALANCING | IRQF_NO_THREAD,
652 DDR_CPUHP_CB_NAME, pmu);
653 if (ret < 0) {
654 dev_err(&pdev->dev, "Request irq failed: %d", ret);
655 goto ddr_perf_err;
656 }
657
658 pmu->irq = irq;
659 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu));
660 if (ret) {
661 dev_err(pmu->dev, "Failed to set interrupt affinity\n");
662 goto ddr_perf_err;
663 }
664
665 ret = perf_pmu_register(&pmu->pmu, name, -1);
666 if (ret)
667 goto ddr_perf_err;
668
669 return 0;
670
671ddr_perf_err:
672 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
673cpuhp_instance_err:
674 cpuhp_remove_multi_state(pmu->cpuhp_state);
675cpuhp_state_err:
676format_string_err:
677 ida_free(&ddr_ida, pmu->id);
678 dev_warn(&pdev->dev, "i.MX9 DDR Perf PMU failed (%d), disabled\n", ret);
679 return ret;
680}
681
682static int ddr_perf_remove(struct platform_device *pdev)
683{
684 struct ddr_pmu *pmu = platform_get_drvdata(pdev);
685
686 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
687 cpuhp_remove_multi_state(pmu->cpuhp_state);
688
689 perf_pmu_unregister(&pmu->pmu);
690
691 ida_free(&ddr_ida, pmu->id);
692
693 return 0;
694}
695
696static struct platform_driver imx_ddr_pmu_driver = {
697 .driver = {
698 .name = "imx9-ddr-pmu",
699 .of_match_table = imx_ddr_pmu_dt_ids,
700 .suppress_bind_attrs = true,
701 },
702 .probe = ddr_perf_probe,
703 .remove = ddr_perf_remove,
704};
705module_platform_driver(imx_ddr_pmu_driver);
706
707MODULE_AUTHOR("Xu Yang <xu.yang_2@nxp.com>");
708MODULE_LICENSE("GPL v2");
709MODULE_DESCRIPTION("DDRC PerfMon for i.MX9 SoCs");