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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Motorcomm 8511/8521/8531/8531S/8821 PHY driver.
4 *
5 * Author: Peter Geis <pgwipeout@gmail.com>
6 * Author: Frank <Frank.Sae@motor-comm.com>
7 */
8
9#include <linux/etherdevice.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/phy.h>
13#include <linux/of.h>
14
15#define PHY_ID_YT8511 0x0000010a
16#define PHY_ID_YT8521 0x0000011a
17#define PHY_ID_YT8531 0x4f51e91b
18#define PHY_ID_YT8531S 0x4f51e91a
19#define PHY_ID_YT8821 0x4f51ea19
20/* YT8521/YT8531S/YT8821 Register Overview
21 * UTP Register space | FIBER Register space
22 * ------------------------------------------------------------
23 * | UTP MII | FIBER MII |
24 * | UTP MMD | |
25 * | UTP Extended | FIBER Extended |
26 * ------------------------------------------------------------
27 * | Common Extended |
28 * ------------------------------------------------------------
29 */
30
31/* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */
32
33/* Specific Function Control Register */
34#define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10
35
36/* 2b00 Manual MDI configuration
37 * 2b01 Manual MDIX configuration
38 * 2b10 Reserved
39 * 2b11 Enable automatic crossover for all modes *default*
40 */
41#define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5))
42#define YTPHY_SFCR_CROSSOVER_EN BIT(3)
43#define YTPHY_SFCR_SQE_TEST_EN BIT(2)
44#define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1)
45#define YTPHY_SFCR_JABBER_DIS BIT(0)
46
47/* Specific Status Register */
48#define YTPHY_SPECIFIC_STATUS_REG 0x11
49#define YTPHY_SSR_SPEED_MASK ((0x3 << 14) | BIT(9))
50#define YTPHY_SSR_SPEED_10M ((0x0 << 14))
51#define YTPHY_SSR_SPEED_100M ((0x1 << 14))
52#define YTPHY_SSR_SPEED_1000M ((0x2 << 14))
53#define YTPHY_SSR_SPEED_10G ((0x3 << 14))
54#define YTPHY_SSR_SPEED_2500M ((0x0 << 14) | BIT(9))
55#define YTPHY_SSR_DUPLEX_OFFSET 13
56#define YTPHY_SSR_DUPLEX BIT(13)
57#define YTPHY_SSR_PAGE_RECEIVED BIT(12)
58#define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11)
59#define YTPHY_SSR_LINK BIT(10)
60#define YTPHY_SSR_MDIX_CROSSOVER BIT(6)
61#define YTPHY_SSR_DOWNGRADE BIT(5)
62#define YTPHY_SSR_TRANSMIT_PAUSE BIT(3)
63#define YTPHY_SSR_RECEIVE_PAUSE BIT(2)
64#define YTPHY_SSR_POLARITY BIT(1)
65#define YTPHY_SSR_JABBER BIT(0)
66
67/* Interrupt enable Register */
68#define YTPHY_INTERRUPT_ENABLE_REG 0x12
69#define YTPHY_IER_WOL BIT(6)
70
71/* Interrupt Status Register */
72#define YTPHY_INTERRUPT_STATUS_REG 0x13
73#define YTPHY_ISR_AUTONEG_ERR BIT(15)
74#define YTPHY_ISR_SPEED_CHANGED BIT(14)
75#define YTPHY_ISR_DUPLEX_CHANGED BIT(13)
76#define YTPHY_ISR_PAGE_RECEIVED BIT(12)
77#define YTPHY_ISR_LINK_FAILED BIT(11)
78#define YTPHY_ISR_LINK_SUCCESSED BIT(10)
79#define YTPHY_ISR_WOL BIT(6)
80#define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5)
81#define YTPHY_ISR_SERDES_LINK_FAILED BIT(3)
82#define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2)
83#define YTPHY_ISR_POLARITY_CHANGED BIT(1)
84#define YTPHY_ISR_JABBER_HAPPENED BIT(0)
85
86/* Speed Auto Downgrade Control Register */
87#define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14
88#define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5)
89
90/* If these bits are set to 3, the PHY attempts five times ( 3(set value) +
91 * additional 2) before downgrading, default 0x3
92 */
93#define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2)
94
95/* Rx Error Counter Register */
96#define YTPHY_RX_ERROR_COUNTER_REG 0x15
97
98/* Extended Register's Address Offset Register */
99#define YTPHY_PAGE_SELECT 0x1E
100
101/* Extended Register's Data Register */
102#define YTPHY_PAGE_DATA 0x1F
103
104/* FIBER Auto-Negotiation link partner ability */
105#define YTPHY_FLPA_PAUSE (0x3 << 7)
106#define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7)
107
108#define YT8511_PAGE_SELECT 0x1e
109#define YT8511_PAGE 0x1f
110#define YT8511_EXT_CLK_GATE 0x0c
111#define YT8511_EXT_DELAY_DRIVE 0x0d
112#define YT8511_EXT_SLEEP_CTRL 0x27
113
114/* 2b00 25m from pll
115 * 2b01 25m from xtl *default*
116 * 2b10 62.m from pll
117 * 2b11 125m from pll
118 */
119#define YT8511_CLK_125M (BIT(2) | BIT(1))
120#define YT8511_PLLON_SLP BIT(14)
121
122/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
123#define YT8511_DELAY_RX BIT(0)
124
125/* TX Gig-E Delay is bits 7:4, default 0x5
126 * TX Fast-E Delay is bits 15:12, default 0xf
127 * Delay = 150ps * N - 250ps
128 * On = 2000ps, off = 50ps
129 */
130#define YT8511_DELAY_GE_TX_EN (0xf << 4)
131#define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
132#define YT8511_DELAY_FE_TX_EN (0xf << 12)
133#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
134
135/* Extended register is different from MMD Register and MII Register.
136 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to
137 * operate extended register.
138 * Extended Register start
139 */
140
141/* Phy gmii clock gating Register */
142#define YT8521_CLOCK_GATING_REG 0xC
143#define YT8521_CGR_RX_CLK_EN BIT(12)
144
145#define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27
146#define YT8521_ESC1R_SLEEP_SW BIT(15)
147#define YT8521_ESC1R_PLLON_SLP BIT(14)
148
149/* Phy fiber Link timer cfg2 Register */
150#define YT8521_LINK_TIMER_CFG2_REG 0xA5
151#define YT8521_LTCR_EN_AUTOSEN BIT(15)
152
153/* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers
154 * of yt8521 phy. There is no need to switch reg space when operating these
155 * registers.
156 */
157
158#define YT8521_REG_SPACE_SELECT_REG 0xA000
159#define YT8521_RSSR_SPACE_MASK BIT(1)
160#define YT8521_RSSR_FIBER_SPACE (0x1 << 1)
161#define YT8521_RSSR_UTP_SPACE (0x0 << 1)
162#define YT8521_RSSR_TO_BE_ARBITRATED (0xFF)
163
164#define YT8521_CHIP_CONFIG_REG 0xA001
165#define YT8521_CCR_SW_RST BIT(15)
166#define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4)
167#define YT8531_LDO_VOL_3V3 0x0
168#define YT8531_LDO_VOL_1V8 0x2
169
170/* 1b0 disable 1.9ns rxc clock delay *default*
171 * 1b1 enable 1.9ns rxc clock delay
172 */
173#define YT8521_CCR_RXC_DLY_EN BIT(8)
174#define YT8521_CCR_RXC_DLY_1_900_NS 1900
175
176#define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0))
177#define YT8521_CCR_MODE_UTP_TO_RGMII 0
178#define YT8521_CCR_MODE_FIBER_TO_RGMII 1
179#define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2
180#define YT8521_CCR_MODE_UTP_TO_SGMII 3
181#define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4
182#define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5
183#define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6
184#define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7
185
186/* 3 phy polling modes,poll mode combines utp and fiber mode*/
187#define YT8521_MODE_FIBER 0x1
188#define YT8521_MODE_UTP 0x2
189#define YT8521_MODE_POLL 0x3
190
191#define YT8521_RGMII_CONFIG1_REG 0xA003
192/* 1b0 use original tx_clk_rgmii *default*
193 * 1b1 use inverted tx_clk_rgmii.
194 */
195#define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14)
196#define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10)
197#define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4)
198#define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0)
199#define YT8521_RC1R_RGMII_0_000_NS 0
200#define YT8521_RC1R_RGMII_0_150_NS 1
201#define YT8521_RC1R_RGMII_0_300_NS 2
202#define YT8521_RC1R_RGMII_0_450_NS 3
203#define YT8521_RC1R_RGMII_0_600_NS 4
204#define YT8521_RC1R_RGMII_0_750_NS 5
205#define YT8521_RC1R_RGMII_0_900_NS 6
206#define YT8521_RC1R_RGMII_1_050_NS 7
207#define YT8521_RC1R_RGMII_1_200_NS 8
208#define YT8521_RC1R_RGMII_1_350_NS 9
209#define YT8521_RC1R_RGMII_1_500_NS 10
210#define YT8521_RC1R_RGMII_1_650_NS 11
211#define YT8521_RC1R_RGMII_1_800_NS 12
212#define YT8521_RC1R_RGMII_1_950_NS 13
213#define YT8521_RC1R_RGMII_2_100_NS 14
214#define YT8521_RC1R_RGMII_2_250_NS 15
215
216#define YTPHY_MISC_CONFIG_REG 0xA006
217#define YTPHY_MCR_FIBER_SPEED_MASK BIT(0)
218#define YTPHY_MCR_FIBER_1000BX (0x1 << 0)
219#define YTPHY_MCR_FIBER_100FX (0x0 << 0)
220
221/* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */
222#define YTPHY_WOL_MACADDR2_REG 0xA007
223#define YTPHY_WOL_MACADDR1_REG 0xA008
224#define YTPHY_WOL_MACADDR0_REG 0xA009
225
226#define YTPHY_WOL_CONFIG_REG 0xA00A
227#define YTPHY_WCR_INTR_SEL BIT(6)
228#define YTPHY_WCR_ENABLE BIT(3)
229
230/* 2b00 84ms
231 * 2b01 168ms *default*
232 * 2b10 336ms
233 * 2b11 672ms
234 */
235#define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1))
236#define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1))
237
238/* 1b0 Interrupt and WOL events is level triggered and active LOW *default*
239 * 1b1 Interrupt and WOL events is pulse triggered and active LOW
240 */
241#define YTPHY_WCR_TYPE_PULSE BIT(0)
242
243#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010
244#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13)
245#define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */
246#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */
247#define YT8531_RGMII_RX_DS_DEFAULT 0x3
248
249#define YTPHY_SYNCE_CFG_REG 0xA012
250#define YT8521_SCR_SYNCE_ENABLE BIT(5)
251/* 1b0 output 25m clock
252 * 1b1 output 125m clock *default*
253 */
254#define YT8521_SCR_CLK_FRE_SEL_125M BIT(3)
255#define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1)
256#define YT8521_SCR_CLK_SRC_PLL_125M 0
257#define YT8521_SCR_CLK_SRC_UTP_RX 1
258#define YT8521_SCR_CLK_SRC_SDS_RX 2
259#define YT8521_SCR_CLK_SRC_REF_25M 3
260#define YT8531_SCR_SYNCE_ENABLE BIT(6)
261/* 1b0 output 25m clock *default*
262 * 1b1 output 125m clock
263 */
264#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4)
265#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1)
266#define YT8531_SCR_CLK_SRC_PLL_125M 0
267#define YT8531_SCR_CLK_SRC_UTP_RX 1
268#define YT8531_SCR_CLK_SRC_SDS_RX 2
269#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3
270#define YT8531_SCR_CLK_SRC_REF_25M 4
271#define YT8531_SCR_CLK_SRC_SSC_25M 5
272
273#define YT8821_SDS_EXT_CSR_CTRL_REG 0x23
274#define YT8821_SDS_EXT_CSR_VCO_LDO_EN BIT(15)
275#define YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN BIT(8)
276
277#define YT8821_UTP_EXT_PI_CTRL_REG 0x56
278#define YT8821_UTP_EXT_PI_RST_N_FIFO BIT(5)
279#define YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE BIT(4)
280#define YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE BIT(3)
281#define YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE BIT(2)
282#define YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE BIT(1)
283#define YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE BIT(0)
284
285#define YT8821_UTP_EXT_VCT_CFG6_CTRL_REG 0x97
286#define YT8821_UTP_EXT_FECHO_AMP_TH_HUGE GENMASK(15, 8)
287
288#define YT8821_UTP_EXT_ECHO_CTRL_REG 0x336
289#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000 GENMASK(14, 8)
290
291#define YT8821_UTP_EXT_GAIN_CTRL_REG 0x340
292#define YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000 GENMASK(6, 0)
293
294#define YT8821_UTP_EXT_RPDN_CTRL_REG 0x34E
295#define YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 BIT(15)
296#define YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 BIT(7)
297#define YT8821_UTP_EXT_RPDN_IPR_SHT_2500 GENMASK(6, 0)
298
299#define YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG 0x36A
300#define YT8821_UTP_EXT_TH_20DB_2500 GENMASK(15, 0)
301
302#define YT8821_UTP_EXT_TRACE_CTRL_REG 0x372
303#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 GENMASK(14, 8)
304#define YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500 GENMASK(6, 0)
305
306#define YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG 0x374
307#define YT8821_UTP_EXT_ALPHA_SHT_2500 GENMASK(14, 8)
308#define YT8821_UTP_EXT_IPR_LNG_2500 GENMASK(6, 0)
309
310#define YT8821_UTP_EXT_PLL_CTRL_REG 0x450
311#define YT8821_UTP_EXT_PLL_SPARE_CFG GENMASK(7, 0)
312
313#define YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG 0x466
314#define YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG GENMASK(14, 8)
315#define YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG GENMASK(6, 0)
316
317#define YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG 0x467
318#define YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG GENMASK(14, 8)
319#define YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG GENMASK(6, 0)
320
321#define YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG 0x468
322#define YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG GENMASK(14, 8)
323#define YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG GENMASK(6, 0)
324
325#define YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG 0x469
326#define YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG GENMASK(14, 8)
327#define YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG GENMASK(6, 0)
328
329#define YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG 0x4B3
330#define YT8821_UTP_EXT_MU_COARSE_FR_F_FFE GENMASK(14, 12)
331#define YT8821_UTP_EXT_MU_COARSE_FR_F_FBE GENMASK(10, 8)
332
333#define YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG 0x4B5
334#define YT8821_UTP_EXT_MU_FINE_FR_F_FFE GENMASK(14, 12)
335#define YT8821_UTP_EXT_MU_FINE_FR_F_FBE GENMASK(10, 8)
336
337#define YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG 0x4D2
338#define YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER GENMASK(7, 4)
339#define YT8821_UTP_EXT_VGA_LPF1_CAP_2500 GENMASK(3, 0)
340
341#define YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG 0x4D3
342#define YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER GENMASK(7, 4)
343#define YT8821_UTP_EXT_VGA_LPF2_CAP_2500 GENMASK(3, 0)
344
345#define YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG 0x660
346#define YT8821_UTP_EXT_NFR_TX_ABILITY BIT(3)
347/* Extended Register end */
348
349#define YTPHY_DTS_OUTPUT_CLK_DIS 0
350#define YTPHY_DTS_OUTPUT_CLK_25M 25000000
351#define YTPHY_DTS_OUTPUT_CLK_125M 125000000
352
353#define YT8821_CHIP_MODE_AUTO_BX2500_SGMII 0
354#define YT8821_CHIP_MODE_FORCE_BX2500 1
355
356struct yt8521_priv {
357 /* combo_advertising is used for case of YT8521 in combo mode,
358 * this means that yt8521 may work in utp or fiber mode which depends
359 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED).
360 */
361 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising);
362
363 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/
364 u8 polling_mode;
365 u8 strap_mode; /* 8 working modes */
366 /* current reg page of yt8521 phy:
367 * YT8521_RSSR_UTP_SPACE
368 * YT8521_RSSR_FIBER_SPACE
369 * YT8521_RSSR_TO_BE_ARBITRATED
370 */
371 u8 reg_page;
372};
373
374/**
375 * ytphy_read_ext() - read a PHY's extended register
376 * @phydev: a pointer to a &struct phy_device
377 * @regnum: register number to read
378 *
379 * NOTE:The caller must have taken the MDIO bus lock.
380 *
381 * returns the value of regnum reg or negative error code
382 */
383static int ytphy_read_ext(struct phy_device *phydev, u16 regnum)
384{
385 int ret;
386
387 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
388 if (ret < 0)
389 return ret;
390
391 return __phy_read(phydev, YTPHY_PAGE_DATA);
392}
393
394/**
395 * ytphy_read_ext_with_lock() - read a PHY's extended register
396 * @phydev: a pointer to a &struct phy_device
397 * @regnum: register number to read
398 *
399 * returns the value of regnum reg or negative error code
400 */
401static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum)
402{
403 int ret;
404
405 phy_lock_mdio_bus(phydev);
406 ret = ytphy_read_ext(phydev, regnum);
407 phy_unlock_mdio_bus(phydev);
408
409 return ret;
410}
411
412/**
413 * ytphy_write_ext() - write a PHY's extended register
414 * @phydev: a pointer to a &struct phy_device
415 * @regnum: register number to write
416 * @val: value to write to @regnum
417 *
418 * NOTE:The caller must have taken the MDIO bus lock.
419 *
420 * returns 0 or negative error code
421 */
422static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val)
423{
424 int ret;
425
426 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
427 if (ret < 0)
428 return ret;
429
430 return __phy_write(phydev, YTPHY_PAGE_DATA, val);
431}
432
433/**
434 * ytphy_write_ext_with_lock() - write a PHY's extended register
435 * @phydev: a pointer to a &struct phy_device
436 * @regnum: register number to write
437 * @val: value to write to @regnum
438 *
439 * returns 0 or negative error code
440 */
441static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum,
442 u16 val)
443{
444 int ret;
445
446 phy_lock_mdio_bus(phydev);
447 ret = ytphy_write_ext(phydev, regnum, val);
448 phy_unlock_mdio_bus(phydev);
449
450 return ret;
451}
452
453/**
454 * ytphy_modify_ext() - bits modify a PHY's extended register
455 * @phydev: a pointer to a &struct phy_device
456 * @regnum: register number to write
457 * @mask: bit mask of bits to clear
458 * @set: bit mask of bits to set
459 *
460 * NOTE: Convenience function which allows a PHY's extended register to be
461 * modified as new register value = (old register value & ~mask) | set.
462 * The caller must have taken the MDIO bus lock.
463 *
464 * returns 0 or negative error code
465 */
466static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
467 u16 set)
468{
469 int ret;
470
471 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
472 if (ret < 0)
473 return ret;
474
475 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set);
476}
477
478/**
479 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register
480 * @phydev: a pointer to a &struct phy_device
481 * @regnum: register number to write
482 * @mask: bit mask of bits to clear
483 * @set: bit mask of bits to set
484 *
485 * NOTE: Convenience function which allows a PHY's extended register to be
486 * modified as new register value = (old register value & ~mask) | set.
487 *
488 * returns 0 or negative error code
489 */
490static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum,
491 u16 mask, u16 set)
492{
493 int ret;
494
495 phy_lock_mdio_bus(phydev);
496 ret = ytphy_modify_ext(phydev, regnum, mask, set);
497 phy_unlock_mdio_bus(phydev);
498
499 return ret;
500}
501
502/**
503 * ytphy_get_wol() - report whether wake-on-lan is enabled
504 * @phydev: a pointer to a &struct phy_device
505 * @wol: a pointer to a &struct ethtool_wolinfo
506 *
507 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg.
508 */
509static void ytphy_get_wol(struct phy_device *phydev,
510 struct ethtool_wolinfo *wol)
511{
512 int wol_config;
513
514 wol->supported = WAKE_MAGIC;
515 wol->wolopts = 0;
516
517 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
518 if (wol_config < 0)
519 return;
520
521 if (wol_config & YTPHY_WCR_ENABLE)
522 wol->wolopts |= WAKE_MAGIC;
523}
524
525/**
526 * ytphy_set_wol() - turn wake-on-lan on or off
527 * @phydev: a pointer to a &struct phy_device
528 * @wol: a pointer to a &struct ethtool_wolinfo
529 *
530 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG
531 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The
532 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register.
533 *
534 * returns 0 or negative errno code
535 */
536static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
537{
538 struct net_device *p_attached_dev;
539 const u16 mac_addr_reg[] = {
540 YTPHY_WOL_MACADDR2_REG,
541 YTPHY_WOL_MACADDR1_REG,
542 YTPHY_WOL_MACADDR0_REG,
543 };
544 const u8 *mac_addr;
545 int old_page;
546 int ret = 0;
547 u16 mask;
548 u16 val;
549 u8 i;
550
551 if (wol->wolopts & WAKE_MAGIC) {
552 p_attached_dev = phydev->attached_dev;
553 if (!p_attached_dev)
554 return -ENODEV;
555
556 mac_addr = (const u8 *)p_attached_dev->dev_addr;
557 if (!is_valid_ether_addr(mac_addr))
558 return -EINVAL;
559
560 /* lock mdio bus then switch to utp reg space */
561 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
562 if (old_page < 0)
563 goto err_restore_page;
564
565 /* Store the device address for the magic packet */
566 for (i = 0; i < 3; i++) {
567 ret = ytphy_write_ext(phydev, mac_addr_reg[i],
568 ((mac_addr[i * 2] << 8)) |
569 (mac_addr[i * 2 + 1]));
570 if (ret < 0)
571 goto err_restore_page;
572 }
573
574 /* Enable WOL feature */
575 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
576 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
577 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
578 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val);
579 if (ret < 0)
580 goto err_restore_page;
581
582 /* Enable WOL interrupt */
583 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
584 YTPHY_IER_WOL);
585 if (ret < 0)
586 goto err_restore_page;
587
588 } else {
589 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
590 if (old_page < 0)
591 goto err_restore_page;
592
593 /* Disable WOL feature */
594 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
595 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0);
596
597 /* Disable WOL interrupt */
598 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
599 YTPHY_IER_WOL, 0);
600 if (ret < 0)
601 goto err_restore_page;
602 }
603
604err_restore_page:
605 return phy_restore_page(phydev, old_page, ret);
606}
607
608static int yt8531_set_wol(struct phy_device *phydev,
609 struct ethtool_wolinfo *wol)
610{
611 const u16 mac_addr_reg[] = {
612 YTPHY_WOL_MACADDR2_REG,
613 YTPHY_WOL_MACADDR1_REG,
614 YTPHY_WOL_MACADDR0_REG,
615 };
616 const u8 *mac_addr;
617 u16 mask, val;
618 int ret;
619 u8 i;
620
621 if (wol->wolopts & WAKE_MAGIC) {
622 mac_addr = phydev->attached_dev->dev_addr;
623
624 /* Store the device address for the magic packet */
625 for (i = 0; i < 3; i++) {
626 ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i],
627 ((mac_addr[i * 2] << 8)) |
628 (mac_addr[i * 2 + 1]));
629 if (ret < 0)
630 return ret;
631 }
632
633 /* Enable WOL feature */
634 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
635 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
636 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
637 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG,
638 mask, val);
639 if (ret < 0)
640 return ret;
641
642 /* Enable WOL interrupt */
643 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
644 YTPHY_IER_WOL);
645 if (ret < 0)
646 return ret;
647 } else {
648 /* Disable WOL feature */
649 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
650 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG,
651 mask, 0);
652
653 /* Disable WOL interrupt */
654 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
655 YTPHY_IER_WOL, 0);
656 if (ret < 0)
657 return ret;
658 }
659
660 return 0;
661}
662
663static int yt8511_read_page(struct phy_device *phydev)
664{
665 return __phy_read(phydev, YT8511_PAGE_SELECT);
666};
667
668static int yt8511_write_page(struct phy_device *phydev, int page)
669{
670 return __phy_write(phydev, YT8511_PAGE_SELECT, page);
671};
672
673static int yt8511_config_init(struct phy_device *phydev)
674{
675 int oldpage, ret = 0;
676 unsigned int ge, fe;
677
678 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
679 if (oldpage < 0)
680 goto err_restore_page;
681
682 /* set rgmii delay mode */
683 switch (phydev->interface) {
684 case PHY_INTERFACE_MODE_RGMII:
685 ge = YT8511_DELAY_GE_TX_DIS;
686 fe = YT8511_DELAY_FE_TX_DIS;
687 break;
688 case PHY_INTERFACE_MODE_RGMII_RXID:
689 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
690 fe = YT8511_DELAY_FE_TX_DIS;
691 break;
692 case PHY_INTERFACE_MODE_RGMII_TXID:
693 ge = YT8511_DELAY_GE_TX_EN;
694 fe = YT8511_DELAY_FE_TX_EN;
695 break;
696 case PHY_INTERFACE_MODE_RGMII_ID:
697 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
698 fe = YT8511_DELAY_FE_TX_EN;
699 break;
700 default: /* do not support other modes */
701 ret = -EOPNOTSUPP;
702 goto err_restore_page;
703 }
704
705 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
706 if (ret < 0)
707 goto err_restore_page;
708
709 /* set clock mode to 125mhz */
710 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
711 if (ret < 0)
712 goto err_restore_page;
713
714 /* fast ethernet delay is in a separate page */
715 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
716 if (ret < 0)
717 goto err_restore_page;
718
719 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
720 if (ret < 0)
721 goto err_restore_page;
722
723 /* leave pll enabled in sleep */
724 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
725 if (ret < 0)
726 goto err_restore_page;
727
728 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
729 if (ret < 0)
730 goto err_restore_page;
731
732err_restore_page:
733 return phy_restore_page(phydev, oldpage, ret);
734}
735
736/**
737 * yt8521_read_page() - read reg page
738 * @phydev: a pointer to a &struct phy_device
739 *
740 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/
741 * YT8521_RSSR_UTP_SPACE) or negative errno code
742 */
743static int yt8521_read_page(struct phy_device *phydev)
744{
745 int old_page;
746
747 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG);
748 if (old_page < 0)
749 return old_page;
750
751 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
752 return YT8521_RSSR_FIBER_SPACE;
753
754 return YT8521_RSSR_UTP_SPACE;
755};
756
757/**
758 * yt8521_write_page() - write reg page
759 * @phydev: a pointer to a &struct phy_device
760 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write.
761 *
762 * returns 0 or negative errno code
763 */
764static int yt8521_write_page(struct phy_device *phydev, int page)
765{
766 int mask = YT8521_RSSR_SPACE_MASK;
767 int set;
768
769 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
770 set = YT8521_RSSR_FIBER_SPACE;
771 else
772 set = YT8521_RSSR_UTP_SPACE;
773
774 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set);
775};
776
777/**
778 * struct ytphy_cfg_reg_map - map a config value to a register value
779 * @cfg: value in device configuration
780 * @reg: value in the register
781 */
782struct ytphy_cfg_reg_map {
783 u32 cfg;
784 u32 reg;
785};
786
787static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = {
788 /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */
789 { 0, YT8521_RC1R_RGMII_0_000_NS },
790 { 150, YT8521_RC1R_RGMII_0_150_NS },
791 { 300, YT8521_RC1R_RGMII_0_300_NS },
792 { 450, YT8521_RC1R_RGMII_0_450_NS },
793 { 600, YT8521_RC1R_RGMII_0_600_NS },
794 { 750, YT8521_RC1R_RGMII_0_750_NS },
795 { 900, YT8521_RC1R_RGMII_0_900_NS },
796 { 1050, YT8521_RC1R_RGMII_1_050_NS },
797 { 1200, YT8521_RC1R_RGMII_1_200_NS },
798 { 1350, YT8521_RC1R_RGMII_1_350_NS },
799 { 1500, YT8521_RC1R_RGMII_1_500_NS },
800 { 1650, YT8521_RC1R_RGMII_1_650_NS },
801 { 1800, YT8521_RC1R_RGMII_1_800_NS },
802 { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */
803 { 2100, YT8521_RC1R_RGMII_2_100_NS },
804 { 2250, YT8521_RC1R_RGMII_2_250_NS },
805
806 /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */
807 { 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS },
808 { 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS },
809 { 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS },
810 { 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS },
811 { 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS },
812 { 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS },
813 { 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS },
814 { 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS },
815 { 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS },
816 { 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS },
817 { 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS },
818 { 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS },
819 { 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS },
820 { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS },
821 { 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS },
822 { 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS }
823};
824
825static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
826 const char *prop_name,
827 const struct ytphy_cfg_reg_map *tbl,
828 int tb_size,
829 u16 *rxc_dly_en,
830 u32 dflt)
831{
832 struct device_node *node = phydev->mdio.dev.of_node;
833 int tb_size_half = tb_size / 2;
834 u32 val;
835 int i;
836
837 if (of_property_read_u32(node, prop_name, &val))
838 goto err_dts_val;
839
840 /* when rxc_dly_en is NULL, it is get the delay for tx, only half of
841 * tb_size is valid.
842 */
843 if (!rxc_dly_en)
844 tb_size = tb_size_half;
845
846 for (i = 0; i < tb_size; i++) {
847 if (tbl[i].cfg == val) {
848 if (rxc_dly_en && i < tb_size_half)
849 *rxc_dly_en = 0;
850 return tbl[i].reg;
851 }
852 }
853
854 phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n",
855 val, prop_name, dflt);
856
857err_dts_val:
858 /* when rxc_dly_en is not NULL, it is get the delay for rx.
859 * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps,
860 * so YT8521_CCR_RXC_DLY_EN should not be set.
861 */
862 if (rxc_dly_en)
863 *rxc_dly_en = 0;
864
865 return dflt;
866}
867
868static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
869{
870 int tb_size = ARRAY_SIZE(ytphy_rgmii_delays);
871 u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN;
872 u32 rx_reg, tx_reg;
873 u16 mask, val = 0;
874 int ret;
875
876 rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps",
877 ytphy_rgmii_delays, tb_size,
878 &rxc_dly_en,
879 YT8521_RC1R_RGMII_1_950_NS);
880 tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps",
881 ytphy_rgmii_delays, tb_size, NULL,
882 YT8521_RC1R_RGMII_1_950_NS);
883
884 switch (phydev->interface) {
885 case PHY_INTERFACE_MODE_RGMII:
886 rxc_dly_en = 0;
887 break;
888 case PHY_INTERFACE_MODE_RGMII_RXID:
889 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg);
890 break;
891 case PHY_INTERFACE_MODE_RGMII_TXID:
892 rxc_dly_en = 0;
893 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
894 break;
895 case PHY_INTERFACE_MODE_RGMII_ID:
896 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) |
897 FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
898 break;
899 default: /* do not support other modes */
900 return -EOPNOTSUPP;
901 }
902
903 ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
904 YT8521_CCR_RXC_DLY_EN, rxc_dly_en);
905 if (ret < 0)
906 return ret;
907
908 /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */
909 mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK;
910 return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val);
911}
912
913static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev)
914{
915 int ret;
916
917 phy_lock_mdio_bus(phydev);
918 ret = ytphy_rgmii_clk_delay_config(phydev);
919 phy_unlock_mdio_bus(phydev);
920
921 return ret;
922}
923
924/**
925 * struct ytphy_ldo_vol_map - map a current value to a register value
926 * @vol: ldo voltage
927 * @ds: value in the register
928 * @cur: value in device configuration
929 */
930struct ytphy_ldo_vol_map {
931 u32 vol;
932 u32 ds;
933 u32 cur;
934};
935
936static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = {
937 {.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200},
938 {.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100},
939 {.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700},
940 {.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910},
941 {.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110},
942 {.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600},
943 {.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970},
944 {.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350},
945 {.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070},
946 {.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080},
947 {.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370},
948 {.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680},
949 {.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020},
950 {.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450},
951 {.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740},
952 {.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140},
953};
954
955static u32 yt8531_get_ldo_vol(struct phy_device *phydev)
956{
957 u32 val;
958
959 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
960 val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val);
961
962 return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8;
963}
964
965static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur)
966{
967 u32 vol;
968 int i;
969
970 vol = yt8531_get_ldo_vol(phydev);
971 for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) {
972 if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur)
973 return yt8531_ldo_vol[i].ds;
974 }
975
976 return -EINVAL;
977}
978
979static int yt8531_set_ds(struct phy_device *phydev)
980{
981 struct device_node *node = phydev->mdio.dev.of_node;
982 u32 ds_field_low, ds_field_hi, val;
983 int ret, ds;
984
985 /* set rgmii rx clk driver strength */
986 if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) {
987 ds = yt8531_get_ds_map(phydev, val);
988 if (ds < 0)
989 return dev_err_probe(&phydev->mdio.dev, ds,
990 "No matching current value was found.\n");
991 } else {
992 ds = YT8531_RGMII_RX_DS_DEFAULT;
993 }
994
995 ret = ytphy_modify_ext_with_lock(phydev,
996 YTPHY_PAD_DRIVE_STRENGTH_REG,
997 YT8531_RGMII_RXC_DS_MASK,
998 FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds));
999 if (ret < 0)
1000 return ret;
1001
1002 /* set rgmii rx data driver strength */
1003 if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) {
1004 ds = yt8531_get_ds_map(phydev, val);
1005 if (ds < 0)
1006 return dev_err_probe(&phydev->mdio.dev, ds,
1007 "No matching current value was found.\n");
1008 } else {
1009 ds = YT8531_RGMII_RX_DS_DEFAULT;
1010 }
1011
1012 ds_field_hi = FIELD_GET(BIT(2), ds);
1013 ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi);
1014
1015 ds_field_low = FIELD_GET(GENMASK(1, 0), ds);
1016 ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low);
1017
1018 ret = ytphy_modify_ext_with_lock(phydev,
1019 YTPHY_PAD_DRIVE_STRENGTH_REG,
1020 YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK,
1021 ds_field_low | ds_field_hi);
1022 if (ret < 0)
1023 return ret;
1024
1025 return 0;
1026}
1027
1028/**
1029 * yt8521_probe() - read chip config then set suitable polling_mode
1030 * @phydev: a pointer to a &struct phy_device
1031 *
1032 * returns 0 or negative errno code
1033 */
1034static int yt8521_probe(struct phy_device *phydev)
1035{
1036 struct device_node *node = phydev->mdio.dev.of_node;
1037 struct device *dev = &phydev->mdio.dev;
1038 struct yt8521_priv *priv;
1039 int chip_config;
1040 u16 mask, val;
1041 u32 freq;
1042 int ret;
1043
1044 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1045 if (!priv)
1046 return -ENOMEM;
1047
1048 phydev->priv = priv;
1049
1050 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
1051 if (chip_config < 0)
1052 return chip_config;
1053
1054 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK;
1055 switch (priv->strap_mode) {
1056 case YT8521_CCR_MODE_FIBER_TO_RGMII:
1057 case YT8521_CCR_MODE_SGPHY_TO_RGMAC:
1058 case YT8521_CCR_MODE_SGMAC_TO_RGPHY:
1059 priv->polling_mode = YT8521_MODE_FIBER;
1060 priv->reg_page = YT8521_RSSR_FIBER_SPACE;
1061 phydev->port = PORT_FIBRE;
1062 break;
1063 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII:
1064 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO:
1065 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE:
1066 priv->polling_mode = YT8521_MODE_POLL;
1067 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
1068 phydev->port = PORT_NONE;
1069 break;
1070 case YT8521_CCR_MODE_UTP_TO_SGMII:
1071 case YT8521_CCR_MODE_UTP_TO_RGMII:
1072 priv->polling_mode = YT8521_MODE_UTP;
1073 priv->reg_page = YT8521_RSSR_UTP_SPACE;
1074 phydev->port = PORT_TP;
1075 break;
1076 }
1077 /* set default reg space */
1078 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1079 ret = ytphy_write_ext_with_lock(phydev,
1080 YT8521_REG_SPACE_SELECT_REG,
1081 priv->reg_page);
1082 if (ret < 0)
1083 return ret;
1084 }
1085
1086 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
1087 freq = YTPHY_DTS_OUTPUT_CLK_DIS;
1088
1089 if (phydev->drv->phy_id == PHY_ID_YT8521) {
1090 switch (freq) {
1091 case YTPHY_DTS_OUTPUT_CLK_DIS:
1092 mask = YT8521_SCR_SYNCE_ENABLE;
1093 val = 0;
1094 break;
1095 case YTPHY_DTS_OUTPUT_CLK_25M:
1096 mask = YT8521_SCR_SYNCE_ENABLE |
1097 YT8521_SCR_CLK_SRC_MASK |
1098 YT8521_SCR_CLK_FRE_SEL_125M;
1099 val = YT8521_SCR_SYNCE_ENABLE |
1100 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
1101 YT8521_SCR_CLK_SRC_REF_25M);
1102 break;
1103 case YTPHY_DTS_OUTPUT_CLK_125M:
1104 mask = YT8521_SCR_SYNCE_ENABLE |
1105 YT8521_SCR_CLK_SRC_MASK |
1106 YT8521_SCR_CLK_FRE_SEL_125M;
1107 val = YT8521_SCR_SYNCE_ENABLE |
1108 YT8521_SCR_CLK_FRE_SEL_125M |
1109 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
1110 YT8521_SCR_CLK_SRC_PLL_125M);
1111 break;
1112 default:
1113 phydev_warn(phydev, "Freq err:%u\n", freq);
1114 return -EINVAL;
1115 }
1116 } else if (phydev->drv->phy_id == PHY_ID_YT8531S) {
1117 switch (freq) {
1118 case YTPHY_DTS_OUTPUT_CLK_DIS:
1119 mask = YT8531_SCR_SYNCE_ENABLE;
1120 val = 0;
1121 break;
1122 case YTPHY_DTS_OUTPUT_CLK_25M:
1123 mask = YT8531_SCR_SYNCE_ENABLE |
1124 YT8531_SCR_CLK_SRC_MASK |
1125 YT8531_SCR_CLK_FRE_SEL_125M;
1126 val = YT8531_SCR_SYNCE_ENABLE |
1127 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
1128 YT8531_SCR_CLK_SRC_REF_25M);
1129 break;
1130 case YTPHY_DTS_OUTPUT_CLK_125M:
1131 mask = YT8531_SCR_SYNCE_ENABLE |
1132 YT8531_SCR_CLK_SRC_MASK |
1133 YT8531_SCR_CLK_FRE_SEL_125M;
1134 val = YT8531_SCR_SYNCE_ENABLE |
1135 YT8531_SCR_CLK_FRE_SEL_125M |
1136 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
1137 YT8531_SCR_CLK_SRC_PLL_125M);
1138 break;
1139 default:
1140 phydev_warn(phydev, "Freq err:%u\n", freq);
1141 return -EINVAL;
1142 }
1143 } else {
1144 phydev_warn(phydev, "PHY id err\n");
1145 return -EINVAL;
1146 }
1147
1148 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask,
1149 val);
1150}
1151
1152static int yt8531_probe(struct phy_device *phydev)
1153{
1154 struct device_node *node = phydev->mdio.dev.of_node;
1155 u16 mask, val;
1156 u32 freq;
1157
1158 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
1159 freq = YTPHY_DTS_OUTPUT_CLK_DIS;
1160
1161 switch (freq) {
1162 case YTPHY_DTS_OUTPUT_CLK_DIS:
1163 mask = YT8531_SCR_SYNCE_ENABLE;
1164 val = 0;
1165 break;
1166 case YTPHY_DTS_OUTPUT_CLK_25M:
1167 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
1168 YT8531_SCR_CLK_FRE_SEL_125M;
1169 val = YT8531_SCR_SYNCE_ENABLE |
1170 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
1171 YT8531_SCR_CLK_SRC_REF_25M);
1172 break;
1173 case YTPHY_DTS_OUTPUT_CLK_125M:
1174 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
1175 YT8531_SCR_CLK_FRE_SEL_125M;
1176 val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M |
1177 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
1178 YT8531_SCR_CLK_SRC_PLL_125M);
1179 break;
1180 default:
1181 phydev_warn(phydev, "Freq err:%u\n", freq);
1182 return -EINVAL;
1183 }
1184
1185 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask,
1186 val);
1187}
1188
1189/**
1190 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
1191 * @phydev: a pointer to a &struct phy_device
1192 *
1193 * NOTE:The caller must have taken the MDIO bus lock.
1194 *
1195 * returns 0 or negative errno code
1196 */
1197static int ytphy_utp_read_lpa(struct phy_device *phydev)
1198{
1199 int lpa, lpagb;
1200
1201 if (phydev->autoneg == AUTONEG_ENABLE) {
1202 if (!phydev->autoneg_complete) {
1203 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
1204 0);
1205 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
1206 return 0;
1207 }
1208
1209 if (phydev->is_gigabit_capable) {
1210 lpagb = __phy_read(phydev, MII_STAT1000);
1211 if (lpagb < 0)
1212 return lpagb;
1213
1214 if (lpagb & LPA_1000MSFAIL) {
1215 int adv = __phy_read(phydev, MII_CTRL1000);
1216
1217 if (adv < 0)
1218 return adv;
1219
1220 if (adv & CTL1000_ENABLE_MASTER)
1221 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
1222 else
1223 phydev_err(phydev, "Master/Slave resolution failed\n");
1224 return -ENOLINK;
1225 }
1226
1227 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
1228 lpagb);
1229 }
1230
1231 lpa = __phy_read(phydev, MII_LPA);
1232 if (lpa < 0)
1233 return lpa;
1234
1235 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1236 } else {
1237 linkmode_zero(phydev->lp_advertising);
1238 }
1239
1240 return 0;
1241}
1242
1243/**
1244 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber
1245 * mode, adjust speed and duplex.
1246 * @phydev: a pointer to a &struct phy_device
1247 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG
1248 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode)
1249 *
1250 * NOTE:The caller must have taken the MDIO bus lock.
1251 *
1252 * returns 0
1253 */
1254static int yt8521_adjust_status(struct phy_device *phydev, int status,
1255 bool is_utp)
1256{
1257 int speed_mode, duplex;
1258 int speed;
1259 int err;
1260 int lpa;
1261
1262 if (is_utp)
1263 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET;
1264 else
1265 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */
1266
1267 speed_mode = status & YTPHY_SSR_SPEED_MASK;
1268
1269 switch (speed_mode) {
1270 case YTPHY_SSR_SPEED_10M:
1271 if (is_utp)
1272 speed = SPEED_10;
1273 else
1274 /* for fiber, it will never run here, default to
1275 * SPEED_UNKNOWN
1276 */
1277 speed = SPEED_UNKNOWN;
1278 break;
1279 case YTPHY_SSR_SPEED_100M:
1280 speed = SPEED_100;
1281 break;
1282 case YTPHY_SSR_SPEED_1000M:
1283 speed = SPEED_1000;
1284 break;
1285 default:
1286 speed = SPEED_UNKNOWN;
1287 break;
1288 }
1289
1290 phydev->speed = speed;
1291 phydev->duplex = duplex;
1292
1293 if (is_utp) {
1294 err = ytphy_utp_read_lpa(phydev);
1295 if (err < 0)
1296 return err;
1297
1298 phy_resolve_aneg_pause(phydev);
1299 } else {
1300 lpa = __phy_read(phydev, MII_LPA);
1301 if (lpa < 0)
1302 return lpa;
1303
1304 /* only support 1000baseX Full */
1305 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1306 phydev->lp_advertising, lpa & LPA_1000XFULL);
1307
1308 if (!(lpa & YTPHY_FLPA_PAUSE)) {
1309 phydev->pause = 0;
1310 phydev->asym_pause = 0;
1311 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) {
1312 phydev->pause = 1;
1313 phydev->asym_pause = 1;
1314 } else {
1315 phydev->pause = 1;
1316 phydev->asym_pause = 0;
1317 }
1318 }
1319
1320 return 0;
1321}
1322
1323/**
1324 * yt8521_read_status_paged() - determines the speed and duplex of one page
1325 * @phydev: a pointer to a &struct phy_device
1326 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1327 * operate.
1328 *
1329 * returns 1 (utp or fiber link),0 (no link) or negative errno code
1330 */
1331static int yt8521_read_status_paged(struct phy_device *phydev, int page)
1332{
1333 int fiber_latch_val;
1334 int fiber_curr_val;
1335 int old_page;
1336 int ret = 0;
1337 int status;
1338 int link;
1339
1340 linkmode_zero(phydev->lp_advertising);
1341 phydev->duplex = DUPLEX_UNKNOWN;
1342 phydev->speed = SPEED_UNKNOWN;
1343 phydev->asym_pause = 0;
1344 phydev->pause = 0;
1345
1346 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber
1347 * respectively. but for utp/fiber combo mode, reg space should be
1348 * arbitrated based on media priority. by default, utp takes
1349 * priority. reg space should be properly set before read
1350 * YTPHY_SPECIFIC_STATUS_REG.
1351 */
1352
1353 page &= YT8521_RSSR_SPACE_MASK;
1354 old_page = phy_select_page(phydev, page);
1355 if (old_page < 0)
1356 goto err_restore_page;
1357
1358 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex
1359 * of the PHY is actually using.
1360 */
1361 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
1362 if (ret < 0)
1363 goto err_restore_page;
1364
1365 status = ret;
1366 link = !!(status & YTPHY_SSR_LINK);
1367
1368 /* When PHY is in fiber mode, speed transferred from 1000Mbps to
1369 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so
1370 * we need check MII_BMSR to identify such case.
1371 */
1372 if (page == YT8521_RSSR_FIBER_SPACE) {
1373 ret = __phy_read(phydev, MII_BMSR);
1374 if (ret < 0)
1375 goto err_restore_page;
1376
1377 fiber_latch_val = ret;
1378 ret = __phy_read(phydev, MII_BMSR);
1379 if (ret < 0)
1380 goto err_restore_page;
1381
1382 fiber_curr_val = ret;
1383 if (link && fiber_latch_val != fiber_curr_val) {
1384 link = 0;
1385 phydev_info(phydev,
1386 "%s, fiber link down detect, latch = %04x, curr = %04x\n",
1387 __func__, fiber_latch_val, fiber_curr_val);
1388 }
1389 } else {
1390 /* Read autonegotiation status */
1391 ret = __phy_read(phydev, MII_BMSR);
1392 if (ret < 0)
1393 goto err_restore_page;
1394
1395 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0;
1396 }
1397
1398 if (link) {
1399 if (page == YT8521_RSSR_UTP_SPACE)
1400 yt8521_adjust_status(phydev, status, true);
1401 else
1402 yt8521_adjust_status(phydev, status, false);
1403 }
1404 return phy_restore_page(phydev, old_page, link);
1405
1406err_restore_page:
1407 return phy_restore_page(phydev, old_page, ret);
1408}
1409
1410/**
1411 * yt8521_read_status() - determines the negotiated speed and duplex
1412 * @phydev: a pointer to a &struct phy_device
1413 *
1414 * returns 0 or negative errno code
1415 */
1416static int yt8521_read_status(struct phy_device *phydev)
1417{
1418 struct yt8521_priv *priv = phydev->priv;
1419 int link_fiber = 0;
1420 int link_utp;
1421 int link;
1422 int ret;
1423
1424 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1425 link = yt8521_read_status_paged(phydev, priv->reg_page);
1426 if (link < 0)
1427 return link;
1428 } else {
1429 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is
1430 * needed. by default, utp is higher priority.
1431 */
1432
1433 link_utp = yt8521_read_status_paged(phydev,
1434 YT8521_RSSR_UTP_SPACE);
1435 if (link_utp < 0)
1436 return link_utp;
1437
1438 if (!link_utp) {
1439 link_fiber = yt8521_read_status_paged(phydev,
1440 YT8521_RSSR_FIBER_SPACE);
1441 if (link_fiber < 0)
1442 return link_fiber;
1443 }
1444
1445 link = link_utp || link_fiber;
1446 }
1447
1448 if (link) {
1449 if (phydev->link == 0) {
1450 /* arbitrate reg space based on linkup media type. */
1451 if (priv->polling_mode == YT8521_MODE_POLL &&
1452 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
1453 if (link_fiber)
1454 priv->reg_page =
1455 YT8521_RSSR_FIBER_SPACE;
1456 else
1457 priv->reg_page = YT8521_RSSR_UTP_SPACE;
1458
1459 ret = ytphy_write_ext_with_lock(phydev,
1460 YT8521_REG_SPACE_SELECT_REG,
1461 priv->reg_page);
1462 if (ret < 0)
1463 return ret;
1464
1465 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP;
1466
1467 phydev_info(phydev, "%s, link up, media: %s\n",
1468 __func__,
1469 (phydev->port == PORT_TP) ?
1470 "UTP" : "Fiber");
1471 }
1472 }
1473 phydev->link = 1;
1474 } else {
1475 if (phydev->link == 1) {
1476 phydev_info(phydev, "%s, link down, media: %s\n",
1477 __func__, (phydev->port == PORT_TP) ?
1478 "UTP" : "Fiber");
1479
1480 /* When in YT8521_MODE_POLL mode, need prepare for next
1481 * arbitration.
1482 */
1483 if (priv->polling_mode == YT8521_MODE_POLL) {
1484 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
1485 phydev->port = PORT_NONE;
1486 }
1487 }
1488
1489 phydev->link = 0;
1490 }
1491
1492 return 0;
1493}
1494
1495/**
1496 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page
1497 * @phydev: the phy_device struct
1498 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate
1499 * @mask: bit mask of bits to clear
1500 * @set: bit mask of bits to set
1501 *
1502 * NOTE: Convenience function which allows a PHY's BMCR register to be
1503 * modified as new register value = (old register value & ~mask) | set.
1504 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1505 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1506 * If it is reset, it will wait for completion.
1507 *
1508 * returns 0 or negative errno code
1509 */
1510static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page,
1511 u16 mask, u16 set)
1512{
1513 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */
1514 int old_page;
1515 int ret = 0;
1516
1517 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
1518 if (old_page < 0)
1519 goto err_restore_page;
1520
1521 ret = __phy_modify(phydev, MII_BMCR, mask, set);
1522 if (ret < 0)
1523 goto err_restore_page;
1524
1525 /* If it is reset, need to wait for the reset to complete */
1526 if (set == BMCR_RESET) {
1527 while (max_cnt--) {
1528 usleep_range(1000, 1100);
1529 ret = __phy_read(phydev, MII_BMCR);
1530 if (ret < 0)
1531 goto err_restore_page;
1532
1533 if (!(ret & BMCR_RESET))
1534 return phy_restore_page(phydev, old_page, 0);
1535 }
1536 }
1537
1538err_restore_page:
1539 return phy_restore_page(phydev, old_page, ret);
1540}
1541
1542/**
1543 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register
1544 * @phydev: the phy_device struct
1545 * @mask: bit mask of bits to clear
1546 * @set: bit mask of bits to set
1547 *
1548 * NOTE: Convenience function which allows a PHY's BMCR register to be
1549 * modified as new register value = (old register value & ~mask) | set.
1550 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1551 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1552 *
1553 * returns 0 or negative errno code
1554 */
1555static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask,
1556 u16 set)
1557{
1558 struct yt8521_priv *priv = phydev->priv;
1559 int ret;
1560
1561 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1562 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask,
1563 set);
1564 if (ret < 0)
1565 return ret;
1566 } else {
1567 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE,
1568 mask, set);
1569 if (ret < 0)
1570 return ret;
1571
1572 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE,
1573 mask, set);
1574 if (ret < 0)
1575 return ret;
1576 }
1577 return 0;
1578}
1579
1580/**
1581 * yt8521_soft_reset() - called to issue a PHY software reset
1582 * @phydev: a pointer to a &struct phy_device
1583 *
1584 * returns 0 or negative errno code
1585 */
1586static int yt8521_soft_reset(struct phy_device *phydev)
1587{
1588 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET);
1589}
1590
1591/**
1592 * yt8521_suspend() - suspend the hardware
1593 * @phydev: a pointer to a &struct phy_device
1594 *
1595 * returns 0 or negative errno code
1596 */
1597static int yt8521_suspend(struct phy_device *phydev)
1598{
1599 int wol_config;
1600
1601 /* YTPHY_WOL_CONFIG_REG is common ext reg */
1602 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1603 if (wol_config < 0)
1604 return wol_config;
1605
1606 /* if wol enable, do nothing */
1607 if (wol_config & YTPHY_WCR_ENABLE)
1608 return 0;
1609
1610 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN);
1611}
1612
1613/**
1614 * yt8521_resume() - resume the hardware
1615 * @phydev: a pointer to a &struct phy_device
1616 *
1617 * returns 0 or negative errno code
1618 */
1619static int yt8521_resume(struct phy_device *phydev)
1620{
1621 int ret;
1622 int wol_config;
1623
1624 /* disable auto sleep */
1625 ret = ytphy_modify_ext_with_lock(phydev,
1626 YT8521_EXTREG_SLEEP_CONTROL1_REG,
1627 YT8521_ESC1R_SLEEP_SW, 0);
1628 if (ret < 0)
1629 return ret;
1630
1631 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1632 if (wol_config < 0)
1633 return wol_config;
1634
1635 /* if wol enable, do nothing */
1636 if (wol_config & YTPHY_WCR_ENABLE)
1637 return 0;
1638
1639 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0);
1640}
1641
1642/**
1643 * yt8521_config_init() - called to initialize the PHY
1644 * @phydev: a pointer to a &struct phy_device
1645 *
1646 * returns 0 or negative errno code
1647 */
1648static int yt8521_config_init(struct phy_device *phydev)
1649{
1650 struct device_node *node = phydev->mdio.dev.of_node;
1651 int old_page;
1652 int ret = 0;
1653
1654 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
1655 if (old_page < 0)
1656 goto err_restore_page;
1657
1658 /* set rgmii delay mode */
1659 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1660 ret = ytphy_rgmii_clk_delay_config(phydev);
1661 if (ret < 0)
1662 goto err_restore_page;
1663 }
1664
1665 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
1666 /* disable auto sleep */
1667 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
1668 YT8521_ESC1R_SLEEP_SW, 0);
1669 if (ret < 0)
1670 goto err_restore_page;
1671 }
1672
1673 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
1674 /* enable RXC clock when no wire plug */
1675 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
1676 YT8521_CGR_RX_CLK_EN, 0);
1677 if (ret < 0)
1678 goto err_restore_page;
1679 }
1680err_restore_page:
1681 return phy_restore_page(phydev, old_page, ret);
1682}
1683
1684static int yt8531_config_init(struct phy_device *phydev)
1685{
1686 struct device_node *node = phydev->mdio.dev.of_node;
1687 int ret;
1688
1689 ret = ytphy_rgmii_clk_delay_config_with_lock(phydev);
1690 if (ret < 0)
1691 return ret;
1692
1693 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
1694 /* disable auto sleep */
1695 ret = ytphy_modify_ext_with_lock(phydev,
1696 YT8521_EXTREG_SLEEP_CONTROL1_REG,
1697 YT8521_ESC1R_SLEEP_SW, 0);
1698 if (ret < 0)
1699 return ret;
1700 }
1701
1702 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
1703 /* enable RXC clock when no wire plug */
1704 ret = ytphy_modify_ext_with_lock(phydev,
1705 YT8521_CLOCK_GATING_REG,
1706 YT8521_CGR_RX_CLK_EN, 0);
1707 if (ret < 0)
1708 return ret;
1709 }
1710
1711 ret = yt8531_set_ds(phydev);
1712 if (ret < 0)
1713 return ret;
1714
1715 return 0;
1716}
1717
1718/**
1719 * yt8531_link_change_notify() - Adjust the tx clock direction according to
1720 * the current speed and dts config.
1721 * @phydev: a pointer to a &struct phy_device
1722 *
1723 * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please
1724 * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not
1725 * JH7110.
1726 */
1727static void yt8531_link_change_notify(struct phy_device *phydev)
1728{
1729 struct device_node *node = phydev->mdio.dev.of_node;
1730 bool tx_clk_1000_inverted = false;
1731 bool tx_clk_100_inverted = false;
1732 bool tx_clk_10_inverted = false;
1733 bool tx_clk_adj_enabled = false;
1734 u16 val = 0;
1735 int ret;
1736
1737 if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled"))
1738 tx_clk_adj_enabled = true;
1739
1740 if (!tx_clk_adj_enabled)
1741 return;
1742
1743 if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted"))
1744 tx_clk_10_inverted = true;
1745 if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted"))
1746 tx_clk_100_inverted = true;
1747 if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted"))
1748 tx_clk_1000_inverted = true;
1749
1750 if (phydev->speed < 0)
1751 return;
1752
1753 switch (phydev->speed) {
1754 case SPEED_1000:
1755 if (tx_clk_1000_inverted)
1756 val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1757 break;
1758 case SPEED_100:
1759 if (tx_clk_100_inverted)
1760 val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1761 break;
1762 case SPEED_10:
1763 if (tx_clk_10_inverted)
1764 val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1765 break;
1766 default:
1767 return;
1768 }
1769
1770 ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG,
1771 YT8521_RC1R_TX_CLK_SEL_INVERTED, val);
1772 if (ret < 0)
1773 phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret);
1774}
1775
1776/**
1777 * yt8521_prepare_fiber_features() - A small helper function that setup
1778 * fiber's features.
1779 * @phydev: a pointer to a &struct phy_device
1780 * @dst: a pointer to store fiber's features
1781 */
1782static void yt8521_prepare_fiber_features(struct phy_device *phydev,
1783 unsigned long *dst)
1784{
1785 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst);
1786 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst);
1787 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst);
1788 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst);
1789}
1790
1791/**
1792 * yt8521_fiber_setup_forced - configures/forces speed from @phydev
1793 * @phydev: target phy_device struct
1794 *
1795 * NOTE:The caller must have taken the MDIO bus lock.
1796 *
1797 * returns 0 or negative errno code
1798 */
1799static int yt8521_fiber_setup_forced(struct phy_device *phydev)
1800{
1801 u16 val;
1802 int ret;
1803
1804 if (phydev->speed == SPEED_1000)
1805 val = YTPHY_MCR_FIBER_1000BX;
1806 else if (phydev->speed == SPEED_100)
1807 val = YTPHY_MCR_FIBER_100FX;
1808 else
1809 return -EINVAL;
1810
1811 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1812 if (ret < 0)
1813 return ret;
1814
1815 /* disable Fiber auto sensing */
1816 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1817 YT8521_LTCR_EN_AUTOSEN, 0);
1818 if (ret < 0)
1819 return ret;
1820
1821 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG,
1822 YTPHY_MCR_FIBER_SPEED_MASK, val);
1823 if (ret < 0)
1824 return ret;
1825
1826 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1827 YT8521_CCR_SW_RST, 0);
1828}
1829
1830/**
1831 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation
1832 * @phydev: target phy_device struct
1833 * @restart: whether aneg restart is requested
1834 *
1835 * NOTE:The caller must have taken the MDIO bus lock.
1836 *
1837 * returns 0 or negative errno code
1838 */
1839static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
1840{
1841 int ret;
1842
1843 if (!restart) {
1844 /* Advertisement hasn't changed, but maybe aneg was never on to
1845 * begin with? Or maybe phy was isolated?
1846 */
1847 ret = __phy_read(phydev, MII_BMCR);
1848 if (ret < 0)
1849 return ret;
1850
1851 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
1852 restart = true;
1853 }
1854 /* Enable and Restart Autonegotiation
1855 * Don't isolate the PHY if we're negotiating
1856 */
1857 if (restart)
1858 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
1859 BMCR_ANENABLE | BMCR_ANRESTART);
1860
1861 return 0;
1862}
1863
1864/**
1865 * yt8521_fiber_config_aneg - restart auto-negotiation or write
1866 * YTPHY_MISC_CONFIG_REG.
1867 * @phydev: target phy_device struct
1868 *
1869 * NOTE:The caller must have taken the MDIO bus lock.
1870 *
1871 * returns 0 or negative errno code
1872 */
1873static int yt8521_fiber_config_aneg(struct phy_device *phydev)
1874{
1875 int err, changed = 0;
1876 int bmcr;
1877 u16 adv;
1878
1879 if (phydev->autoneg != AUTONEG_ENABLE)
1880 return yt8521_fiber_setup_forced(phydev);
1881
1882 /* enable Fiber auto sensing */
1883 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1884 0, YT8521_LTCR_EN_AUTOSEN);
1885 if (err < 0)
1886 return err;
1887
1888 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1889 YT8521_CCR_SW_RST, 0);
1890 if (err < 0)
1891 return err;
1892
1893 bmcr = __phy_read(phydev, MII_BMCR);
1894 if (bmcr < 0)
1895 return bmcr;
1896
1897 /* When it is coming from fiber forced mode, add bmcr power down
1898 * and power up to let aneg work fine.
1899 */
1900 if (!(bmcr & BMCR_ANENABLE)) {
1901 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
1902 usleep_range(1000, 1100);
1903 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
1904 }
1905
1906 adv = linkmode_adv_to_mii_adv_x(phydev->advertising,
1907 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
1908
1909 /* Setup fiber advertisement */
1910 err = __phy_modify_changed(phydev, MII_ADVERTISE,
1911 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
1912 ADVERTISE_1000XPAUSE |
1913 ADVERTISE_1000XPSE_ASYM,
1914 adv);
1915 if (err < 0)
1916 return err;
1917
1918 if (err > 0)
1919 changed = 1;
1920
1921 return ytphy_check_and_restart_aneg(phydev, changed);
1922}
1923
1924/**
1925 * ytphy_setup_master_slave
1926 * @phydev: target phy_device struct
1927 *
1928 * NOTE: The caller must have taken the MDIO bus lock.
1929 *
1930 * returns 0 or negative errno code
1931 */
1932static int ytphy_setup_master_slave(struct phy_device *phydev)
1933{
1934 u16 ctl = 0;
1935
1936 if (!phydev->is_gigabit_capable)
1937 return 0;
1938
1939 switch (phydev->master_slave_set) {
1940 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
1941 ctl |= CTL1000_PREFER_MASTER;
1942 break;
1943 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
1944 break;
1945 case MASTER_SLAVE_CFG_MASTER_FORCE:
1946 ctl |= CTL1000_AS_MASTER;
1947 fallthrough;
1948 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1949 ctl |= CTL1000_ENABLE_MASTER;
1950 break;
1951 case MASTER_SLAVE_CFG_UNKNOWN:
1952 case MASTER_SLAVE_CFG_UNSUPPORTED:
1953 return 0;
1954 default:
1955 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1956 return -EOPNOTSUPP;
1957 }
1958
1959 return __phy_modify_changed(phydev, MII_CTRL1000,
1960 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
1961 CTL1000_PREFER_MASTER), ctl);
1962}
1963
1964/**
1965 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters
1966 * @phydev: target phy_device struct
1967 *
1968 * NOTE: Writes MII_ADVERTISE with the appropriate values,
1969 * after sanitizing the values to make sure we only advertise
1970 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
1971 * hasn't changed, and > 0 if it has changed.
1972 * The caller must have taken the MDIO bus lock.
1973 *
1974 * returns 0 or negative errno code
1975 */
1976static int ytphy_utp_config_advert(struct phy_device *phydev)
1977{
1978 int err, bmsr, changed = 0;
1979 u32 adv;
1980
1981 /* Only allow advertising what this PHY supports */
1982 linkmode_and(phydev->advertising, phydev->advertising,
1983 phydev->supported);
1984
1985 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
1986
1987 /* Setup standard advertisement */
1988 err = __phy_modify_changed(phydev, MII_ADVERTISE,
1989 ADVERTISE_ALL | ADVERTISE_100BASE4 |
1990 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
1991 adv);
1992 if (err < 0)
1993 return err;
1994 if (err > 0)
1995 changed = 1;
1996
1997 bmsr = __phy_read(phydev, MII_BMSR);
1998 if (bmsr < 0)
1999 return bmsr;
2000
2001 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
2002 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
2003 * logical 1.
2004 */
2005 if (!(bmsr & BMSR_ESTATEN))
2006 return changed;
2007
2008 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
2009
2010 err = __phy_modify_changed(phydev, MII_CTRL1000,
2011 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
2012 adv);
2013 if (err < 0)
2014 return err;
2015 if (err > 0)
2016 changed = 1;
2017
2018 return changed;
2019}
2020
2021/**
2022 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR
2023 * @phydev: target phy_device struct
2024 * @changed: whether autoneg is requested
2025 *
2026 * NOTE: If auto-negotiation is enabled, we configure the
2027 * advertising, and then restart auto-negotiation. If it is not
2028 * enabled, then we write the BMCR.
2029 * The caller must have taken the MDIO bus lock.
2030 *
2031 * returns 0 or negative errno code
2032 */
2033static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed)
2034{
2035 int err;
2036 u16 ctl;
2037
2038 err = ytphy_setup_master_slave(phydev);
2039 if (err < 0)
2040 return err;
2041 else if (err)
2042 changed = true;
2043
2044 if (phydev->autoneg != AUTONEG_ENABLE) {
2045 /* configures/forces speed/duplex from @phydev */
2046
2047 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
2048
2049 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK |
2050 BMCR_ISOLATE | BMCR_PDOWN), ctl);
2051 }
2052
2053 err = ytphy_utp_config_advert(phydev);
2054 if (err < 0) /* error */
2055 return err;
2056 else if (err)
2057 changed = true;
2058
2059 return ytphy_check_and_restart_aneg(phydev, changed);
2060}
2061
2062/**
2063 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg
2064 * of one page
2065 * @phydev: a pointer to a &struct phy_device
2066 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
2067 * operate.
2068 *
2069 * returns 0 or negative errno code
2070 */
2071static int yt8521_config_aneg_paged(struct phy_device *phydev, int page)
2072{
2073 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported);
2074 struct yt8521_priv *priv = phydev->priv;
2075 int old_page;
2076 int ret = 0;
2077
2078 page &= YT8521_RSSR_SPACE_MASK;
2079
2080 old_page = phy_select_page(phydev, page);
2081 if (old_page < 0)
2082 goto err_restore_page;
2083
2084 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
2085 * phydev->advertising should be updated.
2086 */
2087 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
2088 linkmode_zero(fiber_supported);
2089 yt8521_prepare_fiber_features(phydev, fiber_supported);
2090
2091 /* prepare fiber_supported, then setup advertising. */
2092 if (page == YT8521_RSSR_FIBER_SPACE) {
2093 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2094 fiber_supported);
2095 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2096 fiber_supported);
2097 linkmode_and(phydev->advertising,
2098 priv->combo_advertising, fiber_supported);
2099 } else {
2100 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */
2101 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2102 fiber_supported);
2103 linkmode_andnot(phydev->advertising,
2104 priv->combo_advertising,
2105 fiber_supported);
2106 }
2107 }
2108
2109 if (page == YT8521_RSSR_FIBER_SPACE)
2110 ret = yt8521_fiber_config_aneg(phydev);
2111 else
2112 ret = ytphy_utp_config_aneg(phydev, false);
2113
2114err_restore_page:
2115 return phy_restore_page(phydev, old_page, ret);
2116}
2117
2118/**
2119 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged
2120 * @phydev: a pointer to a &struct phy_device
2121 *
2122 * returns 0 or negative errno code
2123 */
2124static int yt8521_config_aneg(struct phy_device *phydev)
2125{
2126 struct yt8521_priv *priv = phydev->priv;
2127 int ret;
2128
2129 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
2130 ret = yt8521_config_aneg_paged(phydev, priv->reg_page);
2131 if (ret < 0)
2132 return ret;
2133 } else {
2134 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
2135 * phydev->advertising need to be saved at first run.
2136 * Because it contains the advertising which supported by both
2137 * mac and yt8521(utp and fiber).
2138 */
2139 if (linkmode_empty(priv->combo_advertising)) {
2140 linkmode_copy(priv->combo_advertising,
2141 phydev->advertising);
2142 }
2143
2144 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE);
2145 if (ret < 0)
2146 return ret;
2147
2148 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE);
2149 if (ret < 0)
2150 return ret;
2151
2152 /* we don't known which will be link, so restore
2153 * phydev->advertising as default value.
2154 */
2155 linkmode_copy(phydev->advertising, priv->combo_advertising);
2156 }
2157 return 0;
2158}
2159
2160/**
2161 * yt8521_aneg_done_paged() - determines the auto negotiation result of one
2162 * page.
2163 * @phydev: a pointer to a &struct phy_device
2164 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
2165 * operate.
2166 *
2167 * returns 0(no link)or 1(fiber or utp link) or negative errno code
2168 */
2169static int yt8521_aneg_done_paged(struct phy_device *phydev, int page)
2170{
2171 int old_page;
2172 int ret = 0;
2173 int link;
2174
2175 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
2176 if (old_page < 0)
2177 goto err_restore_page;
2178
2179 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
2180 if (ret < 0)
2181 goto err_restore_page;
2182
2183 link = !!(ret & YTPHY_SSR_LINK);
2184 ret = link;
2185
2186err_restore_page:
2187 return phy_restore_page(phydev, old_page, ret);
2188}
2189
2190/**
2191 * yt8521_aneg_done() - determines the auto negotiation result
2192 * @phydev: a pointer to a &struct phy_device
2193 *
2194 * returns 0(no link)or 1(fiber or utp link) or negative errno code
2195 */
2196static int yt8521_aneg_done(struct phy_device *phydev)
2197{
2198 struct yt8521_priv *priv = phydev->priv;
2199 int link_fiber = 0;
2200 int link_utp;
2201 int link;
2202
2203 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
2204 link = yt8521_aneg_done_paged(phydev, priv->reg_page);
2205 } else {
2206 link_utp = yt8521_aneg_done_paged(phydev,
2207 YT8521_RSSR_UTP_SPACE);
2208 if (link_utp < 0)
2209 return link_utp;
2210
2211 if (!link_utp) {
2212 link_fiber = yt8521_aneg_done_paged(phydev,
2213 YT8521_RSSR_FIBER_SPACE);
2214 if (link_fiber < 0)
2215 return link_fiber;
2216 }
2217 link = link_fiber || link_utp;
2218 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n",
2219 __func__, link_fiber, link_utp);
2220 }
2221
2222 return link;
2223}
2224
2225/**
2226 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers
2227 * @phydev: target phy_device struct
2228 *
2229 * NOTE: Reads the PHY's abilities and populates
2230 * phydev->supported accordingly.
2231 * The caller must have taken the MDIO bus lock.
2232 *
2233 * returns 0 or negative errno code
2234 */
2235static int ytphy_utp_read_abilities(struct phy_device *phydev)
2236{
2237 int val;
2238
2239 linkmode_set_bit_array(phy_basic_ports_array,
2240 ARRAY_SIZE(phy_basic_ports_array),
2241 phydev->supported);
2242
2243 val = __phy_read(phydev, MII_BMSR);
2244 if (val < 0)
2245 return val;
2246
2247 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
2248 val & BMSR_ANEGCAPABLE);
2249
2250 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
2251 val & BMSR_100FULL);
2252 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
2253 val & BMSR_100HALF);
2254 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
2255 val & BMSR_10FULL);
2256 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
2257 val & BMSR_10HALF);
2258
2259 if (val & BMSR_ESTATEN) {
2260 val = __phy_read(phydev, MII_ESTATUS);
2261 if (val < 0)
2262 return val;
2263
2264 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2265 phydev->supported, val & ESTATUS_1000_TFULL);
2266 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
2267 phydev->supported, val & ESTATUS_1000_THALF);
2268 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2269 phydev->supported, val & ESTATUS_1000_XFULL);
2270 }
2271
2272 return 0;
2273}
2274
2275/**
2276 * yt8521_get_features_paged() - read supported link modes for one page
2277 * @phydev: a pointer to a &struct phy_device
2278 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
2279 * operate.
2280 *
2281 * returns 0 or negative errno code
2282 */
2283static int yt8521_get_features_paged(struct phy_device *phydev, int page)
2284{
2285 int old_page;
2286 int ret = 0;
2287
2288 page &= YT8521_RSSR_SPACE_MASK;
2289 old_page = phy_select_page(phydev, page);
2290 if (old_page < 0)
2291 goto err_restore_page;
2292
2293 if (page == YT8521_RSSR_FIBER_SPACE) {
2294 linkmode_zero(phydev->supported);
2295 yt8521_prepare_fiber_features(phydev, phydev->supported);
2296 } else {
2297 ret = ytphy_utp_read_abilities(phydev);
2298 if (ret < 0)
2299 goto err_restore_page;
2300 }
2301
2302err_restore_page:
2303 return phy_restore_page(phydev, old_page, ret);
2304}
2305
2306/**
2307 * yt8521_get_features - switch reg space then call yt8521_get_features_paged
2308 * @phydev: target phy_device struct
2309 *
2310 * returns 0 or negative errno code
2311 */
2312static int yt8521_get_features(struct phy_device *phydev)
2313{
2314 struct yt8521_priv *priv = phydev->priv;
2315 int ret;
2316
2317 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
2318 ret = yt8521_get_features_paged(phydev, priv->reg_page);
2319 } else {
2320 ret = yt8521_get_features_paged(phydev,
2321 YT8521_RSSR_UTP_SPACE);
2322 if (ret < 0)
2323 return ret;
2324
2325 /* add fiber's features to phydev->supported */
2326 yt8521_prepare_fiber_features(phydev, phydev->supported);
2327 }
2328 return ret;
2329}
2330
2331/**
2332 * yt8821_get_features - read mmd register to get 2.5G capability
2333 * @phydev: target phy_device struct
2334 *
2335 * Returns: 0 or negative errno code
2336 */
2337static int yt8821_get_features(struct phy_device *phydev)
2338{
2339 int ret;
2340
2341 ret = genphy_c45_pma_read_ext_abilities(phydev);
2342 if (ret < 0)
2343 return ret;
2344
2345 return genphy_read_abilities(phydev);
2346}
2347
2348/**
2349 * yt8821_get_rate_matching - read register to get phy chip mode
2350 * @phydev: target phy_device struct
2351 * @iface: PHY data interface type
2352 *
2353 * Returns: rate matching type or negative errno code
2354 */
2355static int yt8821_get_rate_matching(struct phy_device *phydev,
2356 phy_interface_t iface)
2357{
2358 int val;
2359
2360 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
2361 if (val < 0)
2362 return val;
2363
2364 if (FIELD_GET(YT8521_CCR_MODE_SEL_MASK, val) ==
2365 YT8821_CHIP_MODE_FORCE_BX2500)
2366 return RATE_MATCH_PAUSE;
2367
2368 return RATE_MATCH_NONE;
2369}
2370
2371/**
2372 * yt8821_aneg_done() - determines the auto negotiation result
2373 * @phydev: a pointer to a &struct phy_device
2374 *
2375 * Returns: 0(no link)or 1(utp link) or negative errno code
2376 */
2377static int yt8821_aneg_done(struct phy_device *phydev)
2378{
2379 return yt8521_aneg_done_paged(phydev, YT8521_RSSR_UTP_SPACE);
2380}
2381
2382/**
2383 * yt8821_serdes_init() - serdes init
2384 * @phydev: a pointer to a &struct phy_device
2385 *
2386 * Returns: 0 or negative errno code
2387 */
2388static int yt8821_serdes_init(struct phy_device *phydev)
2389{
2390 int old_page;
2391 int ret = 0;
2392 u16 mask;
2393 u16 set;
2394
2395 old_page = phy_select_page(phydev, YT8521_RSSR_FIBER_SPACE);
2396 if (old_page < 0) {
2397 phydev_err(phydev, "Failed to select page: %d\n",
2398 old_page);
2399 goto err_restore_page;
2400 }
2401
2402 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
2403 if (ret < 0)
2404 goto err_restore_page;
2405
2406 mask = YT8821_SDS_EXT_CSR_VCO_LDO_EN |
2407 YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN;
2408 set = YT8821_SDS_EXT_CSR_VCO_LDO_EN;
2409 ret = ytphy_modify_ext(phydev, YT8821_SDS_EXT_CSR_CTRL_REG, mask,
2410 set);
2411
2412err_restore_page:
2413 return phy_restore_page(phydev, old_page, ret);
2414}
2415
2416/**
2417 * yt8821_utp_init() - utp init
2418 * @phydev: a pointer to a &struct phy_device
2419 *
2420 * Returns: 0 or negative errno code
2421 */
2422static int yt8821_utp_init(struct phy_device *phydev)
2423{
2424 int old_page;
2425 int ret = 0;
2426 u16 mask;
2427 u16 save;
2428 u16 set;
2429
2430 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
2431 if (old_page < 0) {
2432 phydev_err(phydev, "Failed to select page: %d\n",
2433 old_page);
2434 goto err_restore_page;
2435 }
2436
2437 mask = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 |
2438 YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 |
2439 YT8821_UTP_EXT_RPDN_IPR_SHT_2500;
2440 set = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 |
2441 YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500;
2442 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_RPDN_CTRL_REG,
2443 mask, set);
2444 if (ret < 0)
2445 goto err_restore_page;
2446
2447 mask = YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER |
2448 YT8821_UTP_EXT_VGA_LPF1_CAP_2500;
2449 ret = ytphy_modify_ext(phydev,
2450 YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG,
2451 mask, 0);
2452 if (ret < 0)
2453 goto err_restore_page;
2454
2455 mask = YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER |
2456 YT8821_UTP_EXT_VGA_LPF2_CAP_2500;
2457 ret = ytphy_modify_ext(phydev,
2458 YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG,
2459 mask, 0);
2460 if (ret < 0)
2461 goto err_restore_page;
2462
2463 mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 |
2464 YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500;
2465 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500, 0x5a) |
2466 FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500, 0x3c);
2467 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_TRACE_CTRL_REG,
2468 mask, set);
2469 if (ret < 0)
2470 goto err_restore_page;
2471
2472 mask = YT8821_UTP_EXT_IPR_LNG_2500;
2473 set = FIELD_PREP(YT8821_UTP_EXT_IPR_LNG_2500, 0x6c);
2474 ret = ytphy_modify_ext(phydev,
2475 YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG,
2476 mask, set);
2477 if (ret < 0)
2478 goto err_restore_page;
2479
2480 mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000;
2481 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000, 0x2a);
2482 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_ECHO_CTRL_REG,
2483 mask, set);
2484 if (ret < 0)
2485 goto err_restore_page;
2486
2487 mask = YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000;
2488 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000, 0x22);
2489 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_GAIN_CTRL_REG,
2490 mask, set);
2491 if (ret < 0)
2492 goto err_restore_page;
2493
2494 mask = YT8821_UTP_EXT_TH_20DB_2500;
2495 set = FIELD_PREP(YT8821_UTP_EXT_TH_20DB_2500, 0x8000);
2496 ret = ytphy_modify_ext(phydev,
2497 YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG,
2498 mask, set);
2499 if (ret < 0)
2500 goto err_restore_page;
2501
2502 mask = YT8821_UTP_EXT_MU_COARSE_FR_F_FFE |
2503 YT8821_UTP_EXT_MU_COARSE_FR_F_FBE;
2504 set = FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FFE, 0x7) |
2505 FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FBE, 0x7);
2506 ret = ytphy_modify_ext(phydev,
2507 YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG,
2508 mask, set);
2509 if (ret < 0)
2510 goto err_restore_page;
2511
2512 mask = YT8821_UTP_EXT_MU_FINE_FR_F_FFE |
2513 YT8821_UTP_EXT_MU_FINE_FR_F_FBE;
2514 set = FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FFE, 0x2) |
2515 FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FBE, 0x2);
2516 ret = ytphy_modify_ext(phydev,
2517 YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG,
2518 mask, set);
2519 if (ret < 0)
2520 goto err_restore_page;
2521
2522 /* save YT8821_UTP_EXT_PI_CTRL_REG's val for use later */
2523 ret = ytphy_read_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG);
2524 if (ret < 0)
2525 goto err_restore_page;
2526
2527 save = ret;
2528
2529 mask = YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE |
2530 YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE |
2531 YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE |
2532 YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE |
2533 YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE;
2534 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG,
2535 mask, 0);
2536 if (ret < 0)
2537 goto err_restore_page;
2538
2539 /* restore YT8821_UTP_EXT_PI_CTRL_REG's val */
2540 ret = ytphy_write_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, save);
2541 if (ret < 0)
2542 goto err_restore_page;
2543
2544 mask = YT8821_UTP_EXT_FECHO_AMP_TH_HUGE;
2545 set = FIELD_PREP(YT8821_UTP_EXT_FECHO_AMP_TH_HUGE, 0x38);
2546 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_VCT_CFG6_CTRL_REG,
2547 mask, set);
2548 if (ret < 0)
2549 goto err_restore_page;
2550
2551 mask = YT8821_UTP_EXT_NFR_TX_ABILITY;
2552 set = YT8821_UTP_EXT_NFR_TX_ABILITY;
2553 ret = ytphy_modify_ext(phydev,
2554 YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG,
2555 mask, set);
2556 if (ret < 0)
2557 goto err_restore_page;
2558
2559 mask = YT8821_UTP_EXT_PLL_SPARE_CFG;
2560 set = FIELD_PREP(YT8821_UTP_EXT_PLL_SPARE_CFG, 0xe9);
2561 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PLL_CTRL_REG,
2562 mask, set);
2563 if (ret < 0)
2564 goto err_restore_page;
2565
2566 mask = YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG |
2567 YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG;
2568 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG, 0x64) |
2569 FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG, 0x64);
2570 ret = ytphy_modify_ext(phydev,
2571 YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG,
2572 mask, set);
2573 if (ret < 0)
2574 goto err_restore_page;
2575
2576 mask = YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG |
2577 YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG;
2578 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG, 0x64) |
2579 FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG, 0x64);
2580 ret = ytphy_modify_ext(phydev,
2581 YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG,
2582 mask, set);
2583 if (ret < 0)
2584 goto err_restore_page;
2585
2586 mask = YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG |
2587 YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG;
2588 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG, 0x64) |
2589 FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG, 0x64);
2590 ret = ytphy_modify_ext(phydev,
2591 YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG,
2592 mask, set);
2593 if (ret < 0)
2594 goto err_restore_page;
2595
2596 mask = YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG |
2597 YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG;
2598 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG, 0x64) |
2599 FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG, 0x64);
2600 ret = ytphy_modify_ext(phydev,
2601 YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG,
2602 mask, set);
2603
2604err_restore_page:
2605 return phy_restore_page(phydev, old_page, ret);
2606}
2607
2608/**
2609 * yt8821_auto_sleep_config() - phy auto sleep config
2610 * @phydev: a pointer to a &struct phy_device
2611 * @enable: true enable auto sleep, false disable auto sleep
2612 *
2613 * Returns: 0 or negative errno code
2614 */
2615static int yt8821_auto_sleep_config(struct phy_device *phydev,
2616 bool enable)
2617{
2618 int old_page;
2619 int ret = 0;
2620
2621 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
2622 if (old_page < 0) {
2623 phydev_err(phydev, "Failed to select page: %d\n",
2624 old_page);
2625 goto err_restore_page;
2626 }
2627
2628 ret = ytphy_modify_ext(phydev,
2629 YT8521_EXTREG_SLEEP_CONTROL1_REG,
2630 YT8521_ESC1R_SLEEP_SW,
2631 enable ? 1 : 0);
2632
2633err_restore_page:
2634 return phy_restore_page(phydev, old_page, ret);
2635}
2636
2637/**
2638 * yt8821_soft_reset() - soft reset utp and serdes
2639 * @phydev: a pointer to a &struct phy_device
2640 *
2641 * Returns: 0 or negative errno code
2642 */
2643static int yt8821_soft_reset(struct phy_device *phydev)
2644{
2645 return ytphy_modify_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG,
2646 YT8521_CCR_SW_RST, 0);
2647}
2648
2649/**
2650 * yt8821_config_init() - phy initializatioin
2651 * @phydev: a pointer to a &struct phy_device
2652 *
2653 * Returns: 0 or negative errno code
2654 */
2655static int yt8821_config_init(struct phy_device *phydev)
2656{
2657 u8 mode = YT8821_CHIP_MODE_AUTO_BX2500_SGMII;
2658 int ret;
2659 u16 set;
2660
2661 if (phydev->interface == PHY_INTERFACE_MODE_2500BASEX)
2662 mode = YT8821_CHIP_MODE_FORCE_BX2500;
2663
2664 set = FIELD_PREP(YT8521_CCR_MODE_SEL_MASK, mode);
2665 ret = ytphy_modify_ext_with_lock(phydev,
2666 YT8521_CHIP_CONFIG_REG,
2667 YT8521_CCR_MODE_SEL_MASK,
2668 set);
2669 if (ret < 0)
2670 return ret;
2671
2672 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
2673 phydev->possible_interfaces);
2674
2675 if (mode == YT8821_CHIP_MODE_AUTO_BX2500_SGMII) {
2676 __set_bit(PHY_INTERFACE_MODE_SGMII,
2677 phydev->possible_interfaces);
2678
2679 phydev->rate_matching = RATE_MATCH_NONE;
2680 } else if (mode == YT8821_CHIP_MODE_FORCE_BX2500) {
2681 phydev->rate_matching = RATE_MATCH_PAUSE;
2682 }
2683
2684 ret = yt8821_serdes_init(phydev);
2685 if (ret < 0)
2686 return ret;
2687
2688 ret = yt8821_utp_init(phydev);
2689 if (ret < 0)
2690 return ret;
2691
2692 /* disable auto sleep */
2693 ret = yt8821_auto_sleep_config(phydev, false);
2694 if (ret < 0)
2695 return ret;
2696
2697 /* soft reset */
2698 return yt8821_soft_reset(phydev);
2699}
2700
2701/**
2702 * yt8821_adjust_status() - update speed and duplex to phydev
2703 * @phydev: a pointer to a &struct phy_device
2704 * @val: read from YTPHY_SPECIFIC_STATUS_REG
2705 */
2706static void yt8821_adjust_status(struct phy_device *phydev, int val)
2707{
2708 int speed, duplex;
2709 int speed_mode;
2710
2711 duplex = FIELD_GET(YTPHY_SSR_DUPLEX, val);
2712 speed_mode = val & YTPHY_SSR_SPEED_MASK;
2713 switch (speed_mode) {
2714 case YTPHY_SSR_SPEED_10M:
2715 speed = SPEED_10;
2716 break;
2717 case YTPHY_SSR_SPEED_100M:
2718 speed = SPEED_100;
2719 break;
2720 case YTPHY_SSR_SPEED_1000M:
2721 speed = SPEED_1000;
2722 break;
2723 case YTPHY_SSR_SPEED_2500M:
2724 speed = SPEED_2500;
2725 break;
2726 default:
2727 speed = SPEED_UNKNOWN;
2728 break;
2729 }
2730
2731 phydev->speed = speed;
2732 phydev->duplex = duplex;
2733}
2734
2735/**
2736 * yt8821_update_interface() - update interface per current speed
2737 * @phydev: a pointer to a &struct phy_device
2738 */
2739static void yt8821_update_interface(struct phy_device *phydev)
2740{
2741 if (!phydev->link)
2742 return;
2743
2744 switch (phydev->speed) {
2745 case SPEED_2500:
2746 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
2747 break;
2748 case SPEED_1000:
2749 case SPEED_100:
2750 case SPEED_10:
2751 phydev->interface = PHY_INTERFACE_MODE_SGMII;
2752 break;
2753 default:
2754 phydev_warn(phydev, "phy speed err :%d\n", phydev->speed);
2755 break;
2756 }
2757}
2758
2759/**
2760 * yt8821_read_status() - determines the negotiated speed and duplex
2761 * @phydev: a pointer to a &struct phy_device
2762 *
2763 * Returns: 0 or negative errno code
2764 */
2765static int yt8821_read_status(struct phy_device *phydev)
2766{
2767 int link;
2768 int ret;
2769 int val;
2770
2771 ret = ytphy_write_ext_with_lock(phydev,
2772 YT8521_REG_SPACE_SELECT_REG,
2773 YT8521_RSSR_UTP_SPACE);
2774 if (ret < 0)
2775 return ret;
2776
2777 ret = genphy_read_status(phydev);
2778 if (ret < 0)
2779 return ret;
2780
2781 if (phydev->autoneg_complete) {
2782 ret = genphy_c45_read_lpa(phydev);
2783 if (ret < 0)
2784 return ret;
2785 }
2786
2787 ret = phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
2788 if (ret < 0)
2789 return ret;
2790
2791 val = ret;
2792
2793 link = val & YTPHY_SSR_LINK;
2794 if (link)
2795 yt8821_adjust_status(phydev, val);
2796
2797 if (link) {
2798 if (phydev->link == 0)
2799 phydev_dbg(phydev,
2800 "%s, phy addr: %d, link up\n",
2801 __func__, phydev->mdio.addr);
2802 phydev->link = 1;
2803 } else {
2804 if (phydev->link == 1)
2805 phydev_dbg(phydev,
2806 "%s, phy addr: %d, link down\n",
2807 __func__, phydev->mdio.addr);
2808 phydev->link = 0;
2809 }
2810
2811 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
2812 if (val < 0)
2813 return val;
2814
2815 if (FIELD_GET(YT8521_CCR_MODE_SEL_MASK, val) ==
2816 YT8821_CHIP_MODE_AUTO_BX2500_SGMII)
2817 yt8821_update_interface(phydev);
2818
2819 return 0;
2820}
2821
2822/**
2823 * yt8821_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register
2824 * @phydev: the phy_device struct
2825 * @mask: bit mask of bits to clear
2826 * @set: bit mask of bits to set
2827 *
2828 * NOTE: Convenience function which allows a PHY's BMCR register to be
2829 * modified as new register value = (old register value & ~mask) | set.
2830 *
2831 * Returns: 0 or negative errno code
2832 */
2833static int yt8821_modify_utp_fiber_bmcr(struct phy_device *phydev,
2834 u16 mask, u16 set)
2835{
2836 int ret;
2837
2838 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE,
2839 mask, set);
2840 if (ret < 0)
2841 return ret;
2842
2843 return yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE,
2844 mask, set);
2845}
2846
2847/**
2848 * yt8821_suspend() - suspend the hardware
2849 * @phydev: a pointer to a &struct phy_device
2850 *
2851 * Returns: 0 or negative errno code
2852 */
2853static int yt8821_suspend(struct phy_device *phydev)
2854{
2855 int wol_config;
2856
2857 wol_config = ytphy_read_ext_with_lock(phydev,
2858 YTPHY_WOL_CONFIG_REG);
2859 if (wol_config < 0)
2860 return wol_config;
2861
2862 /* if wol enable, do nothing */
2863 if (wol_config & YTPHY_WCR_ENABLE)
2864 return 0;
2865
2866 return yt8821_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN);
2867}
2868
2869/**
2870 * yt8821_resume() - resume the hardware
2871 * @phydev: a pointer to a &struct phy_device
2872 *
2873 * Returns: 0 or negative errno code
2874 */
2875static int yt8821_resume(struct phy_device *phydev)
2876{
2877 int wol_config;
2878 int ret;
2879
2880 /* disable auto sleep */
2881 ret = yt8821_auto_sleep_config(phydev, false);
2882 if (ret < 0)
2883 return ret;
2884
2885 wol_config = ytphy_read_ext_with_lock(phydev,
2886 YTPHY_WOL_CONFIG_REG);
2887 if (wol_config < 0)
2888 return wol_config;
2889
2890 /* if wol enable, do nothing */
2891 if (wol_config & YTPHY_WCR_ENABLE)
2892 return 0;
2893
2894 return yt8821_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0);
2895}
2896
2897static struct phy_driver motorcomm_phy_drvs[] = {
2898 {
2899 PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
2900 .name = "YT8511 Gigabit Ethernet",
2901 .config_init = yt8511_config_init,
2902 .suspend = genphy_suspend,
2903 .resume = genphy_resume,
2904 .read_page = yt8511_read_page,
2905 .write_page = yt8511_write_page,
2906 },
2907 {
2908 PHY_ID_MATCH_EXACT(PHY_ID_YT8521),
2909 .name = "YT8521 Gigabit Ethernet",
2910 .get_features = yt8521_get_features,
2911 .probe = yt8521_probe,
2912 .read_page = yt8521_read_page,
2913 .write_page = yt8521_write_page,
2914 .get_wol = ytphy_get_wol,
2915 .set_wol = ytphy_set_wol,
2916 .config_aneg = yt8521_config_aneg,
2917 .aneg_done = yt8521_aneg_done,
2918 .config_init = yt8521_config_init,
2919 .read_status = yt8521_read_status,
2920 .soft_reset = yt8521_soft_reset,
2921 .suspend = yt8521_suspend,
2922 .resume = yt8521_resume,
2923 },
2924 {
2925 PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
2926 .name = "YT8531 Gigabit Ethernet",
2927 .probe = yt8531_probe,
2928 .config_init = yt8531_config_init,
2929 .suspend = genphy_suspend,
2930 .resume = genphy_resume,
2931 .get_wol = ytphy_get_wol,
2932 .set_wol = yt8531_set_wol,
2933 .link_change_notify = yt8531_link_change_notify,
2934 },
2935 {
2936 PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
2937 .name = "YT8531S Gigabit Ethernet",
2938 .get_features = yt8521_get_features,
2939 .probe = yt8521_probe,
2940 .read_page = yt8521_read_page,
2941 .write_page = yt8521_write_page,
2942 .get_wol = ytphy_get_wol,
2943 .set_wol = ytphy_set_wol,
2944 .config_aneg = yt8521_config_aneg,
2945 .aneg_done = yt8521_aneg_done,
2946 .config_init = yt8521_config_init,
2947 .read_status = yt8521_read_status,
2948 .soft_reset = yt8521_soft_reset,
2949 .suspend = yt8521_suspend,
2950 .resume = yt8521_resume,
2951 },
2952 {
2953 PHY_ID_MATCH_EXACT(PHY_ID_YT8821),
2954 .name = "YT8821 2.5Gbps PHY",
2955 .get_features = yt8821_get_features,
2956 .read_page = yt8521_read_page,
2957 .write_page = yt8521_write_page,
2958 .get_wol = ytphy_get_wol,
2959 .set_wol = ytphy_set_wol,
2960 .config_aneg = genphy_config_aneg,
2961 .aneg_done = yt8821_aneg_done,
2962 .config_init = yt8821_config_init,
2963 .get_rate_matching = yt8821_get_rate_matching,
2964 .read_status = yt8821_read_status,
2965 .soft_reset = yt8821_soft_reset,
2966 .suspend = yt8821_suspend,
2967 .resume = yt8821_resume,
2968 },
2969};
2970
2971module_phy_driver(motorcomm_phy_drvs);
2972
2973MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S/8821 PHY driver");
2974MODULE_AUTHOR("Peter Geis");
2975MODULE_AUTHOR("Frank");
2976MODULE_LICENSE("GPL");
2977
2978static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
2979 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
2980 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
2981 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
2982 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
2983 { PHY_ID_MATCH_EXACT(PHY_ID_YT8821) },
2984 { /* sentinel */ }
2985};
2986
2987MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Motorcomm 8511/8521/8531/8531S PHY driver.
4 *
5 * Author: Peter Geis <pgwipeout@gmail.com>
6 * Author: Frank <Frank.Sae@motor-comm.com>
7 */
8
9#include <linux/etherdevice.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/phy.h>
13#include <linux/of.h>
14
15#define PHY_ID_YT8511 0x0000010a
16#define PHY_ID_YT8521 0x0000011a
17#define PHY_ID_YT8531 0x4f51e91b
18#define PHY_ID_YT8531S 0x4f51e91a
19
20/* YT8521/YT8531S Register Overview
21 * UTP Register space | FIBER Register space
22 * ------------------------------------------------------------
23 * | UTP MII | FIBER MII |
24 * | UTP MMD | |
25 * | UTP Extended | FIBER Extended |
26 * ------------------------------------------------------------
27 * | Common Extended |
28 * ------------------------------------------------------------
29 */
30
31/* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */
32
33/* Specific Function Control Register */
34#define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10
35
36/* 2b00 Manual MDI configuration
37 * 2b01 Manual MDIX configuration
38 * 2b10 Reserved
39 * 2b11 Enable automatic crossover for all modes *default*
40 */
41#define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5))
42#define YTPHY_SFCR_CROSSOVER_EN BIT(3)
43#define YTPHY_SFCR_SQE_TEST_EN BIT(2)
44#define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1)
45#define YTPHY_SFCR_JABBER_DIS BIT(0)
46
47/* Specific Status Register */
48#define YTPHY_SPECIFIC_STATUS_REG 0x11
49#define YTPHY_SSR_SPEED_MODE_OFFSET 14
50
51#define YTPHY_SSR_SPEED_MODE_MASK (BIT(15) | BIT(14))
52#define YTPHY_SSR_SPEED_10M 0x0
53#define YTPHY_SSR_SPEED_100M 0x1
54#define YTPHY_SSR_SPEED_1000M 0x2
55#define YTPHY_SSR_DUPLEX_OFFSET 13
56#define YTPHY_SSR_DUPLEX BIT(13)
57#define YTPHY_SSR_PAGE_RECEIVED BIT(12)
58#define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11)
59#define YTPHY_SSR_LINK BIT(10)
60#define YTPHY_SSR_MDIX_CROSSOVER BIT(6)
61#define YTPHY_SSR_DOWNGRADE BIT(5)
62#define YTPHY_SSR_TRANSMIT_PAUSE BIT(3)
63#define YTPHY_SSR_RECEIVE_PAUSE BIT(2)
64#define YTPHY_SSR_POLARITY BIT(1)
65#define YTPHY_SSR_JABBER BIT(0)
66
67/* Interrupt enable Register */
68#define YTPHY_INTERRUPT_ENABLE_REG 0x12
69#define YTPHY_IER_WOL BIT(6)
70
71/* Interrupt Status Register */
72#define YTPHY_INTERRUPT_STATUS_REG 0x13
73#define YTPHY_ISR_AUTONEG_ERR BIT(15)
74#define YTPHY_ISR_SPEED_CHANGED BIT(14)
75#define YTPHY_ISR_DUPLEX_CHANGED BIT(13)
76#define YTPHY_ISR_PAGE_RECEIVED BIT(12)
77#define YTPHY_ISR_LINK_FAILED BIT(11)
78#define YTPHY_ISR_LINK_SUCCESSED BIT(10)
79#define YTPHY_ISR_WOL BIT(6)
80#define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5)
81#define YTPHY_ISR_SERDES_LINK_FAILED BIT(3)
82#define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2)
83#define YTPHY_ISR_POLARITY_CHANGED BIT(1)
84#define YTPHY_ISR_JABBER_HAPPENED BIT(0)
85
86/* Speed Auto Downgrade Control Register */
87#define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14
88#define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5)
89
90/* If these bits are set to 3, the PHY attempts five times ( 3(set value) +
91 * additional 2) before downgrading, default 0x3
92 */
93#define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2)
94
95/* Rx Error Counter Register */
96#define YTPHY_RX_ERROR_COUNTER_REG 0x15
97
98/* Extended Register's Address Offset Register */
99#define YTPHY_PAGE_SELECT 0x1E
100
101/* Extended Register's Data Register */
102#define YTPHY_PAGE_DATA 0x1F
103
104/* FIBER Auto-Negotiation link partner ability */
105#define YTPHY_FLPA_PAUSE (0x3 << 7)
106#define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7)
107
108#define YT8511_PAGE_SELECT 0x1e
109#define YT8511_PAGE 0x1f
110#define YT8511_EXT_CLK_GATE 0x0c
111#define YT8511_EXT_DELAY_DRIVE 0x0d
112#define YT8511_EXT_SLEEP_CTRL 0x27
113
114/* 2b00 25m from pll
115 * 2b01 25m from xtl *default*
116 * 2b10 62.m from pll
117 * 2b11 125m from pll
118 */
119#define YT8511_CLK_125M (BIT(2) | BIT(1))
120#define YT8511_PLLON_SLP BIT(14)
121
122/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
123#define YT8511_DELAY_RX BIT(0)
124
125/* TX Gig-E Delay is bits 7:4, default 0x5
126 * TX Fast-E Delay is bits 15:12, default 0xf
127 * Delay = 150ps * N - 250ps
128 * On = 2000ps, off = 50ps
129 */
130#define YT8511_DELAY_GE_TX_EN (0xf << 4)
131#define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
132#define YT8511_DELAY_FE_TX_EN (0xf << 12)
133#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
134
135/* Extended register is different from MMD Register and MII Register.
136 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to
137 * operate extended register.
138 * Extended Register start
139 */
140
141/* Phy gmii clock gating Register */
142#define YT8521_CLOCK_GATING_REG 0xC
143#define YT8521_CGR_RX_CLK_EN BIT(12)
144
145#define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27
146#define YT8521_ESC1R_SLEEP_SW BIT(15)
147#define YT8521_ESC1R_PLLON_SLP BIT(14)
148
149/* Phy fiber Link timer cfg2 Register */
150#define YT8521_LINK_TIMER_CFG2_REG 0xA5
151#define YT8521_LTCR_EN_AUTOSEN BIT(15)
152
153/* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers
154 * of yt8521 phy. There is no need to switch reg space when operating these
155 * registers.
156 */
157
158#define YT8521_REG_SPACE_SELECT_REG 0xA000
159#define YT8521_RSSR_SPACE_MASK BIT(1)
160#define YT8521_RSSR_FIBER_SPACE (0x1 << 1)
161#define YT8521_RSSR_UTP_SPACE (0x0 << 1)
162#define YT8521_RSSR_TO_BE_ARBITRATED (0xFF)
163
164#define YT8521_CHIP_CONFIG_REG 0xA001
165#define YT8521_CCR_SW_RST BIT(15)
166#define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4)
167#define YT8531_LDO_VOL_3V3 0x0
168#define YT8531_LDO_VOL_1V8 0x2
169
170/* 1b0 disable 1.9ns rxc clock delay *default*
171 * 1b1 enable 1.9ns rxc clock delay
172 */
173#define YT8521_CCR_RXC_DLY_EN BIT(8)
174#define YT8521_CCR_RXC_DLY_1_900_NS 1900
175
176#define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0))
177#define YT8521_CCR_MODE_UTP_TO_RGMII 0
178#define YT8521_CCR_MODE_FIBER_TO_RGMII 1
179#define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2
180#define YT8521_CCR_MODE_UTP_TO_SGMII 3
181#define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4
182#define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5
183#define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6
184#define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7
185
186/* 3 phy polling modes,poll mode combines utp and fiber mode*/
187#define YT8521_MODE_FIBER 0x1
188#define YT8521_MODE_UTP 0x2
189#define YT8521_MODE_POLL 0x3
190
191#define YT8521_RGMII_CONFIG1_REG 0xA003
192/* 1b0 use original tx_clk_rgmii *default*
193 * 1b1 use inverted tx_clk_rgmii.
194 */
195#define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14)
196#define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10)
197#define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4)
198#define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0)
199#define YT8521_RC1R_RGMII_0_000_NS 0
200#define YT8521_RC1R_RGMII_0_150_NS 1
201#define YT8521_RC1R_RGMII_0_300_NS 2
202#define YT8521_RC1R_RGMII_0_450_NS 3
203#define YT8521_RC1R_RGMII_0_600_NS 4
204#define YT8521_RC1R_RGMII_0_750_NS 5
205#define YT8521_RC1R_RGMII_0_900_NS 6
206#define YT8521_RC1R_RGMII_1_050_NS 7
207#define YT8521_RC1R_RGMII_1_200_NS 8
208#define YT8521_RC1R_RGMII_1_350_NS 9
209#define YT8521_RC1R_RGMII_1_500_NS 10
210#define YT8521_RC1R_RGMII_1_650_NS 11
211#define YT8521_RC1R_RGMII_1_800_NS 12
212#define YT8521_RC1R_RGMII_1_950_NS 13
213#define YT8521_RC1R_RGMII_2_100_NS 14
214#define YT8521_RC1R_RGMII_2_250_NS 15
215
216#define YTPHY_MISC_CONFIG_REG 0xA006
217#define YTPHY_MCR_FIBER_SPEED_MASK BIT(0)
218#define YTPHY_MCR_FIBER_1000BX (0x1 << 0)
219#define YTPHY_MCR_FIBER_100FX (0x0 << 0)
220
221/* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */
222#define YTPHY_WOL_MACADDR2_REG 0xA007
223#define YTPHY_WOL_MACADDR1_REG 0xA008
224#define YTPHY_WOL_MACADDR0_REG 0xA009
225
226#define YTPHY_WOL_CONFIG_REG 0xA00A
227#define YTPHY_WCR_INTR_SEL BIT(6)
228#define YTPHY_WCR_ENABLE BIT(3)
229
230/* 2b00 84ms
231 * 2b01 168ms *default*
232 * 2b10 336ms
233 * 2b11 672ms
234 */
235#define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1))
236#define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1))
237
238/* 1b0 Interrupt and WOL events is level triggered and active LOW *default*
239 * 1b1 Interrupt and WOL events is pulse triggered and active LOW
240 */
241#define YTPHY_WCR_TYPE_PULSE BIT(0)
242
243#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010
244#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13)
245#define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */
246#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */
247#define YT8531_RGMII_RX_DS_DEFAULT 0x3
248
249#define YTPHY_SYNCE_CFG_REG 0xA012
250#define YT8521_SCR_SYNCE_ENABLE BIT(5)
251/* 1b0 output 25m clock
252 * 1b1 output 125m clock *default*
253 */
254#define YT8521_SCR_CLK_FRE_SEL_125M BIT(3)
255#define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1)
256#define YT8521_SCR_CLK_SRC_PLL_125M 0
257#define YT8521_SCR_CLK_SRC_UTP_RX 1
258#define YT8521_SCR_CLK_SRC_SDS_RX 2
259#define YT8521_SCR_CLK_SRC_REF_25M 3
260#define YT8531_SCR_SYNCE_ENABLE BIT(6)
261/* 1b0 output 25m clock *default*
262 * 1b1 output 125m clock
263 */
264#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4)
265#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1)
266#define YT8531_SCR_CLK_SRC_PLL_125M 0
267#define YT8531_SCR_CLK_SRC_UTP_RX 1
268#define YT8531_SCR_CLK_SRC_SDS_RX 2
269#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3
270#define YT8531_SCR_CLK_SRC_REF_25M 4
271#define YT8531_SCR_CLK_SRC_SSC_25M 5
272
273/* Extended Register end */
274
275#define YTPHY_DTS_OUTPUT_CLK_DIS 0
276#define YTPHY_DTS_OUTPUT_CLK_25M 25000000
277#define YTPHY_DTS_OUTPUT_CLK_125M 125000000
278
279struct yt8521_priv {
280 /* combo_advertising is used for case of YT8521 in combo mode,
281 * this means that yt8521 may work in utp or fiber mode which depends
282 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED).
283 */
284 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising);
285
286 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/
287 u8 polling_mode;
288 u8 strap_mode; /* 8 working modes */
289 /* current reg page of yt8521 phy:
290 * YT8521_RSSR_UTP_SPACE
291 * YT8521_RSSR_FIBER_SPACE
292 * YT8521_RSSR_TO_BE_ARBITRATED
293 */
294 u8 reg_page;
295};
296
297/**
298 * ytphy_read_ext() - read a PHY's extended register
299 * @phydev: a pointer to a &struct phy_device
300 * @regnum: register number to read
301 *
302 * NOTE:The caller must have taken the MDIO bus lock.
303 *
304 * returns the value of regnum reg or negative error code
305 */
306static int ytphy_read_ext(struct phy_device *phydev, u16 regnum)
307{
308 int ret;
309
310 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
311 if (ret < 0)
312 return ret;
313
314 return __phy_read(phydev, YTPHY_PAGE_DATA);
315}
316
317/**
318 * ytphy_read_ext_with_lock() - read a PHY's extended register
319 * @phydev: a pointer to a &struct phy_device
320 * @regnum: register number to read
321 *
322 * returns the value of regnum reg or negative error code
323 */
324static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum)
325{
326 int ret;
327
328 phy_lock_mdio_bus(phydev);
329 ret = ytphy_read_ext(phydev, regnum);
330 phy_unlock_mdio_bus(phydev);
331
332 return ret;
333}
334
335/**
336 * ytphy_write_ext() - write a PHY's extended register
337 * @phydev: a pointer to a &struct phy_device
338 * @regnum: register number to write
339 * @val: value to write to @regnum
340 *
341 * NOTE:The caller must have taken the MDIO bus lock.
342 *
343 * returns 0 or negative error code
344 */
345static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val)
346{
347 int ret;
348
349 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
350 if (ret < 0)
351 return ret;
352
353 return __phy_write(phydev, YTPHY_PAGE_DATA, val);
354}
355
356/**
357 * ytphy_write_ext_with_lock() - write a PHY's extended register
358 * @phydev: a pointer to a &struct phy_device
359 * @regnum: register number to write
360 * @val: value to write to @regnum
361 *
362 * returns 0 or negative error code
363 */
364static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum,
365 u16 val)
366{
367 int ret;
368
369 phy_lock_mdio_bus(phydev);
370 ret = ytphy_write_ext(phydev, regnum, val);
371 phy_unlock_mdio_bus(phydev);
372
373 return ret;
374}
375
376/**
377 * ytphy_modify_ext() - bits modify a PHY's extended register
378 * @phydev: a pointer to a &struct phy_device
379 * @regnum: register number to write
380 * @mask: bit mask of bits to clear
381 * @set: bit mask of bits to set
382 *
383 * NOTE: Convenience function which allows a PHY's extended register to be
384 * modified as new register value = (old register value & ~mask) | set.
385 * The caller must have taken the MDIO bus lock.
386 *
387 * returns 0 or negative error code
388 */
389static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
390 u16 set)
391{
392 int ret;
393
394 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
395 if (ret < 0)
396 return ret;
397
398 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set);
399}
400
401/**
402 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register
403 * @phydev: a pointer to a &struct phy_device
404 * @regnum: register number to write
405 * @mask: bit mask of bits to clear
406 * @set: bit mask of bits to set
407 *
408 * NOTE: Convenience function which allows a PHY's extended register to be
409 * modified as new register value = (old register value & ~mask) | set.
410 *
411 * returns 0 or negative error code
412 */
413static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum,
414 u16 mask, u16 set)
415{
416 int ret;
417
418 phy_lock_mdio_bus(phydev);
419 ret = ytphy_modify_ext(phydev, regnum, mask, set);
420 phy_unlock_mdio_bus(phydev);
421
422 return ret;
423}
424
425/**
426 * ytphy_get_wol() - report whether wake-on-lan is enabled
427 * @phydev: a pointer to a &struct phy_device
428 * @wol: a pointer to a &struct ethtool_wolinfo
429 *
430 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg.
431 */
432static void ytphy_get_wol(struct phy_device *phydev,
433 struct ethtool_wolinfo *wol)
434{
435 int wol_config;
436
437 wol->supported = WAKE_MAGIC;
438 wol->wolopts = 0;
439
440 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
441 if (wol_config < 0)
442 return;
443
444 if (wol_config & YTPHY_WCR_ENABLE)
445 wol->wolopts |= WAKE_MAGIC;
446}
447
448/**
449 * ytphy_set_wol() - turn wake-on-lan on or off
450 * @phydev: a pointer to a &struct phy_device
451 * @wol: a pointer to a &struct ethtool_wolinfo
452 *
453 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG
454 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The
455 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register.
456 *
457 * returns 0 or negative errno code
458 */
459static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
460{
461 struct net_device *p_attached_dev;
462 const u16 mac_addr_reg[] = {
463 YTPHY_WOL_MACADDR2_REG,
464 YTPHY_WOL_MACADDR1_REG,
465 YTPHY_WOL_MACADDR0_REG,
466 };
467 const u8 *mac_addr;
468 int old_page;
469 int ret = 0;
470 u16 mask;
471 u16 val;
472 u8 i;
473
474 if (wol->wolopts & WAKE_MAGIC) {
475 p_attached_dev = phydev->attached_dev;
476 if (!p_attached_dev)
477 return -ENODEV;
478
479 mac_addr = (const u8 *)p_attached_dev->dev_addr;
480 if (!is_valid_ether_addr(mac_addr))
481 return -EINVAL;
482
483 /* lock mdio bus then switch to utp reg space */
484 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
485 if (old_page < 0)
486 goto err_restore_page;
487
488 /* Store the device address for the magic packet */
489 for (i = 0; i < 3; i++) {
490 ret = ytphy_write_ext(phydev, mac_addr_reg[i],
491 ((mac_addr[i * 2] << 8)) |
492 (mac_addr[i * 2 + 1]));
493 if (ret < 0)
494 goto err_restore_page;
495 }
496
497 /* Enable WOL feature */
498 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
499 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
500 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
501 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val);
502 if (ret < 0)
503 goto err_restore_page;
504
505 /* Enable WOL interrupt */
506 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
507 YTPHY_IER_WOL);
508 if (ret < 0)
509 goto err_restore_page;
510
511 } else {
512 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
513 if (old_page < 0)
514 goto err_restore_page;
515
516 /* Disable WOL feature */
517 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
518 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0);
519
520 /* Disable WOL interrupt */
521 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
522 YTPHY_IER_WOL, 0);
523 if (ret < 0)
524 goto err_restore_page;
525 }
526
527err_restore_page:
528 return phy_restore_page(phydev, old_page, ret);
529}
530
531static int yt8531_set_wol(struct phy_device *phydev,
532 struct ethtool_wolinfo *wol)
533{
534 const u16 mac_addr_reg[] = {
535 YTPHY_WOL_MACADDR2_REG,
536 YTPHY_WOL_MACADDR1_REG,
537 YTPHY_WOL_MACADDR0_REG,
538 };
539 const u8 *mac_addr;
540 u16 mask, val;
541 int ret;
542 u8 i;
543
544 if (wol->wolopts & WAKE_MAGIC) {
545 mac_addr = phydev->attached_dev->dev_addr;
546
547 /* Store the device address for the magic packet */
548 for (i = 0; i < 3; i++) {
549 ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i],
550 ((mac_addr[i * 2] << 8)) |
551 (mac_addr[i * 2 + 1]));
552 if (ret < 0)
553 return ret;
554 }
555
556 /* Enable WOL feature */
557 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
558 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
559 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
560 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG,
561 mask, val);
562 if (ret < 0)
563 return ret;
564
565 /* Enable WOL interrupt */
566 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
567 YTPHY_IER_WOL);
568 if (ret < 0)
569 return ret;
570 } else {
571 /* Disable WOL feature */
572 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
573 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG,
574 mask, 0);
575
576 /* Disable WOL interrupt */
577 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
578 YTPHY_IER_WOL, 0);
579 if (ret < 0)
580 return ret;
581 }
582
583 return 0;
584}
585
586static int yt8511_read_page(struct phy_device *phydev)
587{
588 return __phy_read(phydev, YT8511_PAGE_SELECT);
589};
590
591static int yt8511_write_page(struct phy_device *phydev, int page)
592{
593 return __phy_write(phydev, YT8511_PAGE_SELECT, page);
594};
595
596static int yt8511_config_init(struct phy_device *phydev)
597{
598 int oldpage, ret = 0;
599 unsigned int ge, fe;
600
601 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
602 if (oldpage < 0)
603 goto err_restore_page;
604
605 /* set rgmii delay mode */
606 switch (phydev->interface) {
607 case PHY_INTERFACE_MODE_RGMII:
608 ge = YT8511_DELAY_GE_TX_DIS;
609 fe = YT8511_DELAY_FE_TX_DIS;
610 break;
611 case PHY_INTERFACE_MODE_RGMII_RXID:
612 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
613 fe = YT8511_DELAY_FE_TX_DIS;
614 break;
615 case PHY_INTERFACE_MODE_RGMII_TXID:
616 ge = YT8511_DELAY_GE_TX_EN;
617 fe = YT8511_DELAY_FE_TX_EN;
618 break;
619 case PHY_INTERFACE_MODE_RGMII_ID:
620 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
621 fe = YT8511_DELAY_FE_TX_EN;
622 break;
623 default: /* do not support other modes */
624 ret = -EOPNOTSUPP;
625 goto err_restore_page;
626 }
627
628 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
629 if (ret < 0)
630 goto err_restore_page;
631
632 /* set clock mode to 125mhz */
633 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
634 if (ret < 0)
635 goto err_restore_page;
636
637 /* fast ethernet delay is in a separate page */
638 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
639 if (ret < 0)
640 goto err_restore_page;
641
642 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
643 if (ret < 0)
644 goto err_restore_page;
645
646 /* leave pll enabled in sleep */
647 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
648 if (ret < 0)
649 goto err_restore_page;
650
651 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
652 if (ret < 0)
653 goto err_restore_page;
654
655err_restore_page:
656 return phy_restore_page(phydev, oldpage, ret);
657}
658
659/**
660 * yt8521_read_page() - read reg page
661 * @phydev: a pointer to a &struct phy_device
662 *
663 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/
664 * YT8521_RSSR_UTP_SPACE) or negative errno code
665 */
666static int yt8521_read_page(struct phy_device *phydev)
667{
668 int old_page;
669
670 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG);
671 if (old_page < 0)
672 return old_page;
673
674 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
675 return YT8521_RSSR_FIBER_SPACE;
676
677 return YT8521_RSSR_UTP_SPACE;
678};
679
680/**
681 * yt8521_write_page() - write reg page
682 * @phydev: a pointer to a &struct phy_device
683 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write.
684 *
685 * returns 0 or negative errno code
686 */
687static int yt8521_write_page(struct phy_device *phydev, int page)
688{
689 int mask = YT8521_RSSR_SPACE_MASK;
690 int set;
691
692 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
693 set = YT8521_RSSR_FIBER_SPACE;
694 else
695 set = YT8521_RSSR_UTP_SPACE;
696
697 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set);
698};
699
700/**
701 * struct ytphy_cfg_reg_map - map a config value to a register value
702 * @cfg: value in device configuration
703 * @reg: value in the register
704 */
705struct ytphy_cfg_reg_map {
706 u32 cfg;
707 u32 reg;
708};
709
710static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = {
711 /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */
712 { 0, YT8521_RC1R_RGMII_0_000_NS },
713 { 150, YT8521_RC1R_RGMII_0_150_NS },
714 { 300, YT8521_RC1R_RGMII_0_300_NS },
715 { 450, YT8521_RC1R_RGMII_0_450_NS },
716 { 600, YT8521_RC1R_RGMII_0_600_NS },
717 { 750, YT8521_RC1R_RGMII_0_750_NS },
718 { 900, YT8521_RC1R_RGMII_0_900_NS },
719 { 1050, YT8521_RC1R_RGMII_1_050_NS },
720 { 1200, YT8521_RC1R_RGMII_1_200_NS },
721 { 1350, YT8521_RC1R_RGMII_1_350_NS },
722 { 1500, YT8521_RC1R_RGMII_1_500_NS },
723 { 1650, YT8521_RC1R_RGMII_1_650_NS },
724 { 1800, YT8521_RC1R_RGMII_1_800_NS },
725 { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */
726 { 2100, YT8521_RC1R_RGMII_2_100_NS },
727 { 2250, YT8521_RC1R_RGMII_2_250_NS },
728
729 /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */
730 { 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS },
731 { 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS },
732 { 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS },
733 { 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS },
734 { 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS },
735 { 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS },
736 { 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS },
737 { 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS },
738 { 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS },
739 { 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS },
740 { 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS },
741 { 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS },
742 { 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS },
743 { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS },
744 { 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS },
745 { 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS }
746};
747
748static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
749 const char *prop_name,
750 const struct ytphy_cfg_reg_map *tbl,
751 int tb_size,
752 u16 *rxc_dly_en,
753 u32 dflt)
754{
755 struct device_node *node = phydev->mdio.dev.of_node;
756 int tb_size_half = tb_size / 2;
757 u32 val;
758 int i;
759
760 if (of_property_read_u32(node, prop_name, &val))
761 goto err_dts_val;
762
763 /* when rxc_dly_en is NULL, it is get the delay for tx, only half of
764 * tb_size is valid.
765 */
766 if (!rxc_dly_en)
767 tb_size = tb_size_half;
768
769 for (i = 0; i < tb_size; i++) {
770 if (tbl[i].cfg == val) {
771 if (rxc_dly_en && i < tb_size_half)
772 *rxc_dly_en = 0;
773 return tbl[i].reg;
774 }
775 }
776
777 phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n",
778 val, prop_name, dflt);
779
780err_dts_val:
781 /* when rxc_dly_en is not NULL, it is get the delay for rx.
782 * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps,
783 * so YT8521_CCR_RXC_DLY_EN should not be set.
784 */
785 if (rxc_dly_en)
786 *rxc_dly_en = 0;
787
788 return dflt;
789}
790
791static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
792{
793 int tb_size = ARRAY_SIZE(ytphy_rgmii_delays);
794 u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN;
795 u32 rx_reg, tx_reg;
796 u16 mask, val = 0;
797 int ret;
798
799 rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps",
800 ytphy_rgmii_delays, tb_size,
801 &rxc_dly_en,
802 YT8521_RC1R_RGMII_1_950_NS);
803 tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps",
804 ytphy_rgmii_delays, tb_size, NULL,
805 YT8521_RC1R_RGMII_1_950_NS);
806
807 switch (phydev->interface) {
808 case PHY_INTERFACE_MODE_RGMII:
809 rxc_dly_en = 0;
810 break;
811 case PHY_INTERFACE_MODE_RGMII_RXID:
812 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg);
813 break;
814 case PHY_INTERFACE_MODE_RGMII_TXID:
815 rxc_dly_en = 0;
816 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
817 break;
818 case PHY_INTERFACE_MODE_RGMII_ID:
819 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) |
820 FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
821 break;
822 default: /* do not support other modes */
823 return -EOPNOTSUPP;
824 }
825
826 ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
827 YT8521_CCR_RXC_DLY_EN, rxc_dly_en);
828 if (ret < 0)
829 return ret;
830
831 /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */
832 mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK;
833 return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val);
834}
835
836static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev)
837{
838 int ret;
839
840 phy_lock_mdio_bus(phydev);
841 ret = ytphy_rgmii_clk_delay_config(phydev);
842 phy_unlock_mdio_bus(phydev);
843
844 return ret;
845}
846
847/**
848 * struct ytphy_ldo_vol_map - map a current value to a register value
849 * @vol: ldo voltage
850 * @ds: value in the register
851 * @cur: value in device configuration
852 */
853struct ytphy_ldo_vol_map {
854 u32 vol;
855 u32 ds;
856 u32 cur;
857};
858
859static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = {
860 {.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200},
861 {.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100},
862 {.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700},
863 {.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910},
864 {.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110},
865 {.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600},
866 {.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970},
867 {.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350},
868 {.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070},
869 {.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080},
870 {.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370},
871 {.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680},
872 {.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020},
873 {.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450},
874 {.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740},
875 {.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140},
876};
877
878static u32 yt8531_get_ldo_vol(struct phy_device *phydev)
879{
880 u32 val;
881
882 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
883 val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val);
884
885 return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8;
886}
887
888static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur)
889{
890 u32 vol;
891 int i;
892
893 vol = yt8531_get_ldo_vol(phydev);
894 for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) {
895 if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur)
896 return yt8531_ldo_vol[i].ds;
897 }
898
899 return -EINVAL;
900}
901
902static int yt8531_set_ds(struct phy_device *phydev)
903{
904 struct device_node *node = phydev->mdio.dev.of_node;
905 u32 ds_field_low, ds_field_hi, val;
906 int ret, ds;
907
908 /* set rgmii rx clk driver strength */
909 if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) {
910 ds = yt8531_get_ds_map(phydev, val);
911 if (ds < 0)
912 return dev_err_probe(&phydev->mdio.dev, ds,
913 "No matching current value was found.\n");
914 } else {
915 ds = YT8531_RGMII_RX_DS_DEFAULT;
916 }
917
918 ret = ytphy_modify_ext_with_lock(phydev,
919 YTPHY_PAD_DRIVE_STRENGTH_REG,
920 YT8531_RGMII_RXC_DS_MASK,
921 FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds));
922 if (ret < 0)
923 return ret;
924
925 /* set rgmii rx data driver strength */
926 if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) {
927 ds = yt8531_get_ds_map(phydev, val);
928 if (ds < 0)
929 return dev_err_probe(&phydev->mdio.dev, ds,
930 "No matching current value was found.\n");
931 } else {
932 ds = YT8531_RGMII_RX_DS_DEFAULT;
933 }
934
935 ds_field_hi = FIELD_GET(BIT(2), ds);
936 ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi);
937
938 ds_field_low = FIELD_GET(GENMASK(1, 0), ds);
939 ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low);
940
941 ret = ytphy_modify_ext_with_lock(phydev,
942 YTPHY_PAD_DRIVE_STRENGTH_REG,
943 YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK,
944 ds_field_low | ds_field_hi);
945 if (ret < 0)
946 return ret;
947
948 return 0;
949}
950
951/**
952 * yt8521_probe() - read chip config then set suitable polling_mode
953 * @phydev: a pointer to a &struct phy_device
954 *
955 * returns 0 or negative errno code
956 */
957static int yt8521_probe(struct phy_device *phydev)
958{
959 struct device_node *node = phydev->mdio.dev.of_node;
960 struct device *dev = &phydev->mdio.dev;
961 struct yt8521_priv *priv;
962 int chip_config;
963 u16 mask, val;
964 u32 freq;
965 int ret;
966
967 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
968 if (!priv)
969 return -ENOMEM;
970
971 phydev->priv = priv;
972
973 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
974 if (chip_config < 0)
975 return chip_config;
976
977 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK;
978 switch (priv->strap_mode) {
979 case YT8521_CCR_MODE_FIBER_TO_RGMII:
980 case YT8521_CCR_MODE_SGPHY_TO_RGMAC:
981 case YT8521_CCR_MODE_SGMAC_TO_RGPHY:
982 priv->polling_mode = YT8521_MODE_FIBER;
983 priv->reg_page = YT8521_RSSR_FIBER_SPACE;
984 phydev->port = PORT_FIBRE;
985 break;
986 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII:
987 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO:
988 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE:
989 priv->polling_mode = YT8521_MODE_POLL;
990 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
991 phydev->port = PORT_NONE;
992 break;
993 case YT8521_CCR_MODE_UTP_TO_SGMII:
994 case YT8521_CCR_MODE_UTP_TO_RGMII:
995 priv->polling_mode = YT8521_MODE_UTP;
996 priv->reg_page = YT8521_RSSR_UTP_SPACE;
997 phydev->port = PORT_TP;
998 break;
999 }
1000 /* set default reg space */
1001 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1002 ret = ytphy_write_ext_with_lock(phydev,
1003 YT8521_REG_SPACE_SELECT_REG,
1004 priv->reg_page);
1005 if (ret < 0)
1006 return ret;
1007 }
1008
1009 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
1010 freq = YTPHY_DTS_OUTPUT_CLK_DIS;
1011
1012 if (phydev->drv->phy_id == PHY_ID_YT8521) {
1013 switch (freq) {
1014 case YTPHY_DTS_OUTPUT_CLK_DIS:
1015 mask = YT8521_SCR_SYNCE_ENABLE;
1016 val = 0;
1017 break;
1018 case YTPHY_DTS_OUTPUT_CLK_25M:
1019 mask = YT8521_SCR_SYNCE_ENABLE |
1020 YT8521_SCR_CLK_SRC_MASK |
1021 YT8521_SCR_CLK_FRE_SEL_125M;
1022 val = YT8521_SCR_SYNCE_ENABLE |
1023 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
1024 YT8521_SCR_CLK_SRC_REF_25M);
1025 break;
1026 case YTPHY_DTS_OUTPUT_CLK_125M:
1027 mask = YT8521_SCR_SYNCE_ENABLE |
1028 YT8521_SCR_CLK_SRC_MASK |
1029 YT8521_SCR_CLK_FRE_SEL_125M;
1030 val = YT8521_SCR_SYNCE_ENABLE |
1031 YT8521_SCR_CLK_FRE_SEL_125M |
1032 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
1033 YT8521_SCR_CLK_SRC_PLL_125M);
1034 break;
1035 default:
1036 phydev_warn(phydev, "Freq err:%u\n", freq);
1037 return -EINVAL;
1038 }
1039 } else if (phydev->drv->phy_id == PHY_ID_YT8531S) {
1040 switch (freq) {
1041 case YTPHY_DTS_OUTPUT_CLK_DIS:
1042 mask = YT8531_SCR_SYNCE_ENABLE;
1043 val = 0;
1044 break;
1045 case YTPHY_DTS_OUTPUT_CLK_25M:
1046 mask = YT8531_SCR_SYNCE_ENABLE |
1047 YT8531_SCR_CLK_SRC_MASK |
1048 YT8531_SCR_CLK_FRE_SEL_125M;
1049 val = YT8531_SCR_SYNCE_ENABLE |
1050 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
1051 YT8531_SCR_CLK_SRC_REF_25M);
1052 break;
1053 case YTPHY_DTS_OUTPUT_CLK_125M:
1054 mask = YT8531_SCR_SYNCE_ENABLE |
1055 YT8531_SCR_CLK_SRC_MASK |
1056 YT8531_SCR_CLK_FRE_SEL_125M;
1057 val = YT8531_SCR_SYNCE_ENABLE |
1058 YT8531_SCR_CLK_FRE_SEL_125M |
1059 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
1060 YT8531_SCR_CLK_SRC_PLL_125M);
1061 break;
1062 default:
1063 phydev_warn(phydev, "Freq err:%u\n", freq);
1064 return -EINVAL;
1065 }
1066 } else {
1067 phydev_warn(phydev, "PHY id err\n");
1068 return -EINVAL;
1069 }
1070
1071 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask,
1072 val);
1073}
1074
1075static int yt8531_probe(struct phy_device *phydev)
1076{
1077 struct device_node *node = phydev->mdio.dev.of_node;
1078 u16 mask, val;
1079 u32 freq;
1080
1081 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
1082 freq = YTPHY_DTS_OUTPUT_CLK_DIS;
1083
1084 switch (freq) {
1085 case YTPHY_DTS_OUTPUT_CLK_DIS:
1086 mask = YT8531_SCR_SYNCE_ENABLE;
1087 val = 0;
1088 break;
1089 case YTPHY_DTS_OUTPUT_CLK_25M:
1090 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
1091 YT8531_SCR_CLK_FRE_SEL_125M;
1092 val = YT8531_SCR_SYNCE_ENABLE |
1093 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
1094 YT8531_SCR_CLK_SRC_REF_25M);
1095 break;
1096 case YTPHY_DTS_OUTPUT_CLK_125M:
1097 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
1098 YT8531_SCR_CLK_FRE_SEL_125M;
1099 val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M |
1100 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
1101 YT8531_SCR_CLK_SRC_PLL_125M);
1102 break;
1103 default:
1104 phydev_warn(phydev, "Freq err:%u\n", freq);
1105 return -EINVAL;
1106 }
1107
1108 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask,
1109 val);
1110}
1111
1112/**
1113 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
1114 * @phydev: a pointer to a &struct phy_device
1115 *
1116 * NOTE:The caller must have taken the MDIO bus lock.
1117 *
1118 * returns 0 or negative errno code
1119 */
1120static int ytphy_utp_read_lpa(struct phy_device *phydev)
1121{
1122 int lpa, lpagb;
1123
1124 if (phydev->autoneg == AUTONEG_ENABLE) {
1125 if (!phydev->autoneg_complete) {
1126 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
1127 0);
1128 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
1129 return 0;
1130 }
1131
1132 if (phydev->is_gigabit_capable) {
1133 lpagb = __phy_read(phydev, MII_STAT1000);
1134 if (lpagb < 0)
1135 return lpagb;
1136
1137 if (lpagb & LPA_1000MSFAIL) {
1138 int adv = __phy_read(phydev, MII_CTRL1000);
1139
1140 if (adv < 0)
1141 return adv;
1142
1143 if (adv & CTL1000_ENABLE_MASTER)
1144 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
1145 else
1146 phydev_err(phydev, "Master/Slave resolution failed\n");
1147 return -ENOLINK;
1148 }
1149
1150 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
1151 lpagb);
1152 }
1153
1154 lpa = __phy_read(phydev, MII_LPA);
1155 if (lpa < 0)
1156 return lpa;
1157
1158 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1159 } else {
1160 linkmode_zero(phydev->lp_advertising);
1161 }
1162
1163 return 0;
1164}
1165
1166/**
1167 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber
1168 * mode, adjust speed and duplex.
1169 * @phydev: a pointer to a &struct phy_device
1170 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG
1171 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode)
1172 *
1173 * NOTE:The caller must have taken the MDIO bus lock.
1174 *
1175 * returns 0
1176 */
1177static int yt8521_adjust_status(struct phy_device *phydev, int status,
1178 bool is_utp)
1179{
1180 int speed_mode, duplex;
1181 int speed;
1182 int err;
1183 int lpa;
1184
1185 if (is_utp)
1186 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET;
1187 else
1188 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */
1189
1190 speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >>
1191 YTPHY_SSR_SPEED_MODE_OFFSET;
1192
1193 switch (speed_mode) {
1194 case YTPHY_SSR_SPEED_10M:
1195 if (is_utp)
1196 speed = SPEED_10;
1197 else
1198 /* for fiber, it will never run here, default to
1199 * SPEED_UNKNOWN
1200 */
1201 speed = SPEED_UNKNOWN;
1202 break;
1203 case YTPHY_SSR_SPEED_100M:
1204 speed = SPEED_100;
1205 break;
1206 case YTPHY_SSR_SPEED_1000M:
1207 speed = SPEED_1000;
1208 break;
1209 default:
1210 speed = SPEED_UNKNOWN;
1211 break;
1212 }
1213
1214 phydev->speed = speed;
1215 phydev->duplex = duplex;
1216
1217 if (is_utp) {
1218 err = ytphy_utp_read_lpa(phydev);
1219 if (err < 0)
1220 return err;
1221
1222 phy_resolve_aneg_pause(phydev);
1223 } else {
1224 lpa = __phy_read(phydev, MII_LPA);
1225 if (lpa < 0)
1226 return lpa;
1227
1228 /* only support 1000baseX Full */
1229 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1230 phydev->lp_advertising, lpa & LPA_1000XFULL);
1231
1232 if (!(lpa & YTPHY_FLPA_PAUSE)) {
1233 phydev->pause = 0;
1234 phydev->asym_pause = 0;
1235 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) {
1236 phydev->pause = 1;
1237 phydev->asym_pause = 1;
1238 } else {
1239 phydev->pause = 1;
1240 phydev->asym_pause = 0;
1241 }
1242 }
1243
1244 return 0;
1245}
1246
1247/**
1248 * yt8521_read_status_paged() - determines the speed and duplex of one page
1249 * @phydev: a pointer to a &struct phy_device
1250 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1251 * operate.
1252 *
1253 * returns 1 (utp or fiber link),0 (no link) or negative errno code
1254 */
1255static int yt8521_read_status_paged(struct phy_device *phydev, int page)
1256{
1257 int fiber_latch_val;
1258 int fiber_curr_val;
1259 int old_page;
1260 int ret = 0;
1261 int status;
1262 int link;
1263
1264 linkmode_zero(phydev->lp_advertising);
1265 phydev->duplex = DUPLEX_UNKNOWN;
1266 phydev->speed = SPEED_UNKNOWN;
1267 phydev->asym_pause = 0;
1268 phydev->pause = 0;
1269
1270 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber
1271 * respectively. but for utp/fiber combo mode, reg space should be
1272 * arbitrated based on media priority. by default, utp takes
1273 * priority. reg space should be properly set before read
1274 * YTPHY_SPECIFIC_STATUS_REG.
1275 */
1276
1277 page &= YT8521_RSSR_SPACE_MASK;
1278 old_page = phy_select_page(phydev, page);
1279 if (old_page < 0)
1280 goto err_restore_page;
1281
1282 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex
1283 * of the PHY is actually using.
1284 */
1285 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
1286 if (ret < 0)
1287 goto err_restore_page;
1288
1289 status = ret;
1290 link = !!(status & YTPHY_SSR_LINK);
1291
1292 /* When PHY is in fiber mode, speed transferred from 1000Mbps to
1293 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so
1294 * we need check MII_BMSR to identify such case.
1295 */
1296 if (page == YT8521_RSSR_FIBER_SPACE) {
1297 ret = __phy_read(phydev, MII_BMSR);
1298 if (ret < 0)
1299 goto err_restore_page;
1300
1301 fiber_latch_val = ret;
1302 ret = __phy_read(phydev, MII_BMSR);
1303 if (ret < 0)
1304 goto err_restore_page;
1305
1306 fiber_curr_val = ret;
1307 if (link && fiber_latch_val != fiber_curr_val) {
1308 link = 0;
1309 phydev_info(phydev,
1310 "%s, fiber link down detect, latch = %04x, curr = %04x\n",
1311 __func__, fiber_latch_val, fiber_curr_val);
1312 }
1313 } else {
1314 /* Read autonegotiation status */
1315 ret = __phy_read(phydev, MII_BMSR);
1316 if (ret < 0)
1317 goto err_restore_page;
1318
1319 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0;
1320 }
1321
1322 if (link) {
1323 if (page == YT8521_RSSR_UTP_SPACE)
1324 yt8521_adjust_status(phydev, status, true);
1325 else
1326 yt8521_adjust_status(phydev, status, false);
1327 }
1328 return phy_restore_page(phydev, old_page, link);
1329
1330err_restore_page:
1331 return phy_restore_page(phydev, old_page, ret);
1332}
1333
1334/**
1335 * yt8521_read_status() - determines the negotiated speed and duplex
1336 * @phydev: a pointer to a &struct phy_device
1337 *
1338 * returns 0 or negative errno code
1339 */
1340static int yt8521_read_status(struct phy_device *phydev)
1341{
1342 struct yt8521_priv *priv = phydev->priv;
1343 int link_fiber = 0;
1344 int link_utp;
1345 int link;
1346 int ret;
1347
1348 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1349 link = yt8521_read_status_paged(phydev, priv->reg_page);
1350 if (link < 0)
1351 return link;
1352 } else {
1353 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is
1354 * needed. by default, utp is higher priority.
1355 */
1356
1357 link_utp = yt8521_read_status_paged(phydev,
1358 YT8521_RSSR_UTP_SPACE);
1359 if (link_utp < 0)
1360 return link_utp;
1361
1362 if (!link_utp) {
1363 link_fiber = yt8521_read_status_paged(phydev,
1364 YT8521_RSSR_FIBER_SPACE);
1365 if (link_fiber < 0)
1366 return link_fiber;
1367 }
1368
1369 link = link_utp || link_fiber;
1370 }
1371
1372 if (link) {
1373 if (phydev->link == 0) {
1374 /* arbitrate reg space based on linkup media type. */
1375 if (priv->polling_mode == YT8521_MODE_POLL &&
1376 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
1377 if (link_fiber)
1378 priv->reg_page =
1379 YT8521_RSSR_FIBER_SPACE;
1380 else
1381 priv->reg_page = YT8521_RSSR_UTP_SPACE;
1382
1383 ret = ytphy_write_ext_with_lock(phydev,
1384 YT8521_REG_SPACE_SELECT_REG,
1385 priv->reg_page);
1386 if (ret < 0)
1387 return ret;
1388
1389 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP;
1390
1391 phydev_info(phydev, "%s, link up, media: %s\n",
1392 __func__,
1393 (phydev->port == PORT_TP) ?
1394 "UTP" : "Fiber");
1395 }
1396 }
1397 phydev->link = 1;
1398 } else {
1399 if (phydev->link == 1) {
1400 phydev_info(phydev, "%s, link down, media: %s\n",
1401 __func__, (phydev->port == PORT_TP) ?
1402 "UTP" : "Fiber");
1403
1404 /* When in YT8521_MODE_POLL mode, need prepare for next
1405 * arbitration.
1406 */
1407 if (priv->polling_mode == YT8521_MODE_POLL) {
1408 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
1409 phydev->port = PORT_NONE;
1410 }
1411 }
1412
1413 phydev->link = 0;
1414 }
1415
1416 return 0;
1417}
1418
1419/**
1420 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page
1421 * @phydev: the phy_device struct
1422 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate
1423 * @mask: bit mask of bits to clear
1424 * @set: bit mask of bits to set
1425 *
1426 * NOTE: Convenience function which allows a PHY's BMCR register to be
1427 * modified as new register value = (old register value & ~mask) | set.
1428 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1429 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1430 * If it is reset, it will wait for completion.
1431 *
1432 * returns 0 or negative errno code
1433 */
1434static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page,
1435 u16 mask, u16 set)
1436{
1437 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */
1438 int old_page;
1439 int ret = 0;
1440
1441 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
1442 if (old_page < 0)
1443 goto err_restore_page;
1444
1445 ret = __phy_modify(phydev, MII_BMCR, mask, set);
1446 if (ret < 0)
1447 goto err_restore_page;
1448
1449 /* If it is reset, need to wait for the reset to complete */
1450 if (set == BMCR_RESET) {
1451 while (max_cnt--) {
1452 usleep_range(1000, 1100);
1453 ret = __phy_read(phydev, MII_BMCR);
1454 if (ret < 0)
1455 goto err_restore_page;
1456
1457 if (!(ret & BMCR_RESET))
1458 return phy_restore_page(phydev, old_page, 0);
1459 }
1460 }
1461
1462err_restore_page:
1463 return phy_restore_page(phydev, old_page, ret);
1464}
1465
1466/**
1467 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register
1468 * @phydev: the phy_device struct
1469 * @mask: bit mask of bits to clear
1470 * @set: bit mask of bits to set
1471 *
1472 * NOTE: Convenience function which allows a PHY's BMCR register to be
1473 * modified as new register value = (old register value & ~mask) | set.
1474 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1475 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1476 *
1477 * returns 0 or negative errno code
1478 */
1479static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask,
1480 u16 set)
1481{
1482 struct yt8521_priv *priv = phydev->priv;
1483 int ret;
1484
1485 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1486 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask,
1487 set);
1488 if (ret < 0)
1489 return ret;
1490 } else {
1491 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE,
1492 mask, set);
1493 if (ret < 0)
1494 return ret;
1495
1496 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE,
1497 mask, set);
1498 if (ret < 0)
1499 return ret;
1500 }
1501 return 0;
1502}
1503
1504/**
1505 * yt8521_soft_reset() - called to issue a PHY software reset
1506 * @phydev: a pointer to a &struct phy_device
1507 *
1508 * returns 0 or negative errno code
1509 */
1510static int yt8521_soft_reset(struct phy_device *phydev)
1511{
1512 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET);
1513}
1514
1515/**
1516 * yt8521_suspend() - suspend the hardware
1517 * @phydev: a pointer to a &struct phy_device
1518 *
1519 * returns 0 or negative errno code
1520 */
1521static int yt8521_suspend(struct phy_device *phydev)
1522{
1523 int wol_config;
1524
1525 /* YTPHY_WOL_CONFIG_REG is common ext reg */
1526 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1527 if (wol_config < 0)
1528 return wol_config;
1529
1530 /* if wol enable, do nothing */
1531 if (wol_config & YTPHY_WCR_ENABLE)
1532 return 0;
1533
1534 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN);
1535}
1536
1537/**
1538 * yt8521_resume() - resume the hardware
1539 * @phydev: a pointer to a &struct phy_device
1540 *
1541 * returns 0 or negative errno code
1542 */
1543static int yt8521_resume(struct phy_device *phydev)
1544{
1545 int ret;
1546 int wol_config;
1547
1548 /* disable auto sleep */
1549 ret = ytphy_modify_ext_with_lock(phydev,
1550 YT8521_EXTREG_SLEEP_CONTROL1_REG,
1551 YT8521_ESC1R_SLEEP_SW, 0);
1552 if (ret < 0)
1553 return ret;
1554
1555 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1556 if (wol_config < 0)
1557 return wol_config;
1558
1559 /* if wol enable, do nothing */
1560 if (wol_config & YTPHY_WCR_ENABLE)
1561 return 0;
1562
1563 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0);
1564}
1565
1566/**
1567 * yt8521_config_init() - called to initialize the PHY
1568 * @phydev: a pointer to a &struct phy_device
1569 *
1570 * returns 0 or negative errno code
1571 */
1572static int yt8521_config_init(struct phy_device *phydev)
1573{
1574 struct device_node *node = phydev->mdio.dev.of_node;
1575 int old_page;
1576 int ret = 0;
1577
1578 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
1579 if (old_page < 0)
1580 goto err_restore_page;
1581
1582 /* set rgmii delay mode */
1583 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1584 ret = ytphy_rgmii_clk_delay_config(phydev);
1585 if (ret < 0)
1586 goto err_restore_page;
1587 }
1588
1589 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
1590 /* disable auto sleep */
1591 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
1592 YT8521_ESC1R_SLEEP_SW, 0);
1593 if (ret < 0)
1594 goto err_restore_page;
1595 }
1596
1597 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
1598 /* enable RXC clock when no wire plug */
1599 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
1600 YT8521_CGR_RX_CLK_EN, 0);
1601 if (ret < 0)
1602 goto err_restore_page;
1603 }
1604err_restore_page:
1605 return phy_restore_page(phydev, old_page, ret);
1606}
1607
1608static int yt8531_config_init(struct phy_device *phydev)
1609{
1610 struct device_node *node = phydev->mdio.dev.of_node;
1611 int ret;
1612
1613 ret = ytphy_rgmii_clk_delay_config_with_lock(phydev);
1614 if (ret < 0)
1615 return ret;
1616
1617 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
1618 /* disable auto sleep */
1619 ret = ytphy_modify_ext_with_lock(phydev,
1620 YT8521_EXTREG_SLEEP_CONTROL1_REG,
1621 YT8521_ESC1R_SLEEP_SW, 0);
1622 if (ret < 0)
1623 return ret;
1624 }
1625
1626 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
1627 /* enable RXC clock when no wire plug */
1628 ret = ytphy_modify_ext_with_lock(phydev,
1629 YT8521_CLOCK_GATING_REG,
1630 YT8521_CGR_RX_CLK_EN, 0);
1631 if (ret < 0)
1632 return ret;
1633 }
1634
1635 ret = yt8531_set_ds(phydev);
1636 if (ret < 0)
1637 return ret;
1638
1639 return 0;
1640}
1641
1642/**
1643 * yt8531_link_change_notify() - Adjust the tx clock direction according to
1644 * the current speed and dts config.
1645 * @phydev: a pointer to a &struct phy_device
1646 *
1647 * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please
1648 * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not
1649 * JH7110.
1650 */
1651static void yt8531_link_change_notify(struct phy_device *phydev)
1652{
1653 struct device_node *node = phydev->mdio.dev.of_node;
1654 bool tx_clk_1000_inverted = false;
1655 bool tx_clk_100_inverted = false;
1656 bool tx_clk_10_inverted = false;
1657 bool tx_clk_adj_enabled = false;
1658 u16 val = 0;
1659 int ret;
1660
1661 if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled"))
1662 tx_clk_adj_enabled = true;
1663
1664 if (!tx_clk_adj_enabled)
1665 return;
1666
1667 if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted"))
1668 tx_clk_10_inverted = true;
1669 if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted"))
1670 tx_clk_100_inverted = true;
1671 if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted"))
1672 tx_clk_1000_inverted = true;
1673
1674 if (phydev->speed < 0)
1675 return;
1676
1677 switch (phydev->speed) {
1678 case SPEED_1000:
1679 if (tx_clk_1000_inverted)
1680 val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1681 break;
1682 case SPEED_100:
1683 if (tx_clk_100_inverted)
1684 val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1685 break;
1686 case SPEED_10:
1687 if (tx_clk_10_inverted)
1688 val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1689 break;
1690 default:
1691 return;
1692 }
1693
1694 ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG,
1695 YT8521_RC1R_TX_CLK_SEL_INVERTED, val);
1696 if (ret < 0)
1697 phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret);
1698}
1699
1700/**
1701 * yt8521_prepare_fiber_features() - A small helper function that setup
1702 * fiber's features.
1703 * @phydev: a pointer to a &struct phy_device
1704 * @dst: a pointer to store fiber's features
1705 */
1706static void yt8521_prepare_fiber_features(struct phy_device *phydev,
1707 unsigned long *dst)
1708{
1709 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst);
1710 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst);
1711 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst);
1712 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst);
1713}
1714
1715/**
1716 * yt8521_fiber_setup_forced - configures/forces speed from @phydev
1717 * @phydev: target phy_device struct
1718 *
1719 * NOTE:The caller must have taken the MDIO bus lock.
1720 *
1721 * returns 0 or negative errno code
1722 */
1723static int yt8521_fiber_setup_forced(struct phy_device *phydev)
1724{
1725 u16 val;
1726 int ret;
1727
1728 if (phydev->speed == SPEED_1000)
1729 val = YTPHY_MCR_FIBER_1000BX;
1730 else if (phydev->speed == SPEED_100)
1731 val = YTPHY_MCR_FIBER_100FX;
1732 else
1733 return -EINVAL;
1734
1735 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1736 if (ret < 0)
1737 return ret;
1738
1739 /* disable Fiber auto sensing */
1740 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1741 YT8521_LTCR_EN_AUTOSEN, 0);
1742 if (ret < 0)
1743 return ret;
1744
1745 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG,
1746 YTPHY_MCR_FIBER_SPEED_MASK, val);
1747 if (ret < 0)
1748 return ret;
1749
1750 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1751 YT8521_CCR_SW_RST, 0);
1752}
1753
1754/**
1755 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation
1756 * @phydev: target phy_device struct
1757 * @restart: whether aneg restart is requested
1758 *
1759 * NOTE:The caller must have taken the MDIO bus lock.
1760 *
1761 * returns 0 or negative errno code
1762 */
1763static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
1764{
1765 int ret;
1766
1767 if (!restart) {
1768 /* Advertisement hasn't changed, but maybe aneg was never on to
1769 * begin with? Or maybe phy was isolated?
1770 */
1771 ret = __phy_read(phydev, MII_BMCR);
1772 if (ret < 0)
1773 return ret;
1774
1775 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
1776 restart = true;
1777 }
1778 /* Enable and Restart Autonegotiation
1779 * Don't isolate the PHY if we're negotiating
1780 */
1781 if (restart)
1782 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
1783 BMCR_ANENABLE | BMCR_ANRESTART);
1784
1785 return 0;
1786}
1787
1788/**
1789 * yt8521_fiber_config_aneg - restart auto-negotiation or write
1790 * YTPHY_MISC_CONFIG_REG.
1791 * @phydev: target phy_device struct
1792 *
1793 * NOTE:The caller must have taken the MDIO bus lock.
1794 *
1795 * returns 0 or negative errno code
1796 */
1797static int yt8521_fiber_config_aneg(struct phy_device *phydev)
1798{
1799 int err, changed = 0;
1800 int bmcr;
1801 u16 adv;
1802
1803 if (phydev->autoneg != AUTONEG_ENABLE)
1804 return yt8521_fiber_setup_forced(phydev);
1805
1806 /* enable Fiber auto sensing */
1807 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1808 0, YT8521_LTCR_EN_AUTOSEN);
1809 if (err < 0)
1810 return err;
1811
1812 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1813 YT8521_CCR_SW_RST, 0);
1814 if (err < 0)
1815 return err;
1816
1817 bmcr = __phy_read(phydev, MII_BMCR);
1818 if (bmcr < 0)
1819 return bmcr;
1820
1821 /* When it is coming from fiber forced mode, add bmcr power down
1822 * and power up to let aneg work fine.
1823 */
1824 if (!(bmcr & BMCR_ANENABLE)) {
1825 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
1826 usleep_range(1000, 1100);
1827 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
1828 }
1829
1830 adv = linkmode_adv_to_mii_adv_x(phydev->advertising,
1831 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
1832
1833 /* Setup fiber advertisement */
1834 err = __phy_modify_changed(phydev, MII_ADVERTISE,
1835 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
1836 ADVERTISE_1000XPAUSE |
1837 ADVERTISE_1000XPSE_ASYM,
1838 adv);
1839 if (err < 0)
1840 return err;
1841
1842 if (err > 0)
1843 changed = 1;
1844
1845 return ytphy_check_and_restart_aneg(phydev, changed);
1846}
1847
1848/**
1849 * ytphy_setup_master_slave
1850 * @phydev: target phy_device struct
1851 *
1852 * NOTE: The caller must have taken the MDIO bus lock.
1853 *
1854 * returns 0 or negative errno code
1855 */
1856static int ytphy_setup_master_slave(struct phy_device *phydev)
1857{
1858 u16 ctl = 0;
1859
1860 if (!phydev->is_gigabit_capable)
1861 return 0;
1862
1863 switch (phydev->master_slave_set) {
1864 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
1865 ctl |= CTL1000_PREFER_MASTER;
1866 break;
1867 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
1868 break;
1869 case MASTER_SLAVE_CFG_MASTER_FORCE:
1870 ctl |= CTL1000_AS_MASTER;
1871 fallthrough;
1872 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1873 ctl |= CTL1000_ENABLE_MASTER;
1874 break;
1875 case MASTER_SLAVE_CFG_UNKNOWN:
1876 case MASTER_SLAVE_CFG_UNSUPPORTED:
1877 return 0;
1878 default:
1879 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1880 return -EOPNOTSUPP;
1881 }
1882
1883 return __phy_modify_changed(phydev, MII_CTRL1000,
1884 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
1885 CTL1000_PREFER_MASTER), ctl);
1886}
1887
1888/**
1889 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters
1890 * @phydev: target phy_device struct
1891 *
1892 * NOTE: Writes MII_ADVERTISE with the appropriate values,
1893 * after sanitizing the values to make sure we only advertise
1894 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
1895 * hasn't changed, and > 0 if it has changed.
1896 * The caller must have taken the MDIO bus lock.
1897 *
1898 * returns 0 or negative errno code
1899 */
1900static int ytphy_utp_config_advert(struct phy_device *phydev)
1901{
1902 int err, bmsr, changed = 0;
1903 u32 adv;
1904
1905 /* Only allow advertising what this PHY supports */
1906 linkmode_and(phydev->advertising, phydev->advertising,
1907 phydev->supported);
1908
1909 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
1910
1911 /* Setup standard advertisement */
1912 err = __phy_modify_changed(phydev, MII_ADVERTISE,
1913 ADVERTISE_ALL | ADVERTISE_100BASE4 |
1914 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
1915 adv);
1916 if (err < 0)
1917 return err;
1918 if (err > 0)
1919 changed = 1;
1920
1921 bmsr = __phy_read(phydev, MII_BMSR);
1922 if (bmsr < 0)
1923 return bmsr;
1924
1925 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
1926 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
1927 * logical 1.
1928 */
1929 if (!(bmsr & BMSR_ESTATEN))
1930 return changed;
1931
1932 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1933
1934 err = __phy_modify_changed(phydev, MII_CTRL1000,
1935 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
1936 adv);
1937 if (err < 0)
1938 return err;
1939 if (err > 0)
1940 changed = 1;
1941
1942 return changed;
1943}
1944
1945/**
1946 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR
1947 * @phydev: target phy_device struct
1948 * @changed: whether autoneg is requested
1949 *
1950 * NOTE: If auto-negotiation is enabled, we configure the
1951 * advertising, and then restart auto-negotiation. If it is not
1952 * enabled, then we write the BMCR.
1953 * The caller must have taken the MDIO bus lock.
1954 *
1955 * returns 0 or negative errno code
1956 */
1957static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed)
1958{
1959 int err;
1960 u16 ctl;
1961
1962 err = ytphy_setup_master_slave(phydev);
1963 if (err < 0)
1964 return err;
1965 else if (err)
1966 changed = true;
1967
1968 if (phydev->autoneg != AUTONEG_ENABLE) {
1969 /* configures/forces speed/duplex from @phydev */
1970
1971 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
1972
1973 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK |
1974 BMCR_ISOLATE | BMCR_PDOWN), ctl);
1975 }
1976
1977 err = ytphy_utp_config_advert(phydev);
1978 if (err < 0) /* error */
1979 return err;
1980 else if (err)
1981 changed = true;
1982
1983 return ytphy_check_and_restart_aneg(phydev, changed);
1984}
1985
1986/**
1987 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg
1988 * of one page
1989 * @phydev: a pointer to a &struct phy_device
1990 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1991 * operate.
1992 *
1993 * returns 0 or negative errno code
1994 */
1995static int yt8521_config_aneg_paged(struct phy_device *phydev, int page)
1996{
1997 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported);
1998 struct yt8521_priv *priv = phydev->priv;
1999 int old_page;
2000 int ret = 0;
2001
2002 page &= YT8521_RSSR_SPACE_MASK;
2003
2004 old_page = phy_select_page(phydev, page);
2005 if (old_page < 0)
2006 goto err_restore_page;
2007
2008 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
2009 * phydev->advertising should be updated.
2010 */
2011 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
2012 linkmode_zero(fiber_supported);
2013 yt8521_prepare_fiber_features(phydev, fiber_supported);
2014
2015 /* prepare fiber_supported, then setup advertising. */
2016 if (page == YT8521_RSSR_FIBER_SPACE) {
2017 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2018 fiber_supported);
2019 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2020 fiber_supported);
2021 linkmode_and(phydev->advertising,
2022 priv->combo_advertising, fiber_supported);
2023 } else {
2024 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */
2025 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2026 fiber_supported);
2027 linkmode_andnot(phydev->advertising,
2028 priv->combo_advertising,
2029 fiber_supported);
2030 }
2031 }
2032
2033 if (page == YT8521_RSSR_FIBER_SPACE)
2034 ret = yt8521_fiber_config_aneg(phydev);
2035 else
2036 ret = ytphy_utp_config_aneg(phydev, false);
2037
2038err_restore_page:
2039 return phy_restore_page(phydev, old_page, ret);
2040}
2041
2042/**
2043 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged
2044 * @phydev: a pointer to a &struct phy_device
2045 *
2046 * returns 0 or negative errno code
2047 */
2048static int yt8521_config_aneg(struct phy_device *phydev)
2049{
2050 struct yt8521_priv *priv = phydev->priv;
2051 int ret;
2052
2053 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
2054 ret = yt8521_config_aneg_paged(phydev, priv->reg_page);
2055 if (ret < 0)
2056 return ret;
2057 } else {
2058 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
2059 * phydev->advertising need to be saved at first run.
2060 * Because it contains the advertising which supported by both
2061 * mac and yt8521(utp and fiber).
2062 */
2063 if (linkmode_empty(priv->combo_advertising)) {
2064 linkmode_copy(priv->combo_advertising,
2065 phydev->advertising);
2066 }
2067
2068 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE);
2069 if (ret < 0)
2070 return ret;
2071
2072 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE);
2073 if (ret < 0)
2074 return ret;
2075
2076 /* we don't known which will be link, so restore
2077 * phydev->advertising as default value.
2078 */
2079 linkmode_copy(phydev->advertising, priv->combo_advertising);
2080 }
2081 return 0;
2082}
2083
2084/**
2085 * yt8521_aneg_done_paged() - determines the auto negotiation result of one
2086 * page.
2087 * @phydev: a pointer to a &struct phy_device
2088 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
2089 * operate.
2090 *
2091 * returns 0(no link)or 1(fiber or utp link) or negative errno code
2092 */
2093static int yt8521_aneg_done_paged(struct phy_device *phydev, int page)
2094{
2095 int old_page;
2096 int ret = 0;
2097 int link;
2098
2099 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
2100 if (old_page < 0)
2101 goto err_restore_page;
2102
2103 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
2104 if (ret < 0)
2105 goto err_restore_page;
2106
2107 link = !!(ret & YTPHY_SSR_LINK);
2108 ret = link;
2109
2110err_restore_page:
2111 return phy_restore_page(phydev, old_page, ret);
2112}
2113
2114/**
2115 * yt8521_aneg_done() - determines the auto negotiation result
2116 * @phydev: a pointer to a &struct phy_device
2117 *
2118 * returns 0(no link)or 1(fiber or utp link) or negative errno code
2119 */
2120static int yt8521_aneg_done(struct phy_device *phydev)
2121{
2122 struct yt8521_priv *priv = phydev->priv;
2123 int link_fiber = 0;
2124 int link_utp;
2125 int link;
2126
2127 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
2128 link = yt8521_aneg_done_paged(phydev, priv->reg_page);
2129 } else {
2130 link_utp = yt8521_aneg_done_paged(phydev,
2131 YT8521_RSSR_UTP_SPACE);
2132 if (link_utp < 0)
2133 return link_utp;
2134
2135 if (!link_utp) {
2136 link_fiber = yt8521_aneg_done_paged(phydev,
2137 YT8521_RSSR_FIBER_SPACE);
2138 if (link_fiber < 0)
2139 return link_fiber;
2140 }
2141 link = link_fiber || link_utp;
2142 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n",
2143 __func__, link_fiber, link_utp);
2144 }
2145
2146 return link;
2147}
2148
2149/**
2150 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers
2151 * @phydev: target phy_device struct
2152 *
2153 * NOTE: Reads the PHY's abilities and populates
2154 * phydev->supported accordingly.
2155 * The caller must have taken the MDIO bus lock.
2156 *
2157 * returns 0 or negative errno code
2158 */
2159static int ytphy_utp_read_abilities(struct phy_device *phydev)
2160{
2161 int val;
2162
2163 linkmode_set_bit_array(phy_basic_ports_array,
2164 ARRAY_SIZE(phy_basic_ports_array),
2165 phydev->supported);
2166
2167 val = __phy_read(phydev, MII_BMSR);
2168 if (val < 0)
2169 return val;
2170
2171 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
2172 val & BMSR_ANEGCAPABLE);
2173
2174 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
2175 val & BMSR_100FULL);
2176 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
2177 val & BMSR_100HALF);
2178 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
2179 val & BMSR_10FULL);
2180 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
2181 val & BMSR_10HALF);
2182
2183 if (val & BMSR_ESTATEN) {
2184 val = __phy_read(phydev, MII_ESTATUS);
2185 if (val < 0)
2186 return val;
2187
2188 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2189 phydev->supported, val & ESTATUS_1000_TFULL);
2190 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
2191 phydev->supported, val & ESTATUS_1000_THALF);
2192 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2193 phydev->supported, val & ESTATUS_1000_XFULL);
2194 }
2195
2196 return 0;
2197}
2198
2199/**
2200 * yt8521_get_features_paged() - read supported link modes for one page
2201 * @phydev: a pointer to a &struct phy_device
2202 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
2203 * operate.
2204 *
2205 * returns 0 or negative errno code
2206 */
2207static int yt8521_get_features_paged(struct phy_device *phydev, int page)
2208{
2209 int old_page;
2210 int ret = 0;
2211
2212 page &= YT8521_RSSR_SPACE_MASK;
2213 old_page = phy_select_page(phydev, page);
2214 if (old_page < 0)
2215 goto err_restore_page;
2216
2217 if (page == YT8521_RSSR_FIBER_SPACE) {
2218 linkmode_zero(phydev->supported);
2219 yt8521_prepare_fiber_features(phydev, phydev->supported);
2220 } else {
2221 ret = ytphy_utp_read_abilities(phydev);
2222 if (ret < 0)
2223 goto err_restore_page;
2224 }
2225
2226err_restore_page:
2227 return phy_restore_page(phydev, old_page, ret);
2228}
2229
2230/**
2231 * yt8521_get_features - switch reg space then call yt8521_get_features_paged
2232 * @phydev: target phy_device struct
2233 *
2234 * returns 0 or negative errno code
2235 */
2236static int yt8521_get_features(struct phy_device *phydev)
2237{
2238 struct yt8521_priv *priv = phydev->priv;
2239 int ret;
2240
2241 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
2242 ret = yt8521_get_features_paged(phydev, priv->reg_page);
2243 } else {
2244 ret = yt8521_get_features_paged(phydev,
2245 YT8521_RSSR_UTP_SPACE);
2246 if (ret < 0)
2247 return ret;
2248
2249 /* add fiber's features to phydev->supported */
2250 yt8521_prepare_fiber_features(phydev, phydev->supported);
2251 }
2252 return ret;
2253}
2254
2255static struct phy_driver motorcomm_phy_drvs[] = {
2256 {
2257 PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
2258 .name = "YT8511 Gigabit Ethernet",
2259 .config_init = yt8511_config_init,
2260 .suspend = genphy_suspend,
2261 .resume = genphy_resume,
2262 .read_page = yt8511_read_page,
2263 .write_page = yt8511_write_page,
2264 },
2265 {
2266 PHY_ID_MATCH_EXACT(PHY_ID_YT8521),
2267 .name = "YT8521 Gigabit Ethernet",
2268 .get_features = yt8521_get_features,
2269 .probe = yt8521_probe,
2270 .read_page = yt8521_read_page,
2271 .write_page = yt8521_write_page,
2272 .get_wol = ytphy_get_wol,
2273 .set_wol = ytphy_set_wol,
2274 .config_aneg = yt8521_config_aneg,
2275 .aneg_done = yt8521_aneg_done,
2276 .config_init = yt8521_config_init,
2277 .read_status = yt8521_read_status,
2278 .soft_reset = yt8521_soft_reset,
2279 .suspend = yt8521_suspend,
2280 .resume = yt8521_resume,
2281 },
2282 {
2283 PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
2284 .name = "YT8531 Gigabit Ethernet",
2285 .probe = yt8531_probe,
2286 .config_init = yt8531_config_init,
2287 .suspend = genphy_suspend,
2288 .resume = genphy_resume,
2289 .get_wol = ytphy_get_wol,
2290 .set_wol = yt8531_set_wol,
2291 .link_change_notify = yt8531_link_change_notify,
2292 },
2293 {
2294 PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
2295 .name = "YT8531S Gigabit Ethernet",
2296 .get_features = yt8521_get_features,
2297 .probe = yt8521_probe,
2298 .read_page = yt8521_read_page,
2299 .write_page = yt8521_write_page,
2300 .get_wol = ytphy_get_wol,
2301 .set_wol = ytphy_set_wol,
2302 .config_aneg = yt8521_config_aneg,
2303 .aneg_done = yt8521_aneg_done,
2304 .config_init = yt8521_config_init,
2305 .read_status = yt8521_read_status,
2306 .soft_reset = yt8521_soft_reset,
2307 .suspend = yt8521_suspend,
2308 .resume = yt8521_resume,
2309 },
2310};
2311
2312module_phy_driver(motorcomm_phy_drvs);
2313
2314MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S PHY driver");
2315MODULE_AUTHOR("Peter Geis");
2316MODULE_AUTHOR("Frank");
2317MODULE_LICENSE("GPL");
2318
2319static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
2320 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
2321 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
2322 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
2323 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
2324 { /* sentinel */ }
2325};
2326
2327MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);