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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2021 Intel Corporation
4 */
5
6/**
7 * DOC: display pinning helpers
8 */
9
10#include "gem/i915_gem_domain.h"
11#include "gem/i915_gem_object.h"
12
13#include "i915_drv.h"
14#include "intel_atomic_plane.h"
15#include "intel_display_types.h"
16#include "intel_dpt.h"
17#include "intel_fb.h"
18#include "intel_fb_pin.h"
19
20static struct i915_vma *
21intel_fb_pin_to_dpt(const struct drm_framebuffer *fb,
22 const struct i915_gtt_view *view,
23 unsigned int alignment,
24 unsigned long *out_flags,
25 struct i915_address_space *vm)
26{
27 struct drm_device *dev = fb->dev;
28 struct drm_i915_private *dev_priv = to_i915(dev);
29 struct drm_gem_object *_obj = intel_fb_bo(fb);
30 struct drm_i915_gem_object *obj = to_intel_bo(_obj);
31 struct i915_gem_ww_ctx ww;
32 struct i915_vma *vma;
33 int ret;
34
35 /*
36 * We are not syncing against the binding (and potential migrations)
37 * below, so this vm must never be async.
38 */
39 if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags))
40 return ERR_PTR(-EINVAL);
41
42 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
43 return ERR_PTR(-EINVAL);
44
45 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
46
47 for_i915_gem_ww(&ww, ret, true) {
48 ret = i915_gem_object_lock(obj, &ww);
49 if (ret)
50 continue;
51
52 if (HAS_LMEM(dev_priv)) {
53 unsigned int flags = obj->flags;
54
55 /*
56 * For this type of buffer we need to able to read from the CPU
57 * the clear color value found in the buffer, hence we need to
58 * ensure it is always in the mappable part of lmem, if this is
59 * a small-bar device.
60 */
61 if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
62 flags &= ~I915_BO_ALLOC_GPU_ONLY;
63 ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0,
64 flags);
65 if (ret)
66 continue;
67 }
68
69 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
70 if (ret)
71 continue;
72
73 vma = i915_vma_instance(obj, vm, view);
74 if (IS_ERR(vma)) {
75 ret = PTR_ERR(vma);
76 continue;
77 }
78
79 if (i915_vma_misplaced(vma, 0, alignment, 0)) {
80 ret = i915_vma_unbind(vma);
81 if (ret)
82 continue;
83 }
84
85 ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL);
86 if (ret)
87 continue;
88 }
89 if (ret) {
90 vma = ERR_PTR(ret);
91 goto err;
92 }
93
94 vma->display_alignment = max(vma->display_alignment, alignment);
95
96 i915_gem_object_flush_if_display(obj);
97
98 i915_vma_get(vma);
99err:
100 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
101
102 return vma;
103}
104
105struct i915_vma *
106intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
107 const struct i915_gtt_view *view,
108 unsigned int alignment,
109 unsigned int phys_alignment,
110 bool uses_fence,
111 unsigned long *out_flags)
112{
113 struct drm_device *dev = fb->dev;
114 struct drm_i915_private *dev_priv = to_i915(dev);
115 struct drm_gem_object *_obj = intel_fb_bo(fb);
116 struct drm_i915_gem_object *obj = to_intel_bo(_obj);
117 intel_wakeref_t wakeref;
118 struct i915_gem_ww_ctx ww;
119 struct i915_vma *vma;
120 unsigned int pinctl;
121 int ret;
122
123 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
124 return ERR_PTR(-EINVAL);
125
126 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
127 return ERR_PTR(-EINVAL);
128
129 /* Note that the w/a also requires 64 PTE of padding following the
130 * bo. We currently fill all unused PTE with the shadow page and so
131 * we should always have valid PTE following the scanout preventing
132 * the VT-d warning.
133 */
134 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
135 alignment = 256 * 1024;
136
137 /*
138 * Global gtt pte registers are special registers which actually forward
139 * writes to a chunk of system memory. Which means that there is no risk
140 * that the register values disappear as soon as we call
141 * intel_runtime_pm_put(), so it is correct to wrap only the
142 * pin/unpin/fence and not more.
143 */
144 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
145
146 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
147
148 /*
149 * Valleyview is definitely limited to scanning out the first
150 * 512MiB. Lets presume this behaviour was inherited from the
151 * g4x display engine and that all earlier gen are similarly
152 * limited. Testing suggests that it is a little more
153 * complicated than this. For example, Cherryview appears quite
154 * happy to scanout from anywhere within its global aperture.
155 */
156 pinctl = 0;
157 if (HAS_GMCH(dev_priv))
158 pinctl |= PIN_MAPPABLE;
159
160 i915_gem_ww_ctx_init(&ww, true);
161retry:
162 ret = i915_gem_object_lock(obj, &ww);
163 if (!ret && phys_alignment)
164 ret = i915_gem_object_attach_phys(obj, phys_alignment);
165 else if (!ret && HAS_LMEM(dev_priv))
166 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
167 if (!ret)
168 ret = i915_gem_object_pin_pages(obj);
169 if (ret)
170 goto err;
171
172 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
173 view, pinctl);
174 if (IS_ERR(vma)) {
175 ret = PTR_ERR(vma);
176 goto err_unpin;
177 }
178
179 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
180 /*
181 * Install a fence for tiled scan-out. Pre-i965 always needs a
182 * fence, whereas 965+ only requires a fence if using
183 * framebuffer compression. For simplicity, we always, when
184 * possible, install a fence as the cost is not that onerous.
185 *
186 * If we fail to fence the tiled scanout, then either the
187 * modeset will reject the change (which is highly unlikely as
188 * the affected systems, all but one, do not have unmappable
189 * space) or we will not be able to enable full powersaving
190 * techniques (also likely not to apply due to various limits
191 * FBC and the like impose on the size of the buffer, which
192 * presumably we violated anyway with this unmappable buffer).
193 * Anyway, it is presumably better to stumble onwards with
194 * something and try to run the system in a "less than optimal"
195 * mode that matches the user configuration.
196 */
197 ret = i915_vma_pin_fence(vma);
198 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
199 i915_vma_unpin(vma);
200 goto err_unpin;
201 }
202 ret = 0;
203
204 if (vma->fence)
205 *out_flags |= PLANE_HAS_FENCE;
206 }
207
208 i915_vma_get(vma);
209
210err_unpin:
211 i915_gem_object_unpin_pages(obj);
212err:
213 if (ret == -EDEADLK) {
214 ret = i915_gem_ww_ctx_backoff(&ww);
215 if (!ret)
216 goto retry;
217 }
218 i915_gem_ww_ctx_fini(&ww);
219 if (ret)
220 vma = ERR_PTR(ret);
221
222 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
223 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
224 return vma;
225}
226
227void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags)
228{
229 if (flags & PLANE_HAS_FENCE)
230 i915_vma_unpin_fence(vma);
231 i915_vma_unpin(vma);
232 i915_vma_put(vma);
233}
234
235static unsigned int
236intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)
237{
238 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
239
240 return fb->min_alignment;
241}
242
243static unsigned int
244intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state)
245{
246 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
247 const struct drm_framebuffer *fb = plane_state->hw.fb;
248
249 if (!intel_plane_needs_physical(plane))
250 return 0;
251
252 return plane->min_alignment(plane, fb, 0);
253}
254
255int intel_plane_pin_fb(struct intel_plane_state *plane_state)
256{
257 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
258 const struct intel_framebuffer *fb =
259 to_intel_framebuffer(plane_state->hw.fb);
260 struct i915_vma *vma;
261
262 if (!intel_fb_uses_dpt(&fb->base)) {
263 vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt,
264 intel_plane_fb_min_alignment(plane_state),
265 intel_plane_fb_min_phys_alignment(plane_state),
266 intel_plane_uses_fence(plane_state),
267 &plane_state->flags);
268 if (IS_ERR(vma))
269 return PTR_ERR(vma);
270
271 plane_state->ggtt_vma = vma;
272
273 /*
274 * Pre-populate the dma address before we enter the vblank
275 * evade critical section as i915_gem_object_get_dma_address()
276 * will trigger might_sleep() even if it won't actually sleep,
277 * which is the case when the fb has already been pinned.
278 */
279 if (intel_plane_needs_physical(plane)) {
280 struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base));
281
282 plane_state->phys_dma_addr = i915_gem_object_get_dma_address(obj, 0);
283 }
284 } else {
285 unsigned int alignment = intel_plane_fb_min_alignment(plane_state);
286
287 vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512);
288 if (IS_ERR(vma))
289 return PTR_ERR(vma);
290
291 plane_state->ggtt_vma = vma;
292
293 vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt,
294 alignment, &plane_state->flags,
295 fb->dpt_vm);
296 if (IS_ERR(vma)) {
297 intel_dpt_unpin_from_ggtt(fb->dpt_vm);
298 plane_state->ggtt_vma = NULL;
299 return PTR_ERR(vma);
300 }
301
302 plane_state->dpt_vma = vma;
303
304 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
305 }
306
307 return 0;
308}
309
310void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
311{
312 const struct intel_framebuffer *fb =
313 to_intel_framebuffer(old_plane_state->hw.fb);
314 struct i915_vma *vma;
315
316 if (!intel_fb_uses_dpt(&fb->base)) {
317 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
318 if (vma)
319 intel_fb_unpin_vma(vma, old_plane_state->flags);
320 } else {
321 vma = fetch_and_zero(&old_plane_state->dpt_vma);
322 if (vma)
323 intel_fb_unpin_vma(vma, old_plane_state->flags);
324
325 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
326 if (vma)
327 intel_dpt_unpin_from_ggtt(fb->dpt_vm);
328 }
329}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2021 Intel Corporation
4 */
5
6/**
7 * DOC: display pinning helpers
8 */
9
10#include "gem/i915_gem_domain.h"
11#include "gem/i915_gem_object.h"
12
13#include "i915_drv.h"
14#include "intel_display_types.h"
15#include "intel_dpt.h"
16#include "intel_fb.h"
17#include "intel_fb_pin.h"
18
19static struct i915_vma *
20intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
21 const struct i915_gtt_view *view,
22 bool uses_fence,
23 unsigned long *out_flags,
24 struct i915_address_space *vm)
25{
26 struct drm_device *dev = fb->dev;
27 struct drm_i915_private *dev_priv = to_i915(dev);
28 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
29 struct i915_gem_ww_ctx ww;
30 struct i915_vma *vma;
31 u32 alignment;
32 int ret;
33
34 /*
35 * We are not syncing against the binding (and potential migrations)
36 * below, so this vm must never be async.
37 */
38 if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags))
39 return ERR_PTR(-EINVAL);
40
41 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
42 return ERR_PTR(-EINVAL);
43
44 alignment = 4096 * 512;
45
46 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
47
48 for_i915_gem_ww(&ww, ret, true) {
49 ret = i915_gem_object_lock(obj, &ww);
50 if (ret)
51 continue;
52
53 if (HAS_LMEM(dev_priv)) {
54 unsigned int flags = obj->flags;
55
56 /*
57 * For this type of buffer we need to able to read from the CPU
58 * the clear color value found in the buffer, hence we need to
59 * ensure it is always in the mappable part of lmem, if this is
60 * a small-bar device.
61 */
62 if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
63 flags &= ~I915_BO_ALLOC_GPU_ONLY;
64 ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0,
65 flags);
66 if (ret)
67 continue;
68 }
69
70 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
71 if (ret)
72 continue;
73
74 vma = i915_vma_instance(obj, vm, view);
75 if (IS_ERR(vma)) {
76 ret = PTR_ERR(vma);
77 continue;
78 }
79
80 if (i915_vma_misplaced(vma, 0, alignment, 0)) {
81 ret = i915_vma_unbind(vma);
82 if (ret)
83 continue;
84 }
85
86 ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL);
87 if (ret)
88 continue;
89 }
90 if (ret) {
91 vma = ERR_PTR(ret);
92 goto err;
93 }
94
95 vma->display_alignment = max(vma->display_alignment, alignment);
96
97 i915_gem_object_flush_if_display(obj);
98
99 i915_vma_get(vma);
100err:
101 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
102
103 return vma;
104}
105
106struct i915_vma *
107intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
108 bool phys_cursor,
109 const struct i915_gtt_view *view,
110 bool uses_fence,
111 unsigned long *out_flags)
112{
113 struct drm_device *dev = fb->dev;
114 struct drm_i915_private *dev_priv = to_i915(dev);
115 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
116 intel_wakeref_t wakeref;
117 struct i915_gem_ww_ctx ww;
118 struct i915_vma *vma;
119 unsigned int pinctl;
120 u32 alignment;
121 int ret;
122
123 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
124 return ERR_PTR(-EINVAL);
125
126 if (phys_cursor)
127 alignment = intel_cursor_alignment(dev_priv);
128 else
129 alignment = intel_surf_alignment(fb, 0);
130 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
131 return ERR_PTR(-EINVAL);
132
133 /* Note that the w/a also requires 64 PTE of padding following the
134 * bo. We currently fill all unused PTE with the shadow page and so
135 * we should always have valid PTE following the scanout preventing
136 * the VT-d warning.
137 */
138 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
139 alignment = 256 * 1024;
140
141 /*
142 * Global gtt pte registers are special registers which actually forward
143 * writes to a chunk of system memory. Which means that there is no risk
144 * that the register values disappear as soon as we call
145 * intel_runtime_pm_put(), so it is correct to wrap only the
146 * pin/unpin/fence and not more.
147 */
148 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
149
150 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
151
152 /*
153 * Valleyview is definitely limited to scanning out the first
154 * 512MiB. Lets presume this behaviour was inherited from the
155 * g4x display engine and that all earlier gen are similarly
156 * limited. Testing suggests that it is a little more
157 * complicated than this. For example, Cherryview appears quite
158 * happy to scanout from anywhere within its global aperture.
159 */
160 pinctl = 0;
161 if (HAS_GMCH(dev_priv))
162 pinctl |= PIN_MAPPABLE;
163
164 i915_gem_ww_ctx_init(&ww, true);
165retry:
166 ret = i915_gem_object_lock(obj, &ww);
167 if (!ret && phys_cursor)
168 ret = i915_gem_object_attach_phys(obj, alignment);
169 else if (!ret && HAS_LMEM(dev_priv))
170 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
171 if (!ret)
172 ret = i915_gem_object_pin_pages(obj);
173 if (ret)
174 goto err;
175
176 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
177 view, pinctl);
178 if (IS_ERR(vma)) {
179 ret = PTR_ERR(vma);
180 goto err_unpin;
181 }
182
183 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
184 /*
185 * Install a fence for tiled scan-out. Pre-i965 always needs a
186 * fence, whereas 965+ only requires a fence if using
187 * framebuffer compression. For simplicity, we always, when
188 * possible, install a fence as the cost is not that onerous.
189 *
190 * If we fail to fence the tiled scanout, then either the
191 * modeset will reject the change (which is highly unlikely as
192 * the affected systems, all but one, do not have unmappable
193 * space) or we will not be able to enable full powersaving
194 * techniques (also likely not to apply due to various limits
195 * FBC and the like impose on the size of the buffer, which
196 * presumably we violated anyway with this unmappable buffer).
197 * Anyway, it is presumably better to stumble onwards with
198 * something and try to run the system in a "less than optimal"
199 * mode that matches the user configuration.
200 */
201 ret = i915_vma_pin_fence(vma);
202 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
203 i915_vma_unpin(vma);
204 goto err_unpin;
205 }
206 ret = 0;
207
208 if (vma->fence)
209 *out_flags |= PLANE_HAS_FENCE;
210 }
211
212 i915_vma_get(vma);
213
214err_unpin:
215 i915_gem_object_unpin_pages(obj);
216err:
217 if (ret == -EDEADLK) {
218 ret = i915_gem_ww_ctx_backoff(&ww);
219 if (!ret)
220 goto retry;
221 }
222 i915_gem_ww_ctx_fini(&ww);
223 if (ret)
224 vma = ERR_PTR(ret);
225
226 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
227 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
228 return vma;
229}
230
231void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
232{
233 if (flags & PLANE_HAS_FENCE)
234 i915_vma_unpin_fence(vma);
235 i915_vma_unpin(vma);
236 i915_vma_put(vma);
237}
238
239int intel_plane_pin_fb(struct intel_plane_state *plane_state)
240{
241 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
242 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
243 struct drm_framebuffer *fb = plane_state->hw.fb;
244 struct i915_vma *vma;
245 bool phys_cursor =
246 plane->id == PLANE_CURSOR &&
247 DISPLAY_INFO(dev_priv)->cursor_needs_physical;
248
249 if (!intel_fb_uses_dpt(fb)) {
250 vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
251 &plane_state->view.gtt,
252 intel_plane_uses_fence(plane_state),
253 &plane_state->flags);
254 if (IS_ERR(vma))
255 return PTR_ERR(vma);
256
257 plane_state->ggtt_vma = vma;
258 } else {
259 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
260
261 vma = intel_dpt_pin(intel_fb->dpt_vm);
262 if (IS_ERR(vma))
263 return PTR_ERR(vma);
264
265 plane_state->ggtt_vma = vma;
266
267 vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
268 &plane_state->flags, intel_fb->dpt_vm);
269 if (IS_ERR(vma)) {
270 intel_dpt_unpin(intel_fb->dpt_vm);
271 plane_state->ggtt_vma = NULL;
272 return PTR_ERR(vma);
273 }
274
275 plane_state->dpt_vma = vma;
276
277 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
278 }
279
280 return 0;
281}
282
283void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
284{
285 struct drm_framebuffer *fb = old_plane_state->hw.fb;
286 struct i915_vma *vma;
287
288 if (!intel_fb_uses_dpt(fb)) {
289 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
290 if (vma)
291 intel_unpin_fb_vma(vma, old_plane_state->flags);
292 } else {
293 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
294
295 vma = fetch_and_zero(&old_plane_state->dpt_vma);
296 if (vma)
297 intel_unpin_fb_vma(vma, old_plane_state->flags);
298
299 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
300 if (vma)
301 intel_dpt_unpin(intel_fb->dpt_vm);
302 }
303}