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1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/ras.h>
3#include "amd64_edac.h"
4#include <asm/amd_nb.h>
5
6static struct edac_pci_ctl_info *pci_ctl;
7
8/*
9 * Set by command line parameter. If BIOS has enabled the ECC, this override is
10 * cleared to prevent re-enabling the hardware by this driver.
11 */
12static int ecc_enable_override;
13module_param(ecc_enable_override, int, 0644);
14
15static struct msr __percpu *msrs;
16
17static inline u32 get_umc_reg(struct amd64_pvt *pvt, u32 reg)
18{
19 if (!pvt->flags.zn_regs_v2)
20 return reg;
21
22 switch (reg) {
23 case UMCCH_ADDR_MASK_SEC: return UMCCH_ADDR_MASK_SEC_DDR5;
24 case UMCCH_DIMM_CFG: return UMCCH_DIMM_CFG_DDR5;
25 }
26
27 WARN_ONCE(1, "%s: unknown register 0x%x", __func__, reg);
28 return 0;
29}
30
31/* Per-node stuff */
32static struct ecc_settings **ecc_stngs;
33
34/* Device for the PCI component */
35static struct device *pci_ctl_dev;
36
37/*
38 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
39 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
40 * or higher value'.
41 *
42 *FIXME: Produce a better mapping/linearisation.
43 */
44static const struct scrubrate {
45 u32 scrubval; /* bit pattern for scrub rate */
46 u32 bandwidth; /* bandwidth consumed (bytes/sec) */
47} scrubrates[] = {
48 { 0x01, 1600000000UL},
49 { 0x02, 800000000UL},
50 { 0x03, 400000000UL},
51 { 0x04, 200000000UL},
52 { 0x05, 100000000UL},
53 { 0x06, 50000000UL},
54 { 0x07, 25000000UL},
55 { 0x08, 12284069UL},
56 { 0x09, 6274509UL},
57 { 0x0A, 3121951UL},
58 { 0x0B, 1560975UL},
59 { 0x0C, 781440UL},
60 { 0x0D, 390720UL},
61 { 0x0E, 195300UL},
62 { 0x0F, 97650UL},
63 { 0x10, 48854UL},
64 { 0x11, 24427UL},
65 { 0x12, 12213UL},
66 { 0x13, 6101UL},
67 { 0x14, 3051UL},
68 { 0x15, 1523UL},
69 { 0x16, 761UL},
70 { 0x00, 0UL}, /* scrubbing off */
71};
72
73int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
74 u32 *val, const char *func)
75{
76 int err = 0;
77
78 err = pci_read_config_dword(pdev, offset, val);
79 if (err)
80 amd64_warn("%s: error reading F%dx%03x.\n",
81 func, PCI_FUNC(pdev->devfn), offset);
82
83 return pcibios_err_to_errno(err);
84}
85
86int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
87 u32 val, const char *func)
88{
89 int err = 0;
90
91 err = pci_write_config_dword(pdev, offset, val);
92 if (err)
93 amd64_warn("%s: error writing to F%dx%03x.\n",
94 func, PCI_FUNC(pdev->devfn), offset);
95
96 return pcibios_err_to_errno(err);
97}
98
99/*
100 * Select DCT to which PCI cfg accesses are routed
101 */
102static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
103{
104 u32 reg = 0;
105
106 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
107 reg &= (pvt->model == 0x30) ? ~3 : ~1;
108 reg |= dct;
109 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
110}
111
112/*
113 *
114 * Depending on the family, F2 DCT reads need special handling:
115 *
116 * K8: has a single DCT only and no address offsets >= 0x100
117 *
118 * F10h: each DCT has its own set of regs
119 * DCT0 -> F2x040..
120 * DCT1 -> F2x140..
121 *
122 * F16h: has only 1 DCT
123 *
124 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
125 */
126static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
127 int offset, u32 *val)
128{
129 switch (pvt->fam) {
130 case 0xf:
131 if (dct || offset >= 0x100)
132 return -EINVAL;
133 break;
134
135 case 0x10:
136 if (dct) {
137 /*
138 * Note: If ganging is enabled, barring the regs
139 * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx
140 * return 0. (cf. Section 2.8.1 F10h BKDG)
141 */
142 if (dct_ganging_enabled(pvt))
143 return 0;
144
145 offset += 0x100;
146 }
147 break;
148
149 case 0x15:
150 /*
151 * F15h: F2x1xx addresses do not map explicitly to DCT1.
152 * We should select which DCT we access using F1x10C[DctCfgSel]
153 */
154 dct = (dct && pvt->model == 0x30) ? 3 : dct;
155 f15h_select_dct(pvt, dct);
156 break;
157
158 case 0x16:
159 if (dct)
160 return -EINVAL;
161 break;
162
163 default:
164 break;
165 }
166 return amd64_read_pci_cfg(pvt->F2, offset, val);
167}
168
169/*
170 * Memory scrubber control interface. For K8, memory scrubbing is handled by
171 * hardware and can involve L2 cache, dcache as well as the main memory. With
172 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
173 * functionality.
174 *
175 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
176 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
177 * bytes/sec for the setting.
178 *
179 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
180 * other archs, we might not have access to the caches directly.
181 */
182
183/*
184 * Scan the scrub rate mapping table for a close or matching bandwidth value to
185 * issue. If requested is too big, then use last maximum value found.
186 */
187static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
188{
189 u32 scrubval;
190 int i;
191
192 /*
193 * map the configured rate (new_bw) to a value specific to the AMD64
194 * memory controller and apply to register. Search for the first
195 * bandwidth entry that is greater or equal than the setting requested
196 * and program that. If at last entry, turn off DRAM scrubbing.
197 *
198 * If no suitable bandwidth is found, turn off DRAM scrubbing entirely
199 * by falling back to the last element in scrubrates[].
200 */
201 for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) {
202 /*
203 * skip scrub rates which aren't recommended
204 * (see F10 BKDG, F3x58)
205 */
206 if (scrubrates[i].scrubval < min_rate)
207 continue;
208
209 if (scrubrates[i].bandwidth <= new_bw)
210 break;
211 }
212
213 scrubval = scrubrates[i].scrubval;
214
215 if (pvt->fam == 0x15 && pvt->model == 0x60) {
216 f15h_select_dct(pvt, 0);
217 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
218 f15h_select_dct(pvt, 1);
219 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
220 } else {
221 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
222 }
223
224 if (scrubval)
225 return scrubrates[i].bandwidth;
226
227 return 0;
228}
229
230static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
231{
232 struct amd64_pvt *pvt = mci->pvt_info;
233 u32 min_scrubrate = 0x5;
234
235 if (pvt->fam == 0xf)
236 min_scrubrate = 0x0;
237
238 if (pvt->fam == 0x15) {
239 /* Erratum #505 */
240 if (pvt->model < 0x10)
241 f15h_select_dct(pvt, 0);
242
243 if (pvt->model == 0x60)
244 min_scrubrate = 0x6;
245 }
246 return __set_scrub_rate(pvt, bw, min_scrubrate);
247}
248
249static int get_scrub_rate(struct mem_ctl_info *mci)
250{
251 struct amd64_pvt *pvt = mci->pvt_info;
252 int i, retval = -EINVAL;
253 u32 scrubval = 0;
254
255 if (pvt->fam == 0x15) {
256 /* Erratum #505 */
257 if (pvt->model < 0x10)
258 f15h_select_dct(pvt, 0);
259
260 if (pvt->model == 0x60)
261 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
262 else
263 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
264 } else {
265 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
266 }
267
268 scrubval = scrubval & 0x001F;
269
270 for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
271 if (scrubrates[i].scrubval == scrubval) {
272 retval = scrubrates[i].bandwidth;
273 break;
274 }
275 }
276 return retval;
277}
278
279/*
280 * returns true if the SysAddr given by sys_addr matches the
281 * DRAM base/limit associated with node_id
282 */
283static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
284{
285 u64 addr;
286
287 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
288 * all ones if the most significant implemented address bit is 1.
289 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
290 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
291 * Application Programming.
292 */
293 addr = sys_addr & 0x000000ffffffffffull;
294
295 return ((addr >= get_dram_base(pvt, nid)) &&
296 (addr <= get_dram_limit(pvt, nid)));
297}
298
299/*
300 * Attempt to map a SysAddr to a node. On success, return a pointer to the
301 * mem_ctl_info structure for the node that the SysAddr maps to.
302 *
303 * On failure, return NULL.
304 */
305static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
306 u64 sys_addr)
307{
308 struct amd64_pvt *pvt;
309 u8 node_id;
310 u32 intlv_en, bits;
311
312 /*
313 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
314 * 3.4.4.2) registers to map the SysAddr to a node ID.
315 */
316 pvt = mci->pvt_info;
317
318 /*
319 * The value of this field should be the same for all DRAM Base
320 * registers. Therefore we arbitrarily choose to read it from the
321 * register for node 0.
322 */
323 intlv_en = dram_intlv_en(pvt, 0);
324
325 if (intlv_en == 0) {
326 for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
327 if (base_limit_match(pvt, sys_addr, node_id))
328 goto found;
329 }
330 goto err_no_match;
331 }
332
333 if (unlikely((intlv_en != 0x01) &&
334 (intlv_en != 0x03) &&
335 (intlv_en != 0x07))) {
336 amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
337 return NULL;
338 }
339
340 bits = (((u32) sys_addr) >> 12) & intlv_en;
341
342 for (node_id = 0; ; ) {
343 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
344 break; /* intlv_sel field matches */
345
346 if (++node_id >= DRAM_RANGES)
347 goto err_no_match;
348 }
349
350 /* sanity test for sys_addr */
351 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
352 amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
353 "range for node %d with node interleaving enabled.\n",
354 __func__, sys_addr, node_id);
355 return NULL;
356 }
357
358found:
359 return edac_mc_find((int)node_id);
360
361err_no_match:
362 edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
363 (unsigned long)sys_addr);
364
365 return NULL;
366}
367
368/*
369 * compute the CS base address of the @csrow on the DRAM controller @dct.
370 * For details see F2x[5C:40] in the processor's BKDG
371 */
372static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
373 u64 *base, u64 *mask)
374{
375 u64 csbase, csmask, base_bits, mask_bits;
376 u8 addr_shift;
377
378 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
379 csbase = pvt->csels[dct].csbases[csrow];
380 csmask = pvt->csels[dct].csmasks[csrow];
381 base_bits = GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);
382 mask_bits = GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);
383 addr_shift = 4;
384
385 /*
386 * F16h and F15h, models 30h and later need two addr_shift values:
387 * 8 for high and 6 for low (cf. F16h BKDG).
388 */
389 } else if (pvt->fam == 0x16 ||
390 (pvt->fam == 0x15 && pvt->model >= 0x30)) {
391 csbase = pvt->csels[dct].csbases[csrow];
392 csmask = pvt->csels[dct].csmasks[csrow >> 1];
393
394 *base = (csbase & GENMASK_ULL(15, 5)) << 6;
395 *base |= (csbase & GENMASK_ULL(30, 19)) << 8;
396
397 *mask = ~0ULL;
398 /* poke holes for the csmask */
399 *mask &= ~((GENMASK_ULL(15, 5) << 6) |
400 (GENMASK_ULL(30, 19) << 8));
401
402 *mask |= (csmask & GENMASK_ULL(15, 5)) << 6;
403 *mask |= (csmask & GENMASK_ULL(30, 19)) << 8;
404
405 return;
406 } else {
407 csbase = pvt->csels[dct].csbases[csrow];
408 csmask = pvt->csels[dct].csmasks[csrow >> 1];
409 addr_shift = 8;
410
411 if (pvt->fam == 0x15)
412 base_bits = mask_bits =
413 GENMASK_ULL(30,19) | GENMASK_ULL(13,5);
414 else
415 base_bits = mask_bits =
416 GENMASK_ULL(28,19) | GENMASK_ULL(13,5);
417 }
418
419 *base = (csbase & base_bits) << addr_shift;
420
421 *mask = ~0ULL;
422 /* poke holes for the csmask */
423 *mask &= ~(mask_bits << addr_shift);
424 /* OR them in */
425 *mask |= (csmask & mask_bits) << addr_shift;
426}
427
428#define for_each_chip_select(i, dct, pvt) \
429 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
430
431#define chip_select_base(i, dct, pvt) \
432 pvt->csels[dct].csbases[i]
433
434#define for_each_chip_select_mask(i, dct, pvt) \
435 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
436
437#define for_each_umc(i) \
438 for (i = 0; i < pvt->max_mcs; i++)
439
440/*
441 * @input_addr is an InputAddr associated with the node given by mci. Return the
442 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
443 */
444static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
445{
446 struct amd64_pvt *pvt;
447 int csrow;
448 u64 base, mask;
449
450 pvt = mci->pvt_info;
451
452 for_each_chip_select(csrow, 0, pvt) {
453 if (!csrow_enabled(csrow, 0, pvt))
454 continue;
455
456 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);
457
458 mask = ~mask;
459
460 if ((input_addr & mask) == (base & mask)) {
461 edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
462 (unsigned long)input_addr, csrow,
463 pvt->mc_node_id);
464
465 return csrow;
466 }
467 }
468 edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
469 (unsigned long)input_addr, pvt->mc_node_id);
470
471 return -1;
472}
473
474/*
475 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
476 * for the node represented by mci. Info is passed back in *hole_base,
477 * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
478 * info is invalid. Info may be invalid for either of the following reasons:
479 *
480 * - The revision of the node is not E or greater. In this case, the DRAM Hole
481 * Address Register does not exist.
482 *
483 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
484 * indicating that its contents are not valid.
485 *
486 * The values passed back in *hole_base, *hole_offset, and *hole_size are
487 * complete 32-bit values despite the fact that the bitfields in the DHAR
488 * only represent bits 31-24 of the base and offset values.
489 */
490static int get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
491 u64 *hole_offset, u64 *hole_size)
492{
493 struct amd64_pvt *pvt = mci->pvt_info;
494
495 /* only revE and later have the DRAM Hole Address Register */
496 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {
497 edac_dbg(1, " revision %d for node %d does not support DHAR\n",
498 pvt->ext_model, pvt->mc_node_id);
499 return 1;
500 }
501
502 /* valid for Fam10h and above */
503 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
504 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n");
505 return 1;
506 }
507
508 if (!dhar_valid(pvt)) {
509 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n",
510 pvt->mc_node_id);
511 return 1;
512 }
513
514 /* This node has Memory Hoisting */
515
516 /* +------------------+--------------------+--------------------+-----
517 * | memory | DRAM hole | relocated |
518 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
519 * | | | DRAM hole |
520 * | | | [0x100000000, |
521 * | | | (0x100000000+ |
522 * | | | (0xffffffff-x))] |
523 * +------------------+--------------------+--------------------+-----
524 *
525 * Above is a diagram of physical memory showing the DRAM hole and the
526 * relocated addresses from the DRAM hole. As shown, the DRAM hole
527 * starts at address x (the base address) and extends through address
528 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
529 * addresses in the hole so that they start at 0x100000000.
530 */
531
532 *hole_base = dhar_base(pvt);
533 *hole_size = (1ULL << 32) - *hole_base;
534
535 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)
536 : k8_dhar_offset(pvt);
537
538 edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
539 pvt->mc_node_id, (unsigned long)*hole_base,
540 (unsigned long)*hole_offset, (unsigned long)*hole_size);
541
542 return 0;
543}
544
545#ifdef CONFIG_EDAC_DEBUG
546#define EDAC_DCT_ATTR_SHOW(reg) \
547static ssize_t reg##_show(struct device *dev, \
548 struct device_attribute *mattr, char *data) \
549{ \
550 struct mem_ctl_info *mci = to_mci(dev); \
551 struct amd64_pvt *pvt = mci->pvt_info; \
552 \
553 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
554}
555
556EDAC_DCT_ATTR_SHOW(dhar);
557EDAC_DCT_ATTR_SHOW(dbam0);
558EDAC_DCT_ATTR_SHOW(top_mem);
559EDAC_DCT_ATTR_SHOW(top_mem2);
560
561static ssize_t dram_hole_show(struct device *dev, struct device_attribute *mattr,
562 char *data)
563{
564 struct mem_ctl_info *mci = to_mci(dev);
565
566 u64 hole_base = 0;
567 u64 hole_offset = 0;
568 u64 hole_size = 0;
569
570 get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
571
572 return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
573 hole_size);
574}
575
576/*
577 * update NUM_DBG_ATTRS in case you add new members
578 */
579static DEVICE_ATTR(dhar, S_IRUGO, dhar_show, NULL);
580static DEVICE_ATTR(dbam, S_IRUGO, dbam0_show, NULL);
581static DEVICE_ATTR(topmem, S_IRUGO, top_mem_show, NULL);
582static DEVICE_ATTR(topmem2, S_IRUGO, top_mem2_show, NULL);
583static DEVICE_ATTR_RO(dram_hole);
584
585static struct attribute *dbg_attrs[] = {
586 &dev_attr_dhar.attr,
587 &dev_attr_dbam.attr,
588 &dev_attr_topmem.attr,
589 &dev_attr_topmem2.attr,
590 &dev_attr_dram_hole.attr,
591 NULL
592};
593
594static const struct attribute_group dbg_group = {
595 .attrs = dbg_attrs,
596};
597
598static ssize_t inject_section_show(struct device *dev,
599 struct device_attribute *mattr, char *buf)
600{
601 struct mem_ctl_info *mci = to_mci(dev);
602 struct amd64_pvt *pvt = mci->pvt_info;
603 return sprintf(buf, "0x%x\n", pvt->injection.section);
604}
605
606/*
607 * store error injection section value which refers to one of 4 16-byte sections
608 * within a 64-byte cacheline
609 *
610 * range: 0..3
611 */
612static ssize_t inject_section_store(struct device *dev,
613 struct device_attribute *mattr,
614 const char *data, size_t count)
615{
616 struct mem_ctl_info *mci = to_mci(dev);
617 struct amd64_pvt *pvt = mci->pvt_info;
618 unsigned long value;
619 int ret;
620
621 ret = kstrtoul(data, 10, &value);
622 if (ret < 0)
623 return ret;
624
625 if (value > 3) {
626 amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
627 return -EINVAL;
628 }
629
630 pvt->injection.section = (u32) value;
631 return count;
632}
633
634static ssize_t inject_word_show(struct device *dev,
635 struct device_attribute *mattr, char *buf)
636{
637 struct mem_ctl_info *mci = to_mci(dev);
638 struct amd64_pvt *pvt = mci->pvt_info;
639 return sprintf(buf, "0x%x\n", pvt->injection.word);
640}
641
642/*
643 * store error injection word value which refers to one of 9 16-bit word of the
644 * 16-byte (128-bit + ECC bits) section
645 *
646 * range: 0..8
647 */
648static ssize_t inject_word_store(struct device *dev,
649 struct device_attribute *mattr,
650 const char *data, size_t count)
651{
652 struct mem_ctl_info *mci = to_mci(dev);
653 struct amd64_pvt *pvt = mci->pvt_info;
654 unsigned long value;
655 int ret;
656
657 ret = kstrtoul(data, 10, &value);
658 if (ret < 0)
659 return ret;
660
661 if (value > 8) {
662 amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
663 return -EINVAL;
664 }
665
666 pvt->injection.word = (u32) value;
667 return count;
668}
669
670static ssize_t inject_ecc_vector_show(struct device *dev,
671 struct device_attribute *mattr,
672 char *buf)
673{
674 struct mem_ctl_info *mci = to_mci(dev);
675 struct amd64_pvt *pvt = mci->pvt_info;
676 return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
677}
678
679/*
680 * store 16 bit error injection vector which enables injecting errors to the
681 * corresponding bit within the error injection word above. When used during a
682 * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
683 */
684static ssize_t inject_ecc_vector_store(struct device *dev,
685 struct device_attribute *mattr,
686 const char *data, size_t count)
687{
688 struct mem_ctl_info *mci = to_mci(dev);
689 struct amd64_pvt *pvt = mci->pvt_info;
690 unsigned long value;
691 int ret;
692
693 ret = kstrtoul(data, 16, &value);
694 if (ret < 0)
695 return ret;
696
697 if (value & 0xFFFF0000) {
698 amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value);
699 return -EINVAL;
700 }
701
702 pvt->injection.bit_map = (u32) value;
703 return count;
704}
705
706/*
707 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
708 * fields needed by the injection registers and read the NB Array Data Port.
709 */
710static ssize_t inject_read_store(struct device *dev,
711 struct device_attribute *mattr,
712 const char *data, size_t count)
713{
714 struct mem_ctl_info *mci = to_mci(dev);
715 struct amd64_pvt *pvt = mci->pvt_info;
716 unsigned long value;
717 u32 section, word_bits;
718 int ret;
719
720 ret = kstrtoul(data, 10, &value);
721 if (ret < 0)
722 return ret;
723
724 /* Form value to choose 16-byte section of cacheline */
725 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
726
727 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
728
729 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);
730
731 /* Issue 'word' and 'bit' along with the READ request */
732 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
733
734 edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
735
736 return count;
737}
738
739/*
740 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
741 * fields needed by the injection registers.
742 */
743static ssize_t inject_write_store(struct device *dev,
744 struct device_attribute *mattr,
745 const char *data, size_t count)
746{
747 struct mem_ctl_info *mci = to_mci(dev);
748 struct amd64_pvt *pvt = mci->pvt_info;
749 u32 section, word_bits, tmp;
750 unsigned long value;
751 int ret;
752
753 ret = kstrtoul(data, 10, &value);
754 if (ret < 0)
755 return ret;
756
757 /* Form value to choose 16-byte section of cacheline */
758 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
759
760 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
761
762 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
763
764 pr_notice_once("Don't forget to decrease MCE polling interval in\n"
765 "/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n"
766 "so that you can get the error report faster.\n");
767
768 on_each_cpu(disable_caches, NULL, 1);
769
770 /* Issue 'word' and 'bit' along with the READ request */
771 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
772
773 retry:
774 /* wait until injection happens */
775 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
776 if (tmp & F10_NB_ARR_ECC_WR_REQ) {
777 cpu_relax();
778 goto retry;
779 }
780
781 on_each_cpu(enable_caches, NULL, 1);
782
783 edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
784
785 return count;
786}
787
788/*
789 * update NUM_INJ_ATTRS in case you add new members
790 */
791
792static DEVICE_ATTR_RW(inject_section);
793static DEVICE_ATTR_RW(inject_word);
794static DEVICE_ATTR_RW(inject_ecc_vector);
795static DEVICE_ATTR_WO(inject_write);
796static DEVICE_ATTR_WO(inject_read);
797
798static struct attribute *inj_attrs[] = {
799 &dev_attr_inject_section.attr,
800 &dev_attr_inject_word.attr,
801 &dev_attr_inject_ecc_vector.attr,
802 &dev_attr_inject_write.attr,
803 &dev_attr_inject_read.attr,
804 NULL
805};
806
807static umode_t inj_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
808{
809 struct device *dev = kobj_to_dev(kobj);
810 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
811 struct amd64_pvt *pvt = mci->pvt_info;
812
813 /* Families which have that injection hw */
814 if (pvt->fam >= 0x10 && pvt->fam <= 0x16)
815 return attr->mode;
816
817 return 0;
818}
819
820static const struct attribute_group inj_group = {
821 .attrs = inj_attrs,
822 .is_visible = inj_is_visible,
823};
824#endif /* CONFIG_EDAC_DEBUG */
825
826/*
827 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
828 * assumed that sys_addr maps to the node given by mci.
829 *
830 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
831 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
832 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
833 * then it is also involved in translating a SysAddr to a DramAddr. Sections
834 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
835 * These parts of the documentation are unclear. I interpret them as follows:
836 *
837 * When node n receives a SysAddr, it processes the SysAddr as follows:
838 *
839 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
840 * Limit registers for node n. If the SysAddr is not within the range
841 * specified by the base and limit values, then node n ignores the Sysaddr
842 * (since it does not map to node n). Otherwise continue to step 2 below.
843 *
844 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
845 * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
846 * the range of relocated addresses (starting at 0x100000000) from the DRAM
847 * hole. If not, skip to step 3 below. Else get the value of the
848 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
849 * offset defined by this value from the SysAddr.
850 *
851 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
852 * Base register for node n. To obtain the DramAddr, subtract the base
853 * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
854 */
855static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
856{
857 struct amd64_pvt *pvt = mci->pvt_info;
858 u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
859 int ret;
860
861 dram_base = get_dram_base(pvt, pvt->mc_node_id);
862
863 ret = get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
864 if (!ret) {
865 if ((sys_addr >= (1ULL << 32)) &&
866 (sys_addr < ((1ULL << 32) + hole_size))) {
867 /* use DHAR to translate SysAddr to DramAddr */
868 dram_addr = sys_addr - hole_offset;
869
870 edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
871 (unsigned long)sys_addr,
872 (unsigned long)dram_addr);
873
874 return dram_addr;
875 }
876 }
877
878 /*
879 * Translate the SysAddr to a DramAddr as shown near the start of
880 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
881 * only deals with 40-bit values. Therefore we discard bits 63-40 of
882 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
883 * discard are all 1s. Otherwise the bits we discard are all 0s. See
884 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
885 * Programmer's Manual Volume 1 Application Programming.
886 */
887 dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
888
889 edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
890 (unsigned long)sys_addr, (unsigned long)dram_addr);
891 return dram_addr;
892}
893
894/*
895 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
896 * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
897 * for node interleaving.
898 */
899static int num_node_interleave_bits(unsigned intlv_en)
900{
901 static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
902 int n;
903
904 BUG_ON(intlv_en > 7);
905 n = intlv_shift_table[intlv_en];
906 return n;
907}
908
909/* Translate the DramAddr given by @dram_addr to an InputAddr. */
910static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
911{
912 struct amd64_pvt *pvt;
913 int intlv_shift;
914 u64 input_addr;
915
916 pvt = mci->pvt_info;
917
918 /*
919 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
920 * concerning translating a DramAddr to an InputAddr.
921 */
922 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
923 input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +
924 (dram_addr & 0xfff);
925
926 edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
927 intlv_shift, (unsigned long)dram_addr,
928 (unsigned long)input_addr);
929
930 return input_addr;
931}
932
933/*
934 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
935 * assumed that @sys_addr maps to the node given by mci.
936 */
937static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
938{
939 u64 input_addr;
940
941 input_addr =
942 dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));
943
944 edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",
945 (unsigned long)sys_addr, (unsigned long)input_addr);
946
947 return input_addr;
948}
949
950/* Map the Error address to a PAGE and PAGE OFFSET. */
951static inline void error_address_to_page_and_offset(u64 error_address,
952 struct err_info *err)
953{
954 err->page = (u32) (error_address >> PAGE_SHIFT);
955 err->offset = ((u32) error_address) & ~PAGE_MASK;
956}
957
958/*
959 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
960 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
961 * of a node that detected an ECC memory error. mci represents the node that
962 * the error address maps to (possibly different from the node that detected
963 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
964 * error.
965 */
966static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
967{
968 int csrow;
969
970 csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
971
972 if (csrow == -1)
973 amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
974 "address 0x%lx\n", (unsigned long)sys_addr);
975 return csrow;
976}
977
978/*
979 * See AMD PPR DF::LclNodeTypeMap
980 *
981 * This register gives information for nodes of the same type within a system.
982 *
983 * Reading this register from a GPU node will tell how many GPU nodes are in the
984 * system and what the lowest AMD Node ID value is for the GPU nodes. Use this
985 * info to fixup the Linux logical "Node ID" value set in the AMD NB code and EDAC.
986 */
987static struct local_node_map {
988 u16 node_count;
989 u16 base_node_id;
990} gpu_node_map;
991
992#define PCI_DEVICE_ID_AMD_MI200_DF_F1 0x14d1
993#define REG_LOCAL_NODE_TYPE_MAP 0x144
994
995/* Local Node Type Map (LNTM) fields */
996#define LNTM_NODE_COUNT GENMASK(27, 16)
997#define LNTM_BASE_NODE_ID GENMASK(11, 0)
998
999static int gpu_get_node_map(struct amd64_pvt *pvt)
1000{
1001 struct pci_dev *pdev;
1002 int ret;
1003 u32 tmp;
1004
1005 /*
1006 * Mapping of nodes from hardware-provided AMD Node ID to a
1007 * Linux logical one is applicable for MI200 models. Therefore,
1008 * return early for other heterogeneous systems.
1009 */
1010 if (pvt->F3->device != PCI_DEVICE_ID_AMD_MI200_DF_F3)
1011 return 0;
1012
1013 /*
1014 * Node ID 0 is reserved for CPUs. Therefore, a non-zero Node ID
1015 * means the values have been already cached.
1016 */
1017 if (gpu_node_map.base_node_id)
1018 return 0;
1019
1020 pdev = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F1, NULL);
1021 if (!pdev) {
1022 ret = -ENODEV;
1023 goto out;
1024 }
1025
1026 ret = pci_read_config_dword(pdev, REG_LOCAL_NODE_TYPE_MAP, &tmp);
1027 if (ret) {
1028 ret = pcibios_err_to_errno(ret);
1029 goto out;
1030 }
1031
1032 gpu_node_map.node_count = FIELD_GET(LNTM_NODE_COUNT, tmp);
1033 gpu_node_map.base_node_id = FIELD_GET(LNTM_BASE_NODE_ID, tmp);
1034
1035out:
1036 pci_dev_put(pdev);
1037 return ret;
1038}
1039
1040static int fixup_node_id(int node_id, struct mce *m)
1041{
1042 /* MCA_IPID[InstanceIdHi] give the AMD Node ID for the bank. */
1043 u8 nid = (m->ipid >> 44) & 0xF;
1044
1045 if (smca_get_bank_type(m->extcpu, m->bank) != SMCA_UMC_V2)
1046 return node_id;
1047
1048 /* Nodes below the GPU base node are CPU nodes and don't need a fixup. */
1049 if (nid < gpu_node_map.base_node_id)
1050 return node_id;
1051
1052 /* Convert the hardware-provided AMD Node ID to a Linux logical one. */
1053 return nid - gpu_node_map.base_node_id + 1;
1054}
1055
1056static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
1057
1058/*
1059 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
1060 * are ECC capable.
1061 */
1062static unsigned long dct_determine_edac_cap(struct amd64_pvt *pvt)
1063{
1064 unsigned long edac_cap = EDAC_FLAG_NONE;
1065 u8 bit;
1066
1067 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
1068 ? 19
1069 : 17;
1070
1071 if (pvt->dclr0 & BIT(bit))
1072 edac_cap = EDAC_FLAG_SECDED;
1073
1074 return edac_cap;
1075}
1076
1077static unsigned long umc_determine_edac_cap(struct amd64_pvt *pvt)
1078{
1079 u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
1080 unsigned long edac_cap = EDAC_FLAG_NONE;
1081
1082 for_each_umc(i) {
1083 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
1084 continue;
1085
1086 umc_en_mask |= BIT(i);
1087
1088 /* UMC Configuration bit 12 (DimmEccEn) */
1089 if (pvt->umc[i].umc_cfg & BIT(12))
1090 dimm_ecc_en_mask |= BIT(i);
1091 }
1092
1093 if (umc_en_mask == dimm_ecc_en_mask)
1094 edac_cap = EDAC_FLAG_SECDED;
1095
1096 return edac_cap;
1097}
1098
1099/*
1100 * debug routine to display the memory sizes of all logical DIMMs and its
1101 * CSROWs
1102 */
1103static void dct_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1104{
1105 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
1106 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
1107 int dimm, size0, size1;
1108
1109 if (pvt->fam == 0xf) {
1110 /* K8 families < revF not supported yet */
1111 if (pvt->ext_model < K8_REV_F)
1112 return;
1113
1114 WARN_ON(ctrl != 0);
1115 }
1116
1117 if (pvt->fam == 0x10) {
1118 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
1119 : pvt->dbam0;
1120 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
1121 pvt->csels[1].csbases :
1122 pvt->csels[0].csbases;
1123 } else if (ctrl) {
1124 dbam = pvt->dbam0;
1125 dcsb = pvt->csels[1].csbases;
1126 }
1127 edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
1128 ctrl, dbam);
1129
1130 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
1131
1132 /* Dump memory sizes for DIMM and its CSROWs */
1133 for (dimm = 0; dimm < 4; dimm++) {
1134 size0 = 0;
1135 if (dcsb[dimm * 2] & DCSB_CS_ENABLE)
1136 /*
1137 * For F15m60h, we need multiplier for LRDIMM cs_size
1138 * calculation. We pass dimm value to the dbam_to_cs
1139 * mapper so we can find the multiplier from the
1140 * corresponding DCSM.
1141 */
1142 size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
1143 DBAM_DIMM(dimm, dbam),
1144 dimm);
1145
1146 size1 = 0;
1147 if (dcsb[dimm * 2 + 1] & DCSB_CS_ENABLE)
1148 size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
1149 DBAM_DIMM(dimm, dbam),
1150 dimm);
1151
1152 amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
1153 dimm * 2, size0,
1154 dimm * 2 + 1, size1);
1155 }
1156}
1157
1158
1159static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
1160{
1161 edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
1162
1163 if (pvt->dram_type == MEM_LRDDR3) {
1164 u32 dcsm = pvt->csels[chan].csmasks[0];
1165 /*
1166 * It's assumed all LRDIMMs in a DCT are going to be of
1167 * same 'type' until proven otherwise. So, use a cs
1168 * value of '0' here to get dcsm value.
1169 */
1170 edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));
1171 }
1172
1173 edac_dbg(1, "All DIMMs support ECC:%s\n",
1174 (dclr & BIT(19)) ? "yes" : "no");
1175
1176
1177 edac_dbg(1, " PAR/ERR parity: %s\n",
1178 (dclr & BIT(8)) ? "enabled" : "disabled");
1179
1180 if (pvt->fam == 0x10)
1181 edac_dbg(1, " DCT 128bit mode width: %s\n",
1182 (dclr & BIT(11)) ? "128b" : "64b");
1183
1184 edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
1185 (dclr & BIT(12)) ? "yes" : "no",
1186 (dclr & BIT(13)) ? "yes" : "no",
1187 (dclr & BIT(14)) ? "yes" : "no",
1188 (dclr & BIT(15)) ? "yes" : "no");
1189}
1190
1191#define CS_EVEN_PRIMARY BIT(0)
1192#define CS_ODD_PRIMARY BIT(1)
1193#define CS_EVEN_SECONDARY BIT(2)
1194#define CS_ODD_SECONDARY BIT(3)
1195#define CS_3R_INTERLEAVE BIT(4)
1196
1197#define CS_EVEN (CS_EVEN_PRIMARY | CS_EVEN_SECONDARY)
1198#define CS_ODD (CS_ODD_PRIMARY | CS_ODD_SECONDARY)
1199
1200static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
1201{
1202 u8 base, count = 0;
1203 int cs_mode = 0;
1204
1205 if (csrow_enabled(2 * dimm, ctrl, pvt))
1206 cs_mode |= CS_EVEN_PRIMARY;
1207
1208 if (csrow_enabled(2 * dimm + 1, ctrl, pvt))
1209 cs_mode |= CS_ODD_PRIMARY;
1210
1211 /* Asymmetric dual-rank DIMM support. */
1212 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))
1213 cs_mode |= CS_ODD_SECONDARY;
1214
1215 /*
1216 * 3 Rank inteleaving support.
1217 * There should be only three bases enabled and their two masks should
1218 * be equal.
1219 */
1220 for_each_chip_select(base, ctrl, pvt)
1221 count += csrow_enabled(base, ctrl, pvt);
1222
1223 if (count == 3 &&
1224 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) {
1225 edac_dbg(1, "3R interleaving in use.\n");
1226 cs_mode |= CS_3R_INTERLEAVE;
1227 }
1228
1229 return cs_mode;
1230}
1231
1232static int __addr_mask_to_cs_size(u32 addr_mask_orig, unsigned int cs_mode,
1233 int csrow_nr, int dimm)
1234{
1235 u32 msb, weight, num_zero_bits;
1236 u32 addr_mask_deinterleaved;
1237 int size = 0;
1238
1239 /*
1240 * The number of zero bits in the mask is equal to the number of bits
1241 * in a full mask minus the number of bits in the current mask.
1242 *
1243 * The MSB is the number of bits in the full mask because BIT[0] is
1244 * always 0.
1245 *
1246 * In the special 3 Rank interleaving case, a single bit is flipped
1247 * without swapping with the most significant bit. This can be handled
1248 * by keeping the MSB where it is and ignoring the single zero bit.
1249 */
1250 msb = fls(addr_mask_orig) - 1;
1251 weight = hweight_long(addr_mask_orig);
1252 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);
1253
1254 /* Take the number of zero bits off from the top of the mask. */
1255 addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1);
1256
1257 edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);
1258 edac_dbg(1, " Original AddrMask: 0x%x\n", addr_mask_orig);
1259 edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved);
1260
1261 /* Register [31:1] = Address [39:9]. Size is in kBs here. */
1262 size = (addr_mask_deinterleaved >> 2) + 1;
1263
1264 /* Return size in MBs. */
1265 return size >> 10;
1266}
1267
1268static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
1269 unsigned int cs_mode, int csrow_nr)
1270{
1271 int cs_mask_nr = csrow_nr;
1272 u32 addr_mask_orig;
1273 int dimm, size = 0;
1274
1275 /* No Chip Selects are enabled. */
1276 if (!cs_mode)
1277 return size;
1278
1279 /* Requested size of an even CS but none are enabled. */
1280 if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))
1281 return size;
1282
1283 /* Requested size of an odd CS but none are enabled. */
1284 if (!(cs_mode & CS_ODD) && (csrow_nr & 1))
1285 return size;
1286
1287 /*
1288 * Family 17h introduced systems with one mask per DIMM,
1289 * and two Chip Selects per DIMM.
1290 *
1291 * CS0 and CS1 -> MASK0 / DIMM0
1292 * CS2 and CS3 -> MASK1 / DIMM1
1293 *
1294 * Family 19h Model 10h introduced systems with one mask per Chip Select,
1295 * and two Chip Selects per DIMM.
1296 *
1297 * CS0 -> MASK0 -> DIMM0
1298 * CS1 -> MASK1 -> DIMM0
1299 * CS2 -> MASK2 -> DIMM1
1300 * CS3 -> MASK3 -> DIMM1
1301 *
1302 * Keep the mask number equal to the Chip Select number for newer systems,
1303 * and shift the mask number for older systems.
1304 */
1305 dimm = csrow_nr >> 1;
1306
1307 if (!pvt->flags.zn_regs_v2)
1308 cs_mask_nr >>= 1;
1309
1310 /* Asymmetric dual-rank DIMM support. */
1311 if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
1312 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];
1313 else
1314 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];
1315
1316 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm);
1317}
1318
1319static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1320{
1321 int dimm, size0, size1, cs0, cs1, cs_mode;
1322
1323 edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
1324
1325 for (dimm = 0; dimm < 2; dimm++) {
1326 cs0 = dimm * 2;
1327 cs1 = dimm * 2 + 1;
1328
1329 cs_mode = umc_get_cs_mode(dimm, ctrl, pvt);
1330
1331 size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0);
1332 size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1);
1333
1334 amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
1335 cs0, size0,
1336 cs1, size1);
1337 }
1338}
1339
1340static void umc_dump_misc_regs(struct amd64_pvt *pvt)
1341{
1342 struct amd64_umc *umc;
1343 u32 i;
1344
1345 for_each_umc(i) {
1346 umc = &pvt->umc[i];
1347
1348 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
1349 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
1350 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
1351 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
1352 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);
1353
1354 edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
1355 i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",
1356 (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");
1357 edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",
1358 i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");
1359 edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",
1360 i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");
1361 edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
1362 i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");
1363
1364 umc_debug_display_dimm_sizes(pvt, i);
1365 }
1366}
1367
1368static void dct_dump_misc_regs(struct amd64_pvt *pvt)
1369{
1370 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
1371
1372 edac_dbg(1, " NB two channel DRAM capable: %s\n",
1373 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
1374
1375 edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n",
1376 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
1377 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
1378
1379 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
1380
1381 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
1382
1383 edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
1384 pvt->dhar, dhar_base(pvt),
1385 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)
1386 : f10_dhar_offset(pvt));
1387
1388 dct_debug_display_dimm_sizes(pvt, 0);
1389
1390 /* everything below this point is Fam10h and above */
1391 if (pvt->fam == 0xf)
1392 return;
1393
1394 dct_debug_display_dimm_sizes(pvt, 1);
1395
1396 /* Only if NOT ganged does dclr1 have valid info */
1397 if (!dct_ganging_enabled(pvt))
1398 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
1399
1400 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
1401
1402 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
1403}
1404
1405/*
1406 * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
1407 */
1408static void dct_prep_chip_selects(struct amd64_pvt *pvt)
1409{
1410 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
1411 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
1412 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
1413 } else if (pvt->fam == 0x15 && pvt->model == 0x30) {
1414 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
1415 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
1416 } else {
1417 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
1418 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
1419 }
1420}
1421
1422static void umc_prep_chip_selects(struct amd64_pvt *pvt)
1423{
1424 int umc;
1425
1426 for_each_umc(umc) {
1427 pvt->csels[umc].b_cnt = 4;
1428 pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2;
1429 }
1430}
1431
1432static void umc_read_base_mask(struct amd64_pvt *pvt)
1433{
1434 u32 umc_base_reg, umc_base_reg_sec;
1435 u32 umc_mask_reg, umc_mask_reg_sec;
1436 u32 base_reg, base_reg_sec;
1437 u32 mask_reg, mask_reg_sec;
1438 u32 *base, *base_sec;
1439 u32 *mask, *mask_sec;
1440 int cs, umc;
1441 u32 tmp;
1442
1443 for_each_umc(umc) {
1444 umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;
1445 umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;
1446
1447 for_each_chip_select(cs, umc, pvt) {
1448 base = &pvt->csels[umc].csbases[cs];
1449 base_sec = &pvt->csels[umc].csbases_sec[cs];
1450
1451 base_reg = umc_base_reg + (cs * 4);
1452 base_reg_sec = umc_base_reg_sec + (cs * 4);
1453
1454 if (!amd_smn_read(pvt->mc_node_id, base_reg, &tmp)) {
1455 *base = tmp;
1456 edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n",
1457 umc, cs, *base, base_reg);
1458 }
1459
1460 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, &tmp)) {
1461 *base_sec = tmp;
1462 edac_dbg(0, " DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n",
1463 umc, cs, *base_sec, base_reg_sec);
1464 }
1465 }
1466
1467 umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;
1468 umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(pvt, UMCCH_ADDR_MASK_SEC);
1469
1470 for_each_chip_select_mask(cs, umc, pvt) {
1471 mask = &pvt->csels[umc].csmasks[cs];
1472 mask_sec = &pvt->csels[umc].csmasks_sec[cs];
1473
1474 mask_reg = umc_mask_reg + (cs * 4);
1475 mask_reg_sec = umc_mask_reg_sec + (cs * 4);
1476
1477 if (!amd_smn_read(pvt->mc_node_id, mask_reg, &tmp)) {
1478 *mask = tmp;
1479 edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n",
1480 umc, cs, *mask, mask_reg);
1481 }
1482
1483 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, &tmp)) {
1484 *mask_sec = tmp;
1485 edac_dbg(0, " DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n",
1486 umc, cs, *mask_sec, mask_reg_sec);
1487 }
1488 }
1489 }
1490}
1491
1492/*
1493 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
1494 */
1495static void dct_read_base_mask(struct amd64_pvt *pvt)
1496{
1497 int cs;
1498
1499 for_each_chip_select(cs, 0, pvt) {
1500 int reg0 = DCSB0 + (cs * 4);
1501 int reg1 = DCSB1 + (cs * 4);
1502 u32 *base0 = &pvt->csels[0].csbases[cs];
1503 u32 *base1 = &pvt->csels[1].csbases[cs];
1504
1505 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
1506 edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
1507 cs, *base0, reg0);
1508
1509 if (pvt->fam == 0xf)
1510 continue;
1511
1512 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
1513 edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
1514 cs, *base1, (pvt->fam == 0x10) ? reg1
1515 : reg0);
1516 }
1517
1518 for_each_chip_select_mask(cs, 0, pvt) {
1519 int reg0 = DCSM0 + (cs * 4);
1520 int reg1 = DCSM1 + (cs * 4);
1521 u32 *mask0 = &pvt->csels[0].csmasks[cs];
1522 u32 *mask1 = &pvt->csels[1].csmasks[cs];
1523
1524 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
1525 edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
1526 cs, *mask0, reg0);
1527
1528 if (pvt->fam == 0xf)
1529 continue;
1530
1531 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
1532 edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
1533 cs, *mask1, (pvt->fam == 0x10) ? reg1
1534 : reg0);
1535 }
1536}
1537
1538static void umc_determine_memory_type(struct amd64_pvt *pvt)
1539{
1540 struct amd64_umc *umc;
1541 u32 i;
1542
1543 for_each_umc(i) {
1544 umc = &pvt->umc[i];
1545
1546 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) {
1547 umc->dram_type = MEM_EMPTY;
1548 continue;
1549 }
1550
1551 /*
1552 * Check if the system supports the "DDR Type" field in UMC Config
1553 * and has DDR5 DIMMs in use.
1554 */
1555 if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {
1556 if (umc->dimm_cfg & BIT(5))
1557 umc->dram_type = MEM_LRDDR5;
1558 else if (umc->dimm_cfg & BIT(4))
1559 umc->dram_type = MEM_RDDR5;
1560 else
1561 umc->dram_type = MEM_DDR5;
1562 } else {
1563 if (umc->dimm_cfg & BIT(5))
1564 umc->dram_type = MEM_LRDDR4;
1565 else if (umc->dimm_cfg & BIT(4))
1566 umc->dram_type = MEM_RDDR4;
1567 else
1568 umc->dram_type = MEM_DDR4;
1569 }
1570
1571 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]);
1572 }
1573}
1574
1575static void dct_determine_memory_type(struct amd64_pvt *pvt)
1576{
1577 u32 dram_ctrl, dcsm;
1578
1579 switch (pvt->fam) {
1580 case 0xf:
1581 if (pvt->ext_model >= K8_REV_F)
1582 goto ddr3;
1583
1584 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
1585 return;
1586
1587 case 0x10:
1588 if (pvt->dchr0 & DDR3_MODE)
1589 goto ddr3;
1590
1591 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
1592 return;
1593
1594 case 0x15:
1595 if (pvt->model < 0x60)
1596 goto ddr3;
1597
1598 /*
1599 * Model 0x60h needs special handling:
1600 *
1601 * We use a Chip Select value of '0' to obtain dcsm.
1602 * Theoretically, it is possible to populate LRDIMMs of different
1603 * 'Rank' value on a DCT. But this is not the common case. So,
1604 * it's reasonable to assume all DIMMs are going to be of same
1605 * 'type' until proven otherwise.
1606 */
1607 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl);
1608 dcsm = pvt->csels[0].csmasks[0];
1609
1610 if (((dram_ctrl >> 8) & 0x7) == 0x2)
1611 pvt->dram_type = MEM_DDR4;
1612 else if (pvt->dclr0 & BIT(16))
1613 pvt->dram_type = MEM_DDR3;
1614 else if (dcsm & 0x3)
1615 pvt->dram_type = MEM_LRDDR3;
1616 else
1617 pvt->dram_type = MEM_RDDR3;
1618
1619 return;
1620
1621 case 0x16:
1622 goto ddr3;
1623
1624 default:
1625 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);
1626 pvt->dram_type = MEM_EMPTY;
1627 }
1628
1629 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]);
1630 return;
1631
1632ddr3:
1633 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
1634}
1635
1636/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
1637static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
1638{
1639 u16 mce_nid = topology_amd_node_id(m->extcpu);
1640 struct mem_ctl_info *mci;
1641 u8 start_bit = 1;
1642 u8 end_bit = 47;
1643 u64 addr;
1644
1645 mci = edac_mc_find(mce_nid);
1646 if (!mci)
1647 return 0;
1648
1649 pvt = mci->pvt_info;
1650
1651 if (pvt->fam == 0xf) {
1652 start_bit = 3;
1653 end_bit = 39;
1654 }
1655
1656 addr = m->addr & GENMASK_ULL(end_bit, start_bit);
1657
1658 /*
1659 * Erratum 637 workaround
1660 */
1661 if (pvt->fam == 0x15) {
1662 u64 cc6_base, tmp_addr;
1663 u32 tmp;
1664 u8 intlv_en;
1665
1666 if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)
1667 return addr;
1668
1669
1670 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
1671 intlv_en = tmp >> 21 & 0x7;
1672
1673 /* add [47:27] + 3 trailing bits */
1674 cc6_base = (tmp & GENMASK_ULL(20, 0)) << 3;
1675
1676 /* reverse and add DramIntlvEn */
1677 cc6_base |= intlv_en ^ 0x7;
1678
1679 /* pin at [47:24] */
1680 cc6_base <<= 24;
1681
1682 if (!intlv_en)
1683 return cc6_base | (addr & GENMASK_ULL(23, 0));
1684
1685 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
1686
1687 /* faster log2 */
1688 tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
1689
1690 /* OR DramIntlvSel into bits [14:12] */
1691 tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;
1692
1693 /* add remaining [11:0] bits from original MC4_ADDR */
1694 tmp_addr |= addr & GENMASK_ULL(11, 0);
1695
1696 return cc6_base | tmp_addr;
1697 }
1698
1699 return addr;
1700}
1701
1702static struct pci_dev *pci_get_related_function(unsigned int vendor,
1703 unsigned int device,
1704 struct pci_dev *related)
1705{
1706 struct pci_dev *dev = NULL;
1707
1708 while ((dev = pci_get_device(vendor, device, dev))) {
1709 if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
1710 (dev->bus->number == related->bus->number) &&
1711 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
1712 break;
1713 }
1714
1715 return dev;
1716}
1717
1718static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
1719{
1720 struct amd_northbridge *nb;
1721 struct pci_dev *f1 = NULL;
1722 unsigned int pci_func;
1723 int off = range << 3;
1724 u32 llim;
1725
1726 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
1727 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
1728
1729 if (pvt->fam == 0xf)
1730 return;
1731
1732 if (!dram_rw(pvt, range))
1733 return;
1734
1735 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
1736 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
1737
1738 /* F15h: factor in CC6 save area by reading dst node's limit reg */
1739 if (pvt->fam != 0x15)
1740 return;
1741
1742 nb = node_to_amd_nb(dram_dst_node(pvt, range));
1743 if (WARN_ON(!nb))
1744 return;
1745
1746 if (pvt->model == 0x60)
1747 pci_func = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1;
1748 else if (pvt->model == 0x30)
1749 pci_func = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1;
1750 else
1751 pci_func = PCI_DEVICE_ID_AMD_15H_NB_F1;
1752
1753 f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc);
1754 if (WARN_ON(!f1))
1755 return;
1756
1757 amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
1758
1759 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
1760
1761 /* {[39:27],111b} */
1762 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
1763
1764 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
1765
1766 /* [47:40] */
1767 pvt->ranges[range].lim.hi |= llim >> 13;
1768
1769 pci_dev_put(f1);
1770}
1771
1772static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1773 struct err_info *err)
1774{
1775 struct amd64_pvt *pvt = mci->pvt_info;
1776
1777 error_address_to_page_and_offset(sys_addr, err);
1778
1779 /*
1780 * Find out which node the error address belongs to. This may be
1781 * different from the node that detected the error.
1782 */
1783 err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
1784 if (!err->src_mci) {
1785 amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
1786 (unsigned long)sys_addr);
1787 err->err_code = ERR_NODE;
1788 return;
1789 }
1790
1791 /* Now map the sys_addr to a CSROW */
1792 err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
1793 if (err->csrow < 0) {
1794 err->err_code = ERR_CSROW;
1795 return;
1796 }
1797
1798 /* CHIPKILL enabled */
1799 if (pvt->nbcfg & NBCFG_CHIPKILL) {
1800 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
1801 if (err->channel < 0) {
1802 /*
1803 * Syndrome didn't map, so we don't know which of the
1804 * 2 DIMMs is in error. So we need to ID 'both' of them
1805 * as suspect.
1806 */
1807 amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - "
1808 "possible error reporting race\n",
1809 err->syndrome);
1810 err->err_code = ERR_CHANNEL;
1811 return;
1812 }
1813 } else {
1814 /*
1815 * non-chipkill ecc mode
1816 *
1817 * The k8 documentation is unclear about how to determine the
1818 * channel number when using non-chipkill memory. This method
1819 * was obtained from email communication with someone at AMD.
1820 * (Wish the email was placed in this comment - norsk)
1821 */
1822 err->channel = ((sys_addr & BIT(3)) != 0);
1823 }
1824}
1825
1826static int ddr2_cs_size(unsigned i, bool dct_width)
1827{
1828 unsigned shift = 0;
1829
1830 if (i <= 2)
1831 shift = i;
1832 else if (!(i & 0x1))
1833 shift = i >> 1;
1834 else
1835 shift = (i + 1) >> 1;
1836
1837 return 128 << (shift + !!dct_width);
1838}
1839
1840static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1841 unsigned cs_mode, int cs_mask_nr)
1842{
1843 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
1844
1845 if (pvt->ext_model >= K8_REV_F) {
1846 WARN_ON(cs_mode > 11);
1847 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
1848 }
1849 else if (pvt->ext_model >= K8_REV_D) {
1850 unsigned diff;
1851 WARN_ON(cs_mode > 10);
1852
1853 /*
1854 * the below calculation, besides trying to win an obfuscated C
1855 * contest, maps cs_mode values to DIMM chip select sizes. The
1856 * mappings are:
1857 *
1858 * cs_mode CS size (mb)
1859 * ======= ============
1860 * 0 32
1861 * 1 64
1862 * 2 128
1863 * 3 128
1864 * 4 256
1865 * 5 512
1866 * 6 256
1867 * 7 512
1868 * 8 1024
1869 * 9 1024
1870 * 10 2048
1871 *
1872 * Basically, it calculates a value with which to shift the
1873 * smallest CS size of 32MB.
1874 *
1875 * ddr[23]_cs_size have a similar purpose.
1876 */
1877 diff = cs_mode/3 + (unsigned)(cs_mode > 5);
1878
1879 return 32 << (cs_mode - diff);
1880 }
1881 else {
1882 WARN_ON(cs_mode > 6);
1883 return 32 << cs_mode;
1884 }
1885}
1886
1887static int ddr3_cs_size(unsigned i, bool dct_width)
1888{
1889 unsigned shift = 0;
1890 int cs_size = 0;
1891
1892 if (i == 0 || i == 3 || i == 4)
1893 cs_size = -1;
1894 else if (i <= 2)
1895 shift = i;
1896 else if (i == 12)
1897 shift = 7;
1898 else if (!(i & 0x1))
1899 shift = i >> 1;
1900 else
1901 shift = (i + 1) >> 1;
1902
1903 if (cs_size != -1)
1904 cs_size = (128 * (1 << !!dct_width)) << shift;
1905
1906 return cs_size;
1907}
1908
1909static int ddr3_lrdimm_cs_size(unsigned i, unsigned rank_multiply)
1910{
1911 unsigned shift = 0;
1912 int cs_size = 0;
1913
1914 if (i < 4 || i == 6)
1915 cs_size = -1;
1916 else if (i == 12)
1917 shift = 7;
1918 else if (!(i & 0x1))
1919 shift = i >> 1;
1920 else
1921 shift = (i + 1) >> 1;
1922
1923 if (cs_size != -1)
1924 cs_size = rank_multiply * (128 << shift);
1925
1926 return cs_size;
1927}
1928
1929static int ddr4_cs_size(unsigned i)
1930{
1931 int cs_size = 0;
1932
1933 if (i == 0)
1934 cs_size = -1;
1935 else if (i == 1)
1936 cs_size = 1024;
1937 else
1938 /* Min cs_size = 1G */
1939 cs_size = 1024 * (1 << (i >> 1));
1940
1941 return cs_size;
1942}
1943
1944static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1945 unsigned cs_mode, int cs_mask_nr)
1946{
1947 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
1948
1949 WARN_ON(cs_mode > 11);
1950
1951 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
1952 return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
1953 else
1954 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
1955}
1956
1957/*
1958 * F15h supports only 64bit DCT interfaces
1959 */
1960static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1961 unsigned cs_mode, int cs_mask_nr)
1962{
1963 WARN_ON(cs_mode > 12);
1964
1965 return ddr3_cs_size(cs_mode, false);
1966}
1967
1968/* F15h M60h supports DDR4 mapping as well.. */
1969static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1970 unsigned cs_mode, int cs_mask_nr)
1971{
1972 int cs_size;
1973 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];
1974
1975 WARN_ON(cs_mode > 12);
1976
1977 if (pvt->dram_type == MEM_DDR4) {
1978 if (cs_mode > 9)
1979 return -1;
1980
1981 cs_size = ddr4_cs_size(cs_mode);
1982 } else if (pvt->dram_type == MEM_LRDDR3) {
1983 unsigned rank_multiply = dcsm & 0xf;
1984
1985 if (rank_multiply == 3)
1986 rank_multiply = 4;
1987 cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply);
1988 } else {
1989 /* Minimum cs size is 512mb for F15hM60h*/
1990 if (cs_mode == 0x1)
1991 return -1;
1992
1993 cs_size = ddr3_cs_size(cs_mode, false);
1994 }
1995
1996 return cs_size;
1997}
1998
1999/*
2000 * F16h and F15h model 30h have only limited cs_modes.
2001 */
2002static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
2003 unsigned cs_mode, int cs_mask_nr)
2004{
2005 WARN_ON(cs_mode > 12);
2006
2007 if (cs_mode == 6 || cs_mode == 8 ||
2008 cs_mode == 9 || cs_mode == 12)
2009 return -1;
2010 else
2011 return ddr3_cs_size(cs_mode, false);
2012}
2013
2014static void read_dram_ctl_register(struct amd64_pvt *pvt)
2015{
2016
2017 if (pvt->fam == 0xf)
2018 return;
2019
2020 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
2021 edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
2022 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
2023
2024 edac_dbg(0, " DCTs operate in %s mode\n",
2025 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
2026
2027 if (!dct_ganging_enabled(pvt))
2028 edac_dbg(0, " Address range split per DCT: %s\n",
2029 (dct_high_range_enabled(pvt) ? "yes" : "no"));
2030
2031 edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
2032 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
2033 (dct_memory_cleared(pvt) ? "yes" : "no"));
2034
2035 edac_dbg(0, " channel interleave: %s, "
2036 "interleave bits selector: 0x%x\n",
2037 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
2038 dct_sel_interleave_addr(pvt));
2039 }
2040
2041 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi);
2042}
2043
2044/*
2045 * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG,
2046 * 2.10.12 Memory Interleaving Modes).
2047 */
2048static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
2049 u8 intlv_en, int num_dcts_intlv,
2050 u32 dct_sel)
2051{
2052 u8 channel = 0;
2053 u8 select;
2054
2055 if (!(intlv_en))
2056 return (u8)(dct_sel);
2057
2058 if (num_dcts_intlv == 2) {
2059 select = (sys_addr >> 8) & 0x3;
2060 channel = select ? 0x3 : 0;
2061 } else if (num_dcts_intlv == 4) {
2062 u8 intlv_addr = dct_sel_interleave_addr(pvt);
2063 switch (intlv_addr) {
2064 case 0x4:
2065 channel = (sys_addr >> 8) & 0x3;
2066 break;
2067 case 0x5:
2068 channel = (sys_addr >> 9) & 0x3;
2069 break;
2070 }
2071 }
2072 return channel;
2073}
2074
2075/*
2076 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
2077 * Interleaving Modes.
2078 */
2079static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
2080 bool hi_range_sel, u8 intlv_en)
2081{
2082 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
2083
2084 if (dct_ganging_enabled(pvt))
2085 return 0;
2086
2087 if (hi_range_sel)
2088 return dct_sel_high;
2089
2090 /*
2091 * see F2x110[DctSelIntLvAddr] - channel interleave mode
2092 */
2093 if (dct_interleave_enabled(pvt)) {
2094 u8 intlv_addr = dct_sel_interleave_addr(pvt);
2095
2096 /* return DCT select function: 0=DCT0, 1=DCT1 */
2097 if (!intlv_addr)
2098 return sys_addr >> 6 & 1;
2099
2100 if (intlv_addr & 0x2) {
2101 u8 shift = intlv_addr & 0x1 ? 9 : 6;
2102 u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) & 1;
2103
2104 return ((sys_addr >> shift) & 1) ^ temp;
2105 }
2106
2107 if (intlv_addr & 0x4) {
2108 u8 shift = intlv_addr & 0x1 ? 9 : 8;
2109
2110 return (sys_addr >> shift) & 1;
2111 }
2112
2113 return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
2114 }
2115
2116 if (dct_high_range_enabled(pvt))
2117 return ~dct_sel_high & 1;
2118
2119 return 0;
2120}
2121
2122/* Convert the sys_addr to the normalized DCT address */
2123static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
2124 u64 sys_addr, bool hi_rng,
2125 u32 dct_sel_base_addr)
2126{
2127 u64 chan_off;
2128 u64 dram_base = get_dram_base(pvt, range);
2129 u64 hole_off = f10_dhar_offset(pvt);
2130 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
2131
2132 if (hi_rng) {
2133 /*
2134 * if
2135 * base address of high range is below 4Gb
2136 * (bits [47:27] at [31:11])
2137 * DRAM address space on this DCT is hoisted above 4Gb &&
2138 * sys_addr > 4Gb
2139 *
2140 * remove hole offset from sys_addr
2141 * else
2142 * remove high range offset from sys_addr
2143 */
2144 if ((!(dct_sel_base_addr >> 16) ||
2145 dct_sel_base_addr < dhar_base(pvt)) &&
2146 dhar_valid(pvt) &&
2147 (sys_addr >= BIT_64(32)))
2148 chan_off = hole_off;
2149 else
2150 chan_off = dct_sel_base_off;
2151 } else {
2152 /*
2153 * if
2154 * we have a valid hole &&
2155 * sys_addr > 4Gb
2156 *
2157 * remove hole
2158 * else
2159 * remove dram base to normalize to DCT address
2160 */
2161 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
2162 chan_off = hole_off;
2163 else
2164 chan_off = dram_base;
2165 }
2166
2167 return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));
2168}
2169
2170/*
2171 * checks if the csrow passed in is marked as SPARED, if so returns the new
2172 * spare row
2173 */
2174static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
2175{
2176 int tmp_cs;
2177
2178 if (online_spare_swap_done(pvt, dct) &&
2179 csrow == online_spare_bad_dramcs(pvt, dct)) {
2180
2181 for_each_chip_select(tmp_cs, dct, pvt) {
2182 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
2183 csrow = tmp_cs;
2184 break;
2185 }
2186 }
2187 }
2188 return csrow;
2189}
2190
2191/*
2192 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
2193 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
2194 *
2195 * Return:
2196 * -EINVAL: NOT FOUND
2197 * 0..csrow = Chip-Select Row
2198 */
2199static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
2200{
2201 struct mem_ctl_info *mci;
2202 struct amd64_pvt *pvt;
2203 u64 cs_base, cs_mask;
2204 int cs_found = -EINVAL;
2205 int csrow;
2206
2207 mci = edac_mc_find(nid);
2208 if (!mci)
2209 return cs_found;
2210
2211 pvt = mci->pvt_info;
2212
2213 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
2214
2215 for_each_chip_select(csrow, dct, pvt) {
2216 if (!csrow_enabled(csrow, dct, pvt))
2217 continue;
2218
2219 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
2220
2221 edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
2222 csrow, cs_base, cs_mask);
2223
2224 cs_mask = ~cs_mask;
2225
2226 edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
2227 (in_addr & cs_mask), (cs_base & cs_mask));
2228
2229 if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
2230 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
2231 cs_found = csrow;
2232 break;
2233 }
2234 cs_found = f10_process_possible_spare(pvt, dct, csrow);
2235
2236 edac_dbg(1, " MATCH csrow=%d\n", cs_found);
2237 break;
2238 }
2239 }
2240 return cs_found;
2241}
2242
2243/*
2244 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
2245 * swapped with a region located at the bottom of memory so that the GPU can use
2246 * the interleaved region and thus two channels.
2247 */
2248static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
2249{
2250 u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;
2251
2252 if (pvt->fam == 0x10) {
2253 /* only revC3 and revE have that feature */
2254 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3))
2255 return sys_addr;
2256 }
2257
2258 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg);
2259
2260 if (!(swap_reg & 0x1))
2261 return sys_addr;
2262
2263 swap_base = (swap_reg >> 3) & 0x7f;
2264 swap_limit = (swap_reg >> 11) & 0x7f;
2265 rgn_size = (swap_reg >> 20) & 0x7f;
2266 tmp_addr = sys_addr >> 27;
2267
2268 if (!(sys_addr >> 34) &&
2269 (((tmp_addr >= swap_base) &&
2270 (tmp_addr <= swap_limit)) ||
2271 (tmp_addr < rgn_size)))
2272 return sys_addr ^ (u64)swap_base << 27;
2273
2274 return sys_addr;
2275}
2276
2277/* For a given @dram_range, check if @sys_addr falls within it. */
2278static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
2279 u64 sys_addr, int *chan_sel)
2280{
2281 int cs_found = -EINVAL;
2282 u64 chan_addr;
2283 u32 dct_sel_base;
2284 u8 channel;
2285 bool high_range = false;
2286
2287 u8 node_id = dram_dst_node(pvt, range);
2288 u8 intlv_en = dram_intlv_en(pvt, range);
2289 u32 intlv_sel = dram_intlv_sel(pvt, range);
2290
2291 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2292 range, sys_addr, get_dram_limit(pvt, range));
2293
2294 if (dhar_valid(pvt) &&
2295 dhar_base(pvt) <= sys_addr &&
2296 sys_addr < BIT_64(32)) {
2297 amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
2298 sys_addr);
2299 return -EINVAL;
2300 }
2301
2302 if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
2303 return -EINVAL;
2304
2305 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
2306
2307 dct_sel_base = dct_sel_baseaddr(pvt);
2308
2309 /*
2310 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
2311 * select between DCT0 and DCT1.
2312 */
2313 if (dct_high_range_enabled(pvt) &&
2314 !dct_ganging_enabled(pvt) &&
2315 ((sys_addr >> 27) >= (dct_sel_base >> 11)))
2316 high_range = true;
2317
2318 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
2319
2320 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
2321 high_range, dct_sel_base);
2322
2323 /* Remove node interleaving, see F1x120 */
2324 if (intlv_en)
2325 chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
2326 (chan_addr & 0xfff);
2327
2328 /* remove channel interleave */
2329 if (dct_interleave_enabled(pvt) &&
2330 !dct_high_range_enabled(pvt) &&
2331 !dct_ganging_enabled(pvt)) {
2332
2333 if (dct_sel_interleave_addr(pvt) != 1) {
2334 if (dct_sel_interleave_addr(pvt) == 0x3)
2335 /* hash 9 */
2336 chan_addr = ((chan_addr >> 10) << 9) |
2337 (chan_addr & 0x1ff);
2338 else
2339 /* A[6] or hash 6 */
2340 chan_addr = ((chan_addr >> 7) << 6) |
2341 (chan_addr & 0x3f);
2342 } else
2343 /* A[12] */
2344 chan_addr = ((chan_addr >> 13) << 12) |
2345 (chan_addr & 0xfff);
2346 }
2347
2348 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
2349
2350 cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
2351
2352 if (cs_found >= 0)
2353 *chan_sel = channel;
2354
2355 return cs_found;
2356}
2357
2358static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
2359 u64 sys_addr, int *chan_sel)
2360{
2361 int cs_found = -EINVAL;
2362 int num_dcts_intlv = 0;
2363 u64 chan_addr, chan_offset;
2364 u64 dct_base, dct_limit;
2365 u32 dct_cont_base_reg, dct_cont_limit_reg, tmp;
2366 u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en;
2367
2368 u64 dhar_offset = f10_dhar_offset(pvt);
2369 u8 intlv_addr = dct_sel_interleave_addr(pvt);
2370 u8 node_id = dram_dst_node(pvt, range);
2371 u8 intlv_en = dram_intlv_en(pvt, range);
2372
2373 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg);
2374 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg);
2375
2376 dct_offset_en = (u8) ((dct_cont_base_reg >> 3) & BIT(0));
2377 dct_sel = (u8) ((dct_cont_base_reg >> 4) & 0x7);
2378
2379 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2380 range, sys_addr, get_dram_limit(pvt, range));
2381
2382 if (!(get_dram_base(pvt, range) <= sys_addr) &&
2383 !(get_dram_limit(pvt, range) >= sys_addr))
2384 return -EINVAL;
2385
2386 if (dhar_valid(pvt) &&
2387 dhar_base(pvt) <= sys_addr &&
2388 sys_addr < BIT_64(32)) {
2389 amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
2390 sys_addr);
2391 return -EINVAL;
2392 }
2393
2394 /* Verify sys_addr is within DCT Range. */
2395 dct_base = (u64) dct_sel_baseaddr(pvt);
2396 dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF;
2397
2398 if (!(dct_cont_base_reg & BIT(0)) &&
2399 !(dct_base <= (sys_addr >> 27) &&
2400 dct_limit >= (sys_addr >> 27)))
2401 return -EINVAL;
2402
2403 /* Verify number of dct's that participate in channel interleaving. */
2404 num_dcts_intlv = (int) hweight8(intlv_en);
2405
2406 if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4))
2407 return -EINVAL;
2408
2409 if (pvt->model >= 0x60)
2410 channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en);
2411 else
2412 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
2413 num_dcts_intlv, dct_sel);
2414
2415 /* Verify we stay within the MAX number of channels allowed */
2416 if (channel > 3)
2417 return -EINVAL;
2418
2419 leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0));
2420
2421 /* Get normalized DCT addr */
2422 if (leg_mmio_hole && (sys_addr >= BIT_64(32)))
2423 chan_offset = dhar_offset;
2424 else
2425 chan_offset = dct_base << 27;
2426
2427 chan_addr = sys_addr - chan_offset;
2428
2429 /* remove channel interleave */
2430 if (num_dcts_intlv == 2) {
2431 if (intlv_addr == 0x4)
2432 chan_addr = ((chan_addr >> 9) << 8) |
2433 (chan_addr & 0xff);
2434 else if (intlv_addr == 0x5)
2435 chan_addr = ((chan_addr >> 10) << 9) |
2436 (chan_addr & 0x1ff);
2437 else
2438 return -EINVAL;
2439
2440 } else if (num_dcts_intlv == 4) {
2441 if (intlv_addr == 0x4)
2442 chan_addr = ((chan_addr >> 10) << 8) |
2443 (chan_addr & 0xff);
2444 else if (intlv_addr == 0x5)
2445 chan_addr = ((chan_addr >> 11) << 9) |
2446 (chan_addr & 0x1ff);
2447 else
2448 return -EINVAL;
2449 }
2450
2451 if (dct_offset_en) {
2452 amd64_read_pci_cfg(pvt->F1,
2453 DRAM_CONT_HIGH_OFF + (int) channel * 4,
2454 &tmp);
2455 chan_addr += (u64) ((tmp >> 11) & 0xfff) << 27;
2456 }
2457
2458 f15h_select_dct(pvt, channel);
2459
2460 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
2461
2462 /*
2463 * Find Chip select:
2464 * if channel = 3, then alias it to 1. This is because, in F15 M30h,
2465 * there is support for 4 DCT's, but only 2 are currently functional.
2466 * They are DCT0 and DCT3. But we have read all registers of DCT3 into
2467 * pvt->csels[1]. So we need to use '1' here to get correct info.
2468 * Refer F15 M30h BKDG Section 2.10 and 2.10.3 for clarifications.
2469 */
2470 alias_channel = (channel == 3) ? 1 : channel;
2471
2472 cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, alias_channel);
2473
2474 if (cs_found >= 0)
2475 *chan_sel = alias_channel;
2476
2477 return cs_found;
2478}
2479
2480static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt,
2481 u64 sys_addr,
2482 int *chan_sel)
2483{
2484 int cs_found = -EINVAL;
2485 unsigned range;
2486
2487 for (range = 0; range < DRAM_RANGES; range++) {
2488 if (!dram_rw(pvt, range))
2489 continue;
2490
2491 if (pvt->fam == 0x15 && pvt->model >= 0x30)
2492 cs_found = f15_m30h_match_to_this_node(pvt, range,
2493 sys_addr,
2494 chan_sel);
2495
2496 else if ((get_dram_base(pvt, range) <= sys_addr) &&
2497 (get_dram_limit(pvt, range) >= sys_addr)) {
2498 cs_found = f1x_match_to_this_node(pvt, range,
2499 sys_addr, chan_sel);
2500 if (cs_found >= 0)
2501 break;
2502 }
2503 }
2504 return cs_found;
2505}
2506
2507/*
2508 * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
2509 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
2510 *
2511 * The @sys_addr is usually an error address received from the hardware
2512 * (MCX_ADDR).
2513 */
2514static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
2515 struct err_info *err)
2516{
2517 struct amd64_pvt *pvt = mci->pvt_info;
2518
2519 error_address_to_page_and_offset(sys_addr, err);
2520
2521 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
2522 if (err->csrow < 0) {
2523 err->err_code = ERR_CSROW;
2524 return;
2525 }
2526
2527 /*
2528 * We need the syndromes for channel detection only when we're
2529 * ganged. Otherwise @chan should already contain the channel at
2530 * this point.
2531 */
2532 if (dct_ganging_enabled(pvt))
2533 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
2534}
2535
2536/*
2537 * These are tables of eigenvectors (one per line) which can be used for the
2538 * construction of the syndrome tables. The modified syndrome search algorithm
2539 * uses those to find the symbol in error and thus the DIMM.
2540 *
2541 * Algorithm courtesy of Ross LaFetra from AMD.
2542 */
2543static const u16 x4_vectors[] = {
2544 0x2f57, 0x1afe, 0x66cc, 0xdd88,
2545 0x11eb, 0x3396, 0x7f4c, 0xeac8,
2546 0x0001, 0x0002, 0x0004, 0x0008,
2547 0x1013, 0x3032, 0x4044, 0x8088,
2548 0x106b, 0x30d6, 0x70fc, 0xe0a8,
2549 0x4857, 0xc4fe, 0x13cc, 0x3288,
2550 0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
2551 0x1f39, 0x251e, 0xbd6c, 0x6bd8,
2552 0x15c1, 0x2a42, 0x89ac, 0x4758,
2553 0x2b03, 0x1602, 0x4f0c, 0xca08,
2554 0x1f07, 0x3a0e, 0x6b04, 0xbd08,
2555 0x8ba7, 0x465e, 0x244c, 0x1cc8,
2556 0x2b87, 0x164e, 0x642c, 0xdc18,
2557 0x40b9, 0x80de, 0x1094, 0x20e8,
2558 0x27db, 0x1eb6, 0x9dac, 0x7b58,
2559 0x11c1, 0x2242, 0x84ac, 0x4c58,
2560 0x1be5, 0x2d7a, 0x5e34, 0xa718,
2561 0x4b39, 0x8d1e, 0x14b4, 0x28d8,
2562 0x4c97, 0xc87e, 0x11fc, 0x33a8,
2563 0x8e97, 0x497e, 0x2ffc, 0x1aa8,
2564 0x16b3, 0x3d62, 0x4f34, 0x8518,
2565 0x1e2f, 0x391a, 0x5cac, 0xf858,
2566 0x1d9f, 0x3b7a, 0x572c, 0xfe18,
2567 0x15f5, 0x2a5a, 0x5264, 0xa3b8,
2568 0x1dbb, 0x3b66, 0x715c, 0xe3f8,
2569 0x4397, 0xc27e, 0x17fc, 0x3ea8,
2570 0x1617, 0x3d3e, 0x6464, 0xb8b8,
2571 0x23ff, 0x12aa, 0xab6c, 0x56d8,
2572 0x2dfb, 0x1ba6, 0x913c, 0x7328,
2573 0x185d, 0x2ca6, 0x7914, 0x9e28,
2574 0x171b, 0x3e36, 0x7d7c, 0xebe8,
2575 0x4199, 0x82ee, 0x19f4, 0x2e58,
2576 0x4807, 0xc40e, 0x130c, 0x3208,
2577 0x1905, 0x2e0a, 0x5804, 0xac08,
2578 0x213f, 0x132a, 0xadfc, 0x5ba8,
2579 0x19a9, 0x2efe, 0xb5cc, 0x6f88,
2580};
2581
2582static const u16 x8_vectors[] = {
2583 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
2584 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
2585 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
2586 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
2587 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
2588 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
2589 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
2590 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
2591 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
2592 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
2593 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
2594 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
2595 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
2596 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
2597 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
2598 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
2599 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
2600 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2601 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
2602};
2603
2604static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs,
2605 unsigned v_dim)
2606{
2607 unsigned int i, err_sym;
2608
2609 for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
2610 u16 s = syndrome;
2611 unsigned v_idx = err_sym * v_dim;
2612 unsigned v_end = (err_sym + 1) * v_dim;
2613
2614 /* walk over all 16 bits of the syndrome */
2615 for (i = 1; i < (1U << 16); i <<= 1) {
2616
2617 /* if bit is set in that eigenvector... */
2618 if (v_idx < v_end && vectors[v_idx] & i) {
2619 u16 ev_comp = vectors[v_idx++];
2620
2621 /* ... and bit set in the modified syndrome, */
2622 if (s & i) {
2623 /* remove it. */
2624 s ^= ev_comp;
2625
2626 if (!s)
2627 return err_sym;
2628 }
2629
2630 } else if (s & i)
2631 /* can't get to zero, move to next symbol */
2632 break;
2633 }
2634 }
2635
2636 edac_dbg(0, "syndrome(%x) not found\n", syndrome);
2637 return -1;
2638}
2639
2640static int map_err_sym_to_channel(int err_sym, int sym_size)
2641{
2642 if (sym_size == 4)
2643 switch (err_sym) {
2644 case 0x20:
2645 case 0x21:
2646 return 0;
2647 case 0x22:
2648 case 0x23:
2649 return 1;
2650 default:
2651 return err_sym >> 4;
2652 }
2653 /* x8 symbols */
2654 else
2655 switch (err_sym) {
2656 /* imaginary bits not in a DIMM */
2657 case 0x10:
2658 WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
2659 err_sym);
2660 return -1;
2661 case 0x11:
2662 return 0;
2663 case 0x12:
2664 return 1;
2665 default:
2666 return err_sym >> 3;
2667 }
2668 return -1;
2669}
2670
2671static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
2672{
2673 struct amd64_pvt *pvt = mci->pvt_info;
2674 int err_sym = -1;
2675
2676 if (pvt->ecc_sym_sz == 8)
2677 err_sym = decode_syndrome(syndrome, x8_vectors,
2678 ARRAY_SIZE(x8_vectors),
2679 pvt->ecc_sym_sz);
2680 else if (pvt->ecc_sym_sz == 4)
2681 err_sym = decode_syndrome(syndrome, x4_vectors,
2682 ARRAY_SIZE(x4_vectors),
2683 pvt->ecc_sym_sz);
2684 else {
2685 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
2686 return err_sym;
2687 }
2688
2689 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
2690}
2691
2692static void __log_ecc_error(struct mem_ctl_info *mci, struct err_info *err,
2693 u8 ecc_type)
2694{
2695 enum hw_event_mc_err_type err_type;
2696 const char *string;
2697
2698 if (ecc_type == 2)
2699 err_type = HW_EVENT_ERR_CORRECTED;
2700 else if (ecc_type == 1)
2701 err_type = HW_EVENT_ERR_UNCORRECTED;
2702 else if (ecc_type == 3)
2703 err_type = HW_EVENT_ERR_DEFERRED;
2704 else {
2705 WARN(1, "Something is rotten in the state of Denmark.\n");
2706 return;
2707 }
2708
2709 switch (err->err_code) {
2710 case DECODE_OK:
2711 string = "";
2712 break;
2713 case ERR_NODE:
2714 string = "Failed to map error addr to a node";
2715 break;
2716 case ERR_CSROW:
2717 string = "Failed to map error addr to a csrow";
2718 break;
2719 case ERR_CHANNEL:
2720 string = "Unknown syndrome - possible error reporting race";
2721 break;
2722 case ERR_SYND:
2723 string = "MCA_SYND not valid - unknown syndrome and csrow";
2724 break;
2725 case ERR_NORM_ADDR:
2726 string = "Cannot decode normalized address";
2727 break;
2728 default:
2729 string = "WTF error";
2730 break;
2731 }
2732
2733 edac_mc_handle_error(err_type, mci, 1,
2734 err->page, err->offset, err->syndrome,
2735 err->csrow, err->channel, -1,
2736 string, "");
2737}
2738
2739static inline void decode_bus_error(int node_id, struct mce *m)
2740{
2741 struct mem_ctl_info *mci;
2742 struct amd64_pvt *pvt;
2743 u8 ecc_type = (m->status >> 45) & 0x3;
2744 u8 xec = XEC(m->status, 0x1f);
2745 u16 ec = EC(m->status);
2746 u64 sys_addr;
2747 struct err_info err;
2748
2749 mci = edac_mc_find(node_id);
2750 if (!mci)
2751 return;
2752
2753 pvt = mci->pvt_info;
2754
2755 /* Bail out early if this was an 'observed' error */
2756 if (PP(ec) == NBSL_PP_OBS)
2757 return;
2758
2759 /* Do only ECC errors */
2760 if (xec && xec != F10_NBSL_EXT_ERR_ECC)
2761 return;
2762
2763 memset(&err, 0, sizeof(err));
2764
2765 sys_addr = get_error_address(pvt, m);
2766
2767 if (ecc_type == 2)
2768 err.syndrome = extract_syndrome(m->status);
2769
2770 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);
2771
2772 __log_ecc_error(mci, &err, ecc_type);
2773}
2774
2775/*
2776 * To find the UMC channel represented by this bank we need to match on its
2777 * instance_id. The instance_id of a bank is held in the lower 32 bits of its
2778 * IPID.
2779 *
2780 * Currently, we can derive the channel number by looking at the 6th nibble in
2781 * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel
2782 * number.
2783 *
2784 * For DRAM ECC errors, the Chip Select number is given in bits [2:0] of
2785 * the MCA_SYND[ErrorInformation] field.
2786 */
2787static void umc_get_err_info(struct mce *m, struct err_info *err)
2788{
2789 err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
2790 err->csrow = m->synd & 0x7;
2791}
2792
2793static void decode_umc_error(int node_id, struct mce *m)
2794{
2795 u8 ecc_type = (m->status >> 45) & 0x3;
2796 struct mem_ctl_info *mci;
2797 unsigned long sys_addr;
2798 struct amd64_pvt *pvt;
2799 struct atl_err a_err;
2800 struct err_info err;
2801
2802 node_id = fixup_node_id(node_id, m);
2803
2804 mci = edac_mc_find(node_id);
2805 if (!mci)
2806 return;
2807
2808 pvt = mci->pvt_info;
2809
2810 memset(&err, 0, sizeof(err));
2811
2812 if (m->status & MCI_STATUS_DEFERRED)
2813 ecc_type = 3;
2814
2815 if (!(m->status & MCI_STATUS_SYNDV)) {
2816 err.err_code = ERR_SYND;
2817 goto log_error;
2818 }
2819
2820 if (ecc_type == 2) {
2821 u8 length = (m->synd >> 18) & 0x3f;
2822
2823 if (length)
2824 err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0);
2825 else
2826 err.err_code = ERR_CHANNEL;
2827 }
2828
2829 pvt->ops->get_err_info(m, &err);
2830
2831 a_err.addr = m->addr;
2832 a_err.ipid = m->ipid;
2833 a_err.cpu = m->extcpu;
2834
2835 sys_addr = amd_convert_umc_mca_addr_to_sys_addr(&a_err);
2836 if (IS_ERR_VALUE(sys_addr)) {
2837 err.err_code = ERR_NORM_ADDR;
2838 goto log_error;
2839 }
2840
2841 error_address_to_page_and_offset(sys_addr, &err);
2842
2843log_error:
2844 __log_ecc_error(mci, &err, ecc_type);
2845}
2846
2847/*
2848 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
2849 * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
2850 */
2851static int
2852reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
2853{
2854 /* Reserve the ADDRESS MAP Device */
2855 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
2856 if (!pvt->F1) {
2857 edac_dbg(1, "F1 not found: device 0x%x\n", pci_id1);
2858 return -ENODEV;
2859 }
2860
2861 /* Reserve the DCT Device */
2862 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
2863 if (!pvt->F2) {
2864 pci_dev_put(pvt->F1);
2865 pvt->F1 = NULL;
2866
2867 edac_dbg(1, "F2 not found: device 0x%x\n", pci_id2);
2868 return -ENODEV;
2869 }
2870
2871 if (!pci_ctl_dev)
2872 pci_ctl_dev = &pvt->F2->dev;
2873
2874 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
2875 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
2876 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
2877
2878 return 0;
2879}
2880
2881static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
2882{
2883 pvt->ecc_sym_sz = 4;
2884
2885 if (pvt->fam >= 0x10) {
2886 u32 tmp;
2887
2888 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
2889 /* F16h has only DCT0, so no need to read dbam1. */
2890 if (pvt->fam != 0x16)
2891 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1);
2892
2893 /* F10h, revD and later can do x8 ECC too. */
2894 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))
2895 pvt->ecc_sym_sz = 8;
2896 }
2897}
2898
2899/*
2900 * Retrieve the hardware registers of the memory controller.
2901 */
2902static void umc_read_mc_regs(struct amd64_pvt *pvt)
2903{
2904 u8 nid = pvt->mc_node_id;
2905 struct amd64_umc *umc;
2906 u32 i, tmp, umc_base;
2907
2908 /* Read registers from each UMC */
2909 for_each_umc(i) {
2910
2911 umc_base = get_umc_base(i);
2912 umc = &pvt->umc[i];
2913
2914 if (!amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &tmp))
2915 umc->dimm_cfg = tmp;
2916
2917 if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &tmp))
2918 umc->umc_cfg = tmp;
2919
2920 if (!amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &tmp))
2921 umc->sdp_ctrl = tmp;
2922
2923 if (!amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &tmp))
2924 umc->ecc_ctrl = tmp;
2925
2926 if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &tmp))
2927 umc->umc_cap_hi = tmp;
2928 }
2929}
2930
2931/*
2932 * Retrieve the hardware registers of the memory controller (this includes the
2933 * 'Address Map' and 'Misc' device regs)
2934 */
2935static void dct_read_mc_regs(struct amd64_pvt *pvt)
2936{
2937 unsigned int range;
2938 u64 msr_val;
2939
2940 /*
2941 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
2942 * those are Read-As-Zero.
2943 */
2944 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
2945 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
2946
2947 /* Check first whether TOP_MEM2 is enabled: */
2948 rdmsrl(MSR_AMD64_SYSCFG, msr_val);
2949 if (msr_val & BIT(21)) {
2950 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
2951 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
2952 } else {
2953 edac_dbg(0, " TOP_MEM2 disabled\n");
2954 }
2955
2956 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
2957
2958 read_dram_ctl_register(pvt);
2959
2960 for (range = 0; range < DRAM_RANGES; range++) {
2961 u8 rw;
2962
2963 /* read settings for this DRAM range */
2964 read_dram_base_limit_regs(pvt, range);
2965
2966 rw = dram_rw(pvt, range);
2967 if (!rw)
2968 continue;
2969
2970 edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
2971 range,
2972 get_dram_base(pvt, range),
2973 get_dram_limit(pvt, range));
2974
2975 edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
2976 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
2977 (rw & 0x1) ? "R" : "-",
2978 (rw & 0x2) ? "W" : "-",
2979 dram_intlv_sel(pvt, range),
2980 dram_dst_node(pvt, range));
2981 }
2982
2983 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
2984 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0);
2985
2986 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
2987
2988 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0);
2989 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0);
2990
2991 if (!dct_ganging_enabled(pvt)) {
2992 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1);
2993 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
2994 }
2995
2996 determine_ecc_sym_sz(pvt);
2997}
2998
2999/*
3000 * NOTE: CPU Revision Dependent code
3001 *
3002 * Input:
3003 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
3004 * k8 private pointer to -->
3005 * DRAM Bank Address mapping register
3006 * node_id
3007 * DCL register where dual_channel_active is
3008 *
3009 * The DBAM register consists of 4 sets of 4 bits each definitions:
3010 *
3011 * Bits: CSROWs
3012 * 0-3 CSROWs 0 and 1
3013 * 4-7 CSROWs 2 and 3
3014 * 8-11 CSROWs 4 and 5
3015 * 12-15 CSROWs 6 and 7
3016 *
3017 * Values range from: 0 to 15
3018 * The meaning of the values depends on CPU revision and dual-channel state,
3019 * see relevant BKDG more info.
3020 *
3021 * The memory controller provides for total of only 8 CSROWs in its current
3022 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
3023 * single channel or two (2) DIMMs in dual channel mode.
3024 *
3025 * The following code logic collapses the various tables for CSROW based on CPU
3026 * revision.
3027 *
3028 * Returns:
3029 * The number of PAGE_SIZE pages on the specified CSROW number it
3030 * encompasses
3031 *
3032 */
3033static u32 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
3034{
3035 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
3036 u32 cs_mode, nr_pages;
3037
3038 csrow_nr >>= 1;
3039 cs_mode = DBAM_DIMM(csrow_nr, dbam);
3040
3041 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
3042 nr_pages <<= 20 - PAGE_SHIFT;
3043
3044 edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
3045 csrow_nr, dct, cs_mode);
3046 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3047
3048 return nr_pages;
3049}
3050
3051static u32 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig)
3052{
3053 int csrow_nr = csrow_nr_orig;
3054 u32 cs_mode, nr_pages;
3055
3056 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt);
3057
3058 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);
3059 nr_pages <<= 20 - PAGE_SHIFT;
3060
3061 edac_dbg(0, "csrow: %d, channel: %d, cs_mode %d\n",
3062 csrow_nr_orig, dct, cs_mode);
3063 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3064
3065 return nr_pages;
3066}
3067
3068static void umc_init_csrows(struct mem_ctl_info *mci)
3069{
3070 struct amd64_pvt *pvt = mci->pvt_info;
3071 enum edac_type edac_mode = EDAC_NONE;
3072 enum dev_type dev_type = DEV_UNKNOWN;
3073 struct dimm_info *dimm;
3074 u8 umc, cs;
3075
3076 if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) {
3077 edac_mode = EDAC_S16ECD16ED;
3078 dev_type = DEV_X16;
3079 } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) {
3080 edac_mode = EDAC_S8ECD8ED;
3081 dev_type = DEV_X8;
3082 } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) {
3083 edac_mode = EDAC_S4ECD4ED;
3084 dev_type = DEV_X4;
3085 } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) {
3086 edac_mode = EDAC_SECDED;
3087 }
3088
3089 for_each_umc(umc) {
3090 for_each_chip_select(cs, umc, pvt) {
3091 if (!csrow_enabled(cs, umc, pvt))
3092 continue;
3093
3094 dimm = mci->csrows[cs]->channels[umc]->dimm;
3095
3096 edac_dbg(1, "MC node: %d, csrow: %d\n",
3097 pvt->mc_node_id, cs);
3098
3099 dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs);
3100 dimm->mtype = pvt->umc[umc].dram_type;
3101 dimm->edac_mode = edac_mode;
3102 dimm->dtype = dev_type;
3103 dimm->grain = 64;
3104 }
3105 }
3106}
3107
3108/*
3109 * Initialize the array of csrow attribute instances, based on the values
3110 * from pci config hardware registers.
3111 */
3112static void dct_init_csrows(struct mem_ctl_info *mci)
3113{
3114 struct amd64_pvt *pvt = mci->pvt_info;
3115 enum edac_type edac_mode = EDAC_NONE;
3116 struct csrow_info *csrow;
3117 struct dimm_info *dimm;
3118 int nr_pages = 0;
3119 int i, j;
3120 u32 val;
3121
3122 amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
3123
3124 pvt->nbcfg = val;
3125
3126 edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
3127 pvt->mc_node_id, val,
3128 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
3129
3130 /*
3131 * We iterate over DCT0 here but we look at DCT1 in parallel, if needed.
3132 */
3133 for_each_chip_select(i, 0, pvt) {
3134 bool row_dct0 = !!csrow_enabled(i, 0, pvt);
3135 bool row_dct1 = false;
3136
3137 if (pvt->fam != 0xf)
3138 row_dct1 = !!csrow_enabled(i, 1, pvt);
3139
3140 if (!row_dct0 && !row_dct1)
3141 continue;
3142
3143 csrow = mci->csrows[i];
3144
3145 edac_dbg(1, "MC node: %d, csrow: %d\n",
3146 pvt->mc_node_id, i);
3147
3148 if (row_dct0) {
3149 nr_pages = dct_get_csrow_nr_pages(pvt, 0, i);
3150 csrow->channels[0]->dimm->nr_pages = nr_pages;
3151 }
3152
3153 /* K8 has only one DCT */
3154 if (pvt->fam != 0xf && row_dct1) {
3155 int row_dct1_pages = dct_get_csrow_nr_pages(pvt, 1, i);
3156
3157 csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
3158 nr_pages += row_dct1_pages;
3159 }
3160
3161 edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
3162
3163 /* Determine DIMM ECC mode: */
3164 if (pvt->nbcfg & NBCFG_ECC_ENABLE) {
3165 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL)
3166 ? EDAC_S4ECD4ED
3167 : EDAC_SECDED;
3168 }
3169
3170 for (j = 0; j < pvt->max_mcs; j++) {
3171 dimm = csrow->channels[j]->dimm;
3172 dimm->mtype = pvt->dram_type;
3173 dimm->edac_mode = edac_mode;
3174 dimm->grain = 64;
3175 }
3176 }
3177}
3178
3179/* get all cores on this DCT */
3180static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
3181{
3182 int cpu;
3183
3184 for_each_online_cpu(cpu)
3185 if (topology_amd_node_id(cpu) == nid)
3186 cpumask_set_cpu(cpu, mask);
3187}
3188
3189/* check MCG_CTL on all the cpus on this node */
3190static bool nb_mce_bank_enabled_on_node(u16 nid)
3191{
3192 cpumask_var_t mask;
3193 int cpu, nbe;
3194 bool ret = false;
3195
3196 if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
3197 amd64_warn("%s: Error allocating mask\n", __func__);
3198 return false;
3199 }
3200
3201 get_cpus_on_this_dct_cpumask(mask, nid);
3202
3203 rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);
3204
3205 for_each_cpu(cpu, mask) {
3206 struct msr *reg = per_cpu_ptr(msrs, cpu);
3207 nbe = reg->l & MSR_MCGCTL_NBE;
3208
3209 edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
3210 cpu, reg->q,
3211 (nbe ? "enabled" : "disabled"));
3212
3213 if (!nbe)
3214 goto out;
3215 }
3216 ret = true;
3217
3218out:
3219 free_cpumask_var(mask);
3220 return ret;
3221}
3222
3223static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on)
3224{
3225 cpumask_var_t cmask;
3226 int cpu;
3227
3228 if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
3229 amd64_warn("%s: error allocating mask\n", __func__);
3230 return -ENOMEM;
3231 }
3232
3233 get_cpus_on_this_dct_cpumask(cmask, nid);
3234
3235 rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
3236
3237 for_each_cpu(cpu, cmask) {
3238
3239 struct msr *reg = per_cpu_ptr(msrs, cpu);
3240
3241 if (on) {
3242 if (reg->l & MSR_MCGCTL_NBE)
3243 s->flags.nb_mce_enable = 1;
3244
3245 reg->l |= MSR_MCGCTL_NBE;
3246 } else {
3247 /*
3248 * Turn off NB MCE reporting only when it was off before
3249 */
3250 if (!s->flags.nb_mce_enable)
3251 reg->l &= ~MSR_MCGCTL_NBE;
3252 }
3253 }
3254 wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
3255
3256 free_cpumask_var(cmask);
3257
3258 return 0;
3259}
3260
3261static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid,
3262 struct pci_dev *F3)
3263{
3264 bool ret = true;
3265 u32 value, mask = 0x3; /* UECC/CECC enable */
3266
3267 if (toggle_ecc_err_reporting(s, nid, ON)) {
3268 amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
3269 return false;
3270 }
3271
3272 amd64_read_pci_cfg(F3, NBCTL, &value);
3273
3274 s->old_nbctl = value & mask;
3275 s->nbctl_valid = true;
3276
3277 value |= mask;
3278 amd64_write_pci_cfg(F3, NBCTL, value);
3279
3280 amd64_read_pci_cfg(F3, NBCFG, &value);
3281
3282 edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
3283 nid, value, !!(value & NBCFG_ECC_ENABLE));
3284
3285 if (!(value & NBCFG_ECC_ENABLE)) {
3286 amd64_warn("DRAM ECC disabled on this node, enabling...\n");
3287
3288 s->flags.nb_ecc_prev = 0;
3289
3290 /* Attempt to turn on DRAM ECC Enable */
3291 value |= NBCFG_ECC_ENABLE;
3292 amd64_write_pci_cfg(F3, NBCFG, value);
3293
3294 amd64_read_pci_cfg(F3, NBCFG, &value);
3295
3296 if (!(value & NBCFG_ECC_ENABLE)) {
3297 amd64_warn("Hardware rejected DRAM ECC enable,"
3298 "check memory DIMM configuration.\n");
3299 ret = false;
3300 } else {
3301 amd64_info("Hardware accepted DRAM ECC Enable\n");
3302 }
3303 } else {
3304 s->flags.nb_ecc_prev = 1;
3305 }
3306
3307 edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
3308 nid, value, !!(value & NBCFG_ECC_ENABLE));
3309
3310 return ret;
3311}
3312
3313static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
3314 struct pci_dev *F3)
3315{
3316 u32 value, mask = 0x3; /* UECC/CECC enable */
3317
3318 if (!s->nbctl_valid)
3319 return;
3320
3321 amd64_read_pci_cfg(F3, NBCTL, &value);
3322 value &= ~mask;
3323 value |= s->old_nbctl;
3324
3325 amd64_write_pci_cfg(F3, NBCTL, value);
3326
3327 /* restore previous BIOS DRAM ECC "off" setting we force-enabled */
3328 if (!s->flags.nb_ecc_prev) {
3329 amd64_read_pci_cfg(F3, NBCFG, &value);
3330 value &= ~NBCFG_ECC_ENABLE;
3331 amd64_write_pci_cfg(F3, NBCFG, value);
3332 }
3333
3334 /* restore the NB Enable MCGCTL bit */
3335 if (toggle_ecc_err_reporting(s, nid, OFF))
3336 amd64_warn("Error restoring NB MCGCTL settings!\n");
3337}
3338
3339static bool dct_ecc_enabled(struct amd64_pvt *pvt)
3340{
3341 u16 nid = pvt->mc_node_id;
3342 bool nb_mce_en = false;
3343 u8 ecc_en = 0;
3344 u32 value;
3345
3346 amd64_read_pci_cfg(pvt->F3, NBCFG, &value);
3347
3348 ecc_en = !!(value & NBCFG_ECC_ENABLE);
3349
3350 nb_mce_en = nb_mce_bank_enabled_on_node(nid);
3351 if (!nb_mce_en)
3352 edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
3353 MSR_IA32_MCG_CTL, nid);
3354
3355 edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));
3356
3357 if (!ecc_en || !nb_mce_en)
3358 return false;
3359 else
3360 return true;
3361}
3362
3363static bool umc_ecc_enabled(struct amd64_pvt *pvt)
3364{
3365 struct amd64_umc *umc;
3366 bool ecc_en = false;
3367 int i;
3368
3369 /* Check whether at least one UMC is enabled: */
3370 for_each_umc(i) {
3371 umc = &pvt->umc[i];
3372
3373 if (umc->sdp_ctrl & UMC_SDP_INIT &&
3374 umc->umc_cap_hi & UMC_ECC_ENABLED) {
3375 ecc_en = true;
3376 break;
3377 }
3378 }
3379
3380 edac_dbg(3, "Node %d: DRAM ECC %s.\n", pvt->mc_node_id, (ecc_en ? "enabled" : "disabled"));
3381
3382 return ecc_en;
3383}
3384
3385static inline void
3386umc_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
3387{
3388 u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1;
3389
3390 for_each_umc(i) {
3391 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
3392 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);
3393 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);
3394
3395 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6));
3396 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));
3397 }
3398 }
3399
3400 /* Set chipkill only if ECC is enabled: */
3401 if (ecc_en) {
3402 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
3403
3404 if (!cpk_en)
3405 return;
3406
3407 if (dev_x4)
3408 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
3409 else if (dev_x16)
3410 mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED;
3411 else
3412 mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED;
3413 }
3414}
3415
3416static void dct_setup_mci_misc_attrs(struct mem_ctl_info *mci)
3417{
3418 struct amd64_pvt *pvt = mci->pvt_info;
3419
3420 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
3421 mci->edac_ctl_cap = EDAC_FLAG_NONE;
3422
3423 if (pvt->nbcap & NBCAP_SECDED)
3424 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
3425
3426 if (pvt->nbcap & NBCAP_CHIPKILL)
3427 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
3428
3429 mci->edac_cap = dct_determine_edac_cap(pvt);
3430 mci->mod_name = EDAC_MOD_STR;
3431 mci->ctl_name = pvt->ctl_name;
3432 mci->dev_name = pci_name(pvt->F3);
3433 mci->ctl_page_to_phys = NULL;
3434
3435 /* memory scrubber interface */
3436 mci->set_sdram_scrub_rate = set_scrub_rate;
3437 mci->get_sdram_scrub_rate = get_scrub_rate;
3438
3439 dct_init_csrows(mci);
3440}
3441
3442static void umc_setup_mci_misc_attrs(struct mem_ctl_info *mci)
3443{
3444 struct amd64_pvt *pvt = mci->pvt_info;
3445
3446 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
3447 mci->edac_ctl_cap = EDAC_FLAG_NONE;
3448
3449 umc_determine_edac_ctl_cap(mci, pvt);
3450
3451 mci->edac_cap = umc_determine_edac_cap(pvt);
3452 mci->mod_name = EDAC_MOD_STR;
3453 mci->ctl_name = pvt->ctl_name;
3454 mci->dev_name = pci_name(pvt->F3);
3455 mci->ctl_page_to_phys = NULL;
3456
3457 umc_init_csrows(mci);
3458}
3459
3460static int dct_hw_info_get(struct amd64_pvt *pvt)
3461{
3462 int ret = reserve_mc_sibling_devs(pvt, pvt->f1_id, pvt->f2_id);
3463
3464 if (ret)
3465 return ret;
3466
3467 dct_prep_chip_selects(pvt);
3468 dct_read_base_mask(pvt);
3469 dct_read_mc_regs(pvt);
3470 dct_determine_memory_type(pvt);
3471
3472 return 0;
3473}
3474
3475static int umc_hw_info_get(struct amd64_pvt *pvt)
3476{
3477 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);
3478 if (!pvt->umc)
3479 return -ENOMEM;
3480
3481 umc_prep_chip_selects(pvt);
3482 umc_read_base_mask(pvt);
3483 umc_read_mc_regs(pvt);
3484 umc_determine_memory_type(pvt);
3485
3486 return 0;
3487}
3488
3489/*
3490 * The CPUs have one channel per UMC, so UMC number is equivalent to a
3491 * channel number. The GPUs have 8 channels per UMC, so the UMC number no
3492 * longer works as a channel number.
3493 *
3494 * The channel number within a GPU UMC is given in MCA_IPID[15:12].
3495 * However, the IDs are split such that two UMC values go to one UMC, and
3496 * the channel numbers are split in two groups of four.
3497 *
3498 * Refer to comment on gpu_get_umc_base().
3499 *
3500 * For example,
3501 * UMC0 CH[3:0] = 0x0005[3:0]000
3502 * UMC0 CH[7:4] = 0x0015[3:0]000
3503 * UMC1 CH[3:0] = 0x0025[3:0]000
3504 * UMC1 CH[7:4] = 0x0035[3:0]000
3505 */
3506static void gpu_get_err_info(struct mce *m, struct err_info *err)
3507{
3508 u8 ch = (m->ipid & GENMASK(31, 0)) >> 20;
3509 u8 phy = ((m->ipid >> 12) & 0xf);
3510
3511 err->channel = ch % 2 ? phy + 4 : phy;
3512 err->csrow = phy;
3513}
3514
3515static int gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
3516 unsigned int cs_mode, int csrow_nr)
3517{
3518 u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr];
3519
3520 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, csrow_nr >> 1);
3521}
3522
3523static void gpu_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
3524{
3525 int size, cs_mode, cs = 0;
3526
3527 edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
3528
3529 cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY;
3530
3531 for_each_chip_select(cs, ctrl, pvt) {
3532 size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs);
3533 amd64_info(EDAC_MC ": %d: %5dMB\n", cs, size);
3534 }
3535}
3536
3537static void gpu_dump_misc_regs(struct amd64_pvt *pvt)
3538{
3539 struct amd64_umc *umc;
3540 u32 i;
3541
3542 for_each_umc(i) {
3543 umc = &pvt->umc[i];
3544
3545 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
3546 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
3547 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
3548 edac_dbg(1, "UMC%d All HBMs support ECC: yes\n", i);
3549
3550 gpu_debug_display_dimm_sizes(pvt, i);
3551 }
3552}
3553
3554static u32 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
3555{
3556 u32 nr_pages;
3557 int cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY;
3558
3559 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);
3560 nr_pages <<= 20 - PAGE_SHIFT;
3561
3562 edac_dbg(0, "csrow: %d, channel: %d\n", csrow_nr, dct);
3563 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3564
3565 return nr_pages;
3566}
3567
3568static void gpu_init_csrows(struct mem_ctl_info *mci)
3569{
3570 struct amd64_pvt *pvt = mci->pvt_info;
3571 struct dimm_info *dimm;
3572 u8 umc, cs;
3573
3574 for_each_umc(umc) {
3575 for_each_chip_select(cs, umc, pvt) {
3576 if (!csrow_enabled(cs, umc, pvt))
3577 continue;
3578
3579 dimm = mci->csrows[umc]->channels[cs]->dimm;
3580
3581 edac_dbg(1, "MC node: %d, csrow: %d\n",
3582 pvt->mc_node_id, cs);
3583
3584 dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs);
3585 dimm->edac_mode = EDAC_SECDED;
3586 dimm->mtype = pvt->dram_type;
3587 dimm->dtype = DEV_X16;
3588 dimm->grain = 64;
3589 }
3590 }
3591}
3592
3593static void gpu_setup_mci_misc_attrs(struct mem_ctl_info *mci)
3594{
3595 struct amd64_pvt *pvt = mci->pvt_info;
3596
3597 mci->mtype_cap = MEM_FLAG_HBM2;
3598 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
3599
3600 mci->edac_cap = EDAC_FLAG_EC;
3601 mci->mod_name = EDAC_MOD_STR;
3602 mci->ctl_name = pvt->ctl_name;
3603 mci->dev_name = pci_name(pvt->F3);
3604 mci->ctl_page_to_phys = NULL;
3605
3606 gpu_init_csrows(mci);
3607}
3608
3609/* ECC is enabled by default on GPU nodes */
3610static bool gpu_ecc_enabled(struct amd64_pvt *pvt)
3611{
3612 return true;
3613}
3614
3615static inline u32 gpu_get_umc_base(struct amd64_pvt *pvt, u8 umc, u8 channel)
3616{
3617 /*
3618 * On CPUs, there is one channel per UMC, so UMC numbering equals
3619 * channel numbering. On GPUs, there are eight channels per UMC,
3620 * so the channel numbering is different from UMC numbering.
3621 *
3622 * On CPU nodes channels are selected in 6th nibble
3623 * UMC chY[3:0]= [(chY*2 + 1) : (chY*2)]50000;
3624 *
3625 * On GPU nodes channels are selected in 3rd nibble
3626 * HBM chX[3:0]= [Y ]5X[3:0]000;
3627 * HBM chX[7:4]= [Y+1]5X[3:0]000
3628 *
3629 * On MI300 APU nodes, same as GPU nodes but channels are selected
3630 * in the base address of 0x90000
3631 */
3632 umc *= 2;
3633
3634 if (channel >= 4)
3635 umc++;
3636
3637 return pvt->gpu_umc_base + (umc << 20) + ((channel % 4) << 12);
3638}
3639
3640static void gpu_read_mc_regs(struct amd64_pvt *pvt)
3641{
3642 u8 nid = pvt->mc_node_id;
3643 struct amd64_umc *umc;
3644 u32 i, tmp, umc_base;
3645
3646 /* Read registers from each UMC */
3647 for_each_umc(i) {
3648 umc_base = gpu_get_umc_base(pvt, i, 0);
3649 umc = &pvt->umc[i];
3650
3651 if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &tmp))
3652 umc->umc_cfg = tmp;
3653
3654 if (!amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &tmp))
3655 umc->sdp_ctrl = tmp;
3656
3657 if (!amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &tmp))
3658 umc->ecc_ctrl = tmp;
3659 }
3660}
3661
3662static void gpu_read_base_mask(struct amd64_pvt *pvt)
3663{
3664 u32 base_reg, mask_reg;
3665 u32 *base, *mask;
3666 int umc, cs;
3667
3668 for_each_umc(umc) {
3669 for_each_chip_select(cs, umc, pvt) {
3670 base_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_BASE_ADDR;
3671 base = &pvt->csels[umc].csbases[cs];
3672
3673 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) {
3674 edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n",
3675 umc, cs, *base, base_reg);
3676 }
3677
3678 mask_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_ADDR_MASK;
3679 mask = &pvt->csels[umc].csmasks[cs];
3680
3681 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) {
3682 edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n",
3683 umc, cs, *mask, mask_reg);
3684 }
3685 }
3686 }
3687}
3688
3689static void gpu_prep_chip_selects(struct amd64_pvt *pvt)
3690{
3691 int umc;
3692
3693 for_each_umc(umc) {
3694 pvt->csels[umc].b_cnt = 8;
3695 pvt->csels[umc].m_cnt = 8;
3696 }
3697}
3698
3699static int gpu_hw_info_get(struct amd64_pvt *pvt)
3700{
3701 int ret;
3702
3703 ret = gpu_get_node_map(pvt);
3704 if (ret)
3705 return ret;
3706
3707 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);
3708 if (!pvt->umc)
3709 return -ENOMEM;
3710
3711 gpu_prep_chip_selects(pvt);
3712 gpu_read_base_mask(pvt);
3713 gpu_read_mc_regs(pvt);
3714
3715 return 0;
3716}
3717
3718static void hw_info_put(struct amd64_pvt *pvt)
3719{
3720 pci_dev_put(pvt->F1);
3721 pci_dev_put(pvt->F2);
3722 kfree(pvt->umc);
3723}
3724
3725static struct low_ops umc_ops = {
3726 .hw_info_get = umc_hw_info_get,
3727 .ecc_enabled = umc_ecc_enabled,
3728 .setup_mci_misc_attrs = umc_setup_mci_misc_attrs,
3729 .dump_misc_regs = umc_dump_misc_regs,
3730 .get_err_info = umc_get_err_info,
3731};
3732
3733static struct low_ops gpu_ops = {
3734 .hw_info_get = gpu_hw_info_get,
3735 .ecc_enabled = gpu_ecc_enabled,
3736 .setup_mci_misc_attrs = gpu_setup_mci_misc_attrs,
3737 .dump_misc_regs = gpu_dump_misc_regs,
3738 .get_err_info = gpu_get_err_info,
3739};
3740
3741/* Use Family 16h versions for defaults and adjust as needed below. */
3742static struct low_ops dct_ops = {
3743 .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
3744 .dbam_to_cs = f16_dbam_to_chip_select,
3745 .hw_info_get = dct_hw_info_get,
3746 .ecc_enabled = dct_ecc_enabled,
3747 .setup_mci_misc_attrs = dct_setup_mci_misc_attrs,
3748 .dump_misc_regs = dct_dump_misc_regs,
3749};
3750
3751static int per_family_init(struct amd64_pvt *pvt)
3752{
3753 pvt->ext_model = boot_cpu_data.x86_model >> 4;
3754 pvt->stepping = boot_cpu_data.x86_stepping;
3755 pvt->model = boot_cpu_data.x86_model;
3756 pvt->fam = boot_cpu_data.x86;
3757 pvt->max_mcs = 2;
3758
3759 /*
3760 * Decide on which ops group to use here and do any family/model
3761 * overrides below.
3762 */
3763 if (pvt->fam >= 0x17)
3764 pvt->ops = &umc_ops;
3765 else
3766 pvt->ops = &dct_ops;
3767
3768 switch (pvt->fam) {
3769 case 0xf:
3770 pvt->ctl_name = (pvt->ext_model >= K8_REV_F) ?
3771 "K8 revF or later" : "K8 revE or earlier";
3772 pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP;
3773 pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL;
3774 pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow;
3775 pvt->ops->dbam_to_cs = k8_dbam_to_chip_select;
3776 break;
3777
3778 case 0x10:
3779 pvt->ctl_name = "F10h";
3780 pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP;
3781 pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM;
3782 pvt->ops->dbam_to_cs = f10_dbam_to_chip_select;
3783 break;
3784
3785 case 0x15:
3786 switch (pvt->model) {
3787 case 0x30:
3788 pvt->ctl_name = "F15h_M30h";
3789 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1;
3790 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2;
3791 break;
3792 case 0x60:
3793 pvt->ctl_name = "F15h_M60h";
3794 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1;
3795 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2;
3796 pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select;
3797 break;
3798 case 0x13:
3799 /* Richland is only client */
3800 return -ENODEV;
3801 default:
3802 pvt->ctl_name = "F15h";
3803 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1;
3804 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2;
3805 pvt->ops->dbam_to_cs = f15_dbam_to_chip_select;
3806 break;
3807 }
3808 break;
3809
3810 case 0x16:
3811 switch (pvt->model) {
3812 case 0x30:
3813 pvt->ctl_name = "F16h_M30h";
3814 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1;
3815 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2;
3816 break;
3817 default:
3818 pvt->ctl_name = "F16h";
3819 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1;
3820 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2;
3821 break;
3822 }
3823 break;
3824
3825 case 0x17:
3826 switch (pvt->model) {
3827 case 0x10 ... 0x2f:
3828 pvt->ctl_name = "F17h_M10h";
3829 break;
3830 case 0x30 ... 0x3f:
3831 pvt->ctl_name = "F17h_M30h";
3832 pvt->max_mcs = 8;
3833 break;
3834 case 0x60 ... 0x6f:
3835 pvt->ctl_name = "F17h_M60h";
3836 break;
3837 case 0x70 ... 0x7f:
3838 pvt->ctl_name = "F17h_M70h";
3839 break;
3840 default:
3841 pvt->ctl_name = "F17h";
3842 break;
3843 }
3844 break;
3845
3846 case 0x18:
3847 pvt->ctl_name = "F18h";
3848 break;
3849
3850 case 0x19:
3851 switch (pvt->model) {
3852 case 0x00 ... 0x0f:
3853 pvt->ctl_name = "F19h";
3854 pvt->max_mcs = 8;
3855 break;
3856 case 0x10 ... 0x1f:
3857 pvt->ctl_name = "F19h_M10h";
3858 pvt->max_mcs = 12;
3859 pvt->flags.zn_regs_v2 = 1;
3860 break;
3861 case 0x20 ... 0x2f:
3862 pvt->ctl_name = "F19h_M20h";
3863 break;
3864 case 0x30 ... 0x3f:
3865 if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) {
3866 pvt->ctl_name = "MI200";
3867 pvt->max_mcs = 4;
3868 pvt->dram_type = MEM_HBM2;
3869 pvt->gpu_umc_base = 0x50000;
3870 pvt->ops = &gpu_ops;
3871 } else {
3872 pvt->ctl_name = "F19h_M30h";
3873 pvt->max_mcs = 8;
3874 }
3875 break;
3876 case 0x50 ... 0x5f:
3877 pvt->ctl_name = "F19h_M50h";
3878 break;
3879 case 0x60 ... 0x6f:
3880 pvt->ctl_name = "F19h_M60h";
3881 pvt->flags.zn_regs_v2 = 1;
3882 break;
3883 case 0x70 ... 0x7f:
3884 pvt->ctl_name = "F19h_M70h";
3885 pvt->flags.zn_regs_v2 = 1;
3886 break;
3887 case 0x90 ... 0x9f:
3888 pvt->ctl_name = "F19h_M90h";
3889 pvt->max_mcs = 4;
3890 pvt->dram_type = MEM_HBM3;
3891 pvt->gpu_umc_base = 0x90000;
3892 pvt->ops = &gpu_ops;
3893 break;
3894 case 0xa0 ... 0xaf:
3895 pvt->ctl_name = "F19h_MA0h";
3896 pvt->max_mcs = 12;
3897 pvt->flags.zn_regs_v2 = 1;
3898 break;
3899 }
3900 break;
3901
3902 case 0x1A:
3903 switch (pvt->model) {
3904 case 0x00 ... 0x1f:
3905 pvt->ctl_name = "F1Ah";
3906 pvt->max_mcs = 12;
3907 pvt->flags.zn_regs_v2 = 1;
3908 break;
3909 case 0x40 ... 0x4f:
3910 pvt->ctl_name = "F1Ah_M40h";
3911 pvt->flags.zn_regs_v2 = 1;
3912 break;
3913 }
3914 break;
3915
3916 default:
3917 amd64_err("Unsupported family!\n");
3918 return -ENODEV;
3919 }
3920
3921 return 0;
3922}
3923
3924static const struct attribute_group *amd64_edac_attr_groups[] = {
3925#ifdef CONFIG_EDAC_DEBUG
3926 &dbg_group,
3927 &inj_group,
3928#endif
3929 NULL
3930};
3931
3932/*
3933 * For heterogeneous and APU models EDAC CHIP_SELECT and CHANNEL layers
3934 * should be swapped to fit into the layers.
3935 */
3936static unsigned int get_layer_size(struct amd64_pvt *pvt, u8 layer)
3937{
3938 bool is_gpu = (pvt->ops == &gpu_ops);
3939
3940 if (!layer)
3941 return is_gpu ? pvt->max_mcs
3942 : pvt->csels[0].b_cnt;
3943 else
3944 return is_gpu ? pvt->csels[0].b_cnt
3945 : pvt->max_mcs;
3946}
3947
3948static int init_one_instance(struct amd64_pvt *pvt)
3949{
3950 struct mem_ctl_info *mci = NULL;
3951 struct edac_mc_layer layers[2];
3952 int ret = -ENOMEM;
3953
3954 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
3955 layers[0].size = get_layer_size(pvt, 0);
3956 layers[0].is_virt_csrow = true;
3957 layers[1].type = EDAC_MC_LAYER_CHANNEL;
3958 layers[1].size = get_layer_size(pvt, 1);
3959 layers[1].is_virt_csrow = false;
3960
3961 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0);
3962 if (!mci)
3963 return ret;
3964
3965 mci->pvt_info = pvt;
3966 mci->pdev = &pvt->F3->dev;
3967
3968 pvt->ops->setup_mci_misc_attrs(mci);
3969
3970 ret = -ENODEV;
3971 if (edac_mc_add_mc_with_groups(mci, amd64_edac_attr_groups)) {
3972 edac_dbg(1, "failed edac_mc_add_mc()\n");
3973 edac_mc_free(mci);
3974 return ret;
3975 }
3976
3977 return 0;
3978}
3979
3980static bool instance_has_memory(struct amd64_pvt *pvt)
3981{
3982 bool cs_enabled = false;
3983 int cs = 0, dct = 0;
3984
3985 for (dct = 0; dct < pvt->max_mcs; dct++) {
3986 for_each_chip_select(cs, dct, pvt)
3987 cs_enabled |= csrow_enabled(cs, dct, pvt);
3988 }
3989
3990 return cs_enabled;
3991}
3992
3993static int probe_one_instance(unsigned int nid)
3994{
3995 struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
3996 struct amd64_pvt *pvt = NULL;
3997 struct ecc_settings *s;
3998 int ret;
3999
4000 ret = -ENOMEM;
4001 s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
4002 if (!s)
4003 goto err_out;
4004
4005 ecc_stngs[nid] = s;
4006
4007 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
4008 if (!pvt)
4009 goto err_settings;
4010
4011 pvt->mc_node_id = nid;
4012 pvt->F3 = F3;
4013
4014 ret = per_family_init(pvt);
4015 if (ret < 0)
4016 goto err_enable;
4017
4018 ret = pvt->ops->hw_info_get(pvt);
4019 if (ret < 0)
4020 goto err_enable;
4021
4022 ret = 0;
4023 if (!instance_has_memory(pvt)) {
4024 amd64_info("Node %d: No DIMMs detected.\n", nid);
4025 goto err_enable;
4026 }
4027
4028 if (!pvt->ops->ecc_enabled(pvt)) {
4029 ret = -ENODEV;
4030
4031 if (!ecc_enable_override)
4032 goto err_enable;
4033
4034 if (boot_cpu_data.x86 >= 0x17) {
4035 amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS.");
4036 goto err_enable;
4037 } else
4038 amd64_warn("Forcing ECC on!\n");
4039
4040 if (!enable_ecc_error_reporting(s, nid, F3))
4041 goto err_enable;
4042 }
4043
4044 ret = init_one_instance(pvt);
4045 if (ret < 0) {
4046 amd64_err("Error probing instance: %d\n", nid);
4047
4048 if (boot_cpu_data.x86 < 0x17)
4049 restore_ecc_error_reporting(s, nid, F3);
4050
4051 goto err_enable;
4052 }
4053
4054 amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id);
4055
4056 /* Display and decode various registers for debug purposes. */
4057 pvt->ops->dump_misc_regs(pvt);
4058
4059 return ret;
4060
4061err_enable:
4062 hw_info_put(pvt);
4063 kfree(pvt);
4064
4065err_settings:
4066 kfree(s);
4067 ecc_stngs[nid] = NULL;
4068
4069err_out:
4070 return ret;
4071}
4072
4073static void remove_one_instance(unsigned int nid)
4074{
4075 struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
4076 struct ecc_settings *s = ecc_stngs[nid];
4077 struct mem_ctl_info *mci;
4078 struct amd64_pvt *pvt;
4079
4080 /* Remove from EDAC CORE tracking list */
4081 mci = edac_mc_del_mc(&F3->dev);
4082 if (!mci)
4083 return;
4084
4085 pvt = mci->pvt_info;
4086
4087 restore_ecc_error_reporting(s, nid, F3);
4088
4089 kfree(ecc_stngs[nid]);
4090 ecc_stngs[nid] = NULL;
4091
4092 /* Free the EDAC CORE resources */
4093 mci->pvt_info = NULL;
4094
4095 hw_info_put(pvt);
4096 kfree(pvt);
4097 edac_mc_free(mci);
4098}
4099
4100static void setup_pci_device(void)
4101{
4102 if (pci_ctl)
4103 return;
4104
4105 pci_ctl = edac_pci_create_generic_ctl(pci_ctl_dev, EDAC_MOD_STR);
4106 if (!pci_ctl) {
4107 pr_warn("%s(): Unable to create PCI control\n", __func__);
4108 pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
4109 }
4110}
4111
4112static const struct x86_cpu_id amd64_cpuids[] = {
4113 X86_MATCH_VENDOR_FAM(AMD, 0x0F, NULL),
4114 X86_MATCH_VENDOR_FAM(AMD, 0x10, NULL),
4115 X86_MATCH_VENDOR_FAM(AMD, 0x15, NULL),
4116 X86_MATCH_VENDOR_FAM(AMD, 0x16, NULL),
4117 X86_MATCH_VENDOR_FAM(AMD, 0x17, NULL),
4118 X86_MATCH_VENDOR_FAM(HYGON, 0x18, NULL),
4119 X86_MATCH_VENDOR_FAM(AMD, 0x19, NULL),
4120 X86_MATCH_VENDOR_FAM(AMD, 0x1A, NULL),
4121 { }
4122};
4123MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);
4124
4125static int __init amd64_edac_init(void)
4126{
4127 const char *owner;
4128 int err = -ENODEV;
4129 int i;
4130
4131 if (ghes_get_devices())
4132 return -EBUSY;
4133
4134 owner = edac_get_owner();
4135 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
4136 return -EBUSY;
4137
4138 if (!x86_match_cpu(amd64_cpuids))
4139 return -ENODEV;
4140
4141 if (!amd_nb_num())
4142 return -ENODEV;
4143
4144 opstate_init();
4145
4146 err = -ENOMEM;
4147 ecc_stngs = kcalloc(amd_nb_num(), sizeof(ecc_stngs[0]), GFP_KERNEL);
4148 if (!ecc_stngs)
4149 goto err_free;
4150
4151 msrs = msrs_alloc();
4152 if (!msrs)
4153 goto err_free;
4154
4155 for (i = 0; i < amd_nb_num(); i++) {
4156 err = probe_one_instance(i);
4157 if (err) {
4158 /* unwind properly */
4159 while (--i >= 0)
4160 remove_one_instance(i);
4161
4162 goto err_pci;
4163 }
4164 }
4165
4166 if (!edac_has_mcs()) {
4167 err = -ENODEV;
4168 goto err_pci;
4169 }
4170
4171 /* register stuff with EDAC MCE */
4172 if (boot_cpu_data.x86 >= 0x17) {
4173 amd_register_ecc_decoder(decode_umc_error);
4174 } else {
4175 amd_register_ecc_decoder(decode_bus_error);
4176 setup_pci_device();
4177 }
4178
4179#ifdef CONFIG_X86_32
4180 amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR);
4181#endif
4182
4183 return 0;
4184
4185err_pci:
4186 pci_ctl_dev = NULL;
4187
4188 msrs_free(msrs);
4189 msrs = NULL;
4190
4191err_free:
4192 kfree(ecc_stngs);
4193 ecc_stngs = NULL;
4194
4195 return err;
4196}
4197
4198static void __exit amd64_edac_exit(void)
4199{
4200 int i;
4201
4202 if (pci_ctl)
4203 edac_pci_release_generic_ctl(pci_ctl);
4204
4205 /* unregister from EDAC MCE */
4206 if (boot_cpu_data.x86 >= 0x17)
4207 amd_unregister_ecc_decoder(decode_umc_error);
4208 else
4209 amd_unregister_ecc_decoder(decode_bus_error);
4210
4211 for (i = 0; i < amd_nb_num(); i++)
4212 remove_one_instance(i);
4213
4214 kfree(ecc_stngs);
4215 ecc_stngs = NULL;
4216
4217 pci_ctl_dev = NULL;
4218
4219 msrs_free(msrs);
4220 msrs = NULL;
4221}
4222
4223module_init(amd64_edac_init);
4224module_exit(amd64_edac_exit);
4225
4226MODULE_LICENSE("GPL");
4227MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, Dave Peterson, Thayne Harbaugh; AMD");
4228MODULE_DESCRIPTION("MC support for AMD64 memory controllers");
4229
4230module_param(edac_op_state, int, 0444);
4231MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1// SPDX-License-Identifier: GPL-2.0-only
2#include "amd64_edac.h"
3#include <asm/amd_nb.h>
4
5static struct edac_pci_ctl_info *pci_ctl;
6
7/*
8 * Set by command line parameter. If BIOS has enabled the ECC, this override is
9 * cleared to prevent re-enabling the hardware by this driver.
10 */
11static int ecc_enable_override;
12module_param(ecc_enable_override, int, 0644);
13
14static struct msr __percpu *msrs;
15
16static inline u32 get_umc_reg(struct amd64_pvt *pvt, u32 reg)
17{
18 if (!pvt->flags.zn_regs_v2)
19 return reg;
20
21 switch (reg) {
22 case UMCCH_ADDR_CFG: return UMCCH_ADDR_CFG_DDR5;
23 case UMCCH_ADDR_MASK_SEC: return UMCCH_ADDR_MASK_SEC_DDR5;
24 case UMCCH_DIMM_CFG: return UMCCH_DIMM_CFG_DDR5;
25 }
26
27 WARN_ONCE(1, "%s: unknown register 0x%x", __func__, reg);
28 return 0;
29}
30
31/* Per-node stuff */
32static struct ecc_settings **ecc_stngs;
33
34/* Device for the PCI component */
35static struct device *pci_ctl_dev;
36
37/*
38 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
39 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
40 * or higher value'.
41 *
42 *FIXME: Produce a better mapping/linearisation.
43 */
44static const struct scrubrate {
45 u32 scrubval; /* bit pattern for scrub rate */
46 u32 bandwidth; /* bandwidth consumed (bytes/sec) */
47} scrubrates[] = {
48 { 0x01, 1600000000UL},
49 { 0x02, 800000000UL},
50 { 0x03, 400000000UL},
51 { 0x04, 200000000UL},
52 { 0x05, 100000000UL},
53 { 0x06, 50000000UL},
54 { 0x07, 25000000UL},
55 { 0x08, 12284069UL},
56 { 0x09, 6274509UL},
57 { 0x0A, 3121951UL},
58 { 0x0B, 1560975UL},
59 { 0x0C, 781440UL},
60 { 0x0D, 390720UL},
61 { 0x0E, 195300UL},
62 { 0x0F, 97650UL},
63 { 0x10, 48854UL},
64 { 0x11, 24427UL},
65 { 0x12, 12213UL},
66 { 0x13, 6101UL},
67 { 0x14, 3051UL},
68 { 0x15, 1523UL},
69 { 0x16, 761UL},
70 { 0x00, 0UL}, /* scrubbing off */
71};
72
73int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
74 u32 *val, const char *func)
75{
76 int err = 0;
77
78 err = pci_read_config_dword(pdev, offset, val);
79 if (err)
80 amd64_warn("%s: error reading F%dx%03x.\n",
81 func, PCI_FUNC(pdev->devfn), offset);
82
83 return err;
84}
85
86int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
87 u32 val, const char *func)
88{
89 int err = 0;
90
91 err = pci_write_config_dword(pdev, offset, val);
92 if (err)
93 amd64_warn("%s: error writing to F%dx%03x.\n",
94 func, PCI_FUNC(pdev->devfn), offset);
95
96 return err;
97}
98
99/*
100 * Select DCT to which PCI cfg accesses are routed
101 */
102static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
103{
104 u32 reg = 0;
105
106 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
107 reg &= (pvt->model == 0x30) ? ~3 : ~1;
108 reg |= dct;
109 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
110}
111
112/*
113 *
114 * Depending on the family, F2 DCT reads need special handling:
115 *
116 * K8: has a single DCT only and no address offsets >= 0x100
117 *
118 * F10h: each DCT has its own set of regs
119 * DCT0 -> F2x040..
120 * DCT1 -> F2x140..
121 *
122 * F16h: has only 1 DCT
123 *
124 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
125 */
126static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
127 int offset, u32 *val)
128{
129 switch (pvt->fam) {
130 case 0xf:
131 if (dct || offset >= 0x100)
132 return -EINVAL;
133 break;
134
135 case 0x10:
136 if (dct) {
137 /*
138 * Note: If ganging is enabled, barring the regs
139 * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx
140 * return 0. (cf. Section 2.8.1 F10h BKDG)
141 */
142 if (dct_ganging_enabled(pvt))
143 return 0;
144
145 offset += 0x100;
146 }
147 break;
148
149 case 0x15:
150 /*
151 * F15h: F2x1xx addresses do not map explicitly to DCT1.
152 * We should select which DCT we access using F1x10C[DctCfgSel]
153 */
154 dct = (dct && pvt->model == 0x30) ? 3 : dct;
155 f15h_select_dct(pvt, dct);
156 break;
157
158 case 0x16:
159 if (dct)
160 return -EINVAL;
161 break;
162
163 default:
164 break;
165 }
166 return amd64_read_pci_cfg(pvt->F2, offset, val);
167}
168
169/*
170 * Memory scrubber control interface. For K8, memory scrubbing is handled by
171 * hardware and can involve L2 cache, dcache as well as the main memory. With
172 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
173 * functionality.
174 *
175 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
176 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
177 * bytes/sec for the setting.
178 *
179 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
180 * other archs, we might not have access to the caches directly.
181 */
182
183/*
184 * Scan the scrub rate mapping table for a close or matching bandwidth value to
185 * issue. If requested is too big, then use last maximum value found.
186 */
187static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
188{
189 u32 scrubval;
190 int i;
191
192 /*
193 * map the configured rate (new_bw) to a value specific to the AMD64
194 * memory controller and apply to register. Search for the first
195 * bandwidth entry that is greater or equal than the setting requested
196 * and program that. If at last entry, turn off DRAM scrubbing.
197 *
198 * If no suitable bandwidth is found, turn off DRAM scrubbing entirely
199 * by falling back to the last element in scrubrates[].
200 */
201 for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) {
202 /*
203 * skip scrub rates which aren't recommended
204 * (see F10 BKDG, F3x58)
205 */
206 if (scrubrates[i].scrubval < min_rate)
207 continue;
208
209 if (scrubrates[i].bandwidth <= new_bw)
210 break;
211 }
212
213 scrubval = scrubrates[i].scrubval;
214
215 if (pvt->fam == 0x15 && pvt->model == 0x60) {
216 f15h_select_dct(pvt, 0);
217 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
218 f15h_select_dct(pvt, 1);
219 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
220 } else {
221 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
222 }
223
224 if (scrubval)
225 return scrubrates[i].bandwidth;
226
227 return 0;
228}
229
230static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
231{
232 struct amd64_pvt *pvt = mci->pvt_info;
233 u32 min_scrubrate = 0x5;
234
235 if (pvt->fam == 0xf)
236 min_scrubrate = 0x0;
237
238 if (pvt->fam == 0x15) {
239 /* Erratum #505 */
240 if (pvt->model < 0x10)
241 f15h_select_dct(pvt, 0);
242
243 if (pvt->model == 0x60)
244 min_scrubrate = 0x6;
245 }
246 return __set_scrub_rate(pvt, bw, min_scrubrate);
247}
248
249static int get_scrub_rate(struct mem_ctl_info *mci)
250{
251 struct amd64_pvt *pvt = mci->pvt_info;
252 int i, retval = -EINVAL;
253 u32 scrubval = 0;
254
255 if (pvt->fam == 0x15) {
256 /* Erratum #505 */
257 if (pvt->model < 0x10)
258 f15h_select_dct(pvt, 0);
259
260 if (pvt->model == 0x60)
261 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
262 else
263 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
264 } else {
265 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
266 }
267
268 scrubval = scrubval & 0x001F;
269
270 for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
271 if (scrubrates[i].scrubval == scrubval) {
272 retval = scrubrates[i].bandwidth;
273 break;
274 }
275 }
276 return retval;
277}
278
279/*
280 * returns true if the SysAddr given by sys_addr matches the
281 * DRAM base/limit associated with node_id
282 */
283static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
284{
285 u64 addr;
286
287 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
288 * all ones if the most significant implemented address bit is 1.
289 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
290 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
291 * Application Programming.
292 */
293 addr = sys_addr & 0x000000ffffffffffull;
294
295 return ((addr >= get_dram_base(pvt, nid)) &&
296 (addr <= get_dram_limit(pvt, nid)));
297}
298
299/*
300 * Attempt to map a SysAddr to a node. On success, return a pointer to the
301 * mem_ctl_info structure for the node that the SysAddr maps to.
302 *
303 * On failure, return NULL.
304 */
305static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
306 u64 sys_addr)
307{
308 struct amd64_pvt *pvt;
309 u8 node_id;
310 u32 intlv_en, bits;
311
312 /*
313 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
314 * 3.4.4.2) registers to map the SysAddr to a node ID.
315 */
316 pvt = mci->pvt_info;
317
318 /*
319 * The value of this field should be the same for all DRAM Base
320 * registers. Therefore we arbitrarily choose to read it from the
321 * register for node 0.
322 */
323 intlv_en = dram_intlv_en(pvt, 0);
324
325 if (intlv_en == 0) {
326 for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
327 if (base_limit_match(pvt, sys_addr, node_id))
328 goto found;
329 }
330 goto err_no_match;
331 }
332
333 if (unlikely((intlv_en != 0x01) &&
334 (intlv_en != 0x03) &&
335 (intlv_en != 0x07))) {
336 amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
337 return NULL;
338 }
339
340 bits = (((u32) sys_addr) >> 12) & intlv_en;
341
342 for (node_id = 0; ; ) {
343 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
344 break; /* intlv_sel field matches */
345
346 if (++node_id >= DRAM_RANGES)
347 goto err_no_match;
348 }
349
350 /* sanity test for sys_addr */
351 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
352 amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
353 "range for node %d with node interleaving enabled.\n",
354 __func__, sys_addr, node_id);
355 return NULL;
356 }
357
358found:
359 return edac_mc_find((int)node_id);
360
361err_no_match:
362 edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
363 (unsigned long)sys_addr);
364
365 return NULL;
366}
367
368/*
369 * compute the CS base address of the @csrow on the DRAM controller @dct.
370 * For details see F2x[5C:40] in the processor's BKDG
371 */
372static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
373 u64 *base, u64 *mask)
374{
375 u64 csbase, csmask, base_bits, mask_bits;
376 u8 addr_shift;
377
378 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
379 csbase = pvt->csels[dct].csbases[csrow];
380 csmask = pvt->csels[dct].csmasks[csrow];
381 base_bits = GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);
382 mask_bits = GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);
383 addr_shift = 4;
384
385 /*
386 * F16h and F15h, models 30h and later need two addr_shift values:
387 * 8 for high and 6 for low (cf. F16h BKDG).
388 */
389 } else if (pvt->fam == 0x16 ||
390 (pvt->fam == 0x15 && pvt->model >= 0x30)) {
391 csbase = pvt->csels[dct].csbases[csrow];
392 csmask = pvt->csels[dct].csmasks[csrow >> 1];
393
394 *base = (csbase & GENMASK_ULL(15, 5)) << 6;
395 *base |= (csbase & GENMASK_ULL(30, 19)) << 8;
396
397 *mask = ~0ULL;
398 /* poke holes for the csmask */
399 *mask &= ~((GENMASK_ULL(15, 5) << 6) |
400 (GENMASK_ULL(30, 19) << 8));
401
402 *mask |= (csmask & GENMASK_ULL(15, 5)) << 6;
403 *mask |= (csmask & GENMASK_ULL(30, 19)) << 8;
404
405 return;
406 } else {
407 csbase = pvt->csels[dct].csbases[csrow];
408 csmask = pvt->csels[dct].csmasks[csrow >> 1];
409 addr_shift = 8;
410
411 if (pvt->fam == 0x15)
412 base_bits = mask_bits =
413 GENMASK_ULL(30,19) | GENMASK_ULL(13,5);
414 else
415 base_bits = mask_bits =
416 GENMASK_ULL(28,19) | GENMASK_ULL(13,5);
417 }
418
419 *base = (csbase & base_bits) << addr_shift;
420
421 *mask = ~0ULL;
422 /* poke holes for the csmask */
423 *mask &= ~(mask_bits << addr_shift);
424 /* OR them in */
425 *mask |= (csmask & mask_bits) << addr_shift;
426}
427
428#define for_each_chip_select(i, dct, pvt) \
429 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
430
431#define chip_select_base(i, dct, pvt) \
432 pvt->csels[dct].csbases[i]
433
434#define for_each_chip_select_mask(i, dct, pvt) \
435 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
436
437#define for_each_umc(i) \
438 for (i = 0; i < pvt->max_mcs; i++)
439
440/*
441 * @input_addr is an InputAddr associated with the node given by mci. Return the
442 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
443 */
444static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
445{
446 struct amd64_pvt *pvt;
447 int csrow;
448 u64 base, mask;
449
450 pvt = mci->pvt_info;
451
452 for_each_chip_select(csrow, 0, pvt) {
453 if (!csrow_enabled(csrow, 0, pvt))
454 continue;
455
456 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);
457
458 mask = ~mask;
459
460 if ((input_addr & mask) == (base & mask)) {
461 edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
462 (unsigned long)input_addr, csrow,
463 pvt->mc_node_id);
464
465 return csrow;
466 }
467 }
468 edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
469 (unsigned long)input_addr, pvt->mc_node_id);
470
471 return -1;
472}
473
474/*
475 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
476 * for the node represented by mci. Info is passed back in *hole_base,
477 * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
478 * info is invalid. Info may be invalid for either of the following reasons:
479 *
480 * - The revision of the node is not E or greater. In this case, the DRAM Hole
481 * Address Register does not exist.
482 *
483 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
484 * indicating that its contents are not valid.
485 *
486 * The values passed back in *hole_base, *hole_offset, and *hole_size are
487 * complete 32-bit values despite the fact that the bitfields in the DHAR
488 * only represent bits 31-24 of the base and offset values.
489 */
490static int get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
491 u64 *hole_offset, u64 *hole_size)
492{
493 struct amd64_pvt *pvt = mci->pvt_info;
494
495 /* only revE and later have the DRAM Hole Address Register */
496 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {
497 edac_dbg(1, " revision %d for node %d does not support DHAR\n",
498 pvt->ext_model, pvt->mc_node_id);
499 return 1;
500 }
501
502 /* valid for Fam10h and above */
503 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
504 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n");
505 return 1;
506 }
507
508 if (!dhar_valid(pvt)) {
509 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n",
510 pvt->mc_node_id);
511 return 1;
512 }
513
514 /* This node has Memory Hoisting */
515
516 /* +------------------+--------------------+--------------------+-----
517 * | memory | DRAM hole | relocated |
518 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
519 * | | | DRAM hole |
520 * | | | [0x100000000, |
521 * | | | (0x100000000+ |
522 * | | | (0xffffffff-x))] |
523 * +------------------+--------------------+--------------------+-----
524 *
525 * Above is a diagram of physical memory showing the DRAM hole and the
526 * relocated addresses from the DRAM hole. As shown, the DRAM hole
527 * starts at address x (the base address) and extends through address
528 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
529 * addresses in the hole so that they start at 0x100000000.
530 */
531
532 *hole_base = dhar_base(pvt);
533 *hole_size = (1ULL << 32) - *hole_base;
534
535 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)
536 : k8_dhar_offset(pvt);
537
538 edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
539 pvt->mc_node_id, (unsigned long)*hole_base,
540 (unsigned long)*hole_offset, (unsigned long)*hole_size);
541
542 return 0;
543}
544
545#ifdef CONFIG_EDAC_DEBUG
546#define EDAC_DCT_ATTR_SHOW(reg) \
547static ssize_t reg##_show(struct device *dev, \
548 struct device_attribute *mattr, char *data) \
549{ \
550 struct mem_ctl_info *mci = to_mci(dev); \
551 struct amd64_pvt *pvt = mci->pvt_info; \
552 \
553 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
554}
555
556EDAC_DCT_ATTR_SHOW(dhar);
557EDAC_DCT_ATTR_SHOW(dbam0);
558EDAC_DCT_ATTR_SHOW(top_mem);
559EDAC_DCT_ATTR_SHOW(top_mem2);
560
561static ssize_t dram_hole_show(struct device *dev, struct device_attribute *mattr,
562 char *data)
563{
564 struct mem_ctl_info *mci = to_mci(dev);
565
566 u64 hole_base = 0;
567 u64 hole_offset = 0;
568 u64 hole_size = 0;
569
570 get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
571
572 return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
573 hole_size);
574}
575
576/*
577 * update NUM_DBG_ATTRS in case you add new members
578 */
579static DEVICE_ATTR(dhar, S_IRUGO, dhar_show, NULL);
580static DEVICE_ATTR(dbam, S_IRUGO, dbam0_show, NULL);
581static DEVICE_ATTR(topmem, S_IRUGO, top_mem_show, NULL);
582static DEVICE_ATTR(topmem2, S_IRUGO, top_mem2_show, NULL);
583static DEVICE_ATTR_RO(dram_hole);
584
585static struct attribute *dbg_attrs[] = {
586 &dev_attr_dhar.attr,
587 &dev_attr_dbam.attr,
588 &dev_attr_topmem.attr,
589 &dev_attr_topmem2.attr,
590 &dev_attr_dram_hole.attr,
591 NULL
592};
593
594static const struct attribute_group dbg_group = {
595 .attrs = dbg_attrs,
596};
597
598static ssize_t inject_section_show(struct device *dev,
599 struct device_attribute *mattr, char *buf)
600{
601 struct mem_ctl_info *mci = to_mci(dev);
602 struct amd64_pvt *pvt = mci->pvt_info;
603 return sprintf(buf, "0x%x\n", pvt->injection.section);
604}
605
606/*
607 * store error injection section value which refers to one of 4 16-byte sections
608 * within a 64-byte cacheline
609 *
610 * range: 0..3
611 */
612static ssize_t inject_section_store(struct device *dev,
613 struct device_attribute *mattr,
614 const char *data, size_t count)
615{
616 struct mem_ctl_info *mci = to_mci(dev);
617 struct amd64_pvt *pvt = mci->pvt_info;
618 unsigned long value;
619 int ret;
620
621 ret = kstrtoul(data, 10, &value);
622 if (ret < 0)
623 return ret;
624
625 if (value > 3) {
626 amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
627 return -EINVAL;
628 }
629
630 pvt->injection.section = (u32) value;
631 return count;
632}
633
634static ssize_t inject_word_show(struct device *dev,
635 struct device_attribute *mattr, char *buf)
636{
637 struct mem_ctl_info *mci = to_mci(dev);
638 struct amd64_pvt *pvt = mci->pvt_info;
639 return sprintf(buf, "0x%x\n", pvt->injection.word);
640}
641
642/*
643 * store error injection word value which refers to one of 9 16-bit word of the
644 * 16-byte (128-bit + ECC bits) section
645 *
646 * range: 0..8
647 */
648static ssize_t inject_word_store(struct device *dev,
649 struct device_attribute *mattr,
650 const char *data, size_t count)
651{
652 struct mem_ctl_info *mci = to_mci(dev);
653 struct amd64_pvt *pvt = mci->pvt_info;
654 unsigned long value;
655 int ret;
656
657 ret = kstrtoul(data, 10, &value);
658 if (ret < 0)
659 return ret;
660
661 if (value > 8) {
662 amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
663 return -EINVAL;
664 }
665
666 pvt->injection.word = (u32) value;
667 return count;
668}
669
670static ssize_t inject_ecc_vector_show(struct device *dev,
671 struct device_attribute *mattr,
672 char *buf)
673{
674 struct mem_ctl_info *mci = to_mci(dev);
675 struct amd64_pvt *pvt = mci->pvt_info;
676 return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
677}
678
679/*
680 * store 16 bit error injection vector which enables injecting errors to the
681 * corresponding bit within the error injection word above. When used during a
682 * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
683 */
684static ssize_t inject_ecc_vector_store(struct device *dev,
685 struct device_attribute *mattr,
686 const char *data, size_t count)
687{
688 struct mem_ctl_info *mci = to_mci(dev);
689 struct amd64_pvt *pvt = mci->pvt_info;
690 unsigned long value;
691 int ret;
692
693 ret = kstrtoul(data, 16, &value);
694 if (ret < 0)
695 return ret;
696
697 if (value & 0xFFFF0000) {
698 amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value);
699 return -EINVAL;
700 }
701
702 pvt->injection.bit_map = (u32) value;
703 return count;
704}
705
706/*
707 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
708 * fields needed by the injection registers and read the NB Array Data Port.
709 */
710static ssize_t inject_read_store(struct device *dev,
711 struct device_attribute *mattr,
712 const char *data, size_t count)
713{
714 struct mem_ctl_info *mci = to_mci(dev);
715 struct amd64_pvt *pvt = mci->pvt_info;
716 unsigned long value;
717 u32 section, word_bits;
718 int ret;
719
720 ret = kstrtoul(data, 10, &value);
721 if (ret < 0)
722 return ret;
723
724 /* Form value to choose 16-byte section of cacheline */
725 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
726
727 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
728
729 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);
730
731 /* Issue 'word' and 'bit' along with the READ request */
732 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
733
734 edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
735
736 return count;
737}
738
739/*
740 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
741 * fields needed by the injection registers.
742 */
743static ssize_t inject_write_store(struct device *dev,
744 struct device_attribute *mattr,
745 const char *data, size_t count)
746{
747 struct mem_ctl_info *mci = to_mci(dev);
748 struct amd64_pvt *pvt = mci->pvt_info;
749 u32 section, word_bits, tmp;
750 unsigned long value;
751 int ret;
752
753 ret = kstrtoul(data, 10, &value);
754 if (ret < 0)
755 return ret;
756
757 /* Form value to choose 16-byte section of cacheline */
758 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
759
760 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
761
762 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
763
764 pr_notice_once("Don't forget to decrease MCE polling interval in\n"
765 "/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n"
766 "so that you can get the error report faster.\n");
767
768 on_each_cpu(disable_caches, NULL, 1);
769
770 /* Issue 'word' and 'bit' along with the READ request */
771 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
772
773 retry:
774 /* wait until injection happens */
775 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
776 if (tmp & F10_NB_ARR_ECC_WR_REQ) {
777 cpu_relax();
778 goto retry;
779 }
780
781 on_each_cpu(enable_caches, NULL, 1);
782
783 edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
784
785 return count;
786}
787
788/*
789 * update NUM_INJ_ATTRS in case you add new members
790 */
791
792static DEVICE_ATTR_RW(inject_section);
793static DEVICE_ATTR_RW(inject_word);
794static DEVICE_ATTR_RW(inject_ecc_vector);
795static DEVICE_ATTR_WO(inject_write);
796static DEVICE_ATTR_WO(inject_read);
797
798static struct attribute *inj_attrs[] = {
799 &dev_attr_inject_section.attr,
800 &dev_attr_inject_word.attr,
801 &dev_attr_inject_ecc_vector.attr,
802 &dev_attr_inject_write.attr,
803 &dev_attr_inject_read.attr,
804 NULL
805};
806
807static umode_t inj_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
808{
809 struct device *dev = kobj_to_dev(kobj);
810 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
811 struct amd64_pvt *pvt = mci->pvt_info;
812
813 /* Families which have that injection hw */
814 if (pvt->fam >= 0x10 && pvt->fam <= 0x16)
815 return attr->mode;
816
817 return 0;
818}
819
820static const struct attribute_group inj_group = {
821 .attrs = inj_attrs,
822 .is_visible = inj_is_visible,
823};
824#endif /* CONFIG_EDAC_DEBUG */
825
826/*
827 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
828 * assumed that sys_addr maps to the node given by mci.
829 *
830 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
831 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
832 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
833 * then it is also involved in translating a SysAddr to a DramAddr. Sections
834 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
835 * These parts of the documentation are unclear. I interpret them as follows:
836 *
837 * When node n receives a SysAddr, it processes the SysAddr as follows:
838 *
839 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
840 * Limit registers for node n. If the SysAddr is not within the range
841 * specified by the base and limit values, then node n ignores the Sysaddr
842 * (since it does not map to node n). Otherwise continue to step 2 below.
843 *
844 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
845 * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
846 * the range of relocated addresses (starting at 0x100000000) from the DRAM
847 * hole. If not, skip to step 3 below. Else get the value of the
848 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
849 * offset defined by this value from the SysAddr.
850 *
851 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
852 * Base register for node n. To obtain the DramAddr, subtract the base
853 * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
854 */
855static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
856{
857 struct amd64_pvt *pvt = mci->pvt_info;
858 u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
859 int ret;
860
861 dram_base = get_dram_base(pvt, pvt->mc_node_id);
862
863 ret = get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
864 if (!ret) {
865 if ((sys_addr >= (1ULL << 32)) &&
866 (sys_addr < ((1ULL << 32) + hole_size))) {
867 /* use DHAR to translate SysAddr to DramAddr */
868 dram_addr = sys_addr - hole_offset;
869
870 edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
871 (unsigned long)sys_addr,
872 (unsigned long)dram_addr);
873
874 return dram_addr;
875 }
876 }
877
878 /*
879 * Translate the SysAddr to a DramAddr as shown near the start of
880 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
881 * only deals with 40-bit values. Therefore we discard bits 63-40 of
882 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
883 * discard are all 1s. Otherwise the bits we discard are all 0s. See
884 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
885 * Programmer's Manual Volume 1 Application Programming.
886 */
887 dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
888
889 edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
890 (unsigned long)sys_addr, (unsigned long)dram_addr);
891 return dram_addr;
892}
893
894/*
895 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
896 * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
897 * for node interleaving.
898 */
899static int num_node_interleave_bits(unsigned intlv_en)
900{
901 static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
902 int n;
903
904 BUG_ON(intlv_en > 7);
905 n = intlv_shift_table[intlv_en];
906 return n;
907}
908
909/* Translate the DramAddr given by @dram_addr to an InputAddr. */
910static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
911{
912 struct amd64_pvt *pvt;
913 int intlv_shift;
914 u64 input_addr;
915
916 pvt = mci->pvt_info;
917
918 /*
919 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
920 * concerning translating a DramAddr to an InputAddr.
921 */
922 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
923 input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +
924 (dram_addr & 0xfff);
925
926 edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
927 intlv_shift, (unsigned long)dram_addr,
928 (unsigned long)input_addr);
929
930 return input_addr;
931}
932
933/*
934 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
935 * assumed that @sys_addr maps to the node given by mci.
936 */
937static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
938{
939 u64 input_addr;
940
941 input_addr =
942 dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));
943
944 edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",
945 (unsigned long)sys_addr, (unsigned long)input_addr);
946
947 return input_addr;
948}
949
950/* Map the Error address to a PAGE and PAGE OFFSET. */
951static inline void error_address_to_page_and_offset(u64 error_address,
952 struct err_info *err)
953{
954 err->page = (u32) (error_address >> PAGE_SHIFT);
955 err->offset = ((u32) error_address) & ~PAGE_MASK;
956}
957
958/*
959 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
960 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
961 * of a node that detected an ECC memory error. mci represents the node that
962 * the error address maps to (possibly different from the node that detected
963 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
964 * error.
965 */
966static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
967{
968 int csrow;
969
970 csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
971
972 if (csrow == -1)
973 amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
974 "address 0x%lx\n", (unsigned long)sys_addr);
975 return csrow;
976}
977
978/*
979 * See AMD PPR DF::LclNodeTypeMap
980 *
981 * This register gives information for nodes of the same type within a system.
982 *
983 * Reading this register from a GPU node will tell how many GPU nodes are in the
984 * system and what the lowest AMD Node ID value is for the GPU nodes. Use this
985 * info to fixup the Linux logical "Node ID" value set in the AMD NB code and EDAC.
986 */
987static struct local_node_map {
988 u16 node_count;
989 u16 base_node_id;
990} gpu_node_map;
991
992#define PCI_DEVICE_ID_AMD_MI200_DF_F1 0x14d1
993#define REG_LOCAL_NODE_TYPE_MAP 0x144
994
995/* Local Node Type Map (LNTM) fields */
996#define LNTM_NODE_COUNT GENMASK(27, 16)
997#define LNTM_BASE_NODE_ID GENMASK(11, 0)
998
999static int gpu_get_node_map(struct amd64_pvt *pvt)
1000{
1001 struct pci_dev *pdev;
1002 int ret;
1003 u32 tmp;
1004
1005 /*
1006 * Mapping of nodes from hardware-provided AMD Node ID to a
1007 * Linux logical one is applicable for MI200 models. Therefore,
1008 * return early for other heterogeneous systems.
1009 */
1010 if (pvt->F3->device != PCI_DEVICE_ID_AMD_MI200_DF_F3)
1011 return 0;
1012
1013 /*
1014 * Node ID 0 is reserved for CPUs. Therefore, a non-zero Node ID
1015 * means the values have been already cached.
1016 */
1017 if (gpu_node_map.base_node_id)
1018 return 0;
1019
1020 pdev = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F1, NULL);
1021 if (!pdev) {
1022 ret = -ENODEV;
1023 goto out;
1024 }
1025
1026 ret = pci_read_config_dword(pdev, REG_LOCAL_NODE_TYPE_MAP, &tmp);
1027 if (ret)
1028 goto out;
1029
1030 gpu_node_map.node_count = FIELD_GET(LNTM_NODE_COUNT, tmp);
1031 gpu_node_map.base_node_id = FIELD_GET(LNTM_BASE_NODE_ID, tmp);
1032
1033out:
1034 pci_dev_put(pdev);
1035 return ret;
1036}
1037
1038static int fixup_node_id(int node_id, struct mce *m)
1039{
1040 /* MCA_IPID[InstanceIdHi] give the AMD Node ID for the bank. */
1041 u8 nid = (m->ipid >> 44) & 0xF;
1042
1043 if (smca_get_bank_type(m->extcpu, m->bank) != SMCA_UMC_V2)
1044 return node_id;
1045
1046 /* Nodes below the GPU base node are CPU nodes and don't need a fixup. */
1047 if (nid < gpu_node_map.base_node_id)
1048 return node_id;
1049
1050 /* Convert the hardware-provided AMD Node ID to a Linux logical one. */
1051 return nid - gpu_node_map.base_node_id + 1;
1052}
1053
1054/* Protect the PCI config register pairs used for DF indirect access. */
1055static DEFINE_MUTEX(df_indirect_mutex);
1056
1057/*
1058 * Data Fabric Indirect Access uses FICAA/FICAD.
1059 *
1060 * Fabric Indirect Configuration Access Address (FICAA): Constructed based
1061 * on the device's Instance Id and the PCI function and register offset of
1062 * the desired register.
1063 *
1064 * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
1065 * and FICAD HI registers but so far we only need the LO register.
1066 *
1067 * Use Instance Id 0xFF to indicate a broadcast read.
1068 */
1069#define DF_BROADCAST 0xFF
1070static int __df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
1071{
1072 struct pci_dev *F4;
1073 u32 ficaa;
1074 int err = -ENODEV;
1075
1076 if (node >= amd_nb_num())
1077 goto out;
1078
1079 F4 = node_to_amd_nb(node)->link;
1080 if (!F4)
1081 goto out;
1082
1083 ficaa = (instance_id == DF_BROADCAST) ? 0 : 1;
1084 ficaa |= reg & 0x3FC;
1085 ficaa |= (func & 0x7) << 11;
1086 ficaa |= instance_id << 16;
1087
1088 mutex_lock(&df_indirect_mutex);
1089
1090 err = pci_write_config_dword(F4, 0x5C, ficaa);
1091 if (err) {
1092 pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
1093 goto out_unlock;
1094 }
1095
1096 err = pci_read_config_dword(F4, 0x98, lo);
1097 if (err)
1098 pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
1099
1100out_unlock:
1101 mutex_unlock(&df_indirect_mutex);
1102
1103out:
1104 return err;
1105}
1106
1107static int df_indirect_read_instance(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
1108{
1109 return __df_indirect_read(node, func, reg, instance_id, lo);
1110}
1111
1112static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo)
1113{
1114 return __df_indirect_read(node, func, reg, DF_BROADCAST, lo);
1115}
1116
1117struct addr_ctx {
1118 u64 ret_addr;
1119 u32 tmp;
1120 u16 nid;
1121 u8 inst_id;
1122};
1123
1124static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
1125{
1126 u64 dram_base_addr, dram_limit_addr, dram_hole_base;
1127
1128 u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
1129 u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
1130 u8 intlv_addr_sel, intlv_addr_bit;
1131 u8 num_intlv_bits, hashed_bit;
1132 u8 lgcy_mmio_hole_en, base = 0;
1133 u8 cs_mask, cs_id = 0;
1134 bool hash_enabled = false;
1135
1136 struct addr_ctx ctx;
1137
1138 memset(&ctx, 0, sizeof(ctx));
1139
1140 /* Start from the normalized address */
1141 ctx.ret_addr = norm_addr;
1142
1143 ctx.nid = nid;
1144 ctx.inst_id = umc;
1145
1146 /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
1147 if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp))
1148 goto out_err;
1149
1150 /* Remove HiAddrOffset from normalized address, if enabled: */
1151 if (ctx.tmp & BIT(0)) {
1152 u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8;
1153
1154 if (norm_addr >= hi_addr_offset) {
1155 ctx.ret_addr -= hi_addr_offset;
1156 base = 1;
1157 }
1158 }
1159
1160 /* Read D18F0x110 (DramBaseAddress). */
1161 if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp))
1162 goto out_err;
1163
1164 /* Check if address range is valid. */
1165 if (!(ctx.tmp & BIT(0))) {
1166 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
1167 __func__, ctx.tmp);
1168 goto out_err;
1169 }
1170
1171 lgcy_mmio_hole_en = ctx.tmp & BIT(1);
1172 intlv_num_chan = (ctx.tmp >> 4) & 0xF;
1173 intlv_addr_sel = (ctx.tmp >> 8) & 0x7;
1174 dram_base_addr = (ctx.tmp & GENMASK_ULL(31, 12)) << 16;
1175
1176 /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
1177 if (intlv_addr_sel > 3) {
1178 pr_err("%s: Invalid interleave address select %d.\n",
1179 __func__, intlv_addr_sel);
1180 goto out_err;
1181 }
1182
1183 /* Read D18F0x114 (DramLimitAddress). */
1184 if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp))
1185 goto out_err;
1186
1187 intlv_num_sockets = (ctx.tmp >> 8) & 0x1;
1188 intlv_num_dies = (ctx.tmp >> 10) & 0x3;
1189 dram_limit_addr = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
1190
1191 intlv_addr_bit = intlv_addr_sel + 8;
1192
1193 /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
1194 switch (intlv_num_chan) {
1195 case 0: intlv_num_chan = 0; break;
1196 case 1: intlv_num_chan = 1; break;
1197 case 3: intlv_num_chan = 2; break;
1198 case 5: intlv_num_chan = 3; break;
1199 case 7: intlv_num_chan = 4; break;
1200
1201 case 8: intlv_num_chan = 1;
1202 hash_enabled = true;
1203 break;
1204 default:
1205 pr_err("%s: Invalid number of interleaved channels %d.\n",
1206 __func__, intlv_num_chan);
1207 goto out_err;
1208 }
1209
1210 num_intlv_bits = intlv_num_chan;
1211
1212 if (intlv_num_dies > 2) {
1213 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
1214 __func__, intlv_num_dies);
1215 goto out_err;
1216 }
1217
1218 num_intlv_bits += intlv_num_dies;
1219
1220 /* Add a bit if sockets are interleaved. */
1221 num_intlv_bits += intlv_num_sockets;
1222
1223 /* Assert num_intlv_bits <= 4 */
1224 if (num_intlv_bits > 4) {
1225 pr_err("%s: Invalid interleave bits %d.\n",
1226 __func__, num_intlv_bits);
1227 goto out_err;
1228 }
1229
1230 if (num_intlv_bits > 0) {
1231 u64 temp_addr_x, temp_addr_i, temp_addr_y;
1232 u8 die_id_bit, sock_id_bit, cs_fabric_id;
1233
1234 /*
1235 * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
1236 * This is the fabric id for this coherent slave. Use
1237 * umc/channel# as instance id of the coherent slave
1238 * for FICAA.
1239 */
1240 if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp))
1241 goto out_err;
1242
1243 cs_fabric_id = (ctx.tmp >> 8) & 0xFF;
1244 die_id_bit = 0;
1245
1246 /* If interleaved over more than 1 channel: */
1247 if (intlv_num_chan) {
1248 die_id_bit = intlv_num_chan;
1249 cs_mask = (1 << die_id_bit) - 1;
1250 cs_id = cs_fabric_id & cs_mask;
1251 }
1252
1253 sock_id_bit = die_id_bit;
1254
1255 /* Read D18F1x208 (SystemFabricIdMask). */
1256 if (intlv_num_dies || intlv_num_sockets)
1257 if (df_indirect_read_broadcast(nid, 1, 0x208, &ctx.tmp))
1258 goto out_err;
1259
1260 /* If interleaved over more than 1 die. */
1261 if (intlv_num_dies) {
1262 sock_id_bit = die_id_bit + intlv_num_dies;
1263 die_id_shift = (ctx.tmp >> 24) & 0xF;
1264 die_id_mask = (ctx.tmp >> 8) & 0xFF;
1265
1266 cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
1267 }
1268
1269 /* If interleaved over more than 1 socket. */
1270 if (intlv_num_sockets) {
1271 socket_id_shift = (ctx.tmp >> 28) & 0xF;
1272 socket_id_mask = (ctx.tmp >> 16) & 0xFF;
1273
1274 cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
1275 }
1276
1277 /*
1278 * The pre-interleaved address consists of XXXXXXIIIYYYYY
1279 * where III is the ID for this CS, and XXXXXXYYYYY are the
1280 * address bits from the post-interleaved address.
1281 * "num_intlv_bits" has been calculated to tell us how many "I"
1282 * bits there are. "intlv_addr_bit" tells us how many "Y" bits
1283 * there are (where "I" starts).
1284 */
1285 temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0);
1286 temp_addr_i = (cs_id << intlv_addr_bit);
1287 temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
1288 ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
1289 }
1290
1291 /* Add dram base address */
1292 ctx.ret_addr += dram_base_addr;
1293
1294 /* If legacy MMIO hole enabled */
1295 if (lgcy_mmio_hole_en) {
1296 if (df_indirect_read_broadcast(nid, 0, 0x104, &ctx.tmp))
1297 goto out_err;
1298
1299 dram_hole_base = ctx.tmp & GENMASK(31, 24);
1300 if (ctx.ret_addr >= dram_hole_base)
1301 ctx.ret_addr += (BIT_ULL(32) - dram_hole_base);
1302 }
1303
1304 if (hash_enabled) {
1305 /* Save some parentheses and grab ls-bit at the end. */
1306 hashed_bit = (ctx.ret_addr >> 12) ^
1307 (ctx.ret_addr >> 18) ^
1308 (ctx.ret_addr >> 21) ^
1309 (ctx.ret_addr >> 30) ^
1310 cs_id;
1311
1312 hashed_bit &= BIT(0);
1313
1314 if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0)))
1315 ctx.ret_addr ^= BIT(intlv_addr_bit);
1316 }
1317
1318 /* Is calculated system address is above DRAM limit address? */
1319 if (ctx.ret_addr > dram_limit_addr)
1320 goto out_err;
1321
1322 *sys_addr = ctx.ret_addr;
1323 return 0;
1324
1325out_err:
1326 return -EINVAL;
1327}
1328
1329static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
1330
1331/*
1332 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
1333 * are ECC capable.
1334 */
1335static unsigned long dct_determine_edac_cap(struct amd64_pvt *pvt)
1336{
1337 unsigned long edac_cap = EDAC_FLAG_NONE;
1338 u8 bit;
1339
1340 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
1341 ? 19
1342 : 17;
1343
1344 if (pvt->dclr0 & BIT(bit))
1345 edac_cap = EDAC_FLAG_SECDED;
1346
1347 return edac_cap;
1348}
1349
1350static unsigned long umc_determine_edac_cap(struct amd64_pvt *pvt)
1351{
1352 u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
1353 unsigned long edac_cap = EDAC_FLAG_NONE;
1354
1355 for_each_umc(i) {
1356 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
1357 continue;
1358
1359 umc_en_mask |= BIT(i);
1360
1361 /* UMC Configuration bit 12 (DimmEccEn) */
1362 if (pvt->umc[i].umc_cfg & BIT(12))
1363 dimm_ecc_en_mask |= BIT(i);
1364 }
1365
1366 if (umc_en_mask == dimm_ecc_en_mask)
1367 edac_cap = EDAC_FLAG_SECDED;
1368
1369 return edac_cap;
1370}
1371
1372/*
1373 * debug routine to display the memory sizes of all logical DIMMs and its
1374 * CSROWs
1375 */
1376static void dct_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1377{
1378 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
1379 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
1380 int dimm, size0, size1;
1381
1382 if (pvt->fam == 0xf) {
1383 /* K8 families < revF not supported yet */
1384 if (pvt->ext_model < K8_REV_F)
1385 return;
1386
1387 WARN_ON(ctrl != 0);
1388 }
1389
1390 if (pvt->fam == 0x10) {
1391 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
1392 : pvt->dbam0;
1393 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
1394 pvt->csels[1].csbases :
1395 pvt->csels[0].csbases;
1396 } else if (ctrl) {
1397 dbam = pvt->dbam0;
1398 dcsb = pvt->csels[1].csbases;
1399 }
1400 edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
1401 ctrl, dbam);
1402
1403 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
1404
1405 /* Dump memory sizes for DIMM and its CSROWs */
1406 for (dimm = 0; dimm < 4; dimm++) {
1407 size0 = 0;
1408 if (dcsb[dimm * 2] & DCSB_CS_ENABLE)
1409 /*
1410 * For F15m60h, we need multiplier for LRDIMM cs_size
1411 * calculation. We pass dimm value to the dbam_to_cs
1412 * mapper so we can find the multiplier from the
1413 * corresponding DCSM.
1414 */
1415 size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
1416 DBAM_DIMM(dimm, dbam),
1417 dimm);
1418
1419 size1 = 0;
1420 if (dcsb[dimm * 2 + 1] & DCSB_CS_ENABLE)
1421 size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
1422 DBAM_DIMM(dimm, dbam),
1423 dimm);
1424
1425 amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
1426 dimm * 2, size0,
1427 dimm * 2 + 1, size1);
1428 }
1429}
1430
1431
1432static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
1433{
1434 edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
1435
1436 if (pvt->dram_type == MEM_LRDDR3) {
1437 u32 dcsm = pvt->csels[chan].csmasks[0];
1438 /*
1439 * It's assumed all LRDIMMs in a DCT are going to be of
1440 * same 'type' until proven otherwise. So, use a cs
1441 * value of '0' here to get dcsm value.
1442 */
1443 edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));
1444 }
1445
1446 edac_dbg(1, "All DIMMs support ECC:%s\n",
1447 (dclr & BIT(19)) ? "yes" : "no");
1448
1449
1450 edac_dbg(1, " PAR/ERR parity: %s\n",
1451 (dclr & BIT(8)) ? "enabled" : "disabled");
1452
1453 if (pvt->fam == 0x10)
1454 edac_dbg(1, " DCT 128bit mode width: %s\n",
1455 (dclr & BIT(11)) ? "128b" : "64b");
1456
1457 edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
1458 (dclr & BIT(12)) ? "yes" : "no",
1459 (dclr & BIT(13)) ? "yes" : "no",
1460 (dclr & BIT(14)) ? "yes" : "no",
1461 (dclr & BIT(15)) ? "yes" : "no");
1462}
1463
1464#define CS_EVEN_PRIMARY BIT(0)
1465#define CS_ODD_PRIMARY BIT(1)
1466#define CS_EVEN_SECONDARY BIT(2)
1467#define CS_ODD_SECONDARY BIT(3)
1468#define CS_3R_INTERLEAVE BIT(4)
1469
1470#define CS_EVEN (CS_EVEN_PRIMARY | CS_EVEN_SECONDARY)
1471#define CS_ODD (CS_ODD_PRIMARY | CS_ODD_SECONDARY)
1472
1473static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
1474{
1475 u8 base, count = 0;
1476 int cs_mode = 0;
1477
1478 if (csrow_enabled(2 * dimm, ctrl, pvt))
1479 cs_mode |= CS_EVEN_PRIMARY;
1480
1481 if (csrow_enabled(2 * dimm + 1, ctrl, pvt))
1482 cs_mode |= CS_ODD_PRIMARY;
1483
1484 /* Asymmetric dual-rank DIMM support. */
1485 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))
1486 cs_mode |= CS_ODD_SECONDARY;
1487
1488 /*
1489 * 3 Rank inteleaving support.
1490 * There should be only three bases enabled and their two masks should
1491 * be equal.
1492 */
1493 for_each_chip_select(base, ctrl, pvt)
1494 count += csrow_enabled(base, ctrl, pvt);
1495
1496 if (count == 3 &&
1497 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) {
1498 edac_dbg(1, "3R interleaving in use.\n");
1499 cs_mode |= CS_3R_INTERLEAVE;
1500 }
1501
1502 return cs_mode;
1503}
1504
1505static int __addr_mask_to_cs_size(u32 addr_mask_orig, unsigned int cs_mode,
1506 int csrow_nr, int dimm)
1507{
1508 u32 msb, weight, num_zero_bits;
1509 u32 addr_mask_deinterleaved;
1510 int size = 0;
1511
1512 /*
1513 * The number of zero bits in the mask is equal to the number of bits
1514 * in a full mask minus the number of bits in the current mask.
1515 *
1516 * The MSB is the number of bits in the full mask because BIT[0] is
1517 * always 0.
1518 *
1519 * In the special 3 Rank interleaving case, a single bit is flipped
1520 * without swapping with the most significant bit. This can be handled
1521 * by keeping the MSB where it is and ignoring the single zero bit.
1522 */
1523 msb = fls(addr_mask_orig) - 1;
1524 weight = hweight_long(addr_mask_orig);
1525 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);
1526
1527 /* Take the number of zero bits off from the top of the mask. */
1528 addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1);
1529
1530 edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);
1531 edac_dbg(1, " Original AddrMask: 0x%x\n", addr_mask_orig);
1532 edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved);
1533
1534 /* Register [31:1] = Address [39:9]. Size is in kBs here. */
1535 size = (addr_mask_deinterleaved >> 2) + 1;
1536
1537 /* Return size in MBs. */
1538 return size >> 10;
1539}
1540
1541static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
1542 unsigned int cs_mode, int csrow_nr)
1543{
1544 int cs_mask_nr = csrow_nr;
1545 u32 addr_mask_orig;
1546 int dimm, size = 0;
1547
1548 /* No Chip Selects are enabled. */
1549 if (!cs_mode)
1550 return size;
1551
1552 /* Requested size of an even CS but none are enabled. */
1553 if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))
1554 return size;
1555
1556 /* Requested size of an odd CS but none are enabled. */
1557 if (!(cs_mode & CS_ODD) && (csrow_nr & 1))
1558 return size;
1559
1560 /*
1561 * Family 17h introduced systems with one mask per DIMM,
1562 * and two Chip Selects per DIMM.
1563 *
1564 * CS0 and CS1 -> MASK0 / DIMM0
1565 * CS2 and CS3 -> MASK1 / DIMM1
1566 *
1567 * Family 19h Model 10h introduced systems with one mask per Chip Select,
1568 * and two Chip Selects per DIMM.
1569 *
1570 * CS0 -> MASK0 -> DIMM0
1571 * CS1 -> MASK1 -> DIMM0
1572 * CS2 -> MASK2 -> DIMM1
1573 * CS3 -> MASK3 -> DIMM1
1574 *
1575 * Keep the mask number equal to the Chip Select number for newer systems,
1576 * and shift the mask number for older systems.
1577 */
1578 dimm = csrow_nr >> 1;
1579
1580 if (!pvt->flags.zn_regs_v2)
1581 cs_mask_nr >>= 1;
1582
1583 /* Asymmetric dual-rank DIMM support. */
1584 if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
1585 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];
1586 else
1587 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];
1588
1589 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm);
1590}
1591
1592static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1593{
1594 int dimm, size0, size1, cs0, cs1, cs_mode;
1595
1596 edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
1597
1598 for (dimm = 0; dimm < 2; dimm++) {
1599 cs0 = dimm * 2;
1600 cs1 = dimm * 2 + 1;
1601
1602 cs_mode = umc_get_cs_mode(dimm, ctrl, pvt);
1603
1604 size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0);
1605 size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1);
1606
1607 amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
1608 cs0, size0,
1609 cs1, size1);
1610 }
1611}
1612
1613static void umc_dump_misc_regs(struct amd64_pvt *pvt)
1614{
1615 struct amd64_umc *umc;
1616 u32 i, tmp, umc_base;
1617
1618 for_each_umc(i) {
1619 umc_base = get_umc_base(i);
1620 umc = &pvt->umc[i];
1621
1622 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
1623 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
1624 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
1625 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
1626
1627 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp);
1628 edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);
1629
1630 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp);
1631 edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);
1632 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);
1633
1634 edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
1635 i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",
1636 (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");
1637 edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",
1638 i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");
1639 edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",
1640 i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");
1641 edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
1642 i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");
1643
1644 if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) {
1645 amd_smn_read(pvt->mc_node_id,
1646 umc_base + get_umc_reg(pvt, UMCCH_ADDR_CFG),
1647 &tmp);
1648 edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",
1649 i, 1 << ((tmp >> 4) & 0x3));
1650 }
1651
1652 umc_debug_display_dimm_sizes(pvt, i);
1653 }
1654}
1655
1656static void dct_dump_misc_regs(struct amd64_pvt *pvt)
1657{
1658 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
1659
1660 edac_dbg(1, " NB two channel DRAM capable: %s\n",
1661 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
1662
1663 edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n",
1664 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
1665 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
1666
1667 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
1668
1669 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
1670
1671 edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
1672 pvt->dhar, dhar_base(pvt),
1673 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)
1674 : f10_dhar_offset(pvt));
1675
1676 dct_debug_display_dimm_sizes(pvt, 0);
1677
1678 /* everything below this point is Fam10h and above */
1679 if (pvt->fam == 0xf)
1680 return;
1681
1682 dct_debug_display_dimm_sizes(pvt, 1);
1683
1684 /* Only if NOT ganged does dclr1 have valid info */
1685 if (!dct_ganging_enabled(pvt))
1686 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
1687
1688 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
1689
1690 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
1691}
1692
1693/*
1694 * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
1695 */
1696static void dct_prep_chip_selects(struct amd64_pvt *pvt)
1697{
1698 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
1699 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
1700 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
1701 } else if (pvt->fam == 0x15 && pvt->model == 0x30) {
1702 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
1703 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
1704 } else {
1705 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
1706 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
1707 }
1708}
1709
1710static void umc_prep_chip_selects(struct amd64_pvt *pvt)
1711{
1712 int umc;
1713
1714 for_each_umc(umc) {
1715 pvt->csels[umc].b_cnt = 4;
1716 pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2;
1717 }
1718}
1719
1720static void umc_read_base_mask(struct amd64_pvt *pvt)
1721{
1722 u32 umc_base_reg, umc_base_reg_sec;
1723 u32 umc_mask_reg, umc_mask_reg_sec;
1724 u32 base_reg, base_reg_sec;
1725 u32 mask_reg, mask_reg_sec;
1726 u32 *base, *base_sec;
1727 u32 *mask, *mask_sec;
1728 int cs, umc;
1729
1730 for_each_umc(umc) {
1731 umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;
1732 umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;
1733
1734 for_each_chip_select(cs, umc, pvt) {
1735 base = &pvt->csels[umc].csbases[cs];
1736 base_sec = &pvt->csels[umc].csbases_sec[cs];
1737
1738 base_reg = umc_base_reg + (cs * 4);
1739 base_reg_sec = umc_base_reg_sec + (cs * 4);
1740
1741 if (!amd_smn_read(pvt->mc_node_id, base_reg, base))
1742 edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n",
1743 umc, cs, *base, base_reg);
1744
1745 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec))
1746 edac_dbg(0, " DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n",
1747 umc, cs, *base_sec, base_reg_sec);
1748 }
1749
1750 umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;
1751 umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(pvt, UMCCH_ADDR_MASK_SEC);
1752
1753 for_each_chip_select_mask(cs, umc, pvt) {
1754 mask = &pvt->csels[umc].csmasks[cs];
1755 mask_sec = &pvt->csels[umc].csmasks_sec[cs];
1756
1757 mask_reg = umc_mask_reg + (cs * 4);
1758 mask_reg_sec = umc_mask_reg_sec + (cs * 4);
1759
1760 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask))
1761 edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n",
1762 umc, cs, *mask, mask_reg);
1763
1764 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec))
1765 edac_dbg(0, " DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n",
1766 umc, cs, *mask_sec, mask_reg_sec);
1767 }
1768 }
1769}
1770
1771/*
1772 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
1773 */
1774static void dct_read_base_mask(struct amd64_pvt *pvt)
1775{
1776 int cs;
1777
1778 for_each_chip_select(cs, 0, pvt) {
1779 int reg0 = DCSB0 + (cs * 4);
1780 int reg1 = DCSB1 + (cs * 4);
1781 u32 *base0 = &pvt->csels[0].csbases[cs];
1782 u32 *base1 = &pvt->csels[1].csbases[cs];
1783
1784 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
1785 edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
1786 cs, *base0, reg0);
1787
1788 if (pvt->fam == 0xf)
1789 continue;
1790
1791 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
1792 edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
1793 cs, *base1, (pvt->fam == 0x10) ? reg1
1794 : reg0);
1795 }
1796
1797 for_each_chip_select_mask(cs, 0, pvt) {
1798 int reg0 = DCSM0 + (cs * 4);
1799 int reg1 = DCSM1 + (cs * 4);
1800 u32 *mask0 = &pvt->csels[0].csmasks[cs];
1801 u32 *mask1 = &pvt->csels[1].csmasks[cs];
1802
1803 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
1804 edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
1805 cs, *mask0, reg0);
1806
1807 if (pvt->fam == 0xf)
1808 continue;
1809
1810 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
1811 edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
1812 cs, *mask1, (pvt->fam == 0x10) ? reg1
1813 : reg0);
1814 }
1815}
1816
1817static void umc_determine_memory_type(struct amd64_pvt *pvt)
1818{
1819 struct amd64_umc *umc;
1820 u32 i;
1821
1822 for_each_umc(i) {
1823 umc = &pvt->umc[i];
1824
1825 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) {
1826 umc->dram_type = MEM_EMPTY;
1827 continue;
1828 }
1829
1830 /*
1831 * Check if the system supports the "DDR Type" field in UMC Config
1832 * and has DDR5 DIMMs in use.
1833 */
1834 if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {
1835 if (umc->dimm_cfg & BIT(5))
1836 umc->dram_type = MEM_LRDDR5;
1837 else if (umc->dimm_cfg & BIT(4))
1838 umc->dram_type = MEM_RDDR5;
1839 else
1840 umc->dram_type = MEM_DDR5;
1841 } else {
1842 if (umc->dimm_cfg & BIT(5))
1843 umc->dram_type = MEM_LRDDR4;
1844 else if (umc->dimm_cfg & BIT(4))
1845 umc->dram_type = MEM_RDDR4;
1846 else
1847 umc->dram_type = MEM_DDR4;
1848 }
1849
1850 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]);
1851 }
1852}
1853
1854static void dct_determine_memory_type(struct amd64_pvt *pvt)
1855{
1856 u32 dram_ctrl, dcsm;
1857
1858 switch (pvt->fam) {
1859 case 0xf:
1860 if (pvt->ext_model >= K8_REV_F)
1861 goto ddr3;
1862
1863 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
1864 return;
1865
1866 case 0x10:
1867 if (pvt->dchr0 & DDR3_MODE)
1868 goto ddr3;
1869
1870 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
1871 return;
1872
1873 case 0x15:
1874 if (pvt->model < 0x60)
1875 goto ddr3;
1876
1877 /*
1878 * Model 0x60h needs special handling:
1879 *
1880 * We use a Chip Select value of '0' to obtain dcsm.
1881 * Theoretically, it is possible to populate LRDIMMs of different
1882 * 'Rank' value on a DCT. But this is not the common case. So,
1883 * it's reasonable to assume all DIMMs are going to be of same
1884 * 'type' until proven otherwise.
1885 */
1886 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl);
1887 dcsm = pvt->csels[0].csmasks[0];
1888
1889 if (((dram_ctrl >> 8) & 0x7) == 0x2)
1890 pvt->dram_type = MEM_DDR4;
1891 else if (pvt->dclr0 & BIT(16))
1892 pvt->dram_type = MEM_DDR3;
1893 else if (dcsm & 0x3)
1894 pvt->dram_type = MEM_LRDDR3;
1895 else
1896 pvt->dram_type = MEM_RDDR3;
1897
1898 return;
1899
1900 case 0x16:
1901 goto ddr3;
1902
1903 default:
1904 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);
1905 pvt->dram_type = MEM_EMPTY;
1906 }
1907
1908 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]);
1909 return;
1910
1911ddr3:
1912 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
1913}
1914
1915/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
1916static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
1917{
1918 u16 mce_nid = topology_die_id(m->extcpu);
1919 struct mem_ctl_info *mci;
1920 u8 start_bit = 1;
1921 u8 end_bit = 47;
1922 u64 addr;
1923
1924 mci = edac_mc_find(mce_nid);
1925 if (!mci)
1926 return 0;
1927
1928 pvt = mci->pvt_info;
1929
1930 if (pvt->fam == 0xf) {
1931 start_bit = 3;
1932 end_bit = 39;
1933 }
1934
1935 addr = m->addr & GENMASK_ULL(end_bit, start_bit);
1936
1937 /*
1938 * Erratum 637 workaround
1939 */
1940 if (pvt->fam == 0x15) {
1941 u64 cc6_base, tmp_addr;
1942 u32 tmp;
1943 u8 intlv_en;
1944
1945 if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)
1946 return addr;
1947
1948
1949 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
1950 intlv_en = tmp >> 21 & 0x7;
1951
1952 /* add [47:27] + 3 trailing bits */
1953 cc6_base = (tmp & GENMASK_ULL(20, 0)) << 3;
1954
1955 /* reverse and add DramIntlvEn */
1956 cc6_base |= intlv_en ^ 0x7;
1957
1958 /* pin at [47:24] */
1959 cc6_base <<= 24;
1960
1961 if (!intlv_en)
1962 return cc6_base | (addr & GENMASK_ULL(23, 0));
1963
1964 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
1965
1966 /* faster log2 */
1967 tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
1968
1969 /* OR DramIntlvSel into bits [14:12] */
1970 tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;
1971
1972 /* add remaining [11:0] bits from original MC4_ADDR */
1973 tmp_addr |= addr & GENMASK_ULL(11, 0);
1974
1975 return cc6_base | tmp_addr;
1976 }
1977
1978 return addr;
1979}
1980
1981static struct pci_dev *pci_get_related_function(unsigned int vendor,
1982 unsigned int device,
1983 struct pci_dev *related)
1984{
1985 struct pci_dev *dev = NULL;
1986
1987 while ((dev = pci_get_device(vendor, device, dev))) {
1988 if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
1989 (dev->bus->number == related->bus->number) &&
1990 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
1991 break;
1992 }
1993
1994 return dev;
1995}
1996
1997static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
1998{
1999 struct amd_northbridge *nb;
2000 struct pci_dev *f1 = NULL;
2001 unsigned int pci_func;
2002 int off = range << 3;
2003 u32 llim;
2004
2005 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
2006 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
2007
2008 if (pvt->fam == 0xf)
2009 return;
2010
2011 if (!dram_rw(pvt, range))
2012 return;
2013
2014 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
2015 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
2016
2017 /* F15h: factor in CC6 save area by reading dst node's limit reg */
2018 if (pvt->fam != 0x15)
2019 return;
2020
2021 nb = node_to_amd_nb(dram_dst_node(pvt, range));
2022 if (WARN_ON(!nb))
2023 return;
2024
2025 if (pvt->model == 0x60)
2026 pci_func = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1;
2027 else if (pvt->model == 0x30)
2028 pci_func = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1;
2029 else
2030 pci_func = PCI_DEVICE_ID_AMD_15H_NB_F1;
2031
2032 f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc);
2033 if (WARN_ON(!f1))
2034 return;
2035
2036 amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
2037
2038 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
2039
2040 /* {[39:27],111b} */
2041 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
2042
2043 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
2044
2045 /* [47:40] */
2046 pvt->ranges[range].lim.hi |= llim >> 13;
2047
2048 pci_dev_put(f1);
2049}
2050
2051static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
2052 struct err_info *err)
2053{
2054 struct amd64_pvt *pvt = mci->pvt_info;
2055
2056 error_address_to_page_and_offset(sys_addr, err);
2057
2058 /*
2059 * Find out which node the error address belongs to. This may be
2060 * different from the node that detected the error.
2061 */
2062 err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
2063 if (!err->src_mci) {
2064 amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
2065 (unsigned long)sys_addr);
2066 err->err_code = ERR_NODE;
2067 return;
2068 }
2069
2070 /* Now map the sys_addr to a CSROW */
2071 err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
2072 if (err->csrow < 0) {
2073 err->err_code = ERR_CSROW;
2074 return;
2075 }
2076
2077 /* CHIPKILL enabled */
2078 if (pvt->nbcfg & NBCFG_CHIPKILL) {
2079 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
2080 if (err->channel < 0) {
2081 /*
2082 * Syndrome didn't map, so we don't know which of the
2083 * 2 DIMMs is in error. So we need to ID 'both' of them
2084 * as suspect.
2085 */
2086 amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - "
2087 "possible error reporting race\n",
2088 err->syndrome);
2089 err->err_code = ERR_CHANNEL;
2090 return;
2091 }
2092 } else {
2093 /*
2094 * non-chipkill ecc mode
2095 *
2096 * The k8 documentation is unclear about how to determine the
2097 * channel number when using non-chipkill memory. This method
2098 * was obtained from email communication with someone at AMD.
2099 * (Wish the email was placed in this comment - norsk)
2100 */
2101 err->channel = ((sys_addr & BIT(3)) != 0);
2102 }
2103}
2104
2105static int ddr2_cs_size(unsigned i, bool dct_width)
2106{
2107 unsigned shift = 0;
2108
2109 if (i <= 2)
2110 shift = i;
2111 else if (!(i & 0x1))
2112 shift = i >> 1;
2113 else
2114 shift = (i + 1) >> 1;
2115
2116 return 128 << (shift + !!dct_width);
2117}
2118
2119static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
2120 unsigned cs_mode, int cs_mask_nr)
2121{
2122 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
2123
2124 if (pvt->ext_model >= K8_REV_F) {
2125 WARN_ON(cs_mode > 11);
2126 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
2127 }
2128 else if (pvt->ext_model >= K8_REV_D) {
2129 unsigned diff;
2130 WARN_ON(cs_mode > 10);
2131
2132 /*
2133 * the below calculation, besides trying to win an obfuscated C
2134 * contest, maps cs_mode values to DIMM chip select sizes. The
2135 * mappings are:
2136 *
2137 * cs_mode CS size (mb)
2138 * ======= ============
2139 * 0 32
2140 * 1 64
2141 * 2 128
2142 * 3 128
2143 * 4 256
2144 * 5 512
2145 * 6 256
2146 * 7 512
2147 * 8 1024
2148 * 9 1024
2149 * 10 2048
2150 *
2151 * Basically, it calculates a value with which to shift the
2152 * smallest CS size of 32MB.
2153 *
2154 * ddr[23]_cs_size have a similar purpose.
2155 */
2156 diff = cs_mode/3 + (unsigned)(cs_mode > 5);
2157
2158 return 32 << (cs_mode - diff);
2159 }
2160 else {
2161 WARN_ON(cs_mode > 6);
2162 return 32 << cs_mode;
2163 }
2164}
2165
2166static int ddr3_cs_size(unsigned i, bool dct_width)
2167{
2168 unsigned shift = 0;
2169 int cs_size = 0;
2170
2171 if (i == 0 || i == 3 || i == 4)
2172 cs_size = -1;
2173 else if (i <= 2)
2174 shift = i;
2175 else if (i == 12)
2176 shift = 7;
2177 else if (!(i & 0x1))
2178 shift = i >> 1;
2179 else
2180 shift = (i + 1) >> 1;
2181
2182 if (cs_size != -1)
2183 cs_size = (128 * (1 << !!dct_width)) << shift;
2184
2185 return cs_size;
2186}
2187
2188static int ddr3_lrdimm_cs_size(unsigned i, unsigned rank_multiply)
2189{
2190 unsigned shift = 0;
2191 int cs_size = 0;
2192
2193 if (i < 4 || i == 6)
2194 cs_size = -1;
2195 else if (i == 12)
2196 shift = 7;
2197 else if (!(i & 0x1))
2198 shift = i >> 1;
2199 else
2200 shift = (i + 1) >> 1;
2201
2202 if (cs_size != -1)
2203 cs_size = rank_multiply * (128 << shift);
2204
2205 return cs_size;
2206}
2207
2208static int ddr4_cs_size(unsigned i)
2209{
2210 int cs_size = 0;
2211
2212 if (i == 0)
2213 cs_size = -1;
2214 else if (i == 1)
2215 cs_size = 1024;
2216 else
2217 /* Min cs_size = 1G */
2218 cs_size = 1024 * (1 << (i >> 1));
2219
2220 return cs_size;
2221}
2222
2223static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
2224 unsigned cs_mode, int cs_mask_nr)
2225{
2226 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
2227
2228 WARN_ON(cs_mode > 11);
2229
2230 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
2231 return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
2232 else
2233 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
2234}
2235
2236/*
2237 * F15h supports only 64bit DCT interfaces
2238 */
2239static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
2240 unsigned cs_mode, int cs_mask_nr)
2241{
2242 WARN_ON(cs_mode > 12);
2243
2244 return ddr3_cs_size(cs_mode, false);
2245}
2246
2247/* F15h M60h supports DDR4 mapping as well.. */
2248static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
2249 unsigned cs_mode, int cs_mask_nr)
2250{
2251 int cs_size;
2252 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];
2253
2254 WARN_ON(cs_mode > 12);
2255
2256 if (pvt->dram_type == MEM_DDR4) {
2257 if (cs_mode > 9)
2258 return -1;
2259
2260 cs_size = ddr4_cs_size(cs_mode);
2261 } else if (pvt->dram_type == MEM_LRDDR3) {
2262 unsigned rank_multiply = dcsm & 0xf;
2263
2264 if (rank_multiply == 3)
2265 rank_multiply = 4;
2266 cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply);
2267 } else {
2268 /* Minimum cs size is 512mb for F15hM60h*/
2269 if (cs_mode == 0x1)
2270 return -1;
2271
2272 cs_size = ddr3_cs_size(cs_mode, false);
2273 }
2274
2275 return cs_size;
2276}
2277
2278/*
2279 * F16h and F15h model 30h have only limited cs_modes.
2280 */
2281static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
2282 unsigned cs_mode, int cs_mask_nr)
2283{
2284 WARN_ON(cs_mode > 12);
2285
2286 if (cs_mode == 6 || cs_mode == 8 ||
2287 cs_mode == 9 || cs_mode == 12)
2288 return -1;
2289 else
2290 return ddr3_cs_size(cs_mode, false);
2291}
2292
2293static void read_dram_ctl_register(struct amd64_pvt *pvt)
2294{
2295
2296 if (pvt->fam == 0xf)
2297 return;
2298
2299 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
2300 edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
2301 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
2302
2303 edac_dbg(0, " DCTs operate in %s mode\n",
2304 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
2305
2306 if (!dct_ganging_enabled(pvt))
2307 edac_dbg(0, " Address range split per DCT: %s\n",
2308 (dct_high_range_enabled(pvt) ? "yes" : "no"));
2309
2310 edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
2311 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
2312 (dct_memory_cleared(pvt) ? "yes" : "no"));
2313
2314 edac_dbg(0, " channel interleave: %s, "
2315 "interleave bits selector: 0x%x\n",
2316 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
2317 dct_sel_interleave_addr(pvt));
2318 }
2319
2320 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi);
2321}
2322
2323/*
2324 * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG,
2325 * 2.10.12 Memory Interleaving Modes).
2326 */
2327static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
2328 u8 intlv_en, int num_dcts_intlv,
2329 u32 dct_sel)
2330{
2331 u8 channel = 0;
2332 u8 select;
2333
2334 if (!(intlv_en))
2335 return (u8)(dct_sel);
2336
2337 if (num_dcts_intlv == 2) {
2338 select = (sys_addr >> 8) & 0x3;
2339 channel = select ? 0x3 : 0;
2340 } else if (num_dcts_intlv == 4) {
2341 u8 intlv_addr = dct_sel_interleave_addr(pvt);
2342 switch (intlv_addr) {
2343 case 0x4:
2344 channel = (sys_addr >> 8) & 0x3;
2345 break;
2346 case 0x5:
2347 channel = (sys_addr >> 9) & 0x3;
2348 break;
2349 }
2350 }
2351 return channel;
2352}
2353
2354/*
2355 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
2356 * Interleaving Modes.
2357 */
2358static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
2359 bool hi_range_sel, u8 intlv_en)
2360{
2361 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
2362
2363 if (dct_ganging_enabled(pvt))
2364 return 0;
2365
2366 if (hi_range_sel)
2367 return dct_sel_high;
2368
2369 /*
2370 * see F2x110[DctSelIntLvAddr] - channel interleave mode
2371 */
2372 if (dct_interleave_enabled(pvt)) {
2373 u8 intlv_addr = dct_sel_interleave_addr(pvt);
2374
2375 /* return DCT select function: 0=DCT0, 1=DCT1 */
2376 if (!intlv_addr)
2377 return sys_addr >> 6 & 1;
2378
2379 if (intlv_addr & 0x2) {
2380 u8 shift = intlv_addr & 0x1 ? 9 : 6;
2381 u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) & 1;
2382
2383 return ((sys_addr >> shift) & 1) ^ temp;
2384 }
2385
2386 if (intlv_addr & 0x4) {
2387 u8 shift = intlv_addr & 0x1 ? 9 : 8;
2388
2389 return (sys_addr >> shift) & 1;
2390 }
2391
2392 return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
2393 }
2394
2395 if (dct_high_range_enabled(pvt))
2396 return ~dct_sel_high & 1;
2397
2398 return 0;
2399}
2400
2401/* Convert the sys_addr to the normalized DCT address */
2402static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
2403 u64 sys_addr, bool hi_rng,
2404 u32 dct_sel_base_addr)
2405{
2406 u64 chan_off;
2407 u64 dram_base = get_dram_base(pvt, range);
2408 u64 hole_off = f10_dhar_offset(pvt);
2409 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
2410
2411 if (hi_rng) {
2412 /*
2413 * if
2414 * base address of high range is below 4Gb
2415 * (bits [47:27] at [31:11])
2416 * DRAM address space on this DCT is hoisted above 4Gb &&
2417 * sys_addr > 4Gb
2418 *
2419 * remove hole offset from sys_addr
2420 * else
2421 * remove high range offset from sys_addr
2422 */
2423 if ((!(dct_sel_base_addr >> 16) ||
2424 dct_sel_base_addr < dhar_base(pvt)) &&
2425 dhar_valid(pvt) &&
2426 (sys_addr >= BIT_64(32)))
2427 chan_off = hole_off;
2428 else
2429 chan_off = dct_sel_base_off;
2430 } else {
2431 /*
2432 * if
2433 * we have a valid hole &&
2434 * sys_addr > 4Gb
2435 *
2436 * remove hole
2437 * else
2438 * remove dram base to normalize to DCT address
2439 */
2440 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
2441 chan_off = hole_off;
2442 else
2443 chan_off = dram_base;
2444 }
2445
2446 return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));
2447}
2448
2449/*
2450 * checks if the csrow passed in is marked as SPARED, if so returns the new
2451 * spare row
2452 */
2453static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
2454{
2455 int tmp_cs;
2456
2457 if (online_spare_swap_done(pvt, dct) &&
2458 csrow == online_spare_bad_dramcs(pvt, dct)) {
2459
2460 for_each_chip_select(tmp_cs, dct, pvt) {
2461 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
2462 csrow = tmp_cs;
2463 break;
2464 }
2465 }
2466 }
2467 return csrow;
2468}
2469
2470/*
2471 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
2472 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
2473 *
2474 * Return:
2475 * -EINVAL: NOT FOUND
2476 * 0..csrow = Chip-Select Row
2477 */
2478static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
2479{
2480 struct mem_ctl_info *mci;
2481 struct amd64_pvt *pvt;
2482 u64 cs_base, cs_mask;
2483 int cs_found = -EINVAL;
2484 int csrow;
2485
2486 mci = edac_mc_find(nid);
2487 if (!mci)
2488 return cs_found;
2489
2490 pvt = mci->pvt_info;
2491
2492 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
2493
2494 for_each_chip_select(csrow, dct, pvt) {
2495 if (!csrow_enabled(csrow, dct, pvt))
2496 continue;
2497
2498 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
2499
2500 edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
2501 csrow, cs_base, cs_mask);
2502
2503 cs_mask = ~cs_mask;
2504
2505 edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
2506 (in_addr & cs_mask), (cs_base & cs_mask));
2507
2508 if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
2509 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
2510 cs_found = csrow;
2511 break;
2512 }
2513 cs_found = f10_process_possible_spare(pvt, dct, csrow);
2514
2515 edac_dbg(1, " MATCH csrow=%d\n", cs_found);
2516 break;
2517 }
2518 }
2519 return cs_found;
2520}
2521
2522/*
2523 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
2524 * swapped with a region located at the bottom of memory so that the GPU can use
2525 * the interleaved region and thus two channels.
2526 */
2527static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
2528{
2529 u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;
2530
2531 if (pvt->fam == 0x10) {
2532 /* only revC3 and revE have that feature */
2533 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3))
2534 return sys_addr;
2535 }
2536
2537 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg);
2538
2539 if (!(swap_reg & 0x1))
2540 return sys_addr;
2541
2542 swap_base = (swap_reg >> 3) & 0x7f;
2543 swap_limit = (swap_reg >> 11) & 0x7f;
2544 rgn_size = (swap_reg >> 20) & 0x7f;
2545 tmp_addr = sys_addr >> 27;
2546
2547 if (!(sys_addr >> 34) &&
2548 (((tmp_addr >= swap_base) &&
2549 (tmp_addr <= swap_limit)) ||
2550 (tmp_addr < rgn_size)))
2551 return sys_addr ^ (u64)swap_base << 27;
2552
2553 return sys_addr;
2554}
2555
2556/* For a given @dram_range, check if @sys_addr falls within it. */
2557static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
2558 u64 sys_addr, int *chan_sel)
2559{
2560 int cs_found = -EINVAL;
2561 u64 chan_addr;
2562 u32 dct_sel_base;
2563 u8 channel;
2564 bool high_range = false;
2565
2566 u8 node_id = dram_dst_node(pvt, range);
2567 u8 intlv_en = dram_intlv_en(pvt, range);
2568 u32 intlv_sel = dram_intlv_sel(pvt, range);
2569
2570 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2571 range, sys_addr, get_dram_limit(pvt, range));
2572
2573 if (dhar_valid(pvt) &&
2574 dhar_base(pvt) <= sys_addr &&
2575 sys_addr < BIT_64(32)) {
2576 amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
2577 sys_addr);
2578 return -EINVAL;
2579 }
2580
2581 if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
2582 return -EINVAL;
2583
2584 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
2585
2586 dct_sel_base = dct_sel_baseaddr(pvt);
2587
2588 /*
2589 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
2590 * select between DCT0 and DCT1.
2591 */
2592 if (dct_high_range_enabled(pvt) &&
2593 !dct_ganging_enabled(pvt) &&
2594 ((sys_addr >> 27) >= (dct_sel_base >> 11)))
2595 high_range = true;
2596
2597 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
2598
2599 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
2600 high_range, dct_sel_base);
2601
2602 /* Remove node interleaving, see F1x120 */
2603 if (intlv_en)
2604 chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
2605 (chan_addr & 0xfff);
2606
2607 /* remove channel interleave */
2608 if (dct_interleave_enabled(pvt) &&
2609 !dct_high_range_enabled(pvt) &&
2610 !dct_ganging_enabled(pvt)) {
2611
2612 if (dct_sel_interleave_addr(pvt) != 1) {
2613 if (dct_sel_interleave_addr(pvt) == 0x3)
2614 /* hash 9 */
2615 chan_addr = ((chan_addr >> 10) << 9) |
2616 (chan_addr & 0x1ff);
2617 else
2618 /* A[6] or hash 6 */
2619 chan_addr = ((chan_addr >> 7) << 6) |
2620 (chan_addr & 0x3f);
2621 } else
2622 /* A[12] */
2623 chan_addr = ((chan_addr >> 13) << 12) |
2624 (chan_addr & 0xfff);
2625 }
2626
2627 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
2628
2629 cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
2630
2631 if (cs_found >= 0)
2632 *chan_sel = channel;
2633
2634 return cs_found;
2635}
2636
2637static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
2638 u64 sys_addr, int *chan_sel)
2639{
2640 int cs_found = -EINVAL;
2641 int num_dcts_intlv = 0;
2642 u64 chan_addr, chan_offset;
2643 u64 dct_base, dct_limit;
2644 u32 dct_cont_base_reg, dct_cont_limit_reg, tmp;
2645 u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en;
2646
2647 u64 dhar_offset = f10_dhar_offset(pvt);
2648 u8 intlv_addr = dct_sel_interleave_addr(pvt);
2649 u8 node_id = dram_dst_node(pvt, range);
2650 u8 intlv_en = dram_intlv_en(pvt, range);
2651
2652 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg);
2653 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg);
2654
2655 dct_offset_en = (u8) ((dct_cont_base_reg >> 3) & BIT(0));
2656 dct_sel = (u8) ((dct_cont_base_reg >> 4) & 0x7);
2657
2658 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2659 range, sys_addr, get_dram_limit(pvt, range));
2660
2661 if (!(get_dram_base(pvt, range) <= sys_addr) &&
2662 !(get_dram_limit(pvt, range) >= sys_addr))
2663 return -EINVAL;
2664
2665 if (dhar_valid(pvt) &&
2666 dhar_base(pvt) <= sys_addr &&
2667 sys_addr < BIT_64(32)) {
2668 amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
2669 sys_addr);
2670 return -EINVAL;
2671 }
2672
2673 /* Verify sys_addr is within DCT Range. */
2674 dct_base = (u64) dct_sel_baseaddr(pvt);
2675 dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF;
2676
2677 if (!(dct_cont_base_reg & BIT(0)) &&
2678 !(dct_base <= (sys_addr >> 27) &&
2679 dct_limit >= (sys_addr >> 27)))
2680 return -EINVAL;
2681
2682 /* Verify number of dct's that participate in channel interleaving. */
2683 num_dcts_intlv = (int) hweight8(intlv_en);
2684
2685 if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4))
2686 return -EINVAL;
2687
2688 if (pvt->model >= 0x60)
2689 channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en);
2690 else
2691 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
2692 num_dcts_intlv, dct_sel);
2693
2694 /* Verify we stay within the MAX number of channels allowed */
2695 if (channel > 3)
2696 return -EINVAL;
2697
2698 leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0));
2699
2700 /* Get normalized DCT addr */
2701 if (leg_mmio_hole && (sys_addr >= BIT_64(32)))
2702 chan_offset = dhar_offset;
2703 else
2704 chan_offset = dct_base << 27;
2705
2706 chan_addr = sys_addr - chan_offset;
2707
2708 /* remove channel interleave */
2709 if (num_dcts_intlv == 2) {
2710 if (intlv_addr == 0x4)
2711 chan_addr = ((chan_addr >> 9) << 8) |
2712 (chan_addr & 0xff);
2713 else if (intlv_addr == 0x5)
2714 chan_addr = ((chan_addr >> 10) << 9) |
2715 (chan_addr & 0x1ff);
2716 else
2717 return -EINVAL;
2718
2719 } else if (num_dcts_intlv == 4) {
2720 if (intlv_addr == 0x4)
2721 chan_addr = ((chan_addr >> 10) << 8) |
2722 (chan_addr & 0xff);
2723 else if (intlv_addr == 0x5)
2724 chan_addr = ((chan_addr >> 11) << 9) |
2725 (chan_addr & 0x1ff);
2726 else
2727 return -EINVAL;
2728 }
2729
2730 if (dct_offset_en) {
2731 amd64_read_pci_cfg(pvt->F1,
2732 DRAM_CONT_HIGH_OFF + (int) channel * 4,
2733 &tmp);
2734 chan_addr += (u64) ((tmp >> 11) & 0xfff) << 27;
2735 }
2736
2737 f15h_select_dct(pvt, channel);
2738
2739 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
2740
2741 /*
2742 * Find Chip select:
2743 * if channel = 3, then alias it to 1. This is because, in F15 M30h,
2744 * there is support for 4 DCT's, but only 2 are currently functional.
2745 * They are DCT0 and DCT3. But we have read all registers of DCT3 into
2746 * pvt->csels[1]. So we need to use '1' here to get correct info.
2747 * Refer F15 M30h BKDG Section 2.10 and 2.10.3 for clarifications.
2748 */
2749 alias_channel = (channel == 3) ? 1 : channel;
2750
2751 cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, alias_channel);
2752
2753 if (cs_found >= 0)
2754 *chan_sel = alias_channel;
2755
2756 return cs_found;
2757}
2758
2759static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt,
2760 u64 sys_addr,
2761 int *chan_sel)
2762{
2763 int cs_found = -EINVAL;
2764 unsigned range;
2765
2766 for (range = 0; range < DRAM_RANGES; range++) {
2767 if (!dram_rw(pvt, range))
2768 continue;
2769
2770 if (pvt->fam == 0x15 && pvt->model >= 0x30)
2771 cs_found = f15_m30h_match_to_this_node(pvt, range,
2772 sys_addr,
2773 chan_sel);
2774
2775 else if ((get_dram_base(pvt, range) <= sys_addr) &&
2776 (get_dram_limit(pvt, range) >= sys_addr)) {
2777 cs_found = f1x_match_to_this_node(pvt, range,
2778 sys_addr, chan_sel);
2779 if (cs_found >= 0)
2780 break;
2781 }
2782 }
2783 return cs_found;
2784}
2785
2786/*
2787 * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
2788 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
2789 *
2790 * The @sys_addr is usually an error address received from the hardware
2791 * (MCX_ADDR).
2792 */
2793static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
2794 struct err_info *err)
2795{
2796 struct amd64_pvt *pvt = mci->pvt_info;
2797
2798 error_address_to_page_and_offset(sys_addr, err);
2799
2800 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
2801 if (err->csrow < 0) {
2802 err->err_code = ERR_CSROW;
2803 return;
2804 }
2805
2806 /*
2807 * We need the syndromes for channel detection only when we're
2808 * ganged. Otherwise @chan should already contain the channel at
2809 * this point.
2810 */
2811 if (dct_ganging_enabled(pvt))
2812 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
2813}
2814
2815/*
2816 * These are tables of eigenvectors (one per line) which can be used for the
2817 * construction of the syndrome tables. The modified syndrome search algorithm
2818 * uses those to find the symbol in error and thus the DIMM.
2819 *
2820 * Algorithm courtesy of Ross LaFetra from AMD.
2821 */
2822static const u16 x4_vectors[] = {
2823 0x2f57, 0x1afe, 0x66cc, 0xdd88,
2824 0x11eb, 0x3396, 0x7f4c, 0xeac8,
2825 0x0001, 0x0002, 0x0004, 0x0008,
2826 0x1013, 0x3032, 0x4044, 0x8088,
2827 0x106b, 0x30d6, 0x70fc, 0xe0a8,
2828 0x4857, 0xc4fe, 0x13cc, 0x3288,
2829 0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
2830 0x1f39, 0x251e, 0xbd6c, 0x6bd8,
2831 0x15c1, 0x2a42, 0x89ac, 0x4758,
2832 0x2b03, 0x1602, 0x4f0c, 0xca08,
2833 0x1f07, 0x3a0e, 0x6b04, 0xbd08,
2834 0x8ba7, 0x465e, 0x244c, 0x1cc8,
2835 0x2b87, 0x164e, 0x642c, 0xdc18,
2836 0x40b9, 0x80de, 0x1094, 0x20e8,
2837 0x27db, 0x1eb6, 0x9dac, 0x7b58,
2838 0x11c1, 0x2242, 0x84ac, 0x4c58,
2839 0x1be5, 0x2d7a, 0x5e34, 0xa718,
2840 0x4b39, 0x8d1e, 0x14b4, 0x28d8,
2841 0x4c97, 0xc87e, 0x11fc, 0x33a8,
2842 0x8e97, 0x497e, 0x2ffc, 0x1aa8,
2843 0x16b3, 0x3d62, 0x4f34, 0x8518,
2844 0x1e2f, 0x391a, 0x5cac, 0xf858,
2845 0x1d9f, 0x3b7a, 0x572c, 0xfe18,
2846 0x15f5, 0x2a5a, 0x5264, 0xa3b8,
2847 0x1dbb, 0x3b66, 0x715c, 0xe3f8,
2848 0x4397, 0xc27e, 0x17fc, 0x3ea8,
2849 0x1617, 0x3d3e, 0x6464, 0xb8b8,
2850 0x23ff, 0x12aa, 0xab6c, 0x56d8,
2851 0x2dfb, 0x1ba6, 0x913c, 0x7328,
2852 0x185d, 0x2ca6, 0x7914, 0x9e28,
2853 0x171b, 0x3e36, 0x7d7c, 0xebe8,
2854 0x4199, 0x82ee, 0x19f4, 0x2e58,
2855 0x4807, 0xc40e, 0x130c, 0x3208,
2856 0x1905, 0x2e0a, 0x5804, 0xac08,
2857 0x213f, 0x132a, 0xadfc, 0x5ba8,
2858 0x19a9, 0x2efe, 0xb5cc, 0x6f88,
2859};
2860
2861static const u16 x8_vectors[] = {
2862 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
2863 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
2864 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
2865 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
2866 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
2867 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
2868 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
2869 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
2870 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
2871 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
2872 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
2873 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
2874 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
2875 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
2876 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
2877 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
2878 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
2879 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2880 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
2881};
2882
2883static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs,
2884 unsigned v_dim)
2885{
2886 unsigned int i, err_sym;
2887
2888 for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
2889 u16 s = syndrome;
2890 unsigned v_idx = err_sym * v_dim;
2891 unsigned v_end = (err_sym + 1) * v_dim;
2892
2893 /* walk over all 16 bits of the syndrome */
2894 for (i = 1; i < (1U << 16); i <<= 1) {
2895
2896 /* if bit is set in that eigenvector... */
2897 if (v_idx < v_end && vectors[v_idx] & i) {
2898 u16 ev_comp = vectors[v_idx++];
2899
2900 /* ... and bit set in the modified syndrome, */
2901 if (s & i) {
2902 /* remove it. */
2903 s ^= ev_comp;
2904
2905 if (!s)
2906 return err_sym;
2907 }
2908
2909 } else if (s & i)
2910 /* can't get to zero, move to next symbol */
2911 break;
2912 }
2913 }
2914
2915 edac_dbg(0, "syndrome(%x) not found\n", syndrome);
2916 return -1;
2917}
2918
2919static int map_err_sym_to_channel(int err_sym, int sym_size)
2920{
2921 if (sym_size == 4)
2922 switch (err_sym) {
2923 case 0x20:
2924 case 0x21:
2925 return 0;
2926 case 0x22:
2927 case 0x23:
2928 return 1;
2929 default:
2930 return err_sym >> 4;
2931 }
2932 /* x8 symbols */
2933 else
2934 switch (err_sym) {
2935 /* imaginary bits not in a DIMM */
2936 case 0x10:
2937 WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
2938 err_sym);
2939 return -1;
2940 case 0x11:
2941 return 0;
2942 case 0x12:
2943 return 1;
2944 default:
2945 return err_sym >> 3;
2946 }
2947 return -1;
2948}
2949
2950static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
2951{
2952 struct amd64_pvt *pvt = mci->pvt_info;
2953 int err_sym = -1;
2954
2955 if (pvt->ecc_sym_sz == 8)
2956 err_sym = decode_syndrome(syndrome, x8_vectors,
2957 ARRAY_SIZE(x8_vectors),
2958 pvt->ecc_sym_sz);
2959 else if (pvt->ecc_sym_sz == 4)
2960 err_sym = decode_syndrome(syndrome, x4_vectors,
2961 ARRAY_SIZE(x4_vectors),
2962 pvt->ecc_sym_sz);
2963 else {
2964 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
2965 return err_sym;
2966 }
2967
2968 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
2969}
2970
2971static void __log_ecc_error(struct mem_ctl_info *mci, struct err_info *err,
2972 u8 ecc_type)
2973{
2974 enum hw_event_mc_err_type err_type;
2975 const char *string;
2976
2977 if (ecc_type == 2)
2978 err_type = HW_EVENT_ERR_CORRECTED;
2979 else if (ecc_type == 1)
2980 err_type = HW_EVENT_ERR_UNCORRECTED;
2981 else if (ecc_type == 3)
2982 err_type = HW_EVENT_ERR_DEFERRED;
2983 else {
2984 WARN(1, "Something is rotten in the state of Denmark.\n");
2985 return;
2986 }
2987
2988 switch (err->err_code) {
2989 case DECODE_OK:
2990 string = "";
2991 break;
2992 case ERR_NODE:
2993 string = "Failed to map error addr to a node";
2994 break;
2995 case ERR_CSROW:
2996 string = "Failed to map error addr to a csrow";
2997 break;
2998 case ERR_CHANNEL:
2999 string = "Unknown syndrome - possible error reporting race";
3000 break;
3001 case ERR_SYND:
3002 string = "MCA_SYND not valid - unknown syndrome and csrow";
3003 break;
3004 case ERR_NORM_ADDR:
3005 string = "Cannot decode normalized address";
3006 break;
3007 default:
3008 string = "WTF error";
3009 break;
3010 }
3011
3012 edac_mc_handle_error(err_type, mci, 1,
3013 err->page, err->offset, err->syndrome,
3014 err->csrow, err->channel, -1,
3015 string, "");
3016}
3017
3018static inline void decode_bus_error(int node_id, struct mce *m)
3019{
3020 struct mem_ctl_info *mci;
3021 struct amd64_pvt *pvt;
3022 u8 ecc_type = (m->status >> 45) & 0x3;
3023 u8 xec = XEC(m->status, 0x1f);
3024 u16 ec = EC(m->status);
3025 u64 sys_addr;
3026 struct err_info err;
3027
3028 mci = edac_mc_find(node_id);
3029 if (!mci)
3030 return;
3031
3032 pvt = mci->pvt_info;
3033
3034 /* Bail out early if this was an 'observed' error */
3035 if (PP(ec) == NBSL_PP_OBS)
3036 return;
3037
3038 /* Do only ECC errors */
3039 if (xec && xec != F10_NBSL_EXT_ERR_ECC)
3040 return;
3041
3042 memset(&err, 0, sizeof(err));
3043
3044 sys_addr = get_error_address(pvt, m);
3045
3046 if (ecc_type == 2)
3047 err.syndrome = extract_syndrome(m->status);
3048
3049 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);
3050
3051 __log_ecc_error(mci, &err, ecc_type);
3052}
3053
3054/*
3055 * To find the UMC channel represented by this bank we need to match on its
3056 * instance_id. The instance_id of a bank is held in the lower 32 bits of its
3057 * IPID.
3058 *
3059 * Currently, we can derive the channel number by looking at the 6th nibble in
3060 * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel
3061 * number.
3062 *
3063 * For DRAM ECC errors, the Chip Select number is given in bits [2:0] of
3064 * the MCA_SYND[ErrorInformation] field.
3065 */
3066static void umc_get_err_info(struct mce *m, struct err_info *err)
3067{
3068 err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
3069 err->csrow = m->synd & 0x7;
3070}
3071
3072static void decode_umc_error(int node_id, struct mce *m)
3073{
3074 u8 ecc_type = (m->status >> 45) & 0x3;
3075 struct mem_ctl_info *mci;
3076 struct amd64_pvt *pvt;
3077 struct err_info err;
3078 u64 sys_addr;
3079
3080 node_id = fixup_node_id(node_id, m);
3081
3082 mci = edac_mc_find(node_id);
3083 if (!mci)
3084 return;
3085
3086 pvt = mci->pvt_info;
3087
3088 memset(&err, 0, sizeof(err));
3089
3090 if (m->status & MCI_STATUS_DEFERRED)
3091 ecc_type = 3;
3092
3093 if (!(m->status & MCI_STATUS_SYNDV)) {
3094 err.err_code = ERR_SYND;
3095 goto log_error;
3096 }
3097
3098 if (ecc_type == 2) {
3099 u8 length = (m->synd >> 18) & 0x3f;
3100
3101 if (length)
3102 err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0);
3103 else
3104 err.err_code = ERR_CHANNEL;
3105 }
3106
3107 pvt->ops->get_err_info(m, &err);
3108
3109 if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) {
3110 err.err_code = ERR_NORM_ADDR;
3111 goto log_error;
3112 }
3113
3114 error_address_to_page_and_offset(sys_addr, &err);
3115
3116log_error:
3117 __log_ecc_error(mci, &err, ecc_type);
3118}
3119
3120/*
3121 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
3122 * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
3123 */
3124static int
3125reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
3126{
3127 /* Reserve the ADDRESS MAP Device */
3128 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
3129 if (!pvt->F1) {
3130 edac_dbg(1, "F1 not found: device 0x%x\n", pci_id1);
3131 return -ENODEV;
3132 }
3133
3134 /* Reserve the DCT Device */
3135 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
3136 if (!pvt->F2) {
3137 pci_dev_put(pvt->F1);
3138 pvt->F1 = NULL;
3139
3140 edac_dbg(1, "F2 not found: device 0x%x\n", pci_id2);
3141 return -ENODEV;
3142 }
3143
3144 if (!pci_ctl_dev)
3145 pci_ctl_dev = &pvt->F2->dev;
3146
3147 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
3148 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
3149 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
3150
3151 return 0;
3152}
3153
3154static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
3155{
3156 pvt->ecc_sym_sz = 4;
3157
3158 if (pvt->fam >= 0x10) {
3159 u32 tmp;
3160
3161 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
3162 /* F16h has only DCT0, so no need to read dbam1. */
3163 if (pvt->fam != 0x16)
3164 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1);
3165
3166 /* F10h, revD and later can do x8 ECC too. */
3167 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))
3168 pvt->ecc_sym_sz = 8;
3169 }
3170}
3171
3172/*
3173 * Retrieve the hardware registers of the memory controller.
3174 */
3175static void umc_read_mc_regs(struct amd64_pvt *pvt)
3176{
3177 u8 nid = pvt->mc_node_id;
3178 struct amd64_umc *umc;
3179 u32 i, umc_base;
3180
3181 /* Read registers from each UMC */
3182 for_each_umc(i) {
3183
3184 umc_base = get_umc_base(i);
3185 umc = &pvt->umc[i];
3186
3187 amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &umc->dimm_cfg);
3188 amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
3189 amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
3190 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
3191 amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);
3192 }
3193}
3194
3195/*
3196 * Retrieve the hardware registers of the memory controller (this includes the
3197 * 'Address Map' and 'Misc' device regs)
3198 */
3199static void dct_read_mc_regs(struct amd64_pvt *pvt)
3200{
3201 unsigned int range;
3202 u64 msr_val;
3203
3204 /*
3205 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
3206 * those are Read-As-Zero.
3207 */
3208 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
3209 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
3210
3211 /* Check first whether TOP_MEM2 is enabled: */
3212 rdmsrl(MSR_AMD64_SYSCFG, msr_val);
3213 if (msr_val & BIT(21)) {
3214 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
3215 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
3216 } else {
3217 edac_dbg(0, " TOP_MEM2 disabled\n");
3218 }
3219
3220 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
3221
3222 read_dram_ctl_register(pvt);
3223
3224 for (range = 0; range < DRAM_RANGES; range++) {
3225 u8 rw;
3226
3227 /* read settings for this DRAM range */
3228 read_dram_base_limit_regs(pvt, range);
3229
3230 rw = dram_rw(pvt, range);
3231 if (!rw)
3232 continue;
3233
3234 edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
3235 range,
3236 get_dram_base(pvt, range),
3237 get_dram_limit(pvt, range));
3238
3239 edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
3240 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
3241 (rw & 0x1) ? "R" : "-",
3242 (rw & 0x2) ? "W" : "-",
3243 dram_intlv_sel(pvt, range),
3244 dram_dst_node(pvt, range));
3245 }
3246
3247 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
3248 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0);
3249
3250 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
3251
3252 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0);
3253 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0);
3254
3255 if (!dct_ganging_enabled(pvt)) {
3256 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1);
3257 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
3258 }
3259
3260 determine_ecc_sym_sz(pvt);
3261}
3262
3263/*
3264 * NOTE: CPU Revision Dependent code
3265 *
3266 * Input:
3267 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
3268 * k8 private pointer to -->
3269 * DRAM Bank Address mapping register
3270 * node_id
3271 * DCL register where dual_channel_active is
3272 *
3273 * The DBAM register consists of 4 sets of 4 bits each definitions:
3274 *
3275 * Bits: CSROWs
3276 * 0-3 CSROWs 0 and 1
3277 * 4-7 CSROWs 2 and 3
3278 * 8-11 CSROWs 4 and 5
3279 * 12-15 CSROWs 6 and 7
3280 *
3281 * Values range from: 0 to 15
3282 * The meaning of the values depends on CPU revision and dual-channel state,
3283 * see relevant BKDG more info.
3284 *
3285 * The memory controller provides for total of only 8 CSROWs in its current
3286 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
3287 * single channel or two (2) DIMMs in dual channel mode.
3288 *
3289 * The following code logic collapses the various tables for CSROW based on CPU
3290 * revision.
3291 *
3292 * Returns:
3293 * The number of PAGE_SIZE pages on the specified CSROW number it
3294 * encompasses
3295 *
3296 */
3297static u32 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
3298{
3299 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
3300 u32 cs_mode, nr_pages;
3301
3302 csrow_nr >>= 1;
3303 cs_mode = DBAM_DIMM(csrow_nr, dbam);
3304
3305 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
3306 nr_pages <<= 20 - PAGE_SHIFT;
3307
3308 edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
3309 csrow_nr, dct, cs_mode);
3310 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3311
3312 return nr_pages;
3313}
3314
3315static u32 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig)
3316{
3317 int csrow_nr = csrow_nr_orig;
3318 u32 cs_mode, nr_pages;
3319
3320 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt);
3321
3322 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);
3323 nr_pages <<= 20 - PAGE_SHIFT;
3324
3325 edac_dbg(0, "csrow: %d, channel: %d, cs_mode %d\n",
3326 csrow_nr_orig, dct, cs_mode);
3327 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3328
3329 return nr_pages;
3330}
3331
3332static void umc_init_csrows(struct mem_ctl_info *mci)
3333{
3334 struct amd64_pvt *pvt = mci->pvt_info;
3335 enum edac_type edac_mode = EDAC_NONE;
3336 enum dev_type dev_type = DEV_UNKNOWN;
3337 struct dimm_info *dimm;
3338 u8 umc, cs;
3339
3340 if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) {
3341 edac_mode = EDAC_S16ECD16ED;
3342 dev_type = DEV_X16;
3343 } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) {
3344 edac_mode = EDAC_S8ECD8ED;
3345 dev_type = DEV_X8;
3346 } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) {
3347 edac_mode = EDAC_S4ECD4ED;
3348 dev_type = DEV_X4;
3349 } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) {
3350 edac_mode = EDAC_SECDED;
3351 }
3352
3353 for_each_umc(umc) {
3354 for_each_chip_select(cs, umc, pvt) {
3355 if (!csrow_enabled(cs, umc, pvt))
3356 continue;
3357
3358 dimm = mci->csrows[cs]->channels[umc]->dimm;
3359
3360 edac_dbg(1, "MC node: %d, csrow: %d\n",
3361 pvt->mc_node_id, cs);
3362
3363 dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs);
3364 dimm->mtype = pvt->umc[umc].dram_type;
3365 dimm->edac_mode = edac_mode;
3366 dimm->dtype = dev_type;
3367 dimm->grain = 64;
3368 }
3369 }
3370}
3371
3372/*
3373 * Initialize the array of csrow attribute instances, based on the values
3374 * from pci config hardware registers.
3375 */
3376static void dct_init_csrows(struct mem_ctl_info *mci)
3377{
3378 struct amd64_pvt *pvt = mci->pvt_info;
3379 enum edac_type edac_mode = EDAC_NONE;
3380 struct csrow_info *csrow;
3381 struct dimm_info *dimm;
3382 int nr_pages = 0;
3383 int i, j;
3384 u32 val;
3385
3386 amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
3387
3388 pvt->nbcfg = val;
3389
3390 edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
3391 pvt->mc_node_id, val,
3392 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
3393
3394 /*
3395 * We iterate over DCT0 here but we look at DCT1 in parallel, if needed.
3396 */
3397 for_each_chip_select(i, 0, pvt) {
3398 bool row_dct0 = !!csrow_enabled(i, 0, pvt);
3399 bool row_dct1 = false;
3400
3401 if (pvt->fam != 0xf)
3402 row_dct1 = !!csrow_enabled(i, 1, pvt);
3403
3404 if (!row_dct0 && !row_dct1)
3405 continue;
3406
3407 csrow = mci->csrows[i];
3408
3409 edac_dbg(1, "MC node: %d, csrow: %d\n",
3410 pvt->mc_node_id, i);
3411
3412 if (row_dct0) {
3413 nr_pages = dct_get_csrow_nr_pages(pvt, 0, i);
3414 csrow->channels[0]->dimm->nr_pages = nr_pages;
3415 }
3416
3417 /* K8 has only one DCT */
3418 if (pvt->fam != 0xf && row_dct1) {
3419 int row_dct1_pages = dct_get_csrow_nr_pages(pvt, 1, i);
3420
3421 csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
3422 nr_pages += row_dct1_pages;
3423 }
3424
3425 edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
3426
3427 /* Determine DIMM ECC mode: */
3428 if (pvt->nbcfg & NBCFG_ECC_ENABLE) {
3429 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL)
3430 ? EDAC_S4ECD4ED
3431 : EDAC_SECDED;
3432 }
3433
3434 for (j = 0; j < pvt->max_mcs; j++) {
3435 dimm = csrow->channels[j]->dimm;
3436 dimm->mtype = pvt->dram_type;
3437 dimm->edac_mode = edac_mode;
3438 dimm->grain = 64;
3439 }
3440 }
3441}
3442
3443/* get all cores on this DCT */
3444static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
3445{
3446 int cpu;
3447
3448 for_each_online_cpu(cpu)
3449 if (topology_die_id(cpu) == nid)
3450 cpumask_set_cpu(cpu, mask);
3451}
3452
3453/* check MCG_CTL on all the cpus on this node */
3454static bool nb_mce_bank_enabled_on_node(u16 nid)
3455{
3456 cpumask_var_t mask;
3457 int cpu, nbe;
3458 bool ret = false;
3459
3460 if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
3461 amd64_warn("%s: Error allocating mask\n", __func__);
3462 return false;
3463 }
3464
3465 get_cpus_on_this_dct_cpumask(mask, nid);
3466
3467 rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);
3468
3469 for_each_cpu(cpu, mask) {
3470 struct msr *reg = per_cpu_ptr(msrs, cpu);
3471 nbe = reg->l & MSR_MCGCTL_NBE;
3472
3473 edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
3474 cpu, reg->q,
3475 (nbe ? "enabled" : "disabled"));
3476
3477 if (!nbe)
3478 goto out;
3479 }
3480 ret = true;
3481
3482out:
3483 free_cpumask_var(mask);
3484 return ret;
3485}
3486
3487static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on)
3488{
3489 cpumask_var_t cmask;
3490 int cpu;
3491
3492 if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
3493 amd64_warn("%s: error allocating mask\n", __func__);
3494 return -ENOMEM;
3495 }
3496
3497 get_cpus_on_this_dct_cpumask(cmask, nid);
3498
3499 rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
3500
3501 for_each_cpu(cpu, cmask) {
3502
3503 struct msr *reg = per_cpu_ptr(msrs, cpu);
3504
3505 if (on) {
3506 if (reg->l & MSR_MCGCTL_NBE)
3507 s->flags.nb_mce_enable = 1;
3508
3509 reg->l |= MSR_MCGCTL_NBE;
3510 } else {
3511 /*
3512 * Turn off NB MCE reporting only when it was off before
3513 */
3514 if (!s->flags.nb_mce_enable)
3515 reg->l &= ~MSR_MCGCTL_NBE;
3516 }
3517 }
3518 wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
3519
3520 free_cpumask_var(cmask);
3521
3522 return 0;
3523}
3524
3525static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid,
3526 struct pci_dev *F3)
3527{
3528 bool ret = true;
3529 u32 value, mask = 0x3; /* UECC/CECC enable */
3530
3531 if (toggle_ecc_err_reporting(s, nid, ON)) {
3532 amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
3533 return false;
3534 }
3535
3536 amd64_read_pci_cfg(F3, NBCTL, &value);
3537
3538 s->old_nbctl = value & mask;
3539 s->nbctl_valid = true;
3540
3541 value |= mask;
3542 amd64_write_pci_cfg(F3, NBCTL, value);
3543
3544 amd64_read_pci_cfg(F3, NBCFG, &value);
3545
3546 edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
3547 nid, value, !!(value & NBCFG_ECC_ENABLE));
3548
3549 if (!(value & NBCFG_ECC_ENABLE)) {
3550 amd64_warn("DRAM ECC disabled on this node, enabling...\n");
3551
3552 s->flags.nb_ecc_prev = 0;
3553
3554 /* Attempt to turn on DRAM ECC Enable */
3555 value |= NBCFG_ECC_ENABLE;
3556 amd64_write_pci_cfg(F3, NBCFG, value);
3557
3558 amd64_read_pci_cfg(F3, NBCFG, &value);
3559
3560 if (!(value & NBCFG_ECC_ENABLE)) {
3561 amd64_warn("Hardware rejected DRAM ECC enable,"
3562 "check memory DIMM configuration.\n");
3563 ret = false;
3564 } else {
3565 amd64_info("Hardware accepted DRAM ECC Enable\n");
3566 }
3567 } else {
3568 s->flags.nb_ecc_prev = 1;
3569 }
3570
3571 edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
3572 nid, value, !!(value & NBCFG_ECC_ENABLE));
3573
3574 return ret;
3575}
3576
3577static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
3578 struct pci_dev *F3)
3579{
3580 u32 value, mask = 0x3; /* UECC/CECC enable */
3581
3582 if (!s->nbctl_valid)
3583 return;
3584
3585 amd64_read_pci_cfg(F3, NBCTL, &value);
3586 value &= ~mask;
3587 value |= s->old_nbctl;
3588
3589 amd64_write_pci_cfg(F3, NBCTL, value);
3590
3591 /* restore previous BIOS DRAM ECC "off" setting we force-enabled */
3592 if (!s->flags.nb_ecc_prev) {
3593 amd64_read_pci_cfg(F3, NBCFG, &value);
3594 value &= ~NBCFG_ECC_ENABLE;
3595 amd64_write_pci_cfg(F3, NBCFG, value);
3596 }
3597
3598 /* restore the NB Enable MCGCTL bit */
3599 if (toggle_ecc_err_reporting(s, nid, OFF))
3600 amd64_warn("Error restoring NB MCGCTL settings!\n");
3601}
3602
3603static bool dct_ecc_enabled(struct amd64_pvt *pvt)
3604{
3605 u16 nid = pvt->mc_node_id;
3606 bool nb_mce_en = false;
3607 u8 ecc_en = 0;
3608 u32 value;
3609
3610 amd64_read_pci_cfg(pvt->F3, NBCFG, &value);
3611
3612 ecc_en = !!(value & NBCFG_ECC_ENABLE);
3613
3614 nb_mce_en = nb_mce_bank_enabled_on_node(nid);
3615 if (!nb_mce_en)
3616 edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
3617 MSR_IA32_MCG_CTL, nid);
3618
3619 edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));
3620
3621 if (!ecc_en || !nb_mce_en)
3622 return false;
3623 else
3624 return true;
3625}
3626
3627static bool umc_ecc_enabled(struct amd64_pvt *pvt)
3628{
3629 u8 umc_en_mask = 0, ecc_en_mask = 0;
3630 u16 nid = pvt->mc_node_id;
3631 struct amd64_umc *umc;
3632 u8 ecc_en = 0, i;
3633
3634 for_each_umc(i) {
3635 umc = &pvt->umc[i];
3636
3637 /* Only check enabled UMCs. */
3638 if (!(umc->sdp_ctrl & UMC_SDP_INIT))
3639 continue;
3640
3641 umc_en_mask |= BIT(i);
3642
3643 if (umc->umc_cap_hi & UMC_ECC_ENABLED)
3644 ecc_en_mask |= BIT(i);
3645 }
3646
3647 /* Check whether at least one UMC is enabled: */
3648 if (umc_en_mask)
3649 ecc_en = umc_en_mask == ecc_en_mask;
3650 else
3651 edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);
3652
3653 edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));
3654
3655 if (!ecc_en)
3656 return false;
3657 else
3658 return true;
3659}
3660
3661static inline void
3662umc_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
3663{
3664 u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1;
3665
3666 for_each_umc(i) {
3667 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
3668 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);
3669 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);
3670
3671 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6));
3672 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));
3673 }
3674 }
3675
3676 /* Set chipkill only if ECC is enabled: */
3677 if (ecc_en) {
3678 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
3679
3680 if (!cpk_en)
3681 return;
3682
3683 if (dev_x4)
3684 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
3685 else if (dev_x16)
3686 mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED;
3687 else
3688 mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED;
3689 }
3690}
3691
3692static void dct_setup_mci_misc_attrs(struct mem_ctl_info *mci)
3693{
3694 struct amd64_pvt *pvt = mci->pvt_info;
3695
3696 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
3697 mci->edac_ctl_cap = EDAC_FLAG_NONE;
3698
3699 if (pvt->nbcap & NBCAP_SECDED)
3700 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
3701
3702 if (pvt->nbcap & NBCAP_CHIPKILL)
3703 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
3704
3705 mci->edac_cap = dct_determine_edac_cap(pvt);
3706 mci->mod_name = EDAC_MOD_STR;
3707 mci->ctl_name = pvt->ctl_name;
3708 mci->dev_name = pci_name(pvt->F3);
3709 mci->ctl_page_to_phys = NULL;
3710
3711 /* memory scrubber interface */
3712 mci->set_sdram_scrub_rate = set_scrub_rate;
3713 mci->get_sdram_scrub_rate = get_scrub_rate;
3714
3715 dct_init_csrows(mci);
3716}
3717
3718static void umc_setup_mci_misc_attrs(struct mem_ctl_info *mci)
3719{
3720 struct amd64_pvt *pvt = mci->pvt_info;
3721
3722 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
3723 mci->edac_ctl_cap = EDAC_FLAG_NONE;
3724
3725 umc_determine_edac_ctl_cap(mci, pvt);
3726
3727 mci->edac_cap = umc_determine_edac_cap(pvt);
3728 mci->mod_name = EDAC_MOD_STR;
3729 mci->ctl_name = pvt->ctl_name;
3730 mci->dev_name = pci_name(pvt->F3);
3731 mci->ctl_page_to_phys = NULL;
3732
3733 umc_init_csrows(mci);
3734}
3735
3736static int dct_hw_info_get(struct amd64_pvt *pvt)
3737{
3738 int ret = reserve_mc_sibling_devs(pvt, pvt->f1_id, pvt->f2_id);
3739
3740 if (ret)
3741 return ret;
3742
3743 dct_prep_chip_selects(pvt);
3744 dct_read_base_mask(pvt);
3745 dct_read_mc_regs(pvt);
3746 dct_determine_memory_type(pvt);
3747
3748 return 0;
3749}
3750
3751static int umc_hw_info_get(struct amd64_pvt *pvt)
3752{
3753 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);
3754 if (!pvt->umc)
3755 return -ENOMEM;
3756
3757 umc_prep_chip_selects(pvt);
3758 umc_read_base_mask(pvt);
3759 umc_read_mc_regs(pvt);
3760 umc_determine_memory_type(pvt);
3761
3762 return 0;
3763}
3764
3765/*
3766 * The CPUs have one channel per UMC, so UMC number is equivalent to a
3767 * channel number. The GPUs have 8 channels per UMC, so the UMC number no
3768 * longer works as a channel number.
3769 *
3770 * The channel number within a GPU UMC is given in MCA_IPID[15:12].
3771 * However, the IDs are split such that two UMC values go to one UMC, and
3772 * the channel numbers are split in two groups of four.
3773 *
3774 * Refer to comment on gpu_get_umc_base().
3775 *
3776 * For example,
3777 * UMC0 CH[3:0] = 0x0005[3:0]000
3778 * UMC0 CH[7:4] = 0x0015[3:0]000
3779 * UMC1 CH[3:0] = 0x0025[3:0]000
3780 * UMC1 CH[7:4] = 0x0035[3:0]000
3781 */
3782static void gpu_get_err_info(struct mce *m, struct err_info *err)
3783{
3784 u8 ch = (m->ipid & GENMASK(31, 0)) >> 20;
3785 u8 phy = ((m->ipid >> 12) & 0xf);
3786
3787 err->channel = ch % 2 ? phy + 4 : phy;
3788 err->csrow = phy;
3789}
3790
3791static int gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
3792 unsigned int cs_mode, int csrow_nr)
3793{
3794 u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr];
3795
3796 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, csrow_nr >> 1);
3797}
3798
3799static void gpu_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
3800{
3801 int size, cs_mode, cs = 0;
3802
3803 edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
3804
3805 cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY;
3806
3807 for_each_chip_select(cs, ctrl, pvt) {
3808 size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs);
3809 amd64_info(EDAC_MC ": %d: %5dMB\n", cs, size);
3810 }
3811}
3812
3813static void gpu_dump_misc_regs(struct amd64_pvt *pvt)
3814{
3815 struct amd64_umc *umc;
3816 u32 i;
3817
3818 for_each_umc(i) {
3819 umc = &pvt->umc[i];
3820
3821 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
3822 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
3823 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
3824 edac_dbg(1, "UMC%d All HBMs support ECC: yes\n", i);
3825
3826 gpu_debug_display_dimm_sizes(pvt, i);
3827 }
3828}
3829
3830static u32 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
3831{
3832 u32 nr_pages;
3833 int cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY;
3834
3835 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);
3836 nr_pages <<= 20 - PAGE_SHIFT;
3837
3838 edac_dbg(0, "csrow: %d, channel: %d\n", csrow_nr, dct);
3839 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3840
3841 return nr_pages;
3842}
3843
3844static void gpu_init_csrows(struct mem_ctl_info *mci)
3845{
3846 struct amd64_pvt *pvt = mci->pvt_info;
3847 struct dimm_info *dimm;
3848 u8 umc, cs;
3849
3850 for_each_umc(umc) {
3851 for_each_chip_select(cs, umc, pvt) {
3852 if (!csrow_enabled(cs, umc, pvt))
3853 continue;
3854
3855 dimm = mci->csrows[umc]->channels[cs]->dimm;
3856
3857 edac_dbg(1, "MC node: %d, csrow: %d\n",
3858 pvt->mc_node_id, cs);
3859
3860 dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs);
3861 dimm->edac_mode = EDAC_SECDED;
3862 dimm->mtype = pvt->dram_type;
3863 dimm->dtype = DEV_X16;
3864 dimm->grain = 64;
3865 }
3866 }
3867}
3868
3869static void gpu_setup_mci_misc_attrs(struct mem_ctl_info *mci)
3870{
3871 struct amd64_pvt *pvt = mci->pvt_info;
3872
3873 mci->mtype_cap = MEM_FLAG_HBM2;
3874 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
3875
3876 mci->edac_cap = EDAC_FLAG_EC;
3877 mci->mod_name = EDAC_MOD_STR;
3878 mci->ctl_name = pvt->ctl_name;
3879 mci->dev_name = pci_name(pvt->F3);
3880 mci->ctl_page_to_phys = NULL;
3881
3882 gpu_init_csrows(mci);
3883}
3884
3885/* ECC is enabled by default on GPU nodes */
3886static bool gpu_ecc_enabled(struct amd64_pvt *pvt)
3887{
3888 return true;
3889}
3890
3891static inline u32 gpu_get_umc_base(struct amd64_pvt *pvt, u8 umc, u8 channel)
3892{
3893 /*
3894 * On CPUs, there is one channel per UMC, so UMC numbering equals
3895 * channel numbering. On GPUs, there are eight channels per UMC,
3896 * so the channel numbering is different from UMC numbering.
3897 *
3898 * On CPU nodes channels are selected in 6th nibble
3899 * UMC chY[3:0]= [(chY*2 + 1) : (chY*2)]50000;
3900 *
3901 * On GPU nodes channels are selected in 3rd nibble
3902 * HBM chX[3:0]= [Y ]5X[3:0]000;
3903 * HBM chX[7:4]= [Y+1]5X[3:0]000
3904 *
3905 * On MI300 APU nodes, same as GPU nodes but channels are selected
3906 * in the base address of 0x90000
3907 */
3908 umc *= 2;
3909
3910 if (channel >= 4)
3911 umc++;
3912
3913 return pvt->gpu_umc_base + (umc << 20) + ((channel % 4) << 12);
3914}
3915
3916static void gpu_read_mc_regs(struct amd64_pvt *pvt)
3917{
3918 u8 nid = pvt->mc_node_id;
3919 struct amd64_umc *umc;
3920 u32 i, umc_base;
3921
3922 /* Read registers from each UMC */
3923 for_each_umc(i) {
3924 umc_base = gpu_get_umc_base(pvt, i, 0);
3925 umc = &pvt->umc[i];
3926
3927 amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
3928 amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
3929 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
3930 }
3931}
3932
3933static void gpu_read_base_mask(struct amd64_pvt *pvt)
3934{
3935 u32 base_reg, mask_reg;
3936 u32 *base, *mask;
3937 int umc, cs;
3938
3939 for_each_umc(umc) {
3940 for_each_chip_select(cs, umc, pvt) {
3941 base_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_BASE_ADDR;
3942 base = &pvt->csels[umc].csbases[cs];
3943
3944 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) {
3945 edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n",
3946 umc, cs, *base, base_reg);
3947 }
3948
3949 mask_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_ADDR_MASK;
3950 mask = &pvt->csels[umc].csmasks[cs];
3951
3952 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) {
3953 edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n",
3954 umc, cs, *mask, mask_reg);
3955 }
3956 }
3957 }
3958}
3959
3960static void gpu_prep_chip_selects(struct amd64_pvt *pvt)
3961{
3962 int umc;
3963
3964 for_each_umc(umc) {
3965 pvt->csels[umc].b_cnt = 8;
3966 pvt->csels[umc].m_cnt = 8;
3967 }
3968}
3969
3970static int gpu_hw_info_get(struct amd64_pvt *pvt)
3971{
3972 int ret;
3973
3974 ret = gpu_get_node_map(pvt);
3975 if (ret)
3976 return ret;
3977
3978 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);
3979 if (!pvt->umc)
3980 return -ENOMEM;
3981
3982 gpu_prep_chip_selects(pvt);
3983 gpu_read_base_mask(pvt);
3984 gpu_read_mc_regs(pvt);
3985
3986 return 0;
3987}
3988
3989static void hw_info_put(struct amd64_pvt *pvt)
3990{
3991 pci_dev_put(pvt->F1);
3992 pci_dev_put(pvt->F2);
3993 kfree(pvt->umc);
3994}
3995
3996static struct low_ops umc_ops = {
3997 .hw_info_get = umc_hw_info_get,
3998 .ecc_enabled = umc_ecc_enabled,
3999 .setup_mci_misc_attrs = umc_setup_mci_misc_attrs,
4000 .dump_misc_regs = umc_dump_misc_regs,
4001 .get_err_info = umc_get_err_info,
4002};
4003
4004static struct low_ops gpu_ops = {
4005 .hw_info_get = gpu_hw_info_get,
4006 .ecc_enabled = gpu_ecc_enabled,
4007 .setup_mci_misc_attrs = gpu_setup_mci_misc_attrs,
4008 .dump_misc_regs = gpu_dump_misc_regs,
4009 .get_err_info = gpu_get_err_info,
4010};
4011
4012/* Use Family 16h versions for defaults and adjust as needed below. */
4013static struct low_ops dct_ops = {
4014 .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
4015 .dbam_to_cs = f16_dbam_to_chip_select,
4016 .hw_info_get = dct_hw_info_get,
4017 .ecc_enabled = dct_ecc_enabled,
4018 .setup_mci_misc_attrs = dct_setup_mci_misc_attrs,
4019 .dump_misc_regs = dct_dump_misc_regs,
4020};
4021
4022static int per_family_init(struct amd64_pvt *pvt)
4023{
4024 pvt->ext_model = boot_cpu_data.x86_model >> 4;
4025 pvt->stepping = boot_cpu_data.x86_stepping;
4026 pvt->model = boot_cpu_data.x86_model;
4027 pvt->fam = boot_cpu_data.x86;
4028 pvt->max_mcs = 2;
4029
4030 /*
4031 * Decide on which ops group to use here and do any family/model
4032 * overrides below.
4033 */
4034 if (pvt->fam >= 0x17)
4035 pvt->ops = &umc_ops;
4036 else
4037 pvt->ops = &dct_ops;
4038
4039 switch (pvt->fam) {
4040 case 0xf:
4041 pvt->ctl_name = (pvt->ext_model >= K8_REV_F) ?
4042 "K8 revF or later" : "K8 revE or earlier";
4043 pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP;
4044 pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL;
4045 pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow;
4046 pvt->ops->dbam_to_cs = k8_dbam_to_chip_select;
4047 break;
4048
4049 case 0x10:
4050 pvt->ctl_name = "F10h";
4051 pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP;
4052 pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM;
4053 pvt->ops->dbam_to_cs = f10_dbam_to_chip_select;
4054 break;
4055
4056 case 0x15:
4057 switch (pvt->model) {
4058 case 0x30:
4059 pvt->ctl_name = "F15h_M30h";
4060 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1;
4061 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2;
4062 break;
4063 case 0x60:
4064 pvt->ctl_name = "F15h_M60h";
4065 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1;
4066 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2;
4067 pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select;
4068 break;
4069 case 0x13:
4070 /* Richland is only client */
4071 return -ENODEV;
4072 default:
4073 pvt->ctl_name = "F15h";
4074 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1;
4075 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2;
4076 pvt->ops->dbam_to_cs = f15_dbam_to_chip_select;
4077 break;
4078 }
4079 break;
4080
4081 case 0x16:
4082 switch (pvt->model) {
4083 case 0x30:
4084 pvt->ctl_name = "F16h_M30h";
4085 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1;
4086 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2;
4087 break;
4088 default:
4089 pvt->ctl_name = "F16h";
4090 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1;
4091 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2;
4092 break;
4093 }
4094 break;
4095
4096 case 0x17:
4097 switch (pvt->model) {
4098 case 0x10 ... 0x2f:
4099 pvt->ctl_name = "F17h_M10h";
4100 break;
4101 case 0x30 ... 0x3f:
4102 pvt->ctl_name = "F17h_M30h";
4103 pvt->max_mcs = 8;
4104 break;
4105 case 0x60 ... 0x6f:
4106 pvt->ctl_name = "F17h_M60h";
4107 break;
4108 case 0x70 ... 0x7f:
4109 pvt->ctl_name = "F17h_M70h";
4110 break;
4111 default:
4112 pvt->ctl_name = "F17h";
4113 break;
4114 }
4115 break;
4116
4117 case 0x18:
4118 pvt->ctl_name = "F18h";
4119 break;
4120
4121 case 0x19:
4122 switch (pvt->model) {
4123 case 0x00 ... 0x0f:
4124 pvt->ctl_name = "F19h";
4125 pvt->max_mcs = 8;
4126 break;
4127 case 0x10 ... 0x1f:
4128 pvt->ctl_name = "F19h_M10h";
4129 pvt->max_mcs = 12;
4130 pvt->flags.zn_regs_v2 = 1;
4131 break;
4132 case 0x20 ... 0x2f:
4133 pvt->ctl_name = "F19h_M20h";
4134 break;
4135 case 0x30 ... 0x3f:
4136 if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) {
4137 pvt->ctl_name = "MI200";
4138 pvt->max_mcs = 4;
4139 pvt->dram_type = MEM_HBM2;
4140 pvt->gpu_umc_base = 0x50000;
4141 pvt->ops = &gpu_ops;
4142 } else {
4143 pvt->ctl_name = "F19h_M30h";
4144 pvt->max_mcs = 8;
4145 }
4146 break;
4147 case 0x50 ... 0x5f:
4148 pvt->ctl_name = "F19h_M50h";
4149 break;
4150 case 0x60 ... 0x6f:
4151 pvt->ctl_name = "F19h_M60h";
4152 pvt->flags.zn_regs_v2 = 1;
4153 break;
4154 case 0x70 ... 0x7f:
4155 pvt->ctl_name = "F19h_M70h";
4156 pvt->flags.zn_regs_v2 = 1;
4157 break;
4158 case 0x90 ... 0x9f:
4159 pvt->ctl_name = "F19h_M90h";
4160 pvt->max_mcs = 4;
4161 pvt->dram_type = MEM_HBM3;
4162 pvt->gpu_umc_base = 0x90000;
4163 pvt->ops = &gpu_ops;
4164 break;
4165 case 0xa0 ... 0xaf:
4166 pvt->ctl_name = "F19h_MA0h";
4167 pvt->max_mcs = 12;
4168 pvt->flags.zn_regs_v2 = 1;
4169 break;
4170 }
4171 break;
4172
4173 case 0x1A:
4174 switch (pvt->model) {
4175 case 0x00 ... 0x1f:
4176 pvt->ctl_name = "F1Ah";
4177 pvt->max_mcs = 12;
4178 pvt->flags.zn_regs_v2 = 1;
4179 break;
4180 case 0x40 ... 0x4f:
4181 pvt->ctl_name = "F1Ah_M40h";
4182 pvt->flags.zn_regs_v2 = 1;
4183 break;
4184 }
4185 break;
4186
4187 default:
4188 amd64_err("Unsupported family!\n");
4189 return -ENODEV;
4190 }
4191
4192 return 0;
4193}
4194
4195static const struct attribute_group *amd64_edac_attr_groups[] = {
4196#ifdef CONFIG_EDAC_DEBUG
4197 &dbg_group,
4198 &inj_group,
4199#endif
4200 NULL
4201};
4202
4203/*
4204 * For heterogeneous and APU models EDAC CHIP_SELECT and CHANNEL layers
4205 * should be swapped to fit into the layers.
4206 */
4207static unsigned int get_layer_size(struct amd64_pvt *pvt, u8 layer)
4208{
4209 bool is_gpu = (pvt->ops == &gpu_ops);
4210
4211 if (!layer)
4212 return is_gpu ? pvt->max_mcs
4213 : pvt->csels[0].b_cnt;
4214 else
4215 return is_gpu ? pvt->csels[0].b_cnt
4216 : pvt->max_mcs;
4217}
4218
4219static int init_one_instance(struct amd64_pvt *pvt)
4220{
4221 struct mem_ctl_info *mci = NULL;
4222 struct edac_mc_layer layers[2];
4223 int ret = -ENOMEM;
4224
4225 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
4226 layers[0].size = get_layer_size(pvt, 0);
4227 layers[0].is_virt_csrow = true;
4228 layers[1].type = EDAC_MC_LAYER_CHANNEL;
4229 layers[1].size = get_layer_size(pvt, 1);
4230 layers[1].is_virt_csrow = false;
4231
4232 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0);
4233 if (!mci)
4234 return ret;
4235
4236 mci->pvt_info = pvt;
4237 mci->pdev = &pvt->F3->dev;
4238
4239 pvt->ops->setup_mci_misc_attrs(mci);
4240
4241 ret = -ENODEV;
4242 if (edac_mc_add_mc_with_groups(mci, amd64_edac_attr_groups)) {
4243 edac_dbg(1, "failed edac_mc_add_mc()\n");
4244 edac_mc_free(mci);
4245 return ret;
4246 }
4247
4248 return 0;
4249}
4250
4251static bool instance_has_memory(struct amd64_pvt *pvt)
4252{
4253 bool cs_enabled = false;
4254 int cs = 0, dct = 0;
4255
4256 for (dct = 0; dct < pvt->max_mcs; dct++) {
4257 for_each_chip_select(cs, dct, pvt)
4258 cs_enabled |= csrow_enabled(cs, dct, pvt);
4259 }
4260
4261 return cs_enabled;
4262}
4263
4264static int probe_one_instance(unsigned int nid)
4265{
4266 struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
4267 struct amd64_pvt *pvt = NULL;
4268 struct ecc_settings *s;
4269 int ret;
4270
4271 ret = -ENOMEM;
4272 s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
4273 if (!s)
4274 goto err_out;
4275
4276 ecc_stngs[nid] = s;
4277
4278 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
4279 if (!pvt)
4280 goto err_settings;
4281
4282 pvt->mc_node_id = nid;
4283 pvt->F3 = F3;
4284
4285 ret = per_family_init(pvt);
4286 if (ret < 0)
4287 goto err_enable;
4288
4289 ret = pvt->ops->hw_info_get(pvt);
4290 if (ret < 0)
4291 goto err_enable;
4292
4293 ret = 0;
4294 if (!instance_has_memory(pvt)) {
4295 amd64_info("Node %d: No DIMMs detected.\n", nid);
4296 goto err_enable;
4297 }
4298
4299 if (!pvt->ops->ecc_enabled(pvt)) {
4300 ret = -ENODEV;
4301
4302 if (!ecc_enable_override)
4303 goto err_enable;
4304
4305 if (boot_cpu_data.x86 >= 0x17) {
4306 amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS.");
4307 goto err_enable;
4308 } else
4309 amd64_warn("Forcing ECC on!\n");
4310
4311 if (!enable_ecc_error_reporting(s, nid, F3))
4312 goto err_enable;
4313 }
4314
4315 ret = init_one_instance(pvt);
4316 if (ret < 0) {
4317 amd64_err("Error probing instance: %d\n", nid);
4318
4319 if (boot_cpu_data.x86 < 0x17)
4320 restore_ecc_error_reporting(s, nid, F3);
4321
4322 goto err_enable;
4323 }
4324
4325 amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id);
4326
4327 /* Display and decode various registers for debug purposes. */
4328 pvt->ops->dump_misc_regs(pvt);
4329
4330 return ret;
4331
4332err_enable:
4333 hw_info_put(pvt);
4334 kfree(pvt);
4335
4336err_settings:
4337 kfree(s);
4338 ecc_stngs[nid] = NULL;
4339
4340err_out:
4341 return ret;
4342}
4343
4344static void remove_one_instance(unsigned int nid)
4345{
4346 struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
4347 struct ecc_settings *s = ecc_stngs[nid];
4348 struct mem_ctl_info *mci;
4349 struct amd64_pvt *pvt;
4350
4351 /* Remove from EDAC CORE tracking list */
4352 mci = edac_mc_del_mc(&F3->dev);
4353 if (!mci)
4354 return;
4355
4356 pvt = mci->pvt_info;
4357
4358 restore_ecc_error_reporting(s, nid, F3);
4359
4360 kfree(ecc_stngs[nid]);
4361 ecc_stngs[nid] = NULL;
4362
4363 /* Free the EDAC CORE resources */
4364 mci->pvt_info = NULL;
4365
4366 hw_info_put(pvt);
4367 kfree(pvt);
4368 edac_mc_free(mci);
4369}
4370
4371static void setup_pci_device(void)
4372{
4373 if (pci_ctl)
4374 return;
4375
4376 pci_ctl = edac_pci_create_generic_ctl(pci_ctl_dev, EDAC_MOD_STR);
4377 if (!pci_ctl) {
4378 pr_warn("%s(): Unable to create PCI control\n", __func__);
4379 pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
4380 }
4381}
4382
4383static const struct x86_cpu_id amd64_cpuids[] = {
4384 X86_MATCH_VENDOR_FAM(AMD, 0x0F, NULL),
4385 X86_MATCH_VENDOR_FAM(AMD, 0x10, NULL),
4386 X86_MATCH_VENDOR_FAM(AMD, 0x15, NULL),
4387 X86_MATCH_VENDOR_FAM(AMD, 0x16, NULL),
4388 X86_MATCH_VENDOR_FAM(AMD, 0x17, NULL),
4389 X86_MATCH_VENDOR_FAM(HYGON, 0x18, NULL),
4390 X86_MATCH_VENDOR_FAM(AMD, 0x19, NULL),
4391 X86_MATCH_VENDOR_FAM(AMD, 0x1A, NULL),
4392 { }
4393};
4394MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);
4395
4396static int __init amd64_edac_init(void)
4397{
4398 const char *owner;
4399 int err = -ENODEV;
4400 int i;
4401
4402 if (ghes_get_devices())
4403 return -EBUSY;
4404
4405 owner = edac_get_owner();
4406 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
4407 return -EBUSY;
4408
4409 if (!x86_match_cpu(amd64_cpuids))
4410 return -ENODEV;
4411
4412 if (!amd_nb_num())
4413 return -ENODEV;
4414
4415 opstate_init();
4416
4417 err = -ENOMEM;
4418 ecc_stngs = kcalloc(amd_nb_num(), sizeof(ecc_stngs[0]), GFP_KERNEL);
4419 if (!ecc_stngs)
4420 goto err_free;
4421
4422 msrs = msrs_alloc();
4423 if (!msrs)
4424 goto err_free;
4425
4426 for (i = 0; i < amd_nb_num(); i++) {
4427 err = probe_one_instance(i);
4428 if (err) {
4429 /* unwind properly */
4430 while (--i >= 0)
4431 remove_one_instance(i);
4432
4433 goto err_pci;
4434 }
4435 }
4436
4437 if (!edac_has_mcs()) {
4438 err = -ENODEV;
4439 goto err_pci;
4440 }
4441
4442 /* register stuff with EDAC MCE */
4443 if (boot_cpu_data.x86 >= 0x17) {
4444 amd_register_ecc_decoder(decode_umc_error);
4445 } else {
4446 amd_register_ecc_decoder(decode_bus_error);
4447 setup_pci_device();
4448 }
4449
4450#ifdef CONFIG_X86_32
4451 amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR);
4452#endif
4453
4454 return 0;
4455
4456err_pci:
4457 pci_ctl_dev = NULL;
4458
4459 msrs_free(msrs);
4460 msrs = NULL;
4461
4462err_free:
4463 kfree(ecc_stngs);
4464 ecc_stngs = NULL;
4465
4466 return err;
4467}
4468
4469static void __exit amd64_edac_exit(void)
4470{
4471 int i;
4472
4473 if (pci_ctl)
4474 edac_pci_release_generic_ctl(pci_ctl);
4475
4476 /* unregister from EDAC MCE */
4477 if (boot_cpu_data.x86 >= 0x17)
4478 amd_unregister_ecc_decoder(decode_umc_error);
4479 else
4480 amd_unregister_ecc_decoder(decode_bus_error);
4481
4482 for (i = 0; i < amd_nb_num(); i++)
4483 remove_one_instance(i);
4484
4485 kfree(ecc_stngs);
4486 ecc_stngs = NULL;
4487
4488 pci_ctl_dev = NULL;
4489
4490 msrs_free(msrs);
4491 msrs = NULL;
4492}
4493
4494module_init(amd64_edac_init);
4495module_exit(amd64_edac_exit);
4496
4497MODULE_LICENSE("GPL");
4498MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, Dave Peterson, Thayne Harbaugh; AMD");
4499MODULE_DESCRIPTION("MC support for AMD64 memory controllers");
4500
4501module_param(edac_op_state, int, 0444);
4502MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");