Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __KVM_X86_LAPIC_H
3#define __KVM_X86_LAPIC_H
4
5#include <kvm/iodev.h>
6
7#include <linux/kvm_host.h>
8
9#include "hyperv.h"
10#include "smm.h"
11
12#define KVM_APIC_INIT 0
13#define KVM_APIC_SIPI 1
14
15#define APIC_SHORT_MASK 0xc0000
16#define APIC_DEST_NOSHORT 0x0
17#define APIC_DEST_MASK 0x800
18
19#define APIC_BUS_CYCLE_NS_DEFAULT 1
20
21#define APIC_BROADCAST 0xFF
22#define X2APIC_BROADCAST 0xFFFFFFFFul
23
24enum lapic_mode {
25 LAPIC_MODE_DISABLED = 0,
26 LAPIC_MODE_INVALID = X2APIC_ENABLE,
27 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
28 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
29};
30
31enum lapic_lvt_entry {
32 LVT_TIMER,
33 LVT_THERMAL_MONITOR,
34 LVT_PERFORMANCE_COUNTER,
35 LVT_LINT0,
36 LVT_LINT1,
37 LVT_ERROR,
38 LVT_CMCI,
39
40 KVM_APIC_MAX_NR_LVT_ENTRIES,
41};
42
43#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
44
45struct kvm_timer {
46 struct hrtimer timer;
47 s64 period; /* unit: ns */
48 ktime_t target_expiration;
49 u32 timer_mode;
50 u32 timer_mode_mask;
51 u64 tscdeadline;
52 u64 expired_tscdeadline;
53 u32 timer_advance_ns;
54 atomic_t pending; /* accumulated triggered timers */
55 bool hv_timer_in_use;
56};
57
58struct kvm_lapic {
59 unsigned long base_address;
60 struct kvm_io_device dev;
61 struct kvm_timer lapic_timer;
62 u32 divide_count;
63 struct kvm_vcpu *vcpu;
64 bool apicv_active;
65 bool sw_enabled;
66 bool irr_pending;
67 bool lvt0_in_nmi_mode;
68 /* Number of bits set in ISR. */
69 s16 isr_count;
70 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
71 int highest_isr_cache;
72 /**
73 * APIC register page. The layout matches the register layout seen by
74 * the guest 1:1, because it is accessed by the vmx microcode.
75 * Note: Only one register, the TPR, is used by the microcode.
76 */
77 void *regs;
78 gpa_t vapic_addr;
79 struct gfn_to_hva_cache vapic_cache;
80 unsigned long pending_events;
81 unsigned int sipi_vector;
82 int nr_lvt_entries;
83};
84
85struct dest_map;
86
87int kvm_create_lapic(struct kvm_vcpu *vcpu);
88void kvm_free_lapic(struct kvm_vcpu *vcpu);
89
90int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
91void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector);
92int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
93int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
94void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
95u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
96void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
97void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
98void kvm_apic_set_version(struct kvm_vcpu *vcpu);
99void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
100bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
101 int shorthand, unsigned int dest, int dest_mode);
102int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
103void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
104bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
105bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
106void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
107int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
108 struct dest_map *dest_map);
109int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
110void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
111int kvm_alloc_apic_access_page(struct kvm *kvm);
112void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);
113
114bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
115 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
116void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
117
118int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated);
119int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
120int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
121void kvm_apic_update_hwapic_isr(struct kvm_vcpu *vcpu);
122int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
123
124u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
125void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
126
127void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
128void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
129
130int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
131void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
132void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
133
134int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
135int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
136int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
137
138int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
139int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
140
141int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
142void kvm_lapic_exit(void);
143
144u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
145
146#define VEC_POS(v) ((v) & (32 - 1))
147#define REG_POS(v) (((v) >> 5) << 4)
148
149static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
150{
151 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
152}
153
154static inline void kvm_lapic_set_vector(int vec, void *bitmap)
155{
156 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
157}
158
159static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
160{
161 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
162 /*
163 * irr_pending must be true if any interrupt is pending; set it after
164 * APIC_IRR to avoid race with apic_clear_irr
165 */
166 apic->irr_pending = true;
167}
168
169static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
170{
171 return *((u32 *) (regs + reg_off));
172}
173
174static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
175{
176 return __kvm_lapic_get_reg(apic->regs, reg_off);
177}
178
179DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
180
181static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
182{
183 if (static_branch_unlikely(&kvm_has_noapic_vcpu))
184 return vcpu->arch.apic;
185 return true;
186}
187
188extern struct static_key_false_deferred apic_hw_disabled;
189
190static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
191{
192 if (static_branch_unlikely(&apic_hw_disabled.key))
193 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
194 return true;
195}
196
197extern struct static_key_false_deferred apic_sw_disabled;
198
199static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
200{
201 if (static_branch_unlikely(&apic_sw_disabled.key))
202 return apic->sw_enabled;
203 return true;
204}
205
206static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
207{
208 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
209}
210
211static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
212{
213 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
214}
215
216static inline int apic_x2apic_mode(struct kvm_lapic *apic)
217{
218 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
219}
220
221static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
222{
223 return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
224}
225
226static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
227{
228 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
229}
230
231static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
232{
233 return !is_smm(vcpu) &&
234 !kvm_x86_call(apic_init_signal_blocked)(vcpu);
235}
236
237static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
238{
239 return (irq->delivery_mode == APIC_DM_LOWEST ||
240 irq->msi_redir_hint);
241}
242
243static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
244{
245 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
246}
247
248bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
249
250void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
251
252void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
253 unsigned long *vcpu_bitmap);
254
255bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
256 struct kvm_vcpu **dest_vcpu);
257int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
258 const unsigned long *bitmap, u32 bitmap_size);
259void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
260void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
261void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
262bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
263void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
264bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
265
266static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
267{
268 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
269}
270
271static inline enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
272{
273 return kvm_apic_mode(vcpu->arch.apic_base);
274}
275
276static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
277{
278 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
279}
280
281#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __KVM_X86_LAPIC_H
3#define __KVM_X86_LAPIC_H
4
5#include <kvm/iodev.h>
6
7#include <linux/kvm_host.h>
8
9#include "hyperv.h"
10#include "smm.h"
11
12#define KVM_APIC_INIT 0
13#define KVM_APIC_SIPI 1
14
15#define APIC_SHORT_MASK 0xc0000
16#define APIC_DEST_NOSHORT 0x0
17#define APIC_DEST_MASK 0x800
18
19#define APIC_BUS_CYCLE_NS 1
20#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
21
22#define APIC_BROADCAST 0xFF
23#define X2APIC_BROADCAST 0xFFFFFFFFul
24
25enum lapic_mode {
26 LAPIC_MODE_DISABLED = 0,
27 LAPIC_MODE_INVALID = X2APIC_ENABLE,
28 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
29 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
30};
31
32enum lapic_lvt_entry {
33 LVT_TIMER,
34 LVT_THERMAL_MONITOR,
35 LVT_PERFORMANCE_COUNTER,
36 LVT_LINT0,
37 LVT_LINT1,
38 LVT_ERROR,
39 LVT_CMCI,
40
41 KVM_APIC_MAX_NR_LVT_ENTRIES,
42};
43
44#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
45
46struct kvm_timer {
47 struct hrtimer timer;
48 s64 period; /* unit: ns */
49 ktime_t target_expiration;
50 u32 timer_mode;
51 u32 timer_mode_mask;
52 u64 tscdeadline;
53 u64 expired_tscdeadline;
54 u32 timer_advance_ns;
55 atomic_t pending; /* accumulated triggered timers */
56 bool hv_timer_in_use;
57};
58
59struct kvm_lapic {
60 unsigned long base_address;
61 struct kvm_io_device dev;
62 struct kvm_timer lapic_timer;
63 u32 divide_count;
64 struct kvm_vcpu *vcpu;
65 bool apicv_active;
66 bool sw_enabled;
67 bool irr_pending;
68 bool lvt0_in_nmi_mode;
69 /* Number of bits set in ISR. */
70 s16 isr_count;
71 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
72 int highest_isr_cache;
73 /**
74 * APIC register page. The layout matches the register layout seen by
75 * the guest 1:1, because it is accessed by the vmx microcode.
76 * Note: Only one register, the TPR, is used by the microcode.
77 */
78 void *regs;
79 gpa_t vapic_addr;
80 struct gfn_to_hva_cache vapic_cache;
81 unsigned long pending_events;
82 unsigned int sipi_vector;
83 int nr_lvt_entries;
84};
85
86struct dest_map;
87
88int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
89void kvm_free_lapic(struct kvm_vcpu *vcpu);
90
91int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
92int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
93int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
94int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
95void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
96u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
97void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
98void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
99void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
100u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
101void kvm_recalculate_apic_map(struct kvm *kvm);
102void kvm_apic_set_version(struct kvm_vcpu *vcpu);
103void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
104bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
105 int shorthand, unsigned int dest, int dest_mode);
106int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
107void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
108bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
109bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
110void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
111int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
112 struct dest_map *dest_map);
113int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
114void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
115int kvm_alloc_apic_access_page(struct kvm *kvm);
116void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);
117
118bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
119 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
120void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
121
122u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
123int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
124int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
125int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
126enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
127int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
128
129u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
130void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
131
132void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
133void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
134
135int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
136void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
137void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
138
139int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
140int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
141int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
142
143int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
144int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
145
146int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
147void kvm_lapic_exit(void);
148
149u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
150
151#define VEC_POS(v) ((v) & (32 - 1))
152#define REG_POS(v) (((v) >> 5) << 4)
153
154static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
155{
156 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
157}
158
159static inline void kvm_lapic_set_vector(int vec, void *bitmap)
160{
161 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
162}
163
164static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
165{
166 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
167 /*
168 * irr_pending must be true if any interrupt is pending; set it after
169 * APIC_IRR to avoid race with apic_clear_irr
170 */
171 apic->irr_pending = true;
172}
173
174static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
175{
176 return *((u32 *) (regs + reg_off));
177}
178
179static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
180{
181 return __kvm_lapic_get_reg(apic->regs, reg_off);
182}
183
184DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
185
186static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
187{
188 if (static_branch_unlikely(&kvm_has_noapic_vcpu))
189 return vcpu->arch.apic;
190 return true;
191}
192
193extern struct static_key_false_deferred apic_hw_disabled;
194
195static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
196{
197 if (static_branch_unlikely(&apic_hw_disabled.key))
198 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
199 return true;
200}
201
202extern struct static_key_false_deferred apic_sw_disabled;
203
204static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
205{
206 if (static_branch_unlikely(&apic_sw_disabled.key))
207 return apic->sw_enabled;
208 return true;
209}
210
211static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
212{
213 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
214}
215
216static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
217{
218 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
219}
220
221static inline int apic_x2apic_mode(struct kvm_lapic *apic)
222{
223 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
224}
225
226static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
227{
228 return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
229}
230
231static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
232{
233 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
234}
235
236static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
237{
238 return !is_smm(vcpu) &&
239 !static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
240}
241
242static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
243{
244 return (irq->delivery_mode == APIC_DM_LOWEST ||
245 irq->msi_redir_hint);
246}
247
248static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
249{
250 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
251}
252
253bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
254
255void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
256
257void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
258 unsigned long *vcpu_bitmap);
259
260bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
261 struct kvm_vcpu **dest_vcpu);
262int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
263 const unsigned long *bitmap, u32 bitmap_size);
264void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
265void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
266void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
267bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
268void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
269bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
270
271static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
272{
273 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
274}
275
276static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
277{
278 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
279}
280
281#endif