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1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Copyright(c) 2021-2022 Intel Corporation
4//
5// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6// Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7//
8
9#include <linux/devcoredump.h>
10#include <linux/slab.h>
11#include <sound/hdaudio_ext.h>
12#include "avs.h"
13#include "cldma.h"
14#include "messages.h"
15#include "registers.h"
16
17void avs_skl_ipc_interrupt(struct avs_dev *adev)
18{
19 const struct avs_spec *spec = adev->spec;
20 u32 hipc_ack, hipc_rsp;
21
22 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset,
23 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY, 0);
24
25 hipc_ack = snd_hdac_adsp_readl(adev, spec->hipc->ack_offset);
26 hipc_rsp = snd_hdac_adsp_readl(adev, spec->hipc->rsp_offset);
27
28 /* DSP acked host's request. */
29 if (hipc_ack & spec->hipc->ack_done_mask) {
30 complete(&adev->ipc->done_completion);
31
32 /* Tell DSP it has our attention. */
33 snd_hdac_adsp_updatel(adev, spec->hipc->ack_offset, spec->hipc->ack_done_mask,
34 spec->hipc->ack_done_mask);
35 }
36
37 /* DSP sent new response to process */
38 if (hipc_rsp & spec->hipc->rsp_busy_mask) {
39 union avs_reply_msg msg;
40
41 msg.primary = snd_hdac_adsp_readl(adev, SKL_ADSP_REG_HIPCT);
42 msg.ext.val = snd_hdac_adsp_readl(adev, SKL_ADSP_REG_HIPCTE);
43
44 avs_dsp_process_response(adev, msg.val);
45
46 /* Tell DSP we accepted its message. */
47 snd_hdac_adsp_updatel(adev, SKL_ADSP_REG_HIPCT, SKL_ADSP_HIPCT_BUSY,
48 SKL_ADSP_HIPCT_BUSY);
49 }
50
51 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset,
52 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY,
53 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY);
54}
55
56static irqreturn_t avs_skl_dsp_interrupt(struct avs_dev *adev)
57{
58 u32 adspis = snd_hdac_adsp_readl(adev, AVS_ADSP_REG_ADSPIS);
59 irqreturn_t ret = IRQ_NONE;
60
61 if (adspis == UINT_MAX)
62 return ret;
63
64 if (adspis & AVS_ADSP_ADSPIS_CLDMA) {
65 hda_cldma_interrupt(&code_loader);
66 ret = IRQ_HANDLED;
67 }
68
69 if (adspis & AVS_ADSP_ADSPIS_IPC) {
70 avs_skl_ipc_interrupt(adev);
71 ret = IRQ_HANDLED;
72 }
73
74 return ret;
75}
76
77static int __maybe_unused
78avs_skl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
79 u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
80{
81 struct avs_skl_log_state_info *info;
82 u32 size, num_cores = adev->hw_cfg.dsp_cores;
83 int ret, i;
84
85 if (fls_long(resource_mask) > num_cores)
86 return -EINVAL;
87 size = struct_size(info, logs_core, num_cores);
88 info = kzalloc(size, GFP_KERNEL);
89 if (!info)
90 return -ENOMEM;
91
92 info->core_mask = resource_mask;
93 if (enable)
94 for_each_set_bit(i, &resource_mask, num_cores) {
95 info->logs_core[i].enable = enable;
96 info->logs_core[i].min_priority = *priorities++;
97 }
98 else
99 for_each_set_bit(i, &resource_mask, num_cores)
100 info->logs_core[i].enable = enable;
101
102 ret = avs_ipc_set_enable_logs(adev, (u8 *)info, size);
103 kfree(info);
104 if (ret)
105 return AVS_IPC_RET(ret);
106
107 return 0;
108}
109
110int avs_skl_log_buffer_offset(struct avs_dev *adev, u32 core)
111{
112 return core * avs_log_buffer_size(adev);
113}
114
115/* fw DbgLogWp registers */
116#define FW_REGS_DBG_LOG_WP(core) (0x30 + 0x4 * core)
117
118static int avs_skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
119{
120 void __iomem *buf;
121 u16 size, write, offset;
122
123 if (!avs_logging_fw(adev))
124 return 0;
125
126 size = avs_log_buffer_size(adev) / 2;
127 write = readl(avs_sram_addr(adev, AVS_FW_REGS_WINDOW) + FW_REGS_DBG_LOG_WP(msg->log.core));
128 /* determine buffer half */
129 offset = (write < size) ? size : 0;
130
131 /* Address is guaranteed to exist in SRAM2. */
132 buf = avs_log_buffer_addr(adev, msg->log.core) + offset;
133 avs_dump_fw_log_wakeup(adev, buf, size);
134
135 return 0;
136}
137
138static int avs_skl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)
139{
140 u8 *dump;
141
142 dump = vzalloc(AVS_FW_REGS_SIZE);
143 if (!dump)
144 return -ENOMEM;
145
146 memcpy_fromio(dump, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);
147 dev_coredumpv(adev->dev, dump, AVS_FW_REGS_SIZE, GFP_KERNEL);
148
149 return 0;
150}
151
152static bool avs_skl_d0ix_toggle(struct avs_dev *adev, struct avs_ipc_msg *tx, bool wake)
153{
154 /* unsupported on cAVS 1.5 hw */
155 return false;
156}
157
158static int avs_skl_set_d0ix(struct avs_dev *adev, bool enable)
159{
160 /* unsupported on cAVS 1.5 hw */
161 return 0;
162}
163
164const struct avs_dsp_ops avs_skl_dsp_ops = {
165 .power = avs_dsp_core_power,
166 .reset = avs_dsp_core_reset,
167 .stall = avs_dsp_core_stall,
168 .dsp_interrupt = avs_skl_dsp_interrupt,
169 .int_control = avs_dsp_interrupt_control,
170 .load_basefw = avs_cldma_load_basefw,
171 .load_lib = avs_cldma_load_library,
172 .transfer_mods = avs_cldma_transfer_modules,
173 .log_buffer_offset = avs_skl_log_buffer_offset,
174 .log_buffer_status = avs_skl_log_buffer_status,
175 .coredump = avs_skl_coredump,
176 .d0ix_toggle = avs_skl_d0ix_toggle,
177 .set_d0ix = avs_skl_set_d0ix,
178 AVS_SET_ENABLE_LOGS_OP(skl)
179};
1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
4//
5// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6// Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7//
8
9#include <linux/devcoredump.h>
10#include <linux/slab.h>
11#include <sound/hdaudio_ext.h>
12#include "avs.h"
13#include "messages.h"
14
15static int __maybe_unused
16skl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
17 u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
18{
19 struct skl_log_state_info *info;
20 u32 size, num_cores = adev->hw_cfg.dsp_cores;
21 int ret, i;
22
23 if (fls_long(resource_mask) > num_cores)
24 return -EINVAL;
25 size = struct_size(info, logs_core, num_cores);
26 info = kzalloc(size, GFP_KERNEL);
27 if (!info)
28 return -ENOMEM;
29
30 info->core_mask = resource_mask;
31 if (enable)
32 for_each_set_bit(i, &resource_mask, num_cores) {
33 info->logs_core[i].enable = enable;
34 info->logs_core[i].min_priority = *priorities++;
35 }
36 else
37 for_each_set_bit(i, &resource_mask, num_cores)
38 info->logs_core[i].enable = enable;
39
40 ret = avs_ipc_set_enable_logs(adev, (u8 *)info, size);
41 kfree(info);
42 if (ret)
43 return AVS_IPC_RET(ret);
44
45 return 0;
46}
47
48int skl_log_buffer_offset(struct avs_dev *adev, u32 core)
49{
50 return core * avs_log_buffer_size(adev);
51}
52
53/* fw DbgLogWp registers */
54#define FW_REGS_DBG_LOG_WP(core) (0x30 + 0x4 * core)
55
56static int
57skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
58{
59 void __iomem *buf;
60 u16 size, write, offset;
61
62 if (!avs_logging_fw(adev))
63 return 0;
64
65 size = avs_log_buffer_size(adev) / 2;
66 write = readl(avs_sram_addr(adev, AVS_FW_REGS_WINDOW) + FW_REGS_DBG_LOG_WP(msg->log.core));
67 /* determine buffer half */
68 offset = (write < size) ? size : 0;
69
70 /* Address is guaranteed to exist in SRAM2. */
71 buf = avs_log_buffer_addr(adev, msg->log.core) + offset;
72 avs_dump_fw_log_wakeup(adev, buf, size);
73
74 return 0;
75}
76
77static int skl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)
78{
79 u8 *dump;
80
81 dump = vzalloc(AVS_FW_REGS_SIZE);
82 if (!dump)
83 return -ENOMEM;
84
85 memcpy_fromio(dump, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);
86 dev_coredumpv(adev->dev, dump, AVS_FW_REGS_SIZE, GFP_KERNEL);
87
88 return 0;
89}
90
91static bool
92skl_d0ix_toggle(struct avs_dev *adev, struct avs_ipc_msg *tx, bool wake)
93{
94 /* unsupported on cAVS 1.5 hw */
95 return false;
96}
97
98static int skl_set_d0ix(struct avs_dev *adev, bool enable)
99{
100 /* unsupported on cAVS 1.5 hw */
101 return 0;
102}
103
104const struct avs_dsp_ops skl_dsp_ops = {
105 .power = avs_dsp_core_power,
106 .reset = avs_dsp_core_reset,
107 .stall = avs_dsp_core_stall,
108 .irq_handler = avs_dsp_irq_handler,
109 .irq_thread = avs_dsp_irq_thread,
110 .int_control = avs_dsp_interrupt_control,
111 .load_basefw = avs_cldma_load_basefw,
112 .load_lib = avs_cldma_load_library,
113 .transfer_mods = avs_cldma_transfer_modules,
114 .log_buffer_offset = skl_log_buffer_offset,
115 .log_buffer_status = skl_log_buffer_status,
116 .coredump = skl_coredump,
117 .d0ix_toggle = skl_d0ix_toggle,
118 .set_d0ix = skl_set_d0ix,
119 AVS_SET_ENABLE_LOGS_OP(skl)
120};