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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Watchdog driver for Marvell Armada 37xx SoCs
4 *
5 * Author: Marek Behún <kabel@kernel.org>
6 */
7
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19#include <linux/types.h>
20#include <linux/watchdog.h>
21
22/*
23 * There are four counters that can be used for watchdog on Armada 37xx.
24 * The addresses for counter control registers are register base plus ID*0x10,
25 * where ID is 0, 1, 2 or 3.
26 *
27 * In this driver we use IDs 0 and 1. Counter ID 1 is used as watchdog counter,
28 * while counter ID 0 is used to implement pinging the watchdog: counter ID 1 is
29 * set to restart counting from initial value on counter ID 0 end count event.
30 * Pinging is done by forcing immediate end count event on counter ID 0.
31 * If only one counter was used, pinging would have to be implemented by
32 * disabling and enabling the counter, leaving the system in a vulnerable state
33 * for a (really) short period of time.
34 *
35 * Counters ID 2 and 3 are enabled by default even before U-Boot loads,
36 * therefore this driver does not provide a way to use them, eg. by setting a
37 * property in device tree.
38 */
39
40#define CNTR_ID_RETRIGGER 0
41#define CNTR_ID_WDOG 1
42
43/* relative to cpu_misc */
44#define WDT_TIMER_SELECT 0x64
45#define WDT_TIMER_SELECT_MASK 0xf
46#define WDT_TIMER_SELECT_VAL BIT(CNTR_ID_WDOG)
47
48/* relative to reg */
49#define CNTR_CTRL(id) ((id) * 0x10)
50#define CNTR_CTRL_ENABLE 0x0001
51#define CNTR_CTRL_ACTIVE 0x0002
52#define CNTR_CTRL_MODE_MASK 0x000c
53#define CNTR_CTRL_MODE_ONESHOT 0x0000
54#define CNTR_CTRL_MODE_HWSIG 0x000c
55#define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
56#define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
57#define CNTR_CTRL_PRESCALE_MASK 0xff00
58#define CNTR_CTRL_PRESCALE_MIN 2
59#define CNTR_CTRL_PRESCALE_SHIFT 8
60
61#define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
62#define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
63
64#define WATCHDOG_TIMEOUT 120
65
66static unsigned int timeout;
67module_param(timeout, int, 0);
68MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
69
70static bool nowayout = WATCHDOG_NOWAYOUT;
71module_param(nowayout, bool, 0);
72MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
73 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
74
75struct armada_37xx_watchdog {
76 struct watchdog_device wdt;
77 struct regmap *cpu_misc;
78 void __iomem *reg;
79 u64 timeout; /* in clock ticks */
80 unsigned long clk_rate;
81 struct clk *clk;
82};
83
84static u64 get_counter_value(struct armada_37xx_watchdog *dev, int id)
85{
86 u64 val;
87
88 /*
89 * when low is read, high is latched into flip-flops so that it can be
90 * read consistently without using software debouncing
91 */
92 val = readl(dev->reg + CNTR_COUNT_LOW(id));
93 val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32;
94
95 return val;
96}
97
98static void set_counter_value(struct armada_37xx_watchdog *dev, int id, u64 val)
99{
100 writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id));
101 writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id));
102}
103
104static void counter_enable(struct armada_37xx_watchdog *dev, int id)
105{
106 u32 reg;
107
108 reg = readl(dev->reg + CNTR_CTRL(id));
109 reg |= CNTR_CTRL_ENABLE;
110 writel(reg, dev->reg + CNTR_CTRL(id));
111}
112
113static void counter_disable(struct armada_37xx_watchdog *dev, int id)
114{
115 u32 reg;
116
117 reg = readl(dev->reg + CNTR_CTRL(id));
118 reg &= ~CNTR_CTRL_ENABLE;
119 writel(reg, dev->reg + CNTR_CTRL(id));
120}
121
122static void init_counter(struct armada_37xx_watchdog *dev, int id, u32 mode,
123 u32 trig_src)
124{
125 u32 reg;
126
127 reg = readl(dev->reg + CNTR_CTRL(id));
128
129 reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
130 CNTR_CTRL_TRIG_SRC_MASK);
131
132 /* set mode */
133 reg |= mode & CNTR_CTRL_MODE_MASK;
134
135 /* set prescaler to the min value */
136 reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
137
138 /* set trigger source */
139 reg |= trig_src & CNTR_CTRL_TRIG_SRC_MASK;
140
141 writel(reg, dev->reg + CNTR_CTRL(id));
142}
143
144static int armada_37xx_wdt_ping(struct watchdog_device *wdt)
145{
146 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
147
148 /* counter 1 is retriggered by forcing end count on counter 0 */
149 counter_disable(dev, CNTR_ID_RETRIGGER);
150 counter_enable(dev, CNTR_ID_RETRIGGER);
151
152 return 0;
153}
154
155static unsigned int armada_37xx_wdt_get_timeleft(struct watchdog_device *wdt)
156{
157 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
158 u64 res;
159
160 res = get_counter_value(dev, CNTR_ID_WDOG) * CNTR_CTRL_PRESCALE_MIN;
161 do_div(res, dev->clk_rate);
162
163 return res;
164}
165
166static int armada_37xx_wdt_set_timeout(struct watchdog_device *wdt,
167 unsigned int timeout)
168{
169 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
170
171 wdt->timeout = timeout;
172
173 /*
174 * Compute the timeout in clock rate. We use smallest possible
175 * prescaler, which divides the clock rate by 2
176 * (CNTR_CTRL_PRESCALE_MIN).
177 */
178 dev->timeout = (u64)dev->clk_rate * timeout;
179 do_div(dev->timeout, CNTR_CTRL_PRESCALE_MIN);
180
181 set_counter_value(dev, CNTR_ID_WDOG, dev->timeout);
182
183 return 0;
184}
185
186static bool armada_37xx_wdt_is_running(struct armada_37xx_watchdog *dev)
187{
188 u32 reg;
189
190 regmap_read(dev->cpu_misc, WDT_TIMER_SELECT, ®);
191 if ((reg & WDT_TIMER_SELECT_MASK) != WDT_TIMER_SELECT_VAL)
192 return false;
193
194 reg = readl(dev->reg + CNTR_CTRL(CNTR_ID_WDOG));
195 return !!(reg & CNTR_CTRL_ACTIVE);
196}
197
198static int armada_37xx_wdt_start(struct watchdog_device *wdt)
199{
200 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
201
202 /* select counter 1 as watchdog counter */
203 regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, WDT_TIMER_SELECT_VAL);
204
205 /* init counter 0 as retrigger counter for counter 1 */
206 init_counter(dev, CNTR_ID_RETRIGGER, CNTR_CTRL_MODE_ONESHOT, 0);
207 set_counter_value(dev, CNTR_ID_RETRIGGER, 0);
208
209 /* init counter 1 to be retriggerable by counter 0 end count */
210 init_counter(dev, CNTR_ID_WDOG, CNTR_CTRL_MODE_HWSIG,
211 CNTR_CTRL_TRIG_SRC_PREV_CNTR);
212 set_counter_value(dev, CNTR_ID_WDOG, dev->timeout);
213
214 /* enable counter 1 */
215 counter_enable(dev, CNTR_ID_WDOG);
216
217 /* start counter 1 by forcing immediate end count on counter 0 */
218 counter_enable(dev, CNTR_ID_RETRIGGER);
219
220 return 0;
221}
222
223static int armada_37xx_wdt_stop(struct watchdog_device *wdt)
224{
225 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
226
227 counter_disable(dev, CNTR_ID_WDOG);
228 counter_disable(dev, CNTR_ID_RETRIGGER);
229 regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, 0);
230
231 return 0;
232}
233
234static const struct watchdog_info armada_37xx_wdt_info = {
235 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
236 .identity = "Armada 37xx Watchdog",
237};
238
239static const struct watchdog_ops armada_37xx_wdt_ops = {
240 .owner = THIS_MODULE,
241 .start = armada_37xx_wdt_start,
242 .stop = armada_37xx_wdt_stop,
243 .ping = armada_37xx_wdt_ping,
244 .set_timeout = armada_37xx_wdt_set_timeout,
245 .get_timeleft = armada_37xx_wdt_get_timeleft,
246};
247
248static int armada_37xx_wdt_probe(struct platform_device *pdev)
249{
250 struct armada_37xx_watchdog *dev;
251 struct regmap *regmap;
252 int ret;
253
254 dev = devm_kzalloc(&pdev->dev, sizeof(struct armada_37xx_watchdog),
255 GFP_KERNEL);
256 if (!dev)
257 return -ENOMEM;
258
259 dev->wdt.info = &armada_37xx_wdt_info;
260 dev->wdt.ops = &armada_37xx_wdt_ops;
261
262 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
263 "marvell,system-controller");
264 if (IS_ERR(regmap))
265 return PTR_ERR(regmap);
266 dev->cpu_misc = regmap;
267
268 dev->reg = devm_platform_ioremap_resource(pdev, 0);
269 if (IS_ERR(dev->reg))
270 return PTR_ERR(dev->reg);
271
272 /* init clock */
273 dev->clk = devm_clk_get_enabled(&pdev->dev, NULL);
274 if (IS_ERR(dev->clk))
275 return PTR_ERR(dev->clk);
276
277 dev->clk_rate = clk_get_rate(dev->clk);
278 if (!dev->clk_rate)
279 return -EINVAL;
280
281 /*
282 * Since the timeout in seconds is given as 32 bit unsigned int, and
283 * the counters hold 64 bit values, even after multiplication by clock
284 * rate the counter can hold timeout of UINT_MAX seconds.
285 */
286 dev->wdt.min_timeout = 1;
287 dev->wdt.max_timeout = UINT_MAX;
288 dev->wdt.parent = &pdev->dev;
289
290 /* default value, possibly override by module parameter or dtb */
291 dev->wdt.timeout = WATCHDOG_TIMEOUT;
292 watchdog_init_timeout(&dev->wdt, timeout, &pdev->dev);
293
294 platform_set_drvdata(pdev, &dev->wdt);
295 watchdog_set_drvdata(&dev->wdt, dev);
296
297 armada_37xx_wdt_set_timeout(&dev->wdt, dev->wdt.timeout);
298
299 if (armada_37xx_wdt_is_running(dev))
300 set_bit(WDOG_HW_RUNNING, &dev->wdt.status);
301
302 watchdog_set_nowayout(&dev->wdt, nowayout);
303 watchdog_stop_on_reboot(&dev->wdt);
304 ret = devm_watchdog_register_device(&pdev->dev, &dev->wdt);
305 if (ret)
306 return ret;
307
308 dev_info(&pdev->dev, "Initial timeout %d sec%s\n",
309 dev->wdt.timeout, nowayout ? ", nowayout" : "");
310
311 return 0;
312}
313
314static int __maybe_unused armada_37xx_wdt_suspend(struct device *dev)
315{
316 struct watchdog_device *wdt = dev_get_drvdata(dev);
317
318 return armada_37xx_wdt_stop(wdt);
319}
320
321static int __maybe_unused armada_37xx_wdt_resume(struct device *dev)
322{
323 struct watchdog_device *wdt = dev_get_drvdata(dev);
324
325 if (watchdog_active(wdt))
326 return armada_37xx_wdt_start(wdt);
327
328 return 0;
329}
330
331static const struct dev_pm_ops armada_37xx_wdt_dev_pm_ops = {
332 SET_SYSTEM_SLEEP_PM_OPS(armada_37xx_wdt_suspend,
333 armada_37xx_wdt_resume)
334};
335
336#ifdef CONFIG_OF
337static const struct of_device_id armada_37xx_wdt_match[] = {
338 { .compatible = "marvell,armada-3700-wdt", },
339 {},
340};
341MODULE_DEVICE_TABLE(of, armada_37xx_wdt_match);
342#endif
343
344static struct platform_driver armada_37xx_wdt_driver = {
345 .probe = armada_37xx_wdt_probe,
346 .driver = {
347 .name = "armada_37xx_wdt",
348 .of_match_table = of_match_ptr(armada_37xx_wdt_match),
349 .pm = &armada_37xx_wdt_dev_pm_ops,
350 },
351};
352
353module_platform_driver(armada_37xx_wdt_driver);
354
355MODULE_AUTHOR("Marek Behun <kabel@kernel.org>");
356MODULE_DESCRIPTION("Armada 37xx CPU Watchdog");
357
358MODULE_LICENSE("GPL v2");
359MODULE_ALIAS("platform:armada_37xx_wdt");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Watchdog driver for Marvell Armada 37xx SoCs
4 *
5 * Author: Marek Behún <kabel@kernel.org>
6 */
7
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/types.h>
21#include <linux/watchdog.h>
22
23/*
24 * There are four counters that can be used for watchdog on Armada 37xx.
25 * The addresses for counter control registers are register base plus ID*0x10,
26 * where ID is 0, 1, 2 or 3.
27 *
28 * In this driver we use IDs 0 and 1. Counter ID 1 is used as watchdog counter,
29 * while counter ID 0 is used to implement pinging the watchdog: counter ID 1 is
30 * set to restart counting from initial value on counter ID 0 end count event.
31 * Pinging is done by forcing immediate end count event on counter ID 0.
32 * If only one counter was used, pinging would have to be implemented by
33 * disabling and enabling the counter, leaving the system in a vulnerable state
34 * for a (really) short period of time.
35 *
36 * Counters ID 2 and 3 are enabled by default even before U-Boot loads,
37 * therefore this driver does not provide a way to use them, eg. by setting a
38 * property in device tree.
39 */
40
41#define CNTR_ID_RETRIGGER 0
42#define CNTR_ID_WDOG 1
43
44/* relative to cpu_misc */
45#define WDT_TIMER_SELECT 0x64
46#define WDT_TIMER_SELECT_MASK 0xf
47#define WDT_TIMER_SELECT_VAL BIT(CNTR_ID_WDOG)
48
49/* relative to reg */
50#define CNTR_CTRL(id) ((id) * 0x10)
51#define CNTR_CTRL_ENABLE 0x0001
52#define CNTR_CTRL_ACTIVE 0x0002
53#define CNTR_CTRL_MODE_MASK 0x000c
54#define CNTR_CTRL_MODE_ONESHOT 0x0000
55#define CNTR_CTRL_MODE_HWSIG 0x000c
56#define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
57#define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
58#define CNTR_CTRL_PRESCALE_MASK 0xff00
59#define CNTR_CTRL_PRESCALE_MIN 2
60#define CNTR_CTRL_PRESCALE_SHIFT 8
61
62#define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
63#define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
64
65#define WATCHDOG_TIMEOUT 120
66
67static unsigned int timeout;
68module_param(timeout, int, 0);
69MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
70
71static bool nowayout = WATCHDOG_NOWAYOUT;
72module_param(nowayout, bool, 0);
73MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
74 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
75
76struct armada_37xx_watchdog {
77 struct watchdog_device wdt;
78 struct regmap *cpu_misc;
79 void __iomem *reg;
80 u64 timeout; /* in clock ticks */
81 unsigned long clk_rate;
82 struct clk *clk;
83};
84
85static u64 get_counter_value(struct armada_37xx_watchdog *dev, int id)
86{
87 u64 val;
88
89 /*
90 * when low is read, high is latched into flip-flops so that it can be
91 * read consistently without using software debouncing
92 */
93 val = readl(dev->reg + CNTR_COUNT_LOW(id));
94 val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32;
95
96 return val;
97}
98
99static void set_counter_value(struct armada_37xx_watchdog *dev, int id, u64 val)
100{
101 writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id));
102 writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id));
103}
104
105static void counter_enable(struct armada_37xx_watchdog *dev, int id)
106{
107 u32 reg;
108
109 reg = readl(dev->reg + CNTR_CTRL(id));
110 reg |= CNTR_CTRL_ENABLE;
111 writel(reg, dev->reg + CNTR_CTRL(id));
112}
113
114static void counter_disable(struct armada_37xx_watchdog *dev, int id)
115{
116 u32 reg;
117
118 reg = readl(dev->reg + CNTR_CTRL(id));
119 reg &= ~CNTR_CTRL_ENABLE;
120 writel(reg, dev->reg + CNTR_CTRL(id));
121}
122
123static void init_counter(struct armada_37xx_watchdog *dev, int id, u32 mode,
124 u32 trig_src)
125{
126 u32 reg;
127
128 reg = readl(dev->reg + CNTR_CTRL(id));
129
130 reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
131 CNTR_CTRL_TRIG_SRC_MASK);
132
133 /* set mode */
134 reg |= mode & CNTR_CTRL_MODE_MASK;
135
136 /* set prescaler to the min value */
137 reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
138
139 /* set trigger source */
140 reg |= trig_src & CNTR_CTRL_TRIG_SRC_MASK;
141
142 writel(reg, dev->reg + CNTR_CTRL(id));
143}
144
145static int armada_37xx_wdt_ping(struct watchdog_device *wdt)
146{
147 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
148
149 /* counter 1 is retriggered by forcing end count on counter 0 */
150 counter_disable(dev, CNTR_ID_RETRIGGER);
151 counter_enable(dev, CNTR_ID_RETRIGGER);
152
153 return 0;
154}
155
156static unsigned int armada_37xx_wdt_get_timeleft(struct watchdog_device *wdt)
157{
158 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
159 u64 res;
160
161 res = get_counter_value(dev, CNTR_ID_WDOG) * CNTR_CTRL_PRESCALE_MIN;
162 do_div(res, dev->clk_rate);
163
164 return res;
165}
166
167static int armada_37xx_wdt_set_timeout(struct watchdog_device *wdt,
168 unsigned int timeout)
169{
170 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
171
172 wdt->timeout = timeout;
173
174 /*
175 * Compute the timeout in clock rate. We use smallest possible
176 * prescaler, which divides the clock rate by 2
177 * (CNTR_CTRL_PRESCALE_MIN).
178 */
179 dev->timeout = (u64)dev->clk_rate * timeout;
180 do_div(dev->timeout, CNTR_CTRL_PRESCALE_MIN);
181
182 set_counter_value(dev, CNTR_ID_WDOG, dev->timeout);
183
184 return 0;
185}
186
187static bool armada_37xx_wdt_is_running(struct armada_37xx_watchdog *dev)
188{
189 u32 reg;
190
191 regmap_read(dev->cpu_misc, WDT_TIMER_SELECT, ®);
192 if ((reg & WDT_TIMER_SELECT_MASK) != WDT_TIMER_SELECT_VAL)
193 return false;
194
195 reg = readl(dev->reg + CNTR_CTRL(CNTR_ID_WDOG));
196 return !!(reg & CNTR_CTRL_ACTIVE);
197}
198
199static int armada_37xx_wdt_start(struct watchdog_device *wdt)
200{
201 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
202
203 /* select counter 1 as watchdog counter */
204 regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, WDT_TIMER_SELECT_VAL);
205
206 /* init counter 0 as retrigger counter for counter 1 */
207 init_counter(dev, CNTR_ID_RETRIGGER, CNTR_CTRL_MODE_ONESHOT, 0);
208 set_counter_value(dev, CNTR_ID_RETRIGGER, 0);
209
210 /* init counter 1 to be retriggerable by counter 0 end count */
211 init_counter(dev, CNTR_ID_WDOG, CNTR_CTRL_MODE_HWSIG,
212 CNTR_CTRL_TRIG_SRC_PREV_CNTR);
213 set_counter_value(dev, CNTR_ID_WDOG, dev->timeout);
214
215 /* enable counter 1 */
216 counter_enable(dev, CNTR_ID_WDOG);
217
218 /* start counter 1 by forcing immediate end count on counter 0 */
219 counter_enable(dev, CNTR_ID_RETRIGGER);
220
221 return 0;
222}
223
224static int armada_37xx_wdt_stop(struct watchdog_device *wdt)
225{
226 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
227
228 counter_disable(dev, CNTR_ID_WDOG);
229 counter_disable(dev, CNTR_ID_RETRIGGER);
230 regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, 0);
231
232 return 0;
233}
234
235static const struct watchdog_info armada_37xx_wdt_info = {
236 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
237 .identity = "Armada 37xx Watchdog",
238};
239
240static const struct watchdog_ops armada_37xx_wdt_ops = {
241 .owner = THIS_MODULE,
242 .start = armada_37xx_wdt_start,
243 .stop = armada_37xx_wdt_stop,
244 .ping = armada_37xx_wdt_ping,
245 .set_timeout = armada_37xx_wdt_set_timeout,
246 .get_timeleft = armada_37xx_wdt_get_timeleft,
247};
248
249static void armada_clk_disable_unprepare(void *data)
250{
251 clk_disable_unprepare(data);
252}
253
254static int armada_37xx_wdt_probe(struct platform_device *pdev)
255{
256 struct armada_37xx_watchdog *dev;
257 struct resource *res;
258 struct regmap *regmap;
259 int ret;
260
261 dev = devm_kzalloc(&pdev->dev, sizeof(struct armada_37xx_watchdog),
262 GFP_KERNEL);
263 if (!dev)
264 return -ENOMEM;
265
266 dev->wdt.info = &armada_37xx_wdt_info;
267 dev->wdt.ops = &armada_37xx_wdt_ops;
268
269 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
270 "marvell,system-controller");
271 if (IS_ERR(regmap))
272 return PTR_ERR(regmap);
273 dev->cpu_misc = regmap;
274
275 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
276 if (!res)
277 return -ENODEV;
278 dev->reg = devm_ioremap(&pdev->dev, res->start, resource_size(res));
279 if (!dev->reg)
280 return -ENOMEM;
281
282 /* init clock */
283 dev->clk = devm_clk_get(&pdev->dev, NULL);
284 if (IS_ERR(dev->clk))
285 return PTR_ERR(dev->clk);
286
287 ret = clk_prepare_enable(dev->clk);
288 if (ret)
289 return ret;
290 ret = devm_add_action_or_reset(&pdev->dev,
291 armada_clk_disable_unprepare, dev->clk);
292 if (ret)
293 return ret;
294
295 dev->clk_rate = clk_get_rate(dev->clk);
296 if (!dev->clk_rate)
297 return -EINVAL;
298
299 /*
300 * Since the timeout in seconds is given as 32 bit unsigned int, and
301 * the counters hold 64 bit values, even after multiplication by clock
302 * rate the counter can hold timeout of UINT_MAX seconds.
303 */
304 dev->wdt.min_timeout = 1;
305 dev->wdt.max_timeout = UINT_MAX;
306 dev->wdt.parent = &pdev->dev;
307
308 /* default value, possibly override by module parameter or dtb */
309 dev->wdt.timeout = WATCHDOG_TIMEOUT;
310 watchdog_init_timeout(&dev->wdt, timeout, &pdev->dev);
311
312 platform_set_drvdata(pdev, &dev->wdt);
313 watchdog_set_drvdata(&dev->wdt, dev);
314
315 armada_37xx_wdt_set_timeout(&dev->wdt, dev->wdt.timeout);
316
317 if (armada_37xx_wdt_is_running(dev))
318 set_bit(WDOG_HW_RUNNING, &dev->wdt.status);
319
320 watchdog_set_nowayout(&dev->wdt, nowayout);
321 watchdog_stop_on_reboot(&dev->wdt);
322 ret = devm_watchdog_register_device(&pdev->dev, &dev->wdt);
323 if (ret)
324 return ret;
325
326 dev_info(&pdev->dev, "Initial timeout %d sec%s\n",
327 dev->wdt.timeout, nowayout ? ", nowayout" : "");
328
329 return 0;
330}
331
332static int __maybe_unused armada_37xx_wdt_suspend(struct device *dev)
333{
334 struct watchdog_device *wdt = dev_get_drvdata(dev);
335
336 return armada_37xx_wdt_stop(wdt);
337}
338
339static int __maybe_unused armada_37xx_wdt_resume(struct device *dev)
340{
341 struct watchdog_device *wdt = dev_get_drvdata(dev);
342
343 if (watchdog_active(wdt))
344 return armada_37xx_wdt_start(wdt);
345
346 return 0;
347}
348
349static const struct dev_pm_ops armada_37xx_wdt_dev_pm_ops = {
350 SET_SYSTEM_SLEEP_PM_OPS(armada_37xx_wdt_suspend,
351 armada_37xx_wdt_resume)
352};
353
354#ifdef CONFIG_OF
355static const struct of_device_id armada_37xx_wdt_match[] = {
356 { .compatible = "marvell,armada-3700-wdt", },
357 {},
358};
359MODULE_DEVICE_TABLE(of, armada_37xx_wdt_match);
360#endif
361
362static struct platform_driver armada_37xx_wdt_driver = {
363 .probe = armada_37xx_wdt_probe,
364 .driver = {
365 .name = "armada_37xx_wdt",
366 .of_match_table = of_match_ptr(armada_37xx_wdt_match),
367 .pm = &armada_37xx_wdt_dev_pm_ops,
368 },
369};
370
371module_platform_driver(armada_37xx_wdt_driver);
372
373MODULE_AUTHOR("Marek Behun <kabel@kernel.org>");
374MODULE_DESCRIPTION("Armada 37xx CPU Watchdog");
375
376MODULE_LICENSE("GPL v2");
377MODULE_ALIAS("platform:armada_37xx_wdt");