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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2024 AIROHA Inc
4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5 * Author: Ray Liu <ray.liu@airoha.com>
6 */
7
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/dma-mapping.h>
13#include <linux/errno.h>
14#include <linux/limits.h>
15#include <linux/math.h>
16#include <linux/minmax.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <linux/platform_device.h>
20#include <linux/property.h>
21#include <linux/regmap.h>
22#include <linux/sizes.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/spi-mem.h>
25#include <linux/types.h>
26#include <linux/unaligned.h>
27
28/* SPI */
29#define REG_SPI_CTRL_BASE 0x1FA10000
30
31#define REG_SPI_CTRL_READ_MODE 0x0000
32#define REG_SPI_CTRL_READ_IDLE_EN 0x0004
33#define REG_SPI_CTRL_SIDLY 0x0008
34#define REG_SPI_CTRL_CSHEXT 0x000c
35#define REG_SPI_CTRL_CSLEXT 0x0010
36
37#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014
38#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0)
39
40#define REG_SPI_CTRL_RDCTL_FSM 0x0018
41#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0)
42
43#define REG_SPI_CTRL_MACMUX_SEL 0x001c
44
45#define REG_SPI_CTRL_MANUAL_EN 0x0020
46#define SPI_CTRL_MANUAL_EN BIT(0)
47
48#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024
49#define SPI_CTRL_OPFIFO_EMPTY BIT(0)
50
51#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028
52#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0)
53#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9)
54
55#define REG_SPI_CTRL_OPFIFO_FULL 0x002c
56#define SPI_CTRL_OPFIFO_FULL BIT(0)
57
58#define REG_SPI_CTRL_OPFIFO_WR 0x0030
59#define SPI_CTRL_OPFIFO_WR BIT(0)
60
61#define REG_SPI_CTRL_DFIFO_FULL 0x0034
62#define SPI_CTRL_DFIFO_FULL BIT(0)
63
64#define REG_SPI_CTRL_DFIFO_WDATA 0x0038
65#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0)
66
67#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c
68#define SPI_CTRL_DFIFO_EMPTY BIT(0)
69
70#define REG_SPI_CTRL_DFIFO_RD 0x0040
71#define SPI_CTRL_DFIFO_RD BIT(0)
72
73#define REG_SPI_CTRL_DFIFO_RDATA 0x0044
74#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0)
75
76#define REG_SPI_CTRL_DUMMY 0x0080
77#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0)
78
79#define REG_SPI_CTRL_PROBE_SEL 0x0088
80#define REG_SPI_CTRL_INTERRUPT 0x0090
81#define REG_SPI_CTRL_INTERRUPT_EN 0x0094
82#define REG_SPI_CTRL_SI_CK_SEL 0x009c
83#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c
84#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110
85#define REG_SPI_CTRL_SFC_STRAP 0x0114
86
87#define REG_SPI_CTRL_NFI2SPI_EN 0x0130
88#define SPI_CTRL_NFI2SPI_EN BIT(0)
89
90/* NFI2SPI */
91#define REG_SPI_NFI_CNFG 0x0000
92#define SPI_NFI_DMA_MODE BIT(0)
93#define SPI_NFI_READ_MODE BIT(1)
94#define SPI_NFI_DMA_BURST_EN BIT(2)
95#define SPI_NFI_HW_ECC_EN BIT(8)
96#define SPI_NFI_AUTO_FDM_EN BIT(9)
97#define SPI_NFI_OPMODE GENMASK(14, 12)
98
99#define REG_SPI_NFI_PAGEFMT 0x0004
100#define SPI_NFI_PAGE_SIZE GENMASK(1, 0)
101#define SPI_NFI_SPARE_SIZE GENMASK(5, 4)
102
103#define REG_SPI_NFI_CON 0x0008
104#define SPI_NFI_FIFO_FLUSH BIT(0)
105#define SPI_NFI_RST BIT(1)
106#define SPI_NFI_RD_TRIG BIT(8)
107#define SPI_NFI_WR_TRIG BIT(9)
108#define SPI_NFI_SEC_NUM GENMASK(15, 12)
109
110#define REG_SPI_NFI_INTR_EN 0x0010
111#define SPI_NFI_RD_DONE_EN BIT(0)
112#define SPI_NFI_WR_DONE_EN BIT(1)
113#define SPI_NFI_RST_DONE_EN BIT(2)
114#define SPI_NFI_ERASE_DONE_EN BIT(3)
115#define SPI_NFI_BUSY_RETURN_EN BIT(4)
116#define SPI_NFI_ACCESS_LOCK_EN BIT(5)
117#define SPI_NFI_AHB_DONE_EN BIT(6)
118#define SPI_NFI_ALL_IRQ_EN \
119 (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \
120 SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \
121 SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \
122 SPI_NFI_AHB_DONE_EN)
123
124#define REG_SPI_NFI_INTR 0x0014
125#define SPI_NFI_AHB_DONE BIT(6)
126
127#define REG_SPI_NFI_CMD 0x0020
128
129#define REG_SPI_NFI_ADDR_NOB 0x0030
130#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4)
131
132#define REG_SPI_NFI_STA 0x0060
133#define REG_SPI_NFI_FIFOSTA 0x0064
134#define REG_SPI_NFI_STRADDR 0x0080
135#define REG_SPI_NFI_FDM0L 0x00a0
136#define REG_SPI_NFI_FDM0M 0x00a4
137#define REG_SPI_NFI_FDM7L 0x00d8
138#define REG_SPI_NFI_FDM7M 0x00dc
139#define REG_SPI_NFI_FIFODATA0 0x0190
140#define REG_SPI_NFI_FIFODATA1 0x0194
141#define REG_SPI_NFI_FIFODATA2 0x0198
142#define REG_SPI_NFI_FIFODATA3 0x019c
143#define REG_SPI_NFI_MASTERSTA 0x0224
144
145#define REG_SPI_NFI_SECCUS_SIZE 0x022c
146#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0)
147#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
148
149#define REG_SPI_NFI_RD_CTL2 0x0510
150#define REG_SPI_NFI_RD_CTL3 0x0514
151
152#define REG_SPI_NFI_PG_CTL1 0x0524
153#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)
154
155#define REG_SPI_NFI_PG_CTL2 0x0528
156#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c
157#define REG_SPI_NFI_NOR_RD_ADDR 0x0534
158
159#define REG_SPI_NFI_SNF_MISC_CTL 0x0538
160#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16)
161
162#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c
163#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0)
164#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16)
165
166#define REG_SPI_NFI_SNF_STA_CTL1 0x0550
167#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25)
168#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26)
169
170#define REG_SPI_NFI_SNF_STA_CTL2 0x0554
171
172#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c
173#define SPI_NFI_SPI_MODE BIT(0)
174
175/* SPI NAND Protocol OP */
176#define SPI_NAND_OP_GET_FEATURE 0x0f
177#define SPI_NAND_OP_SET_FEATURE 0x1f
178#define SPI_NAND_OP_PAGE_READ 0x13
179#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03
180#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b
181#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b
182#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b
183#define SPI_NAND_OP_WRITE_ENABLE 0x06
184#define SPI_NAND_OP_WRITE_DISABLE 0x04
185#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02
186#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32
187#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84
188#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34
189#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10
190#define SPI_NAND_OP_READ_ID 0x9f
191#define SPI_NAND_OP_BLOCK_ERASE 0xd8
192#define SPI_NAND_OP_RESET 0xff
193#define SPI_NAND_OP_DIE_SELECT 0xc2
194
195#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
196#define SPI_MAX_TRANSFER_SIZE 511
197
198enum airoha_snand_mode {
199 SPI_MODE_AUTO,
200 SPI_MODE_MANUAL,
201 SPI_MODE_DMA,
202};
203
204enum airoha_snand_cs {
205 SPI_CHIP_SEL_HIGH,
206 SPI_CHIP_SEL_LOW,
207};
208
209struct airoha_snand_ctrl {
210 struct device *dev;
211 struct regmap *regmap_ctrl;
212 struct regmap *regmap_nfi;
213 struct clk *spi_clk;
214
215 struct {
216 size_t page_size;
217 size_t sec_size;
218 u8 sec_num;
219 u8 spare_size;
220 } nfi_cfg;
221};
222
223static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl,
224 u8 op_cmd, int op_len)
225{
226 int err;
227 u32 val;
228
229 err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA,
230 FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) |
231 FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd));
232 if (err)
233 return err;
234
235 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
236 REG_SPI_CTRL_OPFIFO_FULL,
237 val, !(val & SPI_CTRL_OPFIFO_FULL),
238 0, 250 * USEC_PER_MSEC);
239 if (err)
240 return err;
241
242 err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR,
243 SPI_CTRL_OPFIFO_WR);
244 if (err)
245 return err;
246
247 return regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
248 REG_SPI_CTRL_OPFIFO_EMPTY,
249 val, (val & SPI_CTRL_OPFIFO_EMPTY),
250 0, 250 * USEC_PER_MSEC);
251}
252
253static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs)
254{
255 return airoha_snand_set_fifo_op(as_ctrl, cs, sizeof(cs));
256}
257
258static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl,
259 const u8 *data, int len)
260{
261 int i;
262
263 for (i = 0; i < len; i++) {
264 int err;
265 u32 val;
266
267 /* 1. Wait until dfifo is not full */
268 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
269 REG_SPI_CTRL_DFIFO_FULL, val,
270 !(val & SPI_CTRL_DFIFO_FULL),
271 0, 250 * USEC_PER_MSEC);
272 if (err)
273 return err;
274
275 /* 2. Write data to register DFIFO_WDATA */
276 err = regmap_write(as_ctrl->regmap_ctrl,
277 REG_SPI_CTRL_DFIFO_WDATA,
278 FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i]));
279 if (err)
280 return err;
281
282 /* 3. Wait until dfifo is not full */
283 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
284 REG_SPI_CTRL_DFIFO_FULL, val,
285 !(val & SPI_CTRL_DFIFO_FULL),
286 0, 250 * USEC_PER_MSEC);
287 if (err)
288 return err;
289 }
290
291 return 0;
292}
293
294static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl,
295 u8 *ptr, int len)
296{
297 int i;
298
299 for (i = 0; i < len; i++) {
300 int err;
301 u32 val;
302
303 /* 1. wait until dfifo is not empty */
304 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
305 REG_SPI_CTRL_DFIFO_EMPTY, val,
306 !(val & SPI_CTRL_DFIFO_EMPTY),
307 0, 250 * USEC_PER_MSEC);
308 if (err)
309 return err;
310
311 /* 2. read from dfifo to register DFIFO_RDATA */
312 err = regmap_read(as_ctrl->regmap_ctrl,
313 REG_SPI_CTRL_DFIFO_RDATA, &val);
314 if (err)
315 return err;
316
317 ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val);
318 /* 3. enable register DFIFO_RD to read next byte */
319 err = regmap_write(as_ctrl->regmap_ctrl,
320 REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD);
321 if (err)
322 return err;
323 }
324
325 return 0;
326}
327
328static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl,
329 enum airoha_snand_mode mode)
330{
331 int err;
332
333 switch (mode) {
334 case SPI_MODE_MANUAL: {
335 u32 val;
336
337 err = regmap_write(as_ctrl->regmap_ctrl,
338 REG_SPI_CTRL_NFI2SPI_EN, 0);
339 if (err)
340 return err;
341
342 err = regmap_write(as_ctrl->regmap_ctrl,
343 REG_SPI_CTRL_READ_IDLE_EN, 0);
344 if (err)
345 return err;
346
347 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
348 REG_SPI_CTRL_RDCTL_FSM, val,
349 !(val & SPI_CTRL_RDCTL_FSM),
350 0, 250 * USEC_PER_MSEC);
351 if (err)
352 return err;
353
354 err = regmap_write(as_ctrl->regmap_ctrl,
355 REG_SPI_CTRL_MTX_MODE_TOG, 9);
356 if (err)
357 return err;
358
359 err = regmap_write(as_ctrl->regmap_ctrl,
360 REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN);
361 if (err)
362 return err;
363 break;
364 }
365 case SPI_MODE_DMA:
366 err = regmap_write(as_ctrl->regmap_ctrl,
367 REG_SPI_CTRL_NFI2SPI_EN,
368 SPI_CTRL_MANUAL_EN);
369 if (err < 0)
370 return err;
371
372 err = regmap_write(as_ctrl->regmap_ctrl,
373 REG_SPI_CTRL_MTX_MODE_TOG, 0x0);
374 if (err < 0)
375 return err;
376
377 err = regmap_write(as_ctrl->regmap_ctrl,
378 REG_SPI_CTRL_MANUAL_EN, 0x0);
379 if (err < 0)
380 return err;
381 break;
382 case SPI_MODE_AUTO:
383 default:
384 break;
385 }
386
387 return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
388}
389
390static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
391 const u8 *data, int len)
392{
393 int i, data_len;
394
395 for (i = 0; i < len; i += data_len) {
396 int err;
397
398 data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
399 err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
400 if (err)
401 return err;
402
403 err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
404 data_len);
405 if (err < 0)
406 return err;
407 }
408
409 return 0;
410}
411
412static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
413 int len)
414{
415 int i, data_len;
416
417 for (i = 0; i < len; i += data_len) {
418 int err;
419
420 data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
421 err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
422 if (err)
423 return err;
424
425 err = airoha_snand_read_data_from_fifo(as_ctrl, &data[i],
426 data_len);
427 if (err < 0)
428 return err;
429 }
430
431 return 0;
432}
433
434static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl)
435{
436 int err;
437
438 /* switch to SNFI mode */
439 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG,
440 SPI_NFI_SPI_MODE);
441 if (err)
442 return err;
443
444 /* Enable DMA */
445 return regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR_EN,
446 SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
447}
448
449static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl)
450{
451 int err;
452 u32 val;
453
454 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
455 SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
456 if (err)
457 return err;
458
459 /* auto FDM */
460 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
461 SPI_NFI_AUTO_FDM_EN);
462 if (err)
463 return err;
464
465 /* HW ECC */
466 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
467 SPI_NFI_HW_ECC_EN);
468 if (err)
469 return err;
470
471 /* DMA Burst */
472 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
473 SPI_NFI_DMA_BURST_EN);
474 if (err)
475 return err;
476
477 /* page format */
478 switch (as_ctrl->nfi_cfg.spare_size) {
479 case 26:
480 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
481 break;
482 case 27:
483 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);
484 break;
485 case 28:
486 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);
487 break;
488 default:
489 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);
490 break;
491 }
492
493 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
494 SPI_NFI_SPARE_SIZE, val);
495 if (err)
496 return err;
497
498 switch (as_ctrl->nfi_cfg.page_size) {
499 case 2048:
500 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
501 break;
502 case 4096:
503 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);
504 break;
505 default:
506 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);
507 break;
508 }
509
510 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
511 SPI_NFI_PAGE_SIZE, val);
512 if (err)
513 return err;
514
515 /* sec num */
516 val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
517 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
518 SPI_NFI_SEC_NUM, val);
519 if (err)
520 return err;
521
522 /* enable cust sec size */
523 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
524 SPI_NFI_CUS_SEC_SIZE_EN);
525 if (err)
526 return err;
527
528 /* set cust sec size */
529 val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size);
530 return regmap_update_bits(as_ctrl->regmap_nfi,
531 REG_SPI_NFI_SECCUS_SIZE,
532 SPI_NFI_CUS_SEC_SIZE, val);
533}
534
535static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
536{
537 if (op->addr.nbytes != 2)
538 return false;
539
540 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
541 op->addr.buswidth != 4)
542 return false;
543
544 switch (op->data.dir) {
545 case SPI_MEM_DATA_IN:
546 if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
547 return false;
548
549 /* quad in / quad out */
550 if (op->addr.buswidth == 4)
551 return op->data.buswidth == 4;
552
553 if (op->addr.buswidth == 2)
554 return op->data.buswidth == 2;
555
556 /* standard spi */
557 return op->data.buswidth == 4 || op->data.buswidth == 2 ||
558 op->data.buswidth == 1;
559 case SPI_MEM_DATA_OUT:
560 return !op->dummy.nbytes && op->addr.buswidth == 1 &&
561 (op->data.buswidth == 4 || op->data.buswidth == 1);
562 default:
563 return false;
564 }
565}
566
567static int airoha_snand_adjust_op_size(struct spi_mem *mem,
568 struct spi_mem_op *op)
569{
570 size_t max_len;
571
572 if (airoha_snand_is_page_ops(op)) {
573 struct airoha_snand_ctrl *as_ctrl;
574
575 as_ctrl = spi_controller_get_devdata(mem->spi->controller);
576 max_len = as_ctrl->nfi_cfg.sec_size;
577 max_len += as_ctrl->nfi_cfg.spare_size;
578 max_len *= as_ctrl->nfi_cfg.sec_num;
579
580 if (op->data.nbytes > max_len)
581 op->data.nbytes = max_len;
582 } else {
583 max_len = 1 + op->addr.nbytes + op->dummy.nbytes;
584 if (max_len >= 160)
585 return -EOPNOTSUPP;
586
587 if (op->data.nbytes > 160 - max_len)
588 op->data.nbytes = 160 - max_len;
589 }
590
591 return 0;
592}
593
594static bool airoha_snand_supports_op(struct spi_mem *mem,
595 const struct spi_mem_op *op)
596{
597 if (!spi_mem_default_supports_op(mem, op))
598 return false;
599
600 if (op->cmd.buswidth != 1)
601 return false;
602
603 if (airoha_snand_is_page_ops(op))
604 return true;
605
606 return (!op->addr.nbytes || op->addr.buswidth == 1) &&
607 (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
608 (!op->data.nbytes || op->data.buswidth == 1);
609}
610
611static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
612{
613 u8 *txrx_buf = spi_get_ctldata(desc->mem->spi);
614
615 if (!txrx_buf)
616 return -EINVAL;
617
618 if (desc->info.offset + desc->info.length > U32_MAX)
619 return -EINVAL;
620
621 if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
622 return -EOPNOTSUPP;
623
624 return 0;
625}
626
627static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
628 u64 offs, size_t len, void *buf)
629{
630 struct spi_mem_op *op = &desc->info.op_tmpl;
631 struct spi_device *spi = desc->mem->spi;
632 struct airoha_snand_ctrl *as_ctrl;
633 u8 *txrx_buf = spi_get_ctldata(spi);
634 dma_addr_t dma_addr;
635 u32 val, rd_mode;
636 int err;
637
638 switch (op->cmd.opcode) {
639 case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
640 rd_mode = 1;
641 break;
642 case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
643 rd_mode = 2;
644 break;
645 default:
646 rd_mode = 0;
647 break;
648 }
649
650 as_ctrl = spi_controller_get_devdata(spi->controller);
651 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
652 if (err < 0)
653 return err;
654
655 err = airoha_snand_nfi_config(as_ctrl);
656 if (err)
657 return err;
658
659 dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
660 DMA_FROM_DEVICE);
661 err = dma_mapping_error(as_ctrl->dev, dma_addr);
662 if (err)
663 return err;
664
665 /* set dma addr */
666 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
667 dma_addr);
668 if (err)
669 goto error_dma_unmap;
670
671 /* set cust sec size */
672 val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
673 val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
674 err = regmap_update_bits(as_ctrl->regmap_nfi,
675 REG_SPI_NFI_SNF_MISC_CTL2,
676 SPI_NFI_READ_DATA_BYTE_NUM, val);
677 if (err)
678 goto error_dma_unmap;
679
680 /* set read command */
681 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
682 op->cmd.opcode);
683 if (err)
684 goto error_dma_unmap;
685
686 /* set read mode */
687 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
688 FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
689 if (err)
690 goto error_dma_unmap;
691
692 /* set read addr */
693 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);
694 if (err)
695 goto error_dma_unmap;
696
697 /* set nfi read */
698 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
699 SPI_NFI_OPMODE,
700 FIELD_PREP(SPI_NFI_OPMODE, 6));
701 if (err)
702 goto error_dma_unmap;
703
704 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
705 SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
706 if (err)
707 goto error_dma_unmap;
708
709 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
710 if (err)
711 goto error_dma_unmap;
712
713 /* trigger dma start read */
714 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
715 SPI_NFI_RD_TRIG);
716 if (err)
717 goto error_dma_unmap;
718
719 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
720 SPI_NFI_RD_TRIG);
721 if (err)
722 goto error_dma_unmap;
723
724 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
725 REG_SPI_NFI_SNF_STA_CTL1, val,
726 (val & SPI_NFI_READ_FROM_CACHE_DONE),
727 0, 1 * USEC_PER_SEC);
728 if (err)
729 goto error_dma_unmap;
730
731 /*
732 * SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end
733 * of dirmap_read operation even if it is already set.
734 */
735 err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
736 SPI_NFI_READ_FROM_CACHE_DONE,
737 SPI_NFI_READ_FROM_CACHE_DONE);
738 if (err)
739 goto error_dma_unmap;
740
741 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
742 val, (val & SPI_NFI_AHB_DONE), 0,
743 1 * USEC_PER_SEC);
744 if (err)
745 goto error_dma_unmap;
746
747 /* DMA read need delay for data ready from controller to DRAM */
748 udelay(1);
749
750 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
751 DMA_FROM_DEVICE);
752 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
753 if (err < 0)
754 return err;
755
756 memcpy(buf, txrx_buf + offs, len);
757
758 return len;
759
760error_dma_unmap:
761 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
762 DMA_FROM_DEVICE);
763 return err;
764}
765
766static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
767 u64 offs, size_t len, const void *buf)
768{
769 struct spi_mem_op *op = &desc->info.op_tmpl;
770 struct spi_device *spi = desc->mem->spi;
771 u8 *txrx_buf = spi_get_ctldata(spi);
772 struct airoha_snand_ctrl *as_ctrl;
773 dma_addr_t dma_addr;
774 u32 wr_mode, val;
775 int err;
776
777 as_ctrl = spi_controller_get_devdata(spi->controller);
778 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
779 if (err < 0)
780 return err;
781
782 memcpy(txrx_buf + offs, buf, len);
783 dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
784 DMA_TO_DEVICE);
785 err = dma_mapping_error(as_ctrl->dev, dma_addr);
786 if (err)
787 return err;
788
789 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
790 if (err < 0)
791 goto error_dma_unmap;
792
793 err = airoha_snand_nfi_config(as_ctrl);
794 if (err)
795 goto error_dma_unmap;
796
797 if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD ||
798 op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD)
799 wr_mode = BIT(1);
800 else
801 wr_mode = 0;
802
803 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
804 dma_addr);
805 if (err)
806 goto error_dma_unmap;
807
808 val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
809 as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
810 err = regmap_update_bits(as_ctrl->regmap_nfi,
811 REG_SPI_NFI_SNF_MISC_CTL2,
812 SPI_NFI_PROG_LOAD_BYTE_NUM, val);
813 if (err)
814 goto error_dma_unmap;
815
816 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1,
817 FIELD_PREP(SPI_NFI_PG_LOAD_CMD,
818 op->cmd.opcode));
819 if (err)
820 goto error_dma_unmap;
821
822 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
823 FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
824 if (err)
825 goto error_dma_unmap;
826
827 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);
828 if (err)
829 goto error_dma_unmap;
830
831 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
832 SPI_NFI_READ_MODE);
833 if (err)
834 goto error_dma_unmap;
835
836 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
837 SPI_NFI_OPMODE,
838 FIELD_PREP(SPI_NFI_OPMODE, 3));
839 if (err)
840 goto error_dma_unmap;
841
842 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
843 SPI_NFI_DMA_MODE);
844 if (err)
845 goto error_dma_unmap;
846
847 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
848 if (err)
849 goto error_dma_unmap;
850
851 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
852 SPI_NFI_WR_TRIG);
853 if (err)
854 goto error_dma_unmap;
855
856 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
857 SPI_NFI_WR_TRIG);
858 if (err)
859 goto error_dma_unmap;
860
861 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
862 val, (val & SPI_NFI_AHB_DONE), 0,
863 1 * USEC_PER_SEC);
864 if (err)
865 goto error_dma_unmap;
866
867 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
868 REG_SPI_NFI_SNF_STA_CTL1, val,
869 (val & SPI_NFI_LOAD_TO_CACHE_DONE),
870 0, 1 * USEC_PER_SEC);
871 if (err)
872 goto error_dma_unmap;
873
874 /*
875 * SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end
876 * of dirmap_write operation even if it is already set.
877 */
878 err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
879 SPI_NFI_LOAD_TO_CACHE_DONE,
880 SPI_NFI_LOAD_TO_CACHE_DONE);
881 if (err)
882 goto error_dma_unmap;
883
884 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
885 DMA_TO_DEVICE);
886 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
887 if (err < 0)
888 return err;
889
890 return len;
891
892error_dma_unmap:
893 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
894 DMA_TO_DEVICE);
895 return err;
896}
897
898static int airoha_snand_exec_op(struct spi_mem *mem,
899 const struct spi_mem_op *op)
900{
901 u8 data[8], cmd, opcode = op->cmd.opcode;
902 struct airoha_snand_ctrl *as_ctrl;
903 int i, err;
904
905 as_ctrl = spi_controller_get_devdata(mem->spi->controller);
906
907 /* switch to manual mode */
908 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
909 if (err < 0)
910 return err;
911
912 err = airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_LOW);
913 if (err < 0)
914 return err;
915
916 /* opcode */
917 err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));
918 if (err)
919 return err;
920
921 /* addr part */
922 cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
923 put_unaligned_be64(op->addr.val, data);
924
925 for (i = ARRAY_SIZE(data) - op->addr.nbytes;
926 i < ARRAY_SIZE(data); i++) {
927 err = airoha_snand_write_data(as_ctrl, cmd, &data[i],
928 sizeof(data[0]));
929 if (err)
930 return err;
931 }
932
933 /* dummy */
934 data[0] = 0xff;
935 for (i = 0; i < op->dummy.nbytes; i++) {
936 err = airoha_snand_write_data(as_ctrl, 0x8, &data[0],
937 sizeof(data[0]));
938 if (err)
939 return err;
940 }
941
942 /* data */
943 if (op->data.dir == SPI_MEM_DATA_IN) {
944 err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
945 op->data.nbytes);
946 if (err)
947 return err;
948 } else {
949 err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,
950 op->data.nbytes);
951 if (err)
952 return err;
953 }
954
955 return airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_HIGH);
956}
957
958static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
959 .adjust_op_size = airoha_snand_adjust_op_size,
960 .supports_op = airoha_snand_supports_op,
961 .exec_op = airoha_snand_exec_op,
962 .dirmap_create = airoha_snand_dirmap_create,
963 .dirmap_read = airoha_snand_dirmap_read,
964 .dirmap_write = airoha_snand_dirmap_write,
965};
966
967static int airoha_snand_setup(struct spi_device *spi)
968{
969 struct airoha_snand_ctrl *as_ctrl;
970 u8 *txrx_buf;
971
972 /* prepare device buffer */
973 as_ctrl = spi_controller_get_devdata(spi->controller);
974 txrx_buf = devm_kzalloc(as_ctrl->dev, SPI_NAND_CACHE_SIZE,
975 GFP_KERNEL);
976 if (!txrx_buf)
977 return -ENOMEM;
978
979 spi_set_ctldata(spi, txrx_buf);
980
981 return 0;
982}
983
984static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl)
985{
986 u32 val, sec_size, sec_num;
987 int err;
988
989 err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, &val);
990 if (err)
991 return err;
992
993 sec_num = FIELD_GET(SPI_NFI_SEC_NUM, val);
994
995 err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, &val);
996 if (err)
997 return err;
998
999 sec_size = FIELD_GET(SPI_NFI_CUS_SEC_SIZE, val);
1000
1001 /* init default value */
1002 as_ctrl->nfi_cfg.sec_size = sec_size;
1003 as_ctrl->nfi_cfg.sec_num = sec_num;
1004 as_ctrl->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
1005 as_ctrl->nfi_cfg.spare_size = 16;
1006
1007 err = airoha_snand_nfi_init(as_ctrl);
1008 if (err)
1009 return err;
1010
1011 return airoha_snand_nfi_config(as_ctrl);
1012}
1013
1014static const struct regmap_config spi_ctrl_regmap_config = {
1015 .name = "ctrl",
1016 .reg_bits = 32,
1017 .val_bits = 32,
1018 .reg_stride = 4,
1019 .max_register = REG_SPI_CTRL_NFI2SPI_EN,
1020};
1021
1022static const struct regmap_config spi_nfi_regmap_config = {
1023 .name = "nfi",
1024 .reg_bits = 32,
1025 .val_bits = 32,
1026 .reg_stride = 4,
1027 .max_register = REG_SPI_NFI_SNF_NFI_CNFG,
1028};
1029
1030static const struct of_device_id airoha_snand_ids[] = {
1031 { .compatible = "airoha,en7581-snand" },
1032 { /* sentinel */ }
1033};
1034MODULE_DEVICE_TABLE(of, airoha_snand_ids);
1035
1036static int airoha_snand_probe(struct platform_device *pdev)
1037{
1038 struct airoha_snand_ctrl *as_ctrl;
1039 struct device *dev = &pdev->dev;
1040 struct spi_controller *ctrl;
1041 void __iomem *base;
1042 int err;
1043
1044 ctrl = devm_spi_alloc_host(dev, sizeof(*as_ctrl));
1045 if (!ctrl)
1046 return -ENOMEM;
1047
1048 as_ctrl = spi_controller_get_devdata(ctrl);
1049 as_ctrl->dev = dev;
1050
1051 base = devm_platform_ioremap_resource(pdev, 0);
1052 if (IS_ERR(base))
1053 return PTR_ERR(base);
1054
1055 as_ctrl->regmap_ctrl = devm_regmap_init_mmio(dev, base,
1056 &spi_ctrl_regmap_config);
1057 if (IS_ERR(as_ctrl->regmap_ctrl))
1058 return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_ctrl),
1059 "failed to init spi ctrl regmap\n");
1060
1061 base = devm_platform_ioremap_resource(pdev, 1);
1062 if (IS_ERR(base))
1063 return PTR_ERR(base);
1064
1065 as_ctrl->regmap_nfi = devm_regmap_init_mmio(dev, base,
1066 &spi_nfi_regmap_config);
1067 if (IS_ERR(as_ctrl->regmap_nfi))
1068 return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_nfi),
1069 "failed to init spi nfi regmap\n");
1070
1071 as_ctrl->spi_clk = devm_clk_get_enabled(dev, "spi");
1072 if (IS_ERR(as_ctrl->spi_clk))
1073 return dev_err_probe(dev, PTR_ERR(as_ctrl->spi_clk),
1074 "unable to get spi clk\n");
1075
1076 err = dma_set_mask(as_ctrl->dev, DMA_BIT_MASK(32));
1077 if (err)
1078 return err;
1079
1080 ctrl->num_chipselect = 2;
1081 ctrl->mem_ops = &airoha_snand_mem_ops;
1082 ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
1083 ctrl->mode_bits = SPI_RX_DUAL;
1084 ctrl->setup = airoha_snand_setup;
1085 device_set_node(&ctrl->dev, dev_fwnode(dev));
1086
1087 err = airoha_snand_nfi_setup(as_ctrl);
1088 if (err)
1089 return err;
1090
1091 return devm_spi_register_controller(dev, ctrl);
1092}
1093
1094static struct platform_driver airoha_snand_driver = {
1095 .driver = {
1096 .name = "airoha-spi",
1097 .of_match_table = airoha_snand_ids,
1098 },
1099 .probe = airoha_snand_probe,
1100};
1101module_platform_driver(airoha_snand_driver);
1102
1103MODULE_DESCRIPTION("Airoha SPI-NAND Flash Controller Driver");
1104MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
1105MODULE_AUTHOR("Ray Liu <ray.liu@airoha.com>");
1106MODULE_LICENSE("GPL");