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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Atmel
4 *
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com
6 * Boris Brezillon <boris.brezillon@free-electrons.com
7 */
8
9#define pr_fmt(fmt) "AT91: " fmt
10
11#include <linux/io.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/of_platform.h>
15#include <linux/slab.h>
16#include <linux/sys_soc.h>
17
18#include "soc.h"
19
20#define AT91_DBGU_CIDR 0x40
21#define AT91_DBGU_EXID 0x44
22#define AT91_CHIPID_CIDR 0x00
23#define AT91_CHIPID_EXID 0x04
24#define AT91_CIDR_VERSION(x, m) ((x) & (m))
25#define AT91_CIDR_VERSION_MASK GENMASK(4, 0)
26#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0)
27#define AT91_CIDR_EXT BIT(31)
28#define AT91_CIDR_MATCH_MASK GENMASK(30, 5)
29#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5)
30
31static const struct at91_soc socs[] __initconst = {
32#ifdef CONFIG_SOC_AT91RM9200
33 AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
34 AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),
35#endif
36#ifdef CONFIG_SOC_AT91SAM9
37 AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
38 AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),
39 AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
40 AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),
41 AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
42 AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),
43 AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
44 AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),
45 AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
46 AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),
47 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
48 AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,
49 "at91sam9m11", "at91sam9g45"),
50 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
51 AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,
52 "at91sam9m10", "at91sam9g45"),
53 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
54 AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,
55 "at91sam9g46", "at91sam9g45"),
56 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
57 AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,
58 "at91sam9g45", "at91sam9g45"),
59 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
60 AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,
61 "at91sam9g15", "at91sam9x5"),
62 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
63 AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,
64 "at91sam9g35", "at91sam9x5"),
65 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
66 AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,
67 "at91sam9x35", "at91sam9x5"),
68 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
69 AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,
70 "at91sam9g25", "at91sam9x5"),
71 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
72 AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,
73 "at91sam9x25", "at91sam9x5"),
74 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
75 AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,
76 "at91sam9cn12", "at91sam9n12"),
77 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
78 AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,
79 "at91sam9n12", "at91sam9n12"),
80 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
81 AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,
82 "at91sam9cn11", "at91sam9n12"),
83 AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
84 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),
85 AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
86 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),
87 AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
88 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),
89#endif
90#ifdef CONFIG_SOC_SAM9X60
91 AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
92 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
93 "sam9x60", "sam9x60"),
94 AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
95 AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH,
96 "sam9x60 64MiB DDR2 SiP", "sam9x60"),
97 AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
98 AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH,
99 "sam9x60 128MiB DDR2 SiP", "sam9x60"),
100 AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
101 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
102 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
103#endif
104#ifdef CONFIG_SOC_SAM9X7
105 AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
106 AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,
107 "sam9x70", "sam9x7"),
108 AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
109 AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,
110 "sam9x72", "sam9x7"),
111 AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
112 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
113 "sam9x75", "sam9x7"),
114 AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,
115 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
116 "sam9x75 16MB DDR2 SiP", "sam9x7"),
117 AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,
118 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
119 "sam9x75 64MB DDR2 SiP", "sam9x7"),
120 AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,
121 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
122 "sam9x75 125MB DDR3L SiP ", "sam9x7"),
123 AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,
124 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
125 "sam9x75 250MB DDR3L SiP", "sam9x7"),
126#endif
127#ifdef CONFIG_SOC_SAMA5
128 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
129 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
130 "sama5d21", "sama5d2"),
131 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
132 AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,
133 "sama5d22", "sama5d2"),
134 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
135 AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,
136 "sama5d225c 16MiB SiP", "sama5d2"),
137 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
138 AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,
139 "sama5d23", "sama5d2"),
140 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
141 AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,
142 "sama5d24", "sama5d2"),
143 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
144 AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,
145 "sama5d24", "sama5d2"),
146 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
147 AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,
148 "sama5d26", "sama5d2"),
149 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
150 AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,
151 "sama5d27", "sama5d2"),
152 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
153 AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,
154 "sama5d27", "sama5d2"),
155 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
156 AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,
157 "sama5d27c 128MiB SiP", "sama5d2"),
158 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
159 AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,
160 "sama5d27c 64MiB SiP", "sama5d2"),
161 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
162 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,
163 "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
164 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
165 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,
166 "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
167 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
168 AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,
169 "sama5d28", "sama5d2"),
170 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
171 AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,
172 "sama5d28", "sama5d2"),
173 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
174 AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,
175 "sama5d28c 128MiB SiP", "sama5d2"),
176 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
177 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,
178 "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
179 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
180 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
181 "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
182 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
183 AT91_CIDR_VERSION_MASK, SAMA5D29CN_EXID_MATCH,
184 "sama5d29", "sama5d2"),
185 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
186 AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
187 "sama5d31", "sama5d3"),
188 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
189 AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,
190 "sama5d33", "sama5d3"),
191 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
192 AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,
193 "sama5d34", "sama5d3"),
194 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
195 AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,
196 "sama5d35", "sama5d3"),
197 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
198 AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,
199 "sama5d36", "sama5d3"),
200 AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
201 AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,
202 "sama5d41", "sama5d4"),
203 AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
204 AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,
205 "sama5d42", "sama5d4"),
206 AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
207 AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,
208 "sama5d43", "sama5d4"),
209 AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
210 AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
211 "sama5d44", "sama5d4"),
212#endif
213#ifdef CONFIG_SOC_SAMV7
214 AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
215 AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
216 "same70q21", "same7"),
217 AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
218 AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
219 "same70q20", "same7"),
220 AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
221 AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
222 "same70q19", "same7"),
223 AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
224 AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
225 "sams70q21", "sams7"),
226 AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
227 AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
228 "sams70q20", "sams7"),
229 AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
230 AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
231 "sams70q19", "sams7"),
232 AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
233 AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
234 "samv71q21", "samv7"),
235 AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
236 AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
237 "samv71q20", "samv7"),
238 AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
239 AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
240 "samv71q19", "samv7"),
241 AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
242 AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
243 "samv70q20", "samv7"),
244 AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
245 AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
246 "samv70q19", "samv7"),
247#endif
248#ifdef CONFIG_SOC_SAMA7
249 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
250 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
251 "sama7g51", "sama7g5"),
252 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
253 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,
254 "sama7g52", "sama7g5"),
255 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
256 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,
257 "sama7g53", "sama7g5"),
258 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
259 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
260 "sama7g54", "sama7g5"),
261 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
262 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D1G_EXID_MATCH,
263 "SAMA7G54 1Gb DDR3L SiP", "sama7g5"),
264 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
265 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D2G_EXID_MATCH,
266 "SAMA7G54 2Gb DDR3L SiP", "sama7g5"),
267 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
268 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D4G_EXID_MATCH,
269 "SAMA7G54 4Gb DDR3L SiP", "sama7g5"),
270#endif
271 { /* sentinel */ },
272};
273
274static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
275{
276 struct device_node *np;
277 void __iomem *regs;
278
279 np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
280 if (!np)
281 np = of_find_compatible_node(NULL, NULL,
282 "atmel,at91sam9260-dbgu");
283 if (!np)
284 return -ENODEV;
285
286 regs = of_iomap(np, 0);
287 of_node_put(np);
288
289 if (!regs) {
290 pr_warn("Could not map DBGU iomem range");
291 return -ENXIO;
292 }
293
294 *cidr = readl(regs + AT91_DBGU_CIDR);
295 *exid = readl(regs + AT91_DBGU_EXID);
296
297 iounmap(regs);
298
299 return 0;
300}
301
302static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
303{
304 struct device_node *np;
305 void __iomem *regs;
306 static const struct of_device_id chipids[] = {
307 { .compatible = "atmel,sama5d2-chipid" },
308 { .compatible = "microchip,sama7g5-chipid" },
309 { },
310 };
311
312 np = of_find_matching_node(NULL, chipids);
313 if (!np)
314 return -ENODEV;
315
316 regs = of_iomap(np, 0);
317 of_node_put(np);
318
319 if (!regs) {
320 pr_warn("Could not map DBGU iomem range");
321 return -ENXIO;
322 }
323
324 *cidr = readl(regs + AT91_CHIPID_CIDR);
325 *exid = readl(regs + AT91_CHIPID_EXID);
326
327 iounmap(regs);
328
329 return 0;
330}
331
332struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
333{
334 struct soc_device_attribute *soc_dev_attr;
335 const struct at91_soc *soc;
336 struct soc_device *soc_dev;
337 u32 cidr, exid;
338 int ret;
339
340 /*
341 * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
342 * in the dbgu device but in the chipid device whose purpose is only
343 * to expose these two registers.
344 */
345 ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
346 if (ret)
347 ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
348 if (ret) {
349 if (ret == -ENODEV)
350 pr_warn("Could not find identification node");
351 return NULL;
352 }
353
354 for (soc = socs; soc->name; soc++) {
355 if (soc->cidr_match != (cidr & soc->cidr_mask))
356 continue;
357
358 if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
359 break;
360 }
361
362 if (!soc->name) {
363 pr_warn("Could not find matching SoC description\n");
364 return NULL;
365 }
366
367 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
368 if (!soc_dev_attr)
369 return NULL;
370
371 soc_dev_attr->family = soc->family;
372 soc_dev_attr->soc_id = soc->name;
373 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
374 AT91_CIDR_VERSION(cidr, soc->version_mask));
375 soc_dev = soc_device_register(soc_dev_attr);
376 if (IS_ERR(soc_dev)) {
377 kfree(soc_dev_attr->revision);
378 kfree(soc_dev_attr);
379 pr_warn("Could not register SoC device\n");
380 return NULL;
381 }
382
383 if (soc->family)
384 pr_info("Detected SoC family: %s\n", soc->family);
385 pr_info("Detected SoC: %s, revision %X\n", soc->name,
386 AT91_CIDR_VERSION(cidr, soc->version_mask));
387
388 return soc_dev;
389}
390
391static const struct of_device_id at91_soc_allowed_list[] __initconst = {
392 { .compatible = "atmel,at91rm9200", },
393 { .compatible = "atmel,at91sam9", },
394 { .compatible = "atmel,sama5", },
395 { .compatible = "atmel,samv7", },
396 { .compatible = "microchip,sama7g5", },
397 { }
398};
399
400static int __init atmel_soc_device_init(void)
401{
402 struct device_node *np __free(device_node) = of_find_node_by_path("/");
403
404 if (!of_match_node(at91_soc_allowed_list, np))
405 return 0;
406
407 at91_soc_init(socs);
408
409 return 0;
410}
411subsys_initcall(atmel_soc_device_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Atmel
4 *
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com
6 * Boris Brezillon <boris.brezillon@free-electrons.com
7 */
8
9#define pr_fmt(fmt) "AT91: " fmt
10
11#include <linux/io.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/of_platform.h>
15#include <linux/slab.h>
16#include <linux/sys_soc.h>
17
18#include "soc.h"
19
20#define AT91_DBGU_CIDR 0x40
21#define AT91_DBGU_EXID 0x44
22#define AT91_CHIPID_CIDR 0x00
23#define AT91_CHIPID_EXID 0x04
24#define AT91_CIDR_VERSION(x, m) ((x) & (m))
25#define AT91_CIDR_VERSION_MASK GENMASK(4, 0)
26#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0)
27#define AT91_CIDR_EXT BIT(31)
28#define AT91_CIDR_MATCH_MASK GENMASK(30, 5)
29#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5)
30
31static const struct at91_soc socs[] __initconst = {
32#ifdef CONFIG_SOC_AT91RM9200
33 AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
34 AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),
35#endif
36#ifdef CONFIG_SOC_AT91SAM9
37 AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
38 AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),
39 AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
40 AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),
41 AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
42 AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),
43 AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
44 AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),
45 AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
46 AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),
47 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
48 AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,
49 "at91sam9m11", "at91sam9g45"),
50 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
51 AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,
52 "at91sam9m10", "at91sam9g45"),
53 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
54 AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,
55 "at91sam9g46", "at91sam9g45"),
56 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
57 AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,
58 "at91sam9g45", "at91sam9g45"),
59 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
60 AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,
61 "at91sam9g15", "at91sam9x5"),
62 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
63 AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,
64 "at91sam9g35", "at91sam9x5"),
65 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
66 AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,
67 "at91sam9x35", "at91sam9x5"),
68 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
69 AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,
70 "at91sam9g25", "at91sam9x5"),
71 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
72 AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,
73 "at91sam9x25", "at91sam9x5"),
74 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
75 AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,
76 "at91sam9cn12", "at91sam9n12"),
77 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
78 AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,
79 "at91sam9n12", "at91sam9n12"),
80 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
81 AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,
82 "at91sam9cn11", "at91sam9n12"),
83 AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
84 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),
85 AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
86 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),
87 AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
88 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),
89#endif
90#ifdef CONFIG_SOC_SAM9X60
91 AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
92 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
93 "sam9x60", "sam9x60"),
94 AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
95 AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH,
96 "sam9x60 64MiB DDR2 SiP", "sam9x60"),
97 AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
98 AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH,
99 "sam9x60 128MiB DDR2 SiP", "sam9x60"),
100 AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
101 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
102 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
103#endif
104#ifdef CONFIG_SOC_SAMA5
105 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
106 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
107 "sama5d21", "sama5d2"),
108 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
109 AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,
110 "sama5d22", "sama5d2"),
111 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
112 AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,
113 "sama5d225c 16MiB SiP", "sama5d2"),
114 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
115 AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,
116 "sama5d23", "sama5d2"),
117 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
118 AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,
119 "sama5d24", "sama5d2"),
120 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
121 AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,
122 "sama5d24", "sama5d2"),
123 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
124 AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,
125 "sama5d26", "sama5d2"),
126 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
127 AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,
128 "sama5d27", "sama5d2"),
129 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
130 AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,
131 "sama5d27", "sama5d2"),
132 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
133 AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,
134 "sama5d27c 128MiB SiP", "sama5d2"),
135 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
136 AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,
137 "sama5d27c 64MiB SiP", "sama5d2"),
138 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
139 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,
140 "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
141 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
142 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,
143 "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
144 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
145 AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,
146 "sama5d28", "sama5d2"),
147 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
148 AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,
149 "sama5d28", "sama5d2"),
150 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
151 AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,
152 "sama5d28c 128MiB SiP", "sama5d2"),
153 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
154 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,
155 "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
156 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
157 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
158 "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
159 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
160 AT91_CIDR_VERSION_MASK, SAMA5D29CN_EXID_MATCH,
161 "sama5d29", "sama5d2"),
162 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
163 AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
164 "sama5d31", "sama5d3"),
165 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
166 AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,
167 "sama5d33", "sama5d3"),
168 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
169 AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,
170 "sama5d34", "sama5d3"),
171 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
172 AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,
173 "sama5d35", "sama5d3"),
174 AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
175 AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,
176 "sama5d36", "sama5d3"),
177 AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
178 AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,
179 "sama5d41", "sama5d4"),
180 AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
181 AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,
182 "sama5d42", "sama5d4"),
183 AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
184 AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,
185 "sama5d43", "sama5d4"),
186 AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
187 AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
188 "sama5d44", "sama5d4"),
189#endif
190#ifdef CONFIG_SOC_SAMV7
191 AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
192 AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
193 "same70q21", "same7"),
194 AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
195 AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
196 "same70q20", "same7"),
197 AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
198 AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
199 "same70q19", "same7"),
200 AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
201 AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
202 "sams70q21", "sams7"),
203 AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
204 AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
205 "sams70q20", "sams7"),
206 AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
207 AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
208 "sams70q19", "sams7"),
209 AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
210 AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
211 "samv71q21", "samv7"),
212 AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
213 AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
214 "samv71q20", "samv7"),
215 AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
216 AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
217 "samv71q19", "samv7"),
218 AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
219 AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
220 "samv70q20", "samv7"),
221 AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
222 AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
223 "samv70q19", "samv7"),
224#endif
225#ifdef CONFIG_SOC_SAMA7
226 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
227 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
228 "sama7g51", "sama7g5"),
229 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
230 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,
231 "sama7g52", "sama7g5"),
232 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
233 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,
234 "sama7g53", "sama7g5"),
235 AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
236 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
237 "sama7g54", "sama7g5"),
238#endif
239 { /* sentinel */ },
240};
241
242static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
243{
244 struct device_node *np;
245 void __iomem *regs;
246
247 np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
248 if (!np)
249 np = of_find_compatible_node(NULL, NULL,
250 "atmel,at91sam9260-dbgu");
251 if (!np)
252 return -ENODEV;
253
254 regs = of_iomap(np, 0);
255 of_node_put(np);
256
257 if (!regs) {
258 pr_warn("Could not map DBGU iomem range");
259 return -ENXIO;
260 }
261
262 *cidr = readl(regs + AT91_DBGU_CIDR);
263 *exid = readl(regs + AT91_DBGU_EXID);
264
265 iounmap(regs);
266
267 return 0;
268}
269
270static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
271{
272 struct device_node *np;
273 void __iomem *regs;
274 static const struct of_device_id chipids[] = {
275 { .compatible = "atmel,sama5d2-chipid" },
276 { .compatible = "microchip,sama7g5-chipid" },
277 { },
278 };
279
280 np = of_find_matching_node(NULL, chipids);
281 if (!np)
282 return -ENODEV;
283
284 regs = of_iomap(np, 0);
285 of_node_put(np);
286
287 if (!regs) {
288 pr_warn("Could not map DBGU iomem range");
289 return -ENXIO;
290 }
291
292 *cidr = readl(regs + AT91_CHIPID_CIDR);
293 *exid = readl(regs + AT91_CHIPID_EXID);
294
295 iounmap(regs);
296
297 return 0;
298}
299
300struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
301{
302 struct soc_device_attribute *soc_dev_attr;
303 const struct at91_soc *soc;
304 struct soc_device *soc_dev;
305 u32 cidr, exid;
306 int ret;
307
308 /*
309 * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
310 * in the dbgu device but in the chipid device whose purpose is only
311 * to expose these two registers.
312 */
313 ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
314 if (ret)
315 ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
316 if (ret) {
317 if (ret == -ENODEV)
318 pr_warn("Could not find identification node");
319 return NULL;
320 }
321
322 for (soc = socs; soc->name; soc++) {
323 if (soc->cidr_match != (cidr & soc->cidr_mask))
324 continue;
325
326 if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
327 break;
328 }
329
330 if (!soc->name) {
331 pr_warn("Could not find matching SoC description\n");
332 return NULL;
333 }
334
335 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
336 if (!soc_dev_attr)
337 return NULL;
338
339 soc_dev_attr->family = soc->family;
340 soc_dev_attr->soc_id = soc->name;
341 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
342 AT91_CIDR_VERSION(cidr, soc->version_mask));
343 soc_dev = soc_device_register(soc_dev_attr);
344 if (IS_ERR(soc_dev)) {
345 kfree(soc_dev_attr->revision);
346 kfree(soc_dev_attr);
347 pr_warn("Could not register SoC device\n");
348 return NULL;
349 }
350
351 if (soc->family)
352 pr_info("Detected SoC family: %s\n", soc->family);
353 pr_info("Detected SoC: %s, revision %X\n", soc->name,
354 AT91_CIDR_VERSION(cidr, soc->version_mask));
355
356 return soc_dev;
357}
358
359static const struct of_device_id at91_soc_allowed_list[] __initconst = {
360 { .compatible = "atmel,at91rm9200", },
361 { .compatible = "atmel,at91sam9", },
362 { .compatible = "atmel,sama5", },
363 { .compatible = "atmel,samv7", },
364 { .compatible = "microchip,sama7g5", },
365 { }
366};
367
368static int __init atmel_soc_device_init(void)
369{
370 struct device_node *np = of_find_node_by_path("/");
371
372 if (!of_match_node(at91_soc_allowed_list, np))
373 return 0;
374
375 at91_soc_init(socs);
376
377 return 0;
378}
379subsys_initcall(atmel_soc_device_init);