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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DesignWare PWM Controller driver (PCI part)
4 *
5 * Copyright (C) 2018-2020 Intel Corporation
6 *
7 * Author: Felipe Balbi (Intel)
8 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
9 * Author: Raymond Tan <raymond.tan@intel.com>
10 *
11 * Limitations:
12 * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low
13 * periods are one or more input clock periods long.
14 */
15
16#define DEFAULT_MOUDLE_NAMESPACE dwc_pwm
17
18#include <linux/bitops.h>
19#include <linux/export.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/pm_runtime.h>
24#include <linux/pwm.h>
25
26#include "pwm-dwc.h"
27
28/* Elkhart Lake */
29static const struct dwc_pwm_info ehl_pwm_info = {
30 .nr = 2,
31 .size = 0x1000,
32};
33
34static int dwc_pwm_init_one(struct device *dev, struct dwc_pwm_drvdata *ddata, unsigned int idx)
35{
36 struct pwm_chip *chip;
37 struct dwc_pwm *dwc;
38 int ret;
39
40 chip = dwc_pwm_alloc(dev);
41 if (IS_ERR(chip))
42 return PTR_ERR(chip);
43
44 dwc = to_dwc_pwm(chip);
45 dwc->base = ddata->io_base + (ddata->info->size * idx);
46
47 ret = devm_pwmchip_add(dev, chip);
48 if (ret)
49 return ret;
50
51 ddata->chips[idx] = chip;
52 return 0;
53}
54
55static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id)
56{
57 const struct dwc_pwm_info *info;
58 struct device *dev = &pci->dev;
59 struct dwc_pwm_drvdata *ddata;
60 unsigned int idx;
61 int ret;
62
63 ret = pcim_enable_device(pci);
64 if (ret)
65 return dev_err_probe(dev, ret, "Failed to enable device\n");
66
67 pci_set_master(pci);
68
69 ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci));
70 if (ret)
71 return dev_err_probe(dev, ret, "Failed to iomap PCI BAR\n");
72
73 info = (const struct dwc_pwm_info *)id->driver_data;
74 ddata = devm_kzalloc(dev, struct_size(ddata, chips, info->nr), GFP_KERNEL);
75 if (!ddata)
76 return -ENOMEM;
77
78 /*
79 * No need to check for pcim_iomap_table() failure,
80 * pcim_iomap_regions() already does it for us.
81 */
82 ddata->io_base = pcim_iomap_table(pci)[0];
83 ddata->info = info;
84
85 for (idx = 0; idx < ddata->info->nr; idx++) {
86 ret = dwc_pwm_init_one(dev, ddata, idx);
87 if (ret)
88 return ret;
89 }
90
91 dev_set_drvdata(dev, ddata);
92
93 pm_runtime_put(dev);
94 pm_runtime_allow(dev);
95
96 return 0;
97}
98
99static void dwc_pwm_remove(struct pci_dev *pci)
100{
101 pm_runtime_forbid(&pci->dev);
102 pm_runtime_get_noresume(&pci->dev);
103}
104
105static int dwc_pwm_suspend(struct device *dev)
106{
107 struct dwc_pwm_drvdata *ddata = dev_get_drvdata(dev);
108 unsigned int idx;
109
110 for (idx = 0; idx < ddata->info->nr; idx++) {
111 struct pwm_chip *chip = ddata->chips[idx];
112 struct dwc_pwm *dwc = to_dwc_pwm(chip);
113 unsigned int i;
114
115 for (i = 0; i < DWC_TIMERS_TOTAL; i++) {
116 if (chip->pwms[i].state.enabled) {
117 dev_err(dev, "PWM %u in use by consumer (%s)\n",
118 i, chip->pwms[i].label);
119 return -EBUSY;
120 }
121 dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i));
122 dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i));
123 dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i));
124 }
125 }
126
127 return 0;
128}
129
130static int dwc_pwm_resume(struct device *dev)
131{
132 struct dwc_pwm_drvdata *ddata = dev_get_drvdata(dev);
133 unsigned int idx;
134
135 for (idx = 0; idx < ddata->info->nr; idx++) {
136 struct pwm_chip *chip = ddata->chips[idx];
137 struct dwc_pwm *dwc = to_dwc_pwm(chip);
138 unsigned int i;
139
140 for (i = 0; i < DWC_TIMERS_TOTAL; i++) {
141 dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i));
142 dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i));
143 dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i));
144 }
145 }
146
147 return 0;
148}
149
150static DEFINE_SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume);
151
152static const struct pci_device_id dwc_pwm_id_table[] = {
153 { PCI_VDEVICE(INTEL, 0x4bb7), (kernel_ulong_t)&ehl_pwm_info },
154 { } /* Terminating Entry */
155};
156MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table);
157
158static struct pci_driver dwc_pwm_driver = {
159 .name = "pwm-dwc",
160 .probe = dwc_pwm_probe,
161 .remove = dwc_pwm_remove,
162 .id_table = dwc_pwm_id_table,
163 .driver = {
164 .pm = pm_sleep_ptr(&dwc_pwm_pm_ops),
165 },
166};
167
168module_pci_driver(dwc_pwm_driver);
169
170MODULE_AUTHOR("Felipe Balbi (Intel)");
171MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
172MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
173MODULE_DESCRIPTION("DesignWare PWM Controller");
174MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DesignWare PWM Controller driver
4 *
5 * Copyright (C) 2018-2020 Intel Corporation
6 *
7 * Author: Felipe Balbi (Intel)
8 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
9 * Author: Raymond Tan <raymond.tan@intel.com>
10 *
11 * Limitations:
12 * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low
13 * periods are one or more input clock periods long.
14 */
15
16#include <linux/bitops.h>
17#include <linux/export.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/pm_runtime.h>
22#include <linux/pwm.h>
23
24#define DWC_TIM_LD_CNT(n) ((n) * 0x14)
25#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0)
26#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04)
27#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08)
28#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c)
29#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10)
30
31#define DWC_TIMERS_INT_STS 0xa0
32#define DWC_TIMERS_EOI 0xa4
33#define DWC_TIMERS_RAW_INT_STS 0xa8
34#define DWC_TIMERS_COMP_VERSION 0xac
35
36#define DWC_TIMERS_TOTAL 8
37#define DWC_CLK_PERIOD_NS 10
38
39/* Timer Control Register */
40#define DWC_TIM_CTRL_EN BIT(0)
41#define DWC_TIM_CTRL_MODE BIT(1)
42#define DWC_TIM_CTRL_MODE_FREE (0 << 1)
43#define DWC_TIM_CTRL_MODE_USER (1 << 1)
44#define DWC_TIM_CTRL_INT_MASK BIT(2)
45#define DWC_TIM_CTRL_PWM BIT(3)
46
47struct dwc_pwm_ctx {
48 u32 cnt;
49 u32 cnt2;
50 u32 ctrl;
51};
52
53struct dwc_pwm {
54 struct pwm_chip chip;
55 void __iomem *base;
56 struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL];
57};
58#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip))
59
60static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset)
61{
62 return readl(dwc->base + offset);
63}
64
65static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset)
66{
67 writel(value, dwc->base + offset);
68}
69
70static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled)
71{
72 u32 reg;
73
74 reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm));
75
76 if (enabled)
77 reg |= DWC_TIM_CTRL_EN;
78 else
79 reg &= ~DWC_TIM_CTRL_EN;
80
81 dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm));
82}
83
84static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
85 struct pwm_device *pwm,
86 const struct pwm_state *state)
87{
88 u64 tmp;
89 u32 ctrl;
90 u32 high;
91 u32 low;
92
93 /*
94 * Calculate width of low and high period in terms of input clock
95 * periods and check are the result within HW limits between 1 and
96 * 2^32 periods.
97 */
98 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS);
99 if (tmp < 1 || tmp > (1ULL << 32))
100 return -ERANGE;
101 low = tmp - 1;
102
103 tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
104 DWC_CLK_PERIOD_NS);
105 if (tmp < 1 || tmp > (1ULL << 32))
106 return -ERANGE;
107 high = tmp - 1;
108
109 /*
110 * Specification says timer usage flow is to disable timer, then
111 * program it followed by enable. It also says Load Count is loaded
112 * into timer after it is enabled - either after a disable or
113 * a reset. Based on measurements it happens also without disable
114 * whenever Load Count is updated. But follow the specification.
115 */
116 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
117
118 /*
119 * Write Load Count and Load Count 2 registers. Former defines the
120 * width of low period and latter the width of high period in terms
121 * multiple of input clock periods:
122 * Width = ((Count + 1) * input clock period).
123 */
124 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
125 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));
126
127 /*
128 * Set user-defined mode, timer reloads from Load Count registers
129 * when it counts down to 0.
130 * Set PWM mode, it makes output to toggle and width of low and high
131 * periods are set by Load Count registers.
132 */
133 ctrl = DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM;
134 dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));
135
136 /*
137 * Enable timer. Output starts from low period.
138 */
139 __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled);
140
141 return 0;
142}
143
144static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
145 const struct pwm_state *state)
146{
147 struct dwc_pwm *dwc = to_dwc_pwm(chip);
148
149 if (state->polarity != PWM_POLARITY_INVERSED)
150 return -EINVAL;
151
152 if (state->enabled) {
153 if (!pwm->state.enabled)
154 pm_runtime_get_sync(chip->dev);
155 return __dwc_pwm_configure_timer(dwc, pwm, state);
156 } else {
157 if (pwm->state.enabled) {
158 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
159 pm_runtime_put_sync(chip->dev);
160 }
161 }
162
163 return 0;
164}
165
166static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
167 struct pwm_state *state)
168{
169 struct dwc_pwm *dwc = to_dwc_pwm(chip);
170 u64 duty, period;
171
172 pm_runtime_get_sync(chip->dev);
173
174 state->enabled = !!(dwc_pwm_readl(dwc,
175 DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN);
176
177 duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
178 duty += 1;
179 duty *= DWC_CLK_PERIOD_NS;
180 state->duty_cycle = duty;
181
182 period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
183 period += 1;
184 period *= DWC_CLK_PERIOD_NS;
185 period += duty;
186 state->period = period;
187
188 state->polarity = PWM_POLARITY_INVERSED;
189
190 pm_runtime_put_sync(chip->dev);
191
192 return 0;
193}
194
195static const struct pwm_ops dwc_pwm_ops = {
196 .apply = dwc_pwm_apply,
197 .get_state = dwc_pwm_get_state,
198 .owner = THIS_MODULE,
199};
200
201static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id)
202{
203 struct device *dev = &pci->dev;
204 struct dwc_pwm *dwc;
205 int ret;
206
207 dwc = devm_kzalloc(&pci->dev, sizeof(*dwc), GFP_KERNEL);
208 if (!dwc)
209 return -ENOMEM;
210
211 ret = pcim_enable_device(pci);
212 if (ret) {
213 dev_err(&pci->dev,
214 "Failed to enable device (%pe)\n", ERR_PTR(ret));
215 return ret;
216 }
217
218 pci_set_master(pci);
219
220 ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci));
221 if (ret) {
222 dev_err(&pci->dev,
223 "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret));
224 return ret;
225 }
226
227 dwc->base = pcim_iomap_table(pci)[0];
228 if (!dwc->base) {
229 dev_err(&pci->dev, "Base address missing\n");
230 return -ENOMEM;
231 }
232
233 pci_set_drvdata(pci, dwc);
234
235 dwc->chip.dev = dev;
236 dwc->chip.ops = &dwc_pwm_ops;
237 dwc->chip.npwm = DWC_TIMERS_TOTAL;
238
239 ret = pwmchip_add(&dwc->chip);
240 if (ret)
241 return ret;
242
243 pm_runtime_put(dev);
244 pm_runtime_allow(dev);
245
246 return 0;
247}
248
249static void dwc_pwm_remove(struct pci_dev *pci)
250{
251 struct dwc_pwm *dwc = pci_get_drvdata(pci);
252
253 pm_runtime_forbid(&pci->dev);
254 pm_runtime_get_noresume(&pci->dev);
255
256 pwmchip_remove(&dwc->chip);
257}
258
259#ifdef CONFIG_PM_SLEEP
260static int dwc_pwm_suspend(struct device *dev)
261{
262 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
263 struct dwc_pwm *dwc = pci_get_drvdata(pdev);
264 int i;
265
266 for (i = 0; i < DWC_TIMERS_TOTAL; i++) {
267 if (dwc->chip.pwms[i].state.enabled) {
268 dev_err(dev, "PWM %u in use by consumer (%s)\n",
269 i, dwc->chip.pwms[i].label);
270 return -EBUSY;
271 }
272 dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i));
273 dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i));
274 dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i));
275 }
276
277 return 0;
278}
279
280static int dwc_pwm_resume(struct device *dev)
281{
282 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
283 struct dwc_pwm *dwc = pci_get_drvdata(pdev);
284 int i;
285
286 for (i = 0; i < DWC_TIMERS_TOTAL; i++) {
287 dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i));
288 dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i));
289 dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i));
290 }
291
292 return 0;
293}
294#endif
295
296static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume);
297
298static const struct pci_device_id dwc_pwm_id_table[] = {
299 { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */
300 { } /* Terminating Entry */
301};
302MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table);
303
304static struct pci_driver dwc_pwm_driver = {
305 .name = "pwm-dwc",
306 .probe = dwc_pwm_probe,
307 .remove = dwc_pwm_remove,
308 .id_table = dwc_pwm_id_table,
309 .driver = {
310 .pm = &dwc_pwm_pm_ops,
311 },
312};
313
314module_pci_driver(dwc_pwm_driver);
315
316MODULE_AUTHOR("Felipe Balbi (Intel)");
317MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
318MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
319MODULE_DESCRIPTION("DesignWare PWM Controller");
320MODULE_LICENSE("GPL");