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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm PCIe root complex driver
4 *
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
7 *
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
9 */
10
11#include <linux/clk.h>
12#include <linux/crc8.h>
13#include <linux/debugfs.h>
14#include <linux/delay.h>
15#include <linux/gpio/consumer.h>
16#include <linux/interconnect.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/kernel.h>
21#include <linux/limits.h>
22#include <linux/init.h>
23#include <linux/of.h>
24#include <linux/pci.h>
25#include <linux/pm_opp.h>
26#include <linux/pm_runtime.h>
27#include <linux/platform_device.h>
28#include <linux/phy/pcie.h>
29#include <linux/phy/phy.h>
30#include <linux/regulator/consumer.h>
31#include <linux/reset.h>
32#include <linux/slab.h>
33#include <linux/types.h>
34#include <linux/units.h>
35
36#include "../../pci.h"
37#include "pcie-designware.h"
38#include "pcie-qcom-common.h"
39
40/* PARF registers */
41#define PARF_SYS_CTRL 0x00
42#define PARF_PM_CTRL 0x20
43#define PARF_PCS_DEEMPH 0x34
44#define PARF_PCS_SWING 0x38
45#define PARF_PHY_CTRL 0x40
46#define PARF_PHY_REFCLK 0x4c
47#define PARF_CONFIG_BITS 0x50
48#define PARF_DBI_BASE_ADDR 0x168
49#define PARF_SLV_ADDR_SPACE_SIZE 0x16c
50#define PARF_MHI_CLOCK_RESET_CTRL 0x174
51#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178
52#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
53#define PARF_Q2A_FLUSH 0x1ac
54#define PARF_LTSSM 0x1b0
55#define PARF_INT_ALL_STATUS 0x224
56#define PARF_INT_ALL_CLEAR 0x228
57#define PARF_INT_ALL_MASK 0x22c
58#define PARF_SID_OFFSET 0x234
59#define PARF_BDF_TRANSLATE_CFG 0x24c
60#define PARF_DBI_BASE_ADDR_V2 0x350
61#define PARF_DBI_BASE_ADDR_V2_HI 0x354
62#define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358
63#define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c
64#define PARF_NO_SNOOP_OVERIDE 0x3d4
65#define PARF_ATU_BASE_ADDR 0x634
66#define PARF_ATU_BASE_ADDR_HI 0x638
67#define PARF_DEVICE_TYPE 0x1000
68#define PARF_BDF_TO_SID_TABLE_N 0x2000
69#define PARF_BDF_TO_SID_CFG 0x2c00
70
71/* ELBI registers */
72#define ELBI_SYS_CTRL 0x04
73
74/* DBI registers */
75#define AXI_MSTR_RESP_COMP_CTRL0 0x818
76#define AXI_MSTR_RESP_COMP_CTRL1 0x81c
77
78/* MHI registers */
79#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
80#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
81#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
82#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
83#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
84
85/* PARF_SYS_CTRL register fields */
86#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
87#define MST_WAKEUP_EN BIT(13)
88#define SLV_WAKEUP_EN BIT(12)
89#define MSTR_ACLK_CGC_DIS BIT(10)
90#define SLV_ACLK_CGC_DIS BIT(9)
91#define CORE_CLK_CGC_DIS BIT(6)
92#define AUX_PWR_DET BIT(4)
93#define L23_CLK_RMV_DIS BIT(2)
94#define L1_CLK_RMV_DIS BIT(1)
95
96/* PARF_PM_CTRL register fields */
97#define REQ_NOT_ENTR_L1 BIT(5)
98
99/* PARF_PCS_DEEMPH register fields */
100#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)
101#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)
102#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
103
104/* PARF_PCS_SWING register fields */
105#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)
106#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
107
108/* PARF_PHY_CTRL register fields */
109#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
110#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
111#define PHY_TEST_PWR_DOWN BIT(0)
112
113/* PARF_PHY_REFCLK register fields */
114#define PHY_REFCLK_SSP_EN BIT(16)
115#define PHY_REFCLK_USE_PAD BIT(12)
116
117/* PARF_CONFIG_BITS register fields */
118#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)
119
120/* PARF_SLV_ADDR_SPACE_SIZE register value */
121#define SLV_ADDR_SPACE_SZ 0x80000000
122
123/* PARF_MHI_CLOCK_RESET_CTRL register fields */
124#define AHB_CLK_EN BIT(0)
125#define MSTR_AXI_CLK_EN BIT(1)
126#define BYPASS BIT(4)
127
128/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
129#define EN BIT(31)
130
131/* PARF_LTSSM register fields */
132#define LTSSM_EN BIT(8)
133
134/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
135#define PARF_INT_ALL_LINK_UP BIT(13)
136#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
137
138/* PARF_NO_SNOOP_OVERIDE register fields */
139#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
140#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
141
142/* PARF_DEVICE_TYPE register fields */
143#define DEVICE_TYPE_RC 0x4
144
145/* PARF_BDF_TO_SID_CFG fields */
146#define BDF_TO_SID_BYPASS BIT(0)
147
148/* ELBI_SYS_CTRL register fields */
149#define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
150
151/* AXI_MSTR_RESP_COMP_CTRL0 register fields */
152#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
153#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
154
155/* AXI_MSTR_RESP_COMP_CTRL1 register fields */
156#define CFG_BRIDGE_SB_INIT BIT(0)
157
158/* PCI_EXP_SLTCAP register fields */
159#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
160#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
161#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
162 PCI_EXP_SLTCAP_PCP | \
163 PCI_EXP_SLTCAP_MRLSP | \
164 PCI_EXP_SLTCAP_AIP | \
165 PCI_EXP_SLTCAP_PIP | \
166 PCI_EXP_SLTCAP_HPS | \
167 PCI_EXP_SLTCAP_EIP | \
168 PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
169 PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
170
171#define PERST_DELAY_US 1000
172
173#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
174
175#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
176 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
177
178struct qcom_pcie_resources_1_0_0 {
179 struct clk_bulk_data *clks;
180 int num_clks;
181 struct reset_control *core;
182 struct regulator *vdda;
183};
184
185#define QCOM_PCIE_2_1_0_MAX_RESETS 6
186#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
187struct qcom_pcie_resources_2_1_0 {
188 struct clk_bulk_data *clks;
189 int num_clks;
190 struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS];
191 int num_resets;
192 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
193};
194
195#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
196struct qcom_pcie_resources_2_3_2 {
197 struct clk_bulk_data *clks;
198 int num_clks;
199 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
200};
201
202#define QCOM_PCIE_2_3_3_MAX_RESETS 7
203struct qcom_pcie_resources_2_3_3 {
204 struct clk_bulk_data *clks;
205 int num_clks;
206 struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS];
207};
208
209#define QCOM_PCIE_2_4_0_MAX_RESETS 12
210struct qcom_pcie_resources_2_4_0 {
211 struct clk_bulk_data *clks;
212 int num_clks;
213 struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS];
214 int num_resets;
215};
216
217#define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2
218struct qcom_pcie_resources_2_7_0 {
219 struct clk_bulk_data *clks;
220 int num_clks;
221 struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES];
222 struct reset_control *rst;
223};
224
225struct qcom_pcie_resources_2_9_0 {
226 struct clk_bulk_data *clks;
227 int num_clks;
228 struct reset_control *rst;
229};
230
231union qcom_pcie_resources {
232 struct qcom_pcie_resources_1_0_0 v1_0_0;
233 struct qcom_pcie_resources_2_1_0 v2_1_0;
234 struct qcom_pcie_resources_2_3_2 v2_3_2;
235 struct qcom_pcie_resources_2_3_3 v2_3_3;
236 struct qcom_pcie_resources_2_4_0 v2_4_0;
237 struct qcom_pcie_resources_2_7_0 v2_7_0;
238 struct qcom_pcie_resources_2_9_0 v2_9_0;
239};
240
241struct qcom_pcie;
242
243struct qcom_pcie_ops {
244 int (*get_resources)(struct qcom_pcie *pcie);
245 int (*init)(struct qcom_pcie *pcie);
246 int (*post_init)(struct qcom_pcie *pcie);
247 void (*host_post_init)(struct qcom_pcie *pcie);
248 void (*deinit)(struct qcom_pcie *pcie);
249 void (*ltssm_enable)(struct qcom_pcie *pcie);
250 int (*config_sid)(struct qcom_pcie *pcie);
251};
252
253 /**
254 * struct qcom_pcie_cfg - Per SoC config struct
255 * @ops: qcom PCIe ops structure
256 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache
257 * snooping
258 */
259struct qcom_pcie_cfg {
260 const struct qcom_pcie_ops *ops;
261 bool override_no_snoop;
262 bool no_l0s;
263};
264
265struct qcom_pcie {
266 struct dw_pcie *pci;
267 void __iomem *parf; /* DT parf */
268 void __iomem *elbi; /* DT elbi */
269 void __iomem *mhi;
270 union qcom_pcie_resources res;
271 struct phy *phy;
272 struct gpio_desc *reset;
273 struct icc_path *icc_mem;
274 struct icc_path *icc_cpu;
275 const struct qcom_pcie_cfg *cfg;
276 struct dentry *debugfs;
277 bool suspended;
278 bool use_pm_opp;
279};
280
281#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
282
283static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
284{
285 gpiod_set_value_cansleep(pcie->reset, 1);
286 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
287}
288
289static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
290{
291 /* Ensure that PERST has been asserted for at least 100 ms */
292 msleep(100);
293 gpiod_set_value_cansleep(pcie->reset, 0);
294 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
295}
296
297static int qcom_pcie_start_link(struct dw_pcie *pci)
298{
299 struct qcom_pcie *pcie = to_qcom_pcie(pci);
300
301 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
302 qcom_pcie_common_set_16gt_equalization(pci);
303 qcom_pcie_common_set_16gt_lane_margining(pci);
304 }
305
306 /* Enable Link Training state machine */
307 if (pcie->cfg->ops->ltssm_enable)
308 pcie->cfg->ops->ltssm_enable(pcie);
309
310 return 0;
311}
312
313static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci)
314{
315 struct qcom_pcie *pcie = to_qcom_pcie(pci);
316 u16 offset;
317 u32 val;
318
319 if (!pcie->cfg->no_l0s)
320 return;
321
322 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
323
324 dw_pcie_dbi_ro_wr_en(pci);
325
326 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
327 val &= ~PCI_EXP_LNKCAP_ASPM_L0S;
328 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
329
330 dw_pcie_dbi_ro_wr_dis(pci);
331}
332
333static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
334{
335 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
336 u32 val;
337
338 dw_pcie_dbi_ro_wr_en(pci);
339
340 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
341 val &= ~PCI_EXP_SLTCAP_HPC;
342 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
343
344 dw_pcie_dbi_ro_wr_dis(pci);
345}
346
347static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie)
348{
349 struct dw_pcie *pci = pcie->pci;
350
351 if (pci->dbi_phys_addr) {
352 /*
353 * PARF_DBI_BASE_ADDR register is in CPU domain and require to
354 * be programmed with CPU physical address.
355 */
356 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +
357 PARF_DBI_BASE_ADDR);
358 writel(SLV_ADDR_SPACE_SZ, pcie->parf +
359 PARF_SLV_ADDR_SPACE_SIZE);
360 }
361}
362
363static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie)
364{
365 struct dw_pcie *pci = pcie->pci;
366
367 if (pci->dbi_phys_addr) {
368 /*
369 * PARF_DBI_BASE_ADDR_V2 and PARF_ATU_BASE_ADDR registers are
370 * in CPU domain and require to be programmed with CPU
371 * physical addresses.
372 */
373 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +
374 PARF_DBI_BASE_ADDR_V2);
375 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf +
376 PARF_DBI_BASE_ADDR_V2_HI);
377
378 if (pci->atu_phys_addr) {
379 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf +
380 PARF_ATU_BASE_ADDR);
381 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf +
382 PARF_ATU_BASE_ADDR_HI);
383 }
384
385 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2);
386 writel(SLV_ADDR_SPACE_SZ, pcie->parf +
387 PARF_SLV_ADDR_SPACE_SIZE_V2_HI);
388 }
389}
390
391static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
392{
393 u32 val;
394
395 /* enable link training */
396 val = readl(pcie->elbi + ELBI_SYS_CTRL);
397 val |= ELBI_SYS_CTRL_LT_ENABLE;
398 writel(val, pcie->elbi + ELBI_SYS_CTRL);
399}
400
401static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
402{
403 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
404 struct dw_pcie *pci = pcie->pci;
405 struct device *dev = pci->dev;
406 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064");
407 int ret;
408
409 res->supplies[0].supply = "vdda";
410 res->supplies[1].supply = "vdda_phy";
411 res->supplies[2].supply = "vdda_refclk";
412 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
413 res->supplies);
414 if (ret)
415 return ret;
416
417 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
418 if (res->num_clks < 0) {
419 dev_err(dev, "Failed to get clocks\n");
420 return res->num_clks;
421 }
422
423 res->resets[0].id = "pci";
424 res->resets[1].id = "axi";
425 res->resets[2].id = "ahb";
426 res->resets[3].id = "por";
427 res->resets[4].id = "phy";
428 res->resets[5].id = "ext";
429
430 /* ext is optional on APQ8016 */
431 res->num_resets = is_apq ? 5 : 6;
432 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets);
433 if (ret < 0)
434 return ret;
435
436 return 0;
437}
438
439static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
440{
441 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
442
443 clk_bulk_disable_unprepare(res->num_clks, res->clks);
444 reset_control_bulk_assert(res->num_resets, res->resets);
445
446 writel(1, pcie->parf + PARF_PHY_CTRL);
447
448 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
449}
450
451static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
452{
453 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
454 struct dw_pcie *pci = pcie->pci;
455 struct device *dev = pci->dev;
456 int ret;
457
458 /* reset the PCIe interface as uboot can leave it undefined state */
459 ret = reset_control_bulk_assert(res->num_resets, res->resets);
460 if (ret < 0) {
461 dev_err(dev, "cannot assert resets\n");
462 return ret;
463 }
464
465 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
466 if (ret < 0) {
467 dev_err(dev, "cannot enable regulators\n");
468 return ret;
469 }
470
471 ret = reset_control_bulk_deassert(res->num_resets, res->resets);
472 if (ret < 0) {
473 dev_err(dev, "cannot deassert resets\n");
474 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
475 return ret;
476 }
477
478 return 0;
479}
480
481static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
482{
483 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
484 struct dw_pcie *pci = pcie->pci;
485 struct device *dev = pci->dev;
486 struct device_node *node = dev->of_node;
487 u32 val;
488 int ret;
489
490 /* enable PCIe clocks and resets */
491 val = readl(pcie->parf + PARF_PHY_CTRL);
492 val &= ~PHY_TEST_PWR_DOWN;
493 writel(val, pcie->parf + PARF_PHY_CTRL);
494
495 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
496 if (ret)
497 return ret;
498
499 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
500 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
501 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
502 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
503 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
504 pcie->parf + PARF_PCS_DEEMPH);
505 writel(PCS_SWING_TX_SWING_FULL(120) |
506 PCS_SWING_TX_SWING_LOW(120),
507 pcie->parf + PARF_PCS_SWING);
508 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
509 }
510
511 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
512 /* set TX termination offset */
513 val = readl(pcie->parf + PARF_PHY_CTRL);
514 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
515 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
516 writel(val, pcie->parf + PARF_PHY_CTRL);
517 }
518
519 /* enable external reference clock */
520 val = readl(pcie->parf + PARF_PHY_REFCLK);
521 /* USE_PAD is required only for ipq806x */
522 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
523 val &= ~PHY_REFCLK_USE_PAD;
524 val |= PHY_REFCLK_SSP_EN;
525 writel(val, pcie->parf + PARF_PHY_REFCLK);
526
527 /* wait for clock acquisition */
528 usleep_range(1000, 1500);
529
530 /* Set the Max TLP size to 2K, instead of using default of 4K */
531 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
532 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0);
533 writel(CFG_BRIDGE_SB_INIT,
534 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
535
536 qcom_pcie_clear_hpc(pcie->pci);
537
538 return 0;
539}
540
541static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
542{
543 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
544 struct dw_pcie *pci = pcie->pci;
545 struct device *dev = pci->dev;
546
547 res->vdda = devm_regulator_get(dev, "vdda");
548 if (IS_ERR(res->vdda))
549 return PTR_ERR(res->vdda);
550
551 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
552 if (res->num_clks < 0) {
553 dev_err(dev, "Failed to get clocks\n");
554 return res->num_clks;
555 }
556
557 res->core = devm_reset_control_get_exclusive(dev, "core");
558 return PTR_ERR_OR_ZERO(res->core);
559}
560
561static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
562{
563 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
564
565 reset_control_assert(res->core);
566 clk_bulk_disable_unprepare(res->num_clks, res->clks);
567 regulator_disable(res->vdda);
568}
569
570static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
571{
572 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
573 struct dw_pcie *pci = pcie->pci;
574 struct device *dev = pci->dev;
575 int ret;
576
577 ret = reset_control_deassert(res->core);
578 if (ret) {
579 dev_err(dev, "cannot deassert core reset\n");
580 return ret;
581 }
582
583 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
584 if (ret) {
585 dev_err(dev, "cannot prepare/enable clocks\n");
586 goto err_assert_reset;
587 }
588
589 ret = regulator_enable(res->vdda);
590 if (ret) {
591 dev_err(dev, "cannot enable vdda regulator\n");
592 goto err_disable_clks;
593 }
594
595 return 0;
596
597err_disable_clks:
598 clk_bulk_disable_unprepare(res->num_clks, res->clks);
599err_assert_reset:
600 reset_control_assert(res->core);
601
602 return ret;
603}
604
605static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
606{
607 qcom_pcie_configure_dbi_base(pcie);
608
609 if (IS_ENABLED(CONFIG_PCI_MSI)) {
610 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
611
612 val |= EN;
613 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
614 }
615
616 qcom_pcie_clear_hpc(pcie->pci);
617
618 return 0;
619}
620
621static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
622{
623 u32 val;
624
625 /* enable link training */
626 val = readl(pcie->parf + PARF_LTSSM);
627 val |= LTSSM_EN;
628 writel(val, pcie->parf + PARF_LTSSM);
629}
630
631static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
632{
633 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
634 struct dw_pcie *pci = pcie->pci;
635 struct device *dev = pci->dev;
636 int ret;
637
638 res->supplies[0].supply = "vdda";
639 res->supplies[1].supply = "vddpe-3v3";
640 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
641 res->supplies);
642 if (ret)
643 return ret;
644
645 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
646 if (res->num_clks < 0) {
647 dev_err(dev, "Failed to get clocks\n");
648 return res->num_clks;
649 }
650
651 return 0;
652}
653
654static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
655{
656 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
657
658 clk_bulk_disable_unprepare(res->num_clks, res->clks);
659 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
660}
661
662static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
663{
664 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
665 struct dw_pcie *pci = pcie->pci;
666 struct device *dev = pci->dev;
667 int ret;
668
669 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
670 if (ret < 0) {
671 dev_err(dev, "cannot enable regulators\n");
672 return ret;
673 }
674
675 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
676 if (ret) {
677 dev_err(dev, "cannot prepare/enable clocks\n");
678 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
679 return ret;
680 }
681
682 return 0;
683}
684
685static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
686{
687 u32 val;
688
689 /* enable PCIe clocks and resets */
690 val = readl(pcie->parf + PARF_PHY_CTRL);
691 val &= ~PHY_TEST_PWR_DOWN;
692 writel(val, pcie->parf + PARF_PHY_CTRL);
693
694 qcom_pcie_configure_dbi_base(pcie);
695
696 /* MAC PHY_POWERDOWN MUX DISABLE */
697 val = readl(pcie->parf + PARF_SYS_CTRL);
698 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
699 writel(val, pcie->parf + PARF_SYS_CTRL);
700
701 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
702 val |= BYPASS;
703 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
704
705 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
706 val |= EN;
707 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
708
709 qcom_pcie_clear_hpc(pcie->pci);
710
711 return 0;
712}
713
714static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
715{
716 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
717 struct dw_pcie *pci = pcie->pci;
718 struct device *dev = pci->dev;
719 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
720 int ret;
721
722 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
723 if (res->num_clks < 0) {
724 dev_err(dev, "Failed to get clocks\n");
725 return res->num_clks;
726 }
727
728 res->resets[0].id = "axi_m";
729 res->resets[1].id = "axi_s";
730 res->resets[2].id = "axi_m_sticky";
731 res->resets[3].id = "pipe_sticky";
732 res->resets[4].id = "pwr";
733 res->resets[5].id = "ahb";
734 res->resets[6].id = "pipe";
735 res->resets[7].id = "axi_m_vmid";
736 res->resets[8].id = "axi_s_xpu";
737 res->resets[9].id = "parf";
738 res->resets[10].id = "phy";
739 res->resets[11].id = "phy_ahb";
740
741 res->num_resets = is_ipq ? 12 : 6;
742
743 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets);
744 if (ret < 0)
745 return ret;
746
747 return 0;
748}
749
750static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
751{
752 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
753
754 reset_control_bulk_assert(res->num_resets, res->resets);
755 clk_bulk_disable_unprepare(res->num_clks, res->clks);
756}
757
758static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
759{
760 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
761 struct dw_pcie *pci = pcie->pci;
762 struct device *dev = pci->dev;
763 int ret;
764
765 ret = reset_control_bulk_assert(res->num_resets, res->resets);
766 if (ret < 0) {
767 dev_err(dev, "cannot assert resets\n");
768 return ret;
769 }
770
771 usleep_range(10000, 12000);
772
773 ret = reset_control_bulk_deassert(res->num_resets, res->resets);
774 if (ret < 0) {
775 dev_err(dev, "cannot deassert resets\n");
776 return ret;
777 }
778
779 usleep_range(10000, 12000);
780
781 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
782 if (ret) {
783 reset_control_bulk_assert(res->num_resets, res->resets);
784 return ret;
785 }
786
787 return 0;
788}
789
790static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
791{
792 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
793 struct dw_pcie *pci = pcie->pci;
794 struct device *dev = pci->dev;
795 int ret;
796
797 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
798 if (res->num_clks < 0) {
799 dev_err(dev, "Failed to get clocks\n");
800 return res->num_clks;
801 }
802
803 res->rst[0].id = "axi_m";
804 res->rst[1].id = "axi_s";
805 res->rst[2].id = "pipe";
806 res->rst[3].id = "axi_m_sticky";
807 res->rst[4].id = "sticky";
808 res->rst[5].id = "ahb";
809 res->rst[6].id = "sleep";
810
811 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst);
812 if (ret < 0)
813 return ret;
814
815 return 0;
816}
817
818static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
819{
820 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
821
822 clk_bulk_disable_unprepare(res->num_clks, res->clks);
823}
824
825static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
826{
827 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
828 struct dw_pcie *pci = pcie->pci;
829 struct device *dev = pci->dev;
830 int ret;
831
832 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
833 if (ret < 0) {
834 dev_err(dev, "cannot assert resets\n");
835 return ret;
836 }
837
838 usleep_range(2000, 2500);
839
840 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst);
841 if (ret < 0) {
842 dev_err(dev, "cannot deassert resets\n");
843 return ret;
844 }
845
846 /*
847 * Don't have a way to see if the reset has completed.
848 * Wait for some time.
849 */
850 usleep_range(2000, 2500);
851
852 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
853 if (ret) {
854 dev_err(dev, "cannot prepare/enable clocks\n");
855 goto err_assert_resets;
856 }
857
858 return 0;
859
860err_assert_resets:
861 /*
862 * Not checking for failure, will anyway return
863 * the original failure in 'ret'.
864 */
865 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
866
867 return ret;
868}
869
870static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
871{
872 struct dw_pcie *pci = pcie->pci;
873 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
874 u32 val;
875
876 val = readl(pcie->parf + PARF_PHY_CTRL);
877 val &= ~PHY_TEST_PWR_DOWN;
878 writel(val, pcie->parf + PARF_PHY_CTRL);
879
880 qcom_pcie_configure_dbi_atu_base(pcie);
881
882 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
883 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
884 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
885 pcie->parf + PARF_SYS_CTRL);
886 writel(0, pcie->parf + PARF_Q2A_FLUSH);
887
888 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
889
890 dw_pcie_dbi_ro_wr_en(pci);
891
892 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
893
894 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
895 val &= ~PCI_EXP_LNKCAP_ASPMS;
896 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
897
898 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
899 PCI_EXP_DEVCTL2);
900
901 dw_pcie_dbi_ro_wr_dis(pci);
902
903 return 0;
904}
905
906static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
907{
908 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
909 struct dw_pcie *pci = pcie->pci;
910 struct device *dev = pci->dev;
911 int ret;
912
913 res->rst = devm_reset_control_array_get_exclusive(dev);
914 if (IS_ERR(res->rst))
915 return PTR_ERR(res->rst);
916
917 res->supplies[0].supply = "vdda";
918 res->supplies[1].supply = "vddpe-3v3";
919 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
920 res->supplies);
921 if (ret)
922 return ret;
923
924 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
925 if (res->num_clks < 0) {
926 dev_err(dev, "Failed to get clocks\n");
927 return res->num_clks;
928 }
929
930 return 0;
931}
932
933static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
934{
935 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
936 struct dw_pcie *pci = pcie->pci;
937 struct device *dev = pci->dev;
938 u32 val;
939 int ret;
940
941 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
942 if (ret < 0) {
943 dev_err(dev, "cannot enable regulators\n");
944 return ret;
945 }
946
947 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
948 if (ret < 0)
949 goto err_disable_regulators;
950
951 ret = reset_control_assert(res->rst);
952 if (ret) {
953 dev_err(dev, "reset assert failed (%d)\n", ret);
954 goto err_disable_clocks;
955 }
956
957 usleep_range(1000, 1500);
958
959 ret = reset_control_deassert(res->rst);
960 if (ret) {
961 dev_err(dev, "reset deassert failed (%d)\n", ret);
962 goto err_disable_clocks;
963 }
964
965 /* Wait for reset to complete, required on SM8450 */
966 usleep_range(1000, 1500);
967
968 /* configure PCIe to RC mode */
969 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
970
971 /* enable PCIe clocks and resets */
972 val = readl(pcie->parf + PARF_PHY_CTRL);
973 val &= ~PHY_TEST_PWR_DOWN;
974 writel(val, pcie->parf + PARF_PHY_CTRL);
975
976 qcom_pcie_configure_dbi_atu_base(pcie);
977
978 /* MAC PHY_POWERDOWN MUX DISABLE */
979 val = readl(pcie->parf + PARF_SYS_CTRL);
980 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
981 writel(val, pcie->parf + PARF_SYS_CTRL);
982
983 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
984 val |= BYPASS;
985 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
986
987 /* Enable L1 and L1SS */
988 val = readl(pcie->parf + PARF_PM_CTRL);
989 val &= ~REQ_NOT_ENTR_L1;
990 writel(val, pcie->parf + PARF_PM_CTRL);
991
992 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
993 val |= EN;
994 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
995
996 return 0;
997err_disable_clocks:
998 clk_bulk_disable_unprepare(res->num_clks, res->clks);
999err_disable_regulators:
1000 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1001
1002 return ret;
1003}
1004
1005static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
1006{
1007 const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
1008
1009 if (pcie_cfg->override_no_snoop)
1010 writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
1011 pcie->parf + PARF_NO_SNOOP_OVERIDE);
1012
1013 qcom_pcie_clear_aspm_l0s(pcie->pci);
1014 qcom_pcie_clear_hpc(pcie->pci);
1015
1016 return 0;
1017}
1018
1019static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata)
1020{
1021 /*
1022 * Downstream devices need to be in D0 state before enabling PCI PM
1023 * substates.
1024 */
1025 pci_set_power_state_locked(pdev, PCI_D0);
1026 pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
1027
1028 return 0;
1029}
1030
1031static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)
1032{
1033 struct dw_pcie_rp *pp = &pcie->pci->pp;
1034
1035 pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL);
1036}
1037
1038static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1039{
1040 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1041
1042 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1043
1044 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1045}
1046
1047static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie)
1048{
1049 /* iommu map structure */
1050 struct {
1051 u32 bdf;
1052 u32 phandle;
1053 u32 smmu_sid;
1054 u32 smmu_sid_len;
1055 } *map;
1056 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;
1057 struct device *dev = pcie->pci->dev;
1058 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
1059 int i, nr_map, size = 0;
1060 u32 smmu_sid_base;
1061 u32 val;
1062
1063 of_get_property(dev->of_node, "iommu-map", &size);
1064 if (!size)
1065 return 0;
1066
1067 /* Enable BDF to SID translation by disabling bypass mode (default) */
1068 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);
1069 val &= ~BDF_TO_SID_BYPASS;
1070 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
1071
1072 map = kzalloc(size, GFP_KERNEL);
1073 if (!map)
1074 return -ENOMEM;
1075
1076 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map,
1077 size / sizeof(u32));
1078
1079 nr_map = size / (sizeof(*map));
1080
1081 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
1082
1083 /* Registers need to be zero out first */
1084 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
1085
1086 /* Extract the SMMU SID base from the first entry of iommu-map */
1087 smmu_sid_base = map[0].smmu_sid;
1088
1089 /* Look for an available entry to hold the mapping */
1090 for (i = 0; i < nr_map; i++) {
1091 __be16 bdf_be = cpu_to_be16(map[i].bdf);
1092 u32 val;
1093 u8 hash;
1094
1095 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0);
1096
1097 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1098
1099 /* If the register is already populated, look for next available entry */
1100 while (val) {
1101 u8 current_hash = hash++;
1102 u8 next_mask = 0xff;
1103
1104 /* If NEXT field is NULL then update it with next hash */
1105 if (!(val & next_mask)) {
1106 val |= (u32)hash;
1107 writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
1108 }
1109
1110 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1111 }
1112
1113 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
1114 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
1115 writel(val, bdf_to_sid_base + hash * sizeof(u32));
1116 }
1117
1118 kfree(map);
1119
1120 return 0;
1121}
1122
1123static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
1124{
1125 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1126 struct dw_pcie *pci = pcie->pci;
1127 struct device *dev = pci->dev;
1128
1129 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
1130 if (res->num_clks < 0) {
1131 dev_err(dev, "Failed to get clocks\n");
1132 return res->num_clks;
1133 }
1134
1135 res->rst = devm_reset_control_array_get_exclusive(dev);
1136 if (IS_ERR(res->rst))
1137 return PTR_ERR(res->rst);
1138
1139 return 0;
1140}
1141
1142static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
1143{
1144 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1145
1146 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1147}
1148
1149static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
1150{
1151 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1152 struct device *dev = pcie->pci->dev;
1153 int ret;
1154
1155 ret = reset_control_assert(res->rst);
1156 if (ret) {
1157 dev_err(dev, "reset assert failed (%d)\n", ret);
1158 return ret;
1159 }
1160
1161 /*
1162 * Delay periods before and after reset deassert are working values
1163 * from downstream Codeaurora kernel
1164 */
1165 usleep_range(2000, 2500);
1166
1167 ret = reset_control_deassert(res->rst);
1168 if (ret) {
1169 dev_err(dev, "reset deassert failed (%d)\n", ret);
1170 return ret;
1171 }
1172
1173 usleep_range(2000, 2500);
1174
1175 return clk_bulk_prepare_enable(res->num_clks, res->clks);
1176}
1177
1178static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
1179{
1180 struct dw_pcie *pci = pcie->pci;
1181 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1182 u32 val;
1183 int i;
1184
1185 val = readl(pcie->parf + PARF_PHY_CTRL);
1186 val &= ~PHY_TEST_PWR_DOWN;
1187 writel(val, pcie->parf + PARF_PHY_CTRL);
1188
1189 qcom_pcie_configure_dbi_atu_base(pcie);
1190
1191 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1192 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
1193 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1194 writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
1195 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
1196 pci->dbi_base + GEN3_RELATED_OFF);
1197
1198 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
1199 SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1200 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1201 pcie->parf + PARF_SYS_CTRL);
1202
1203 writel(0, pcie->parf + PARF_Q2A_FLUSH);
1204
1205 dw_pcie_dbi_ro_wr_en(pci);
1206
1207 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1208
1209 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1210 val &= ~PCI_EXP_LNKCAP_ASPMS;
1211 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1212
1213 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1214 PCI_EXP_DEVCTL2);
1215
1216 dw_pcie_dbi_ro_wr_dis(pci);
1217
1218 for (i = 0; i < 256; i++)
1219 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
1220
1221 return 0;
1222}
1223
1224static int qcom_pcie_link_up(struct dw_pcie *pci)
1225{
1226 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1227 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1228
1229 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1230}
1231
1232static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
1233{
1234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1235 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1236 int ret;
1237
1238 qcom_ep_reset_assert(pcie);
1239
1240 ret = pcie->cfg->ops->init(pcie);
1241 if (ret)
1242 return ret;
1243
1244 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
1245 if (ret)
1246 goto err_deinit;
1247
1248 ret = phy_power_on(pcie->phy);
1249 if (ret)
1250 goto err_deinit;
1251
1252 if (pcie->cfg->ops->post_init) {
1253 ret = pcie->cfg->ops->post_init(pcie);
1254 if (ret)
1255 goto err_disable_phy;
1256 }
1257
1258 qcom_ep_reset_deassert(pcie);
1259
1260 if (pcie->cfg->ops->config_sid) {
1261 ret = pcie->cfg->ops->config_sid(pcie);
1262 if (ret)
1263 goto err_assert_reset;
1264 }
1265
1266 return 0;
1267
1268err_assert_reset:
1269 qcom_ep_reset_assert(pcie);
1270err_disable_phy:
1271 phy_power_off(pcie->phy);
1272err_deinit:
1273 pcie->cfg->ops->deinit(pcie);
1274
1275 return ret;
1276}
1277
1278static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp)
1279{
1280 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1281 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1282
1283 qcom_ep_reset_assert(pcie);
1284 phy_power_off(pcie->phy);
1285 pcie->cfg->ops->deinit(pcie);
1286}
1287
1288static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp)
1289{
1290 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1291 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1292
1293 if (pcie->cfg->ops->host_post_init)
1294 pcie->cfg->ops->host_post_init(pcie);
1295}
1296
1297static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1298 .init = qcom_pcie_host_init,
1299 .deinit = qcom_pcie_host_deinit,
1300 .post_init = qcom_pcie_host_post_init,
1301};
1302
1303/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1304static const struct qcom_pcie_ops ops_2_1_0 = {
1305 .get_resources = qcom_pcie_get_resources_2_1_0,
1306 .init = qcom_pcie_init_2_1_0,
1307 .post_init = qcom_pcie_post_init_2_1_0,
1308 .deinit = qcom_pcie_deinit_2_1_0,
1309 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1310};
1311
1312/* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1313static const struct qcom_pcie_ops ops_1_0_0 = {
1314 .get_resources = qcom_pcie_get_resources_1_0_0,
1315 .init = qcom_pcie_init_1_0_0,
1316 .post_init = qcom_pcie_post_init_1_0_0,
1317 .deinit = qcom_pcie_deinit_1_0_0,
1318 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1319};
1320
1321/* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1322static const struct qcom_pcie_ops ops_2_3_2 = {
1323 .get_resources = qcom_pcie_get_resources_2_3_2,
1324 .init = qcom_pcie_init_2_3_2,
1325 .post_init = qcom_pcie_post_init_2_3_2,
1326 .deinit = qcom_pcie_deinit_2_3_2,
1327 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1328};
1329
1330/* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1331static const struct qcom_pcie_ops ops_2_4_0 = {
1332 .get_resources = qcom_pcie_get_resources_2_4_0,
1333 .init = qcom_pcie_init_2_4_0,
1334 .post_init = qcom_pcie_post_init_2_3_2,
1335 .deinit = qcom_pcie_deinit_2_4_0,
1336 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1337};
1338
1339/* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1340static const struct qcom_pcie_ops ops_2_3_3 = {
1341 .get_resources = qcom_pcie_get_resources_2_3_3,
1342 .init = qcom_pcie_init_2_3_3,
1343 .post_init = qcom_pcie_post_init_2_3_3,
1344 .deinit = qcom_pcie_deinit_2_3_3,
1345 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1346};
1347
1348/* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1349static const struct qcom_pcie_ops ops_2_7_0 = {
1350 .get_resources = qcom_pcie_get_resources_2_7_0,
1351 .init = qcom_pcie_init_2_7_0,
1352 .post_init = qcom_pcie_post_init_2_7_0,
1353 .deinit = qcom_pcie_deinit_2_7_0,
1354 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1355};
1356
1357/* Qcom IP rev.: 1.9.0 */
1358static const struct qcom_pcie_ops ops_1_9_0 = {
1359 .get_resources = qcom_pcie_get_resources_2_7_0,
1360 .init = qcom_pcie_init_2_7_0,
1361 .post_init = qcom_pcie_post_init_2_7_0,
1362 .host_post_init = qcom_pcie_host_post_init_2_7_0,
1363 .deinit = qcom_pcie_deinit_2_7_0,
1364 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1365 .config_sid = qcom_pcie_config_sid_1_9_0,
1366};
1367
1368/* Qcom IP rev.: 1.21.0 Synopsys IP rev.: 5.60a */
1369static const struct qcom_pcie_ops ops_1_21_0 = {
1370 .get_resources = qcom_pcie_get_resources_2_7_0,
1371 .init = qcom_pcie_init_2_7_0,
1372 .post_init = qcom_pcie_post_init_2_7_0,
1373 .host_post_init = qcom_pcie_host_post_init_2_7_0,
1374 .deinit = qcom_pcie_deinit_2_7_0,
1375 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1376};
1377
1378/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
1379static const struct qcom_pcie_ops ops_2_9_0 = {
1380 .get_resources = qcom_pcie_get_resources_2_9_0,
1381 .init = qcom_pcie_init_2_9_0,
1382 .post_init = qcom_pcie_post_init_2_9_0,
1383 .deinit = qcom_pcie_deinit_2_9_0,
1384 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1385};
1386
1387static const struct qcom_pcie_cfg cfg_1_0_0 = {
1388 .ops = &ops_1_0_0,
1389};
1390
1391static const struct qcom_pcie_cfg cfg_1_9_0 = {
1392 .ops = &ops_1_9_0,
1393};
1394
1395static const struct qcom_pcie_cfg cfg_1_34_0 = {
1396 .ops = &ops_1_9_0,
1397 .override_no_snoop = true,
1398};
1399
1400static const struct qcom_pcie_cfg cfg_2_1_0 = {
1401 .ops = &ops_2_1_0,
1402};
1403
1404static const struct qcom_pcie_cfg cfg_2_3_2 = {
1405 .ops = &ops_2_3_2,
1406};
1407
1408static const struct qcom_pcie_cfg cfg_2_3_3 = {
1409 .ops = &ops_2_3_3,
1410};
1411
1412static const struct qcom_pcie_cfg cfg_2_4_0 = {
1413 .ops = &ops_2_4_0,
1414};
1415
1416static const struct qcom_pcie_cfg cfg_2_7_0 = {
1417 .ops = &ops_2_7_0,
1418};
1419
1420static const struct qcom_pcie_cfg cfg_2_9_0 = {
1421 .ops = &ops_2_9_0,
1422};
1423
1424static const struct qcom_pcie_cfg cfg_sc8280xp = {
1425 .ops = &ops_1_21_0,
1426 .no_l0s = true,
1427};
1428
1429static const struct dw_pcie_ops dw_pcie_ops = {
1430 .link_up = qcom_pcie_link_up,
1431 .start_link = qcom_pcie_start_link,
1432};
1433
1434static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
1435{
1436 struct dw_pcie *pci = pcie->pci;
1437 int ret;
1438
1439 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem");
1440 if (IS_ERR(pcie->icc_mem))
1441 return PTR_ERR(pcie->icc_mem);
1442
1443 pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie");
1444 if (IS_ERR(pcie->icc_cpu))
1445 return PTR_ERR(pcie->icc_cpu);
1446 /*
1447 * Some Qualcomm platforms require interconnect bandwidth constraints
1448 * to be set before enabling interconnect clocks.
1449 *
1450 * Set an initial peak bandwidth corresponding to single-lane Gen 1
1451 * for the pcie-mem path.
1452 */
1453 ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
1454 if (ret) {
1455 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
1456 ret);
1457 return ret;
1458 }
1459
1460 /*
1461 * Since the CPU-PCIe path is only used for activities like register
1462 * access of the host controller and endpoint Config/BAR space access,
1463 * HW team has recommended to use a minimal bandwidth of 1KBps just to
1464 * keep the path active.
1465 */
1466 ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1));
1467 if (ret) {
1468 dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n",
1469 ret);
1470 icc_set_bw(pcie->icc_mem, 0, 0);
1471 return ret;
1472 }
1473
1474 return 0;
1475}
1476
1477static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie)
1478{
1479 u32 offset, status, width, speed;
1480 struct dw_pcie *pci = pcie->pci;
1481 unsigned long freq_kbps;
1482 struct dev_pm_opp *opp;
1483 int ret, freq_mbps;
1484
1485 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1486 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1487
1488 /* Only update constraints if link is up. */
1489 if (!(status & PCI_EXP_LNKSTA_DLLLA))
1490 return;
1491
1492 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
1493 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
1494
1495 if (pcie->icc_mem) {
1496 ret = icc_set_bw(pcie->icc_mem, 0,
1497 width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
1498 if (ret) {
1499 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
1500 ret);
1501 }
1502 } else if (pcie->use_pm_opp) {
1503 freq_mbps = pcie_dev_speed_mbps(pcie_link_speed[speed]);
1504 if (freq_mbps < 0)
1505 return;
1506
1507 freq_kbps = freq_mbps * KILO;
1508 opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width,
1509 true);
1510 if (!IS_ERR(opp)) {
1511 ret = dev_pm_opp_set_opp(pci->dev, opp);
1512 if (ret)
1513 dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n",
1514 freq_kbps * width, ret);
1515 dev_pm_opp_put(opp);
1516 }
1517 }
1518}
1519
1520static int qcom_pcie_link_transition_count(struct seq_file *s, void *data)
1521{
1522 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private);
1523
1524 seq_printf(s, "L0s transition count: %u\n",
1525 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
1526
1527 seq_printf(s, "L1 transition count: %u\n",
1528 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
1529
1530 seq_printf(s, "L1.1 transition count: %u\n",
1531 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
1532
1533 seq_printf(s, "L1.2 transition count: %u\n",
1534 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
1535
1536 seq_printf(s, "L2 transition count: %u\n",
1537 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
1538
1539 return 0;
1540}
1541
1542static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie)
1543{
1544 struct dw_pcie *pci = pcie->pci;
1545 struct device *dev = pci->dev;
1546 char *name;
1547
1548 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
1549 if (!name)
1550 return;
1551
1552 pcie->debugfs = debugfs_create_dir(name, NULL);
1553 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs,
1554 qcom_pcie_link_transition_count);
1555}
1556
1557static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data)
1558{
1559 struct qcom_pcie *pcie = data;
1560 struct dw_pcie_rp *pp = &pcie->pci->pp;
1561 struct device *dev = pcie->pci->dev;
1562 u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS);
1563
1564 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR);
1565
1566 if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
1567 dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
1568 /* Rescan the bus to enumerate endpoint devices */
1569 pci_lock_rescan_remove();
1570 pci_rescan_bus(pp->bridge->bus);
1571 pci_unlock_rescan_remove();
1572
1573 qcom_pcie_icc_opp_update(pcie);
1574 } else {
1575 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n",
1576 status);
1577 }
1578
1579 return IRQ_HANDLED;
1580}
1581
1582static int qcom_pcie_probe(struct platform_device *pdev)
1583{
1584 const struct qcom_pcie_cfg *pcie_cfg;
1585 unsigned long max_freq = ULONG_MAX;
1586 struct device *dev = &pdev->dev;
1587 struct dev_pm_opp *opp;
1588 struct qcom_pcie *pcie;
1589 struct dw_pcie_rp *pp;
1590 struct resource *res;
1591 struct dw_pcie *pci;
1592 int ret, irq;
1593 char *name;
1594
1595 pcie_cfg = of_device_get_match_data(dev);
1596 if (!pcie_cfg || !pcie_cfg->ops) {
1597 dev_err(dev, "Invalid platform data\n");
1598 return -EINVAL;
1599 }
1600
1601 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1602 if (!pcie)
1603 return -ENOMEM;
1604
1605 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1606 if (!pci)
1607 return -ENOMEM;
1608
1609 pm_runtime_enable(dev);
1610 ret = pm_runtime_get_sync(dev);
1611 if (ret < 0)
1612 goto err_pm_runtime_put;
1613
1614 pci->dev = dev;
1615 pci->ops = &dw_pcie_ops;
1616 pp = &pci->pp;
1617
1618 pcie->pci = pci;
1619
1620 pcie->cfg = pcie_cfg;
1621
1622 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1623 if (IS_ERR(pcie->reset)) {
1624 ret = PTR_ERR(pcie->reset);
1625 goto err_pm_runtime_put;
1626 }
1627
1628 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1629 if (IS_ERR(pcie->parf)) {
1630 ret = PTR_ERR(pcie->parf);
1631 goto err_pm_runtime_put;
1632 }
1633
1634 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1635 if (IS_ERR(pcie->elbi)) {
1636 ret = PTR_ERR(pcie->elbi);
1637 goto err_pm_runtime_put;
1638 }
1639
1640 /* MHI region is optional */
1641 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi");
1642 if (res) {
1643 pcie->mhi = devm_ioremap_resource(dev, res);
1644 if (IS_ERR(pcie->mhi)) {
1645 ret = PTR_ERR(pcie->mhi);
1646 goto err_pm_runtime_put;
1647 }
1648 }
1649
1650 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1651 if (IS_ERR(pcie->phy)) {
1652 ret = PTR_ERR(pcie->phy);
1653 goto err_pm_runtime_put;
1654 }
1655
1656 /* OPP table is optional */
1657 ret = devm_pm_opp_of_add_table(dev);
1658 if (ret && ret != -ENODEV) {
1659 dev_err_probe(dev, ret, "Failed to add OPP table\n");
1660 goto err_pm_runtime_put;
1661 }
1662
1663 /*
1664 * Before the PCIe link is initialized, vote for highest OPP in the OPP
1665 * table, so that we are voting for maximum voltage corner for the
1666 * link to come up in maximum supported speed. At the end of the
1667 * probe(), OPP will be updated using qcom_pcie_icc_opp_update().
1668 */
1669 if (!ret) {
1670 opp = dev_pm_opp_find_freq_floor(dev, &max_freq);
1671 if (IS_ERR(opp)) {
1672 ret = PTR_ERR(opp);
1673 dev_err_probe(pci->dev, ret,
1674 "Unable to find max freq OPP\n");
1675 goto err_pm_runtime_put;
1676 } else {
1677 ret = dev_pm_opp_set_opp(dev, opp);
1678 }
1679
1680 dev_pm_opp_put(opp);
1681 if (ret) {
1682 dev_err_probe(pci->dev, ret,
1683 "Failed to set OPP for freq %lu\n",
1684 max_freq);
1685 goto err_pm_runtime_put;
1686 }
1687
1688 pcie->use_pm_opp = true;
1689 } else {
1690 /* Skip ICC init if OPP is supported as it is handled by OPP */
1691 ret = qcom_pcie_icc_init(pcie);
1692 if (ret)
1693 goto err_pm_runtime_put;
1694 }
1695
1696 ret = pcie->cfg->ops->get_resources(pcie);
1697 if (ret)
1698 goto err_pm_runtime_put;
1699
1700 pp->ops = &qcom_pcie_dw_ops;
1701
1702 ret = phy_init(pcie->phy);
1703 if (ret)
1704 goto err_pm_runtime_put;
1705
1706 platform_set_drvdata(pdev, pcie);
1707
1708 ret = dw_pcie_host_init(pp);
1709 if (ret) {
1710 dev_err(dev, "cannot initialize host\n");
1711 goto err_phy_exit;
1712 }
1713
1714 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d",
1715 pci_domain_nr(pp->bridge->bus));
1716 if (!name) {
1717 ret = -ENOMEM;
1718 goto err_host_deinit;
1719 }
1720
1721 irq = platform_get_irq_byname_optional(pdev, "global");
1722 if (irq > 0) {
1723 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1724 qcom_pcie_global_irq_thread,
1725 IRQF_ONESHOT, name, pcie);
1726 if (ret) {
1727 dev_err_probe(&pdev->dev, ret,
1728 "Failed to request Global IRQ\n");
1729 goto err_host_deinit;
1730 }
1731
1732 writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7,
1733 pcie->parf + PARF_INT_ALL_MASK);
1734 }
1735
1736 qcom_pcie_icc_opp_update(pcie);
1737
1738 if (pcie->mhi)
1739 qcom_pcie_init_debugfs(pcie);
1740
1741 return 0;
1742
1743err_host_deinit:
1744 dw_pcie_host_deinit(pp);
1745err_phy_exit:
1746 phy_exit(pcie->phy);
1747err_pm_runtime_put:
1748 pm_runtime_put(dev);
1749 pm_runtime_disable(dev);
1750
1751 return ret;
1752}
1753
1754static int qcom_pcie_suspend_noirq(struct device *dev)
1755{
1756 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1757 int ret = 0;
1758
1759 /*
1760 * Set minimum bandwidth required to keep data path functional during
1761 * suspend.
1762 */
1763 if (pcie->icc_mem) {
1764 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
1765 if (ret) {
1766 dev_err(dev,
1767 "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
1768 ret);
1769 return ret;
1770 }
1771 }
1772
1773 /*
1774 * Turn OFF the resources only for controllers without active PCIe
1775 * devices. For controllers with active devices, the resources are kept
1776 * ON and the link is expected to be in L0/L1 (sub)states.
1777 *
1778 * Turning OFF the resources for controllers with active PCIe devices
1779 * will trigger access violation during the end of the suspend cycle,
1780 * as kernel tries to access the PCIe devices config space for masking
1781 * MSIs.
1782 *
1783 * Also, it is not desirable to put the link into L2/L3 state as that
1784 * implies VDD supply will be removed and the devices may go into
1785 * powerdown state. This will affect the lifetime of the storage devices
1786 * like NVMe.
1787 */
1788 if (!dw_pcie_link_up(pcie->pci)) {
1789 qcom_pcie_host_deinit(&pcie->pci->pp);
1790 pcie->suspended = true;
1791 }
1792
1793 /*
1794 * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM.
1795 * Because on some platforms, DBI access can happen very late during the
1796 * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC
1797 * error.
1798 */
1799 if (pm_suspend_target_state != PM_SUSPEND_MEM) {
1800 ret = icc_disable(pcie->icc_cpu);
1801 if (ret)
1802 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret);
1803
1804 if (pcie->use_pm_opp)
1805 dev_pm_opp_set_opp(pcie->pci->dev, NULL);
1806 }
1807 return ret;
1808}
1809
1810static int qcom_pcie_resume_noirq(struct device *dev)
1811{
1812 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1813 int ret;
1814
1815 if (pm_suspend_target_state != PM_SUSPEND_MEM) {
1816 ret = icc_enable(pcie->icc_cpu);
1817 if (ret) {
1818 dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret);
1819 return ret;
1820 }
1821 }
1822
1823 if (pcie->suspended) {
1824 ret = qcom_pcie_host_init(&pcie->pci->pp);
1825 if (ret)
1826 return ret;
1827
1828 pcie->suspended = false;
1829 }
1830
1831 qcom_pcie_icc_opp_update(pcie);
1832
1833 return 0;
1834}
1835
1836static const struct of_device_id qcom_pcie_match[] = {
1837 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1838 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1839 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1840 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1841 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1842 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1843 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1844 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1845 { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
1846 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1847 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1848 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
1849 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
1850 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1851 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1852 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
1853 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1854 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1855 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1856 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1857 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1858 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1859 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1860 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1861 { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
1862 { }
1863};
1864
1865static void qcom_fixup_class(struct pci_dev *dev)
1866{
1867 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
1868}
1869DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1870DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1871DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1872DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1873DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1874DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1875DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1876
1877static const struct dev_pm_ops qcom_pcie_pm_ops = {
1878 NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq)
1879};
1880
1881static struct platform_driver qcom_pcie_driver = {
1882 .probe = qcom_pcie_probe,
1883 .driver = {
1884 .name = "qcom-pcie",
1885 .suppress_bind_attrs = true,
1886 .of_match_table = qcom_pcie_match,
1887 .pm = &qcom_pcie_pm_ops,
1888 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1889 },
1890};
1891builtin_platform_driver(qcom_pcie_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm PCIe root complex driver
4 *
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
7 *
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
9 */
10
11#include <linux/clk.h>
12#include <linux/crc8.h>
13#include <linux/delay.h>
14#include <linux/gpio/consumer.h>
15#include <linux/interconnect.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/of_device.h>
22#include <linux/of_gpio.h>
23#include <linux/pci.h>
24#include <linux/pm_runtime.h>
25#include <linux/platform_device.h>
26#include <linux/phy/pcie.h>
27#include <linux/phy/phy.h>
28#include <linux/regulator/consumer.h>
29#include <linux/reset.h>
30#include <linux/slab.h>
31#include <linux/types.h>
32
33#include "../../pci.h"
34#include "pcie-designware.h"
35
36#define PCIE20_PARF_SYS_CTRL 0x00
37#define MST_WAKEUP_EN BIT(13)
38#define SLV_WAKEUP_EN BIT(12)
39#define MSTR_ACLK_CGC_DIS BIT(10)
40#define SLV_ACLK_CGC_DIS BIT(9)
41#define CORE_CLK_CGC_DIS BIT(6)
42#define AUX_PWR_DET BIT(4)
43#define L23_CLK_RMV_DIS BIT(2)
44#define L1_CLK_RMV_DIS BIT(1)
45
46#define PCIE20_PARF_PM_CTRL 0x20
47#define REQ_NOT_ENTR_L1 BIT(5)
48
49#define PCIE20_PARF_PHY_CTRL 0x40
50#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
51#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
52
53#define PCIE20_PARF_PHY_REFCLK 0x4C
54#define PHY_REFCLK_SSP_EN BIT(16)
55#define PHY_REFCLK_USE_PAD BIT(12)
56
57#define PCIE20_PARF_DBI_BASE_ADDR 0x168
58#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
59#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
60#define AHB_CLK_EN BIT(0)
61#define MSTR_AXI_CLK_EN BIT(1)
62#define BYPASS BIT(4)
63
64#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
65#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
66#define PCIE20_PARF_LTSSM 0x1B0
67#define PCIE20_PARF_SID_OFFSET 0x234
68#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
69#define PCIE20_PARF_DEVICE_TYPE 0x1000
70#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000
71
72#define PCIE20_ELBI_SYS_CTRL 0x04
73#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
74
75#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
76#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
77#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
78#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
79#define CFG_BRIDGE_SB_INIT BIT(0)
80
81#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \
82 250)
83#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \
84 1)
85#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
86 PCI_EXP_SLTCAP_PCP | \
87 PCI_EXP_SLTCAP_MRLSP | \
88 PCI_EXP_SLTCAP_AIP | \
89 PCI_EXP_SLTCAP_PIP | \
90 PCI_EXP_SLTCAP_HPS | \
91 PCI_EXP_SLTCAP_HPC | \
92 PCI_EXP_SLTCAP_EIP | \
93 PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
94 PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
95
96#define PCIE20_PARF_Q2A_FLUSH 0x1AC
97
98#define PCIE20_MISC_CONTROL_1_REG 0x8BC
99#define DBI_RO_WR_EN 1
100
101#define PERST_DELAY_US 1000
102/* PARF registers */
103#define PCIE20_PARF_PCS_DEEMPH 0x34
104#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
105#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
106#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
107
108#define PCIE20_PARF_PCS_SWING 0x38
109#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
110#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
111
112#define PCIE20_PARF_CONFIG_BITS 0x50
113#define PHY_RX0_EQ(x) ((x) << 24)
114
115#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
116#define SLV_ADDR_SPACE_SZ 0x10000000
117
118#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
119
120#define DEVICE_TYPE_RC 0x4
121
122#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
123#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
124
125#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
126
127struct qcom_pcie_resources_2_1_0 {
128 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
129 struct reset_control *pci_reset;
130 struct reset_control *axi_reset;
131 struct reset_control *ahb_reset;
132 struct reset_control *por_reset;
133 struct reset_control *phy_reset;
134 struct reset_control *ext_reset;
135 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
136};
137
138struct qcom_pcie_resources_1_0_0 {
139 struct clk *iface;
140 struct clk *aux;
141 struct clk *master_bus;
142 struct clk *slave_bus;
143 struct reset_control *core;
144 struct regulator *vdda;
145};
146
147#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
148struct qcom_pcie_resources_2_3_2 {
149 struct clk *aux_clk;
150 struct clk *master_clk;
151 struct clk *slave_clk;
152 struct clk *cfg_clk;
153 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
154};
155
156#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
157struct qcom_pcie_resources_2_4_0 {
158 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
159 int num_clks;
160 struct reset_control *axi_m_reset;
161 struct reset_control *axi_s_reset;
162 struct reset_control *pipe_reset;
163 struct reset_control *axi_m_vmid_reset;
164 struct reset_control *axi_s_xpu_reset;
165 struct reset_control *parf_reset;
166 struct reset_control *phy_reset;
167 struct reset_control *axi_m_sticky_reset;
168 struct reset_control *pipe_sticky_reset;
169 struct reset_control *pwr_reset;
170 struct reset_control *ahb_reset;
171 struct reset_control *phy_ahb_reset;
172};
173
174struct qcom_pcie_resources_2_3_3 {
175 struct clk *iface;
176 struct clk *axi_m_clk;
177 struct clk *axi_s_clk;
178 struct clk *ahb_clk;
179 struct clk *aux_clk;
180 struct reset_control *rst[7];
181};
182
183/* 6 clocks typically, 7 for sm8250 */
184struct qcom_pcie_resources_2_7_0 {
185 struct clk_bulk_data clks[12];
186 int num_clks;
187 struct regulator_bulk_data supplies[2];
188 struct reset_control *pci_reset;
189};
190
191struct qcom_pcie_resources_2_9_0 {
192 struct clk_bulk_data clks[5];
193 struct reset_control *rst;
194};
195
196union qcom_pcie_resources {
197 struct qcom_pcie_resources_1_0_0 v1_0_0;
198 struct qcom_pcie_resources_2_1_0 v2_1_0;
199 struct qcom_pcie_resources_2_3_2 v2_3_2;
200 struct qcom_pcie_resources_2_3_3 v2_3_3;
201 struct qcom_pcie_resources_2_4_0 v2_4_0;
202 struct qcom_pcie_resources_2_7_0 v2_7_0;
203 struct qcom_pcie_resources_2_9_0 v2_9_0;
204};
205
206struct qcom_pcie;
207
208struct qcom_pcie_ops {
209 int (*get_resources)(struct qcom_pcie *pcie);
210 int (*init)(struct qcom_pcie *pcie);
211 int (*post_init)(struct qcom_pcie *pcie);
212 void (*deinit)(struct qcom_pcie *pcie);
213 void (*ltssm_enable)(struct qcom_pcie *pcie);
214 int (*config_sid)(struct qcom_pcie *pcie);
215};
216
217struct qcom_pcie_cfg {
218 const struct qcom_pcie_ops *ops;
219};
220
221struct qcom_pcie {
222 struct dw_pcie *pci;
223 void __iomem *parf; /* DT parf */
224 void __iomem *elbi; /* DT elbi */
225 union qcom_pcie_resources res;
226 struct phy *phy;
227 struct gpio_desc *reset;
228 struct icc_path *icc_mem;
229 const struct qcom_pcie_cfg *cfg;
230};
231
232#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
233
234static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
235{
236 gpiod_set_value_cansleep(pcie->reset, 1);
237 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
238}
239
240static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
241{
242 /* Ensure that PERST has been asserted for at least 100 ms */
243 msleep(100);
244 gpiod_set_value_cansleep(pcie->reset, 0);
245 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
246}
247
248static int qcom_pcie_start_link(struct dw_pcie *pci)
249{
250 struct qcom_pcie *pcie = to_qcom_pcie(pci);
251
252 /* Enable Link Training state machine */
253 if (pcie->cfg->ops->ltssm_enable)
254 pcie->cfg->ops->ltssm_enable(pcie);
255
256 return 0;
257}
258
259static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
260{
261 u32 val;
262
263 /* enable link training */
264 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
265 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
266 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
267}
268
269static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
270{
271 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
272 struct dw_pcie *pci = pcie->pci;
273 struct device *dev = pci->dev;
274 int ret;
275
276 res->supplies[0].supply = "vdda";
277 res->supplies[1].supply = "vdda_phy";
278 res->supplies[2].supply = "vdda_refclk";
279 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
280 res->supplies);
281 if (ret)
282 return ret;
283
284 res->clks[0].id = "iface";
285 res->clks[1].id = "core";
286 res->clks[2].id = "phy";
287 res->clks[3].id = "aux";
288 res->clks[4].id = "ref";
289
290 /* iface, core, phy are required */
291 ret = devm_clk_bulk_get(dev, 3, res->clks);
292 if (ret < 0)
293 return ret;
294
295 /* aux, ref are optional */
296 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
297 if (ret < 0)
298 return ret;
299
300 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
301 if (IS_ERR(res->pci_reset))
302 return PTR_ERR(res->pci_reset);
303
304 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
305 if (IS_ERR(res->axi_reset))
306 return PTR_ERR(res->axi_reset);
307
308 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
309 if (IS_ERR(res->ahb_reset))
310 return PTR_ERR(res->ahb_reset);
311
312 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
313 if (IS_ERR(res->por_reset))
314 return PTR_ERR(res->por_reset);
315
316 res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
317 if (IS_ERR(res->ext_reset))
318 return PTR_ERR(res->ext_reset);
319
320 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
321 return PTR_ERR_OR_ZERO(res->phy_reset);
322}
323
324static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
325{
326 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
327
328 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
329 reset_control_assert(res->pci_reset);
330 reset_control_assert(res->axi_reset);
331 reset_control_assert(res->ahb_reset);
332 reset_control_assert(res->por_reset);
333 reset_control_assert(res->ext_reset);
334 reset_control_assert(res->phy_reset);
335
336 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
337
338 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
339}
340
341static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
342{
343 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
344 struct dw_pcie *pci = pcie->pci;
345 struct device *dev = pci->dev;
346 int ret;
347
348 /* reset the PCIe interface as uboot can leave it undefined state */
349 reset_control_assert(res->pci_reset);
350 reset_control_assert(res->axi_reset);
351 reset_control_assert(res->ahb_reset);
352 reset_control_assert(res->por_reset);
353 reset_control_assert(res->ext_reset);
354 reset_control_assert(res->phy_reset);
355
356 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
357 if (ret < 0) {
358 dev_err(dev, "cannot enable regulators\n");
359 return ret;
360 }
361
362 ret = reset_control_deassert(res->ahb_reset);
363 if (ret) {
364 dev_err(dev, "cannot deassert ahb reset\n");
365 goto err_deassert_ahb;
366 }
367
368 ret = reset_control_deassert(res->ext_reset);
369 if (ret) {
370 dev_err(dev, "cannot deassert ext reset\n");
371 goto err_deassert_ext;
372 }
373
374 ret = reset_control_deassert(res->phy_reset);
375 if (ret) {
376 dev_err(dev, "cannot deassert phy reset\n");
377 goto err_deassert_phy;
378 }
379
380 ret = reset_control_deassert(res->pci_reset);
381 if (ret) {
382 dev_err(dev, "cannot deassert pci reset\n");
383 goto err_deassert_pci;
384 }
385
386 ret = reset_control_deassert(res->por_reset);
387 if (ret) {
388 dev_err(dev, "cannot deassert por reset\n");
389 goto err_deassert_por;
390 }
391
392 ret = reset_control_deassert(res->axi_reset);
393 if (ret) {
394 dev_err(dev, "cannot deassert axi reset\n");
395 goto err_deassert_axi;
396 }
397
398 return 0;
399
400err_deassert_axi:
401 reset_control_assert(res->por_reset);
402err_deassert_por:
403 reset_control_assert(res->pci_reset);
404err_deassert_pci:
405 reset_control_assert(res->phy_reset);
406err_deassert_phy:
407 reset_control_assert(res->ext_reset);
408err_deassert_ext:
409 reset_control_assert(res->ahb_reset);
410err_deassert_ahb:
411 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
412
413 return ret;
414}
415
416static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
417{
418 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
419 struct dw_pcie *pci = pcie->pci;
420 struct device *dev = pci->dev;
421 struct device_node *node = dev->of_node;
422 u32 val;
423 int ret;
424
425 /* enable PCIe clocks and resets */
426 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
427 val &= ~BIT(0);
428 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
429
430 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
431 if (ret)
432 return ret;
433
434 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
435 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
436 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
437 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
438 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
439 pcie->parf + PCIE20_PARF_PCS_DEEMPH);
440 writel(PCS_SWING_TX_SWING_FULL(120) |
441 PCS_SWING_TX_SWING_LOW(120),
442 pcie->parf + PCIE20_PARF_PCS_SWING);
443 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
444 }
445
446 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
447 /* set TX termination offset */
448 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
449 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
450 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
451 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
452 }
453
454 /* enable external reference clock */
455 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
456 /* USE_PAD is required only for ipq806x */
457 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
458 val &= ~PHY_REFCLK_USE_PAD;
459 val |= PHY_REFCLK_SSP_EN;
460 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
461
462 /* wait for clock acquisition */
463 usleep_range(1000, 1500);
464
465 /* Set the Max TLP size to 2K, instead of using default of 4K */
466 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
467 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
468 writel(CFG_BRIDGE_SB_INIT,
469 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
470
471 return 0;
472}
473
474static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
475{
476 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
477 struct dw_pcie *pci = pcie->pci;
478 struct device *dev = pci->dev;
479
480 res->vdda = devm_regulator_get(dev, "vdda");
481 if (IS_ERR(res->vdda))
482 return PTR_ERR(res->vdda);
483
484 res->iface = devm_clk_get(dev, "iface");
485 if (IS_ERR(res->iface))
486 return PTR_ERR(res->iface);
487
488 res->aux = devm_clk_get(dev, "aux");
489 if (IS_ERR(res->aux))
490 return PTR_ERR(res->aux);
491
492 res->master_bus = devm_clk_get(dev, "master_bus");
493 if (IS_ERR(res->master_bus))
494 return PTR_ERR(res->master_bus);
495
496 res->slave_bus = devm_clk_get(dev, "slave_bus");
497 if (IS_ERR(res->slave_bus))
498 return PTR_ERR(res->slave_bus);
499
500 res->core = devm_reset_control_get_exclusive(dev, "core");
501 return PTR_ERR_OR_ZERO(res->core);
502}
503
504static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
505{
506 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
507
508 reset_control_assert(res->core);
509 clk_disable_unprepare(res->slave_bus);
510 clk_disable_unprepare(res->master_bus);
511 clk_disable_unprepare(res->iface);
512 clk_disable_unprepare(res->aux);
513 regulator_disable(res->vdda);
514}
515
516static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
517{
518 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
519 struct dw_pcie *pci = pcie->pci;
520 struct device *dev = pci->dev;
521 int ret;
522
523 ret = reset_control_deassert(res->core);
524 if (ret) {
525 dev_err(dev, "cannot deassert core reset\n");
526 return ret;
527 }
528
529 ret = clk_prepare_enable(res->aux);
530 if (ret) {
531 dev_err(dev, "cannot prepare/enable aux clock\n");
532 goto err_res;
533 }
534
535 ret = clk_prepare_enable(res->iface);
536 if (ret) {
537 dev_err(dev, "cannot prepare/enable iface clock\n");
538 goto err_aux;
539 }
540
541 ret = clk_prepare_enable(res->master_bus);
542 if (ret) {
543 dev_err(dev, "cannot prepare/enable master_bus clock\n");
544 goto err_iface;
545 }
546
547 ret = clk_prepare_enable(res->slave_bus);
548 if (ret) {
549 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
550 goto err_master;
551 }
552
553 ret = regulator_enable(res->vdda);
554 if (ret) {
555 dev_err(dev, "cannot enable vdda regulator\n");
556 goto err_slave;
557 }
558
559 return 0;
560err_slave:
561 clk_disable_unprepare(res->slave_bus);
562err_master:
563 clk_disable_unprepare(res->master_bus);
564err_iface:
565 clk_disable_unprepare(res->iface);
566err_aux:
567 clk_disable_unprepare(res->aux);
568err_res:
569 reset_control_assert(res->core);
570
571 return ret;
572}
573
574static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
575{
576 /* change DBI base address */
577 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
578
579 if (IS_ENABLED(CONFIG_PCI_MSI)) {
580 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
581
582 val |= BIT(31);
583 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
584 }
585
586 return 0;
587}
588
589static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
590{
591 u32 val;
592
593 /* enable link training */
594 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
595 val |= BIT(8);
596 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
597}
598
599static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
600{
601 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
602 struct dw_pcie *pci = pcie->pci;
603 struct device *dev = pci->dev;
604 int ret;
605
606 res->supplies[0].supply = "vdda";
607 res->supplies[1].supply = "vddpe-3v3";
608 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
609 res->supplies);
610 if (ret)
611 return ret;
612
613 res->aux_clk = devm_clk_get(dev, "aux");
614 if (IS_ERR(res->aux_clk))
615 return PTR_ERR(res->aux_clk);
616
617 res->cfg_clk = devm_clk_get(dev, "cfg");
618 if (IS_ERR(res->cfg_clk))
619 return PTR_ERR(res->cfg_clk);
620
621 res->master_clk = devm_clk_get(dev, "bus_master");
622 if (IS_ERR(res->master_clk))
623 return PTR_ERR(res->master_clk);
624
625 res->slave_clk = devm_clk_get(dev, "bus_slave");
626 if (IS_ERR(res->slave_clk))
627 return PTR_ERR(res->slave_clk);
628
629 return 0;
630}
631
632static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
633{
634 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
635
636 clk_disable_unprepare(res->slave_clk);
637 clk_disable_unprepare(res->master_clk);
638 clk_disable_unprepare(res->cfg_clk);
639 clk_disable_unprepare(res->aux_clk);
640
641 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
642}
643
644static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
645{
646 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
647 struct dw_pcie *pci = pcie->pci;
648 struct device *dev = pci->dev;
649 int ret;
650
651 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
652 if (ret < 0) {
653 dev_err(dev, "cannot enable regulators\n");
654 return ret;
655 }
656
657 ret = clk_prepare_enable(res->aux_clk);
658 if (ret) {
659 dev_err(dev, "cannot prepare/enable aux clock\n");
660 goto err_aux_clk;
661 }
662
663 ret = clk_prepare_enable(res->cfg_clk);
664 if (ret) {
665 dev_err(dev, "cannot prepare/enable cfg clock\n");
666 goto err_cfg_clk;
667 }
668
669 ret = clk_prepare_enable(res->master_clk);
670 if (ret) {
671 dev_err(dev, "cannot prepare/enable master clock\n");
672 goto err_master_clk;
673 }
674
675 ret = clk_prepare_enable(res->slave_clk);
676 if (ret) {
677 dev_err(dev, "cannot prepare/enable slave clock\n");
678 goto err_slave_clk;
679 }
680
681 return 0;
682
683err_slave_clk:
684 clk_disable_unprepare(res->master_clk);
685err_master_clk:
686 clk_disable_unprepare(res->cfg_clk);
687err_cfg_clk:
688 clk_disable_unprepare(res->aux_clk);
689
690err_aux_clk:
691 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
692
693 return ret;
694}
695
696static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
697{
698 u32 val;
699
700 /* enable PCIe clocks and resets */
701 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
702 val &= ~BIT(0);
703 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
704
705 /* change DBI base address */
706 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
707
708 /* MAC PHY_POWERDOWN MUX DISABLE */
709 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
710 val &= ~BIT(29);
711 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
712
713 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
714 val |= BIT(4);
715 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
716
717 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
718 val |= BIT(31);
719 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
720
721 return 0;
722}
723
724static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
725{
726 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
727 struct dw_pcie *pci = pcie->pci;
728 struct device *dev = pci->dev;
729 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
730 int ret;
731
732 res->clks[0].id = "aux";
733 res->clks[1].id = "master_bus";
734 res->clks[2].id = "slave_bus";
735 res->clks[3].id = "iface";
736
737 /* qcom,pcie-ipq4019 is defined without "iface" */
738 res->num_clks = is_ipq ? 3 : 4;
739
740 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
741 if (ret < 0)
742 return ret;
743
744 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
745 if (IS_ERR(res->axi_m_reset))
746 return PTR_ERR(res->axi_m_reset);
747
748 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
749 if (IS_ERR(res->axi_s_reset))
750 return PTR_ERR(res->axi_s_reset);
751
752 if (is_ipq) {
753 /*
754 * These resources relates to the PHY or are secure clocks, but
755 * are controlled here for IPQ4019
756 */
757 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
758 if (IS_ERR(res->pipe_reset))
759 return PTR_ERR(res->pipe_reset);
760
761 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
762 "axi_m_vmid");
763 if (IS_ERR(res->axi_m_vmid_reset))
764 return PTR_ERR(res->axi_m_vmid_reset);
765
766 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
767 "axi_s_xpu");
768 if (IS_ERR(res->axi_s_xpu_reset))
769 return PTR_ERR(res->axi_s_xpu_reset);
770
771 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
772 if (IS_ERR(res->parf_reset))
773 return PTR_ERR(res->parf_reset);
774
775 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
776 if (IS_ERR(res->phy_reset))
777 return PTR_ERR(res->phy_reset);
778 }
779
780 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
781 "axi_m_sticky");
782 if (IS_ERR(res->axi_m_sticky_reset))
783 return PTR_ERR(res->axi_m_sticky_reset);
784
785 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
786 "pipe_sticky");
787 if (IS_ERR(res->pipe_sticky_reset))
788 return PTR_ERR(res->pipe_sticky_reset);
789
790 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
791 if (IS_ERR(res->pwr_reset))
792 return PTR_ERR(res->pwr_reset);
793
794 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
795 if (IS_ERR(res->ahb_reset))
796 return PTR_ERR(res->ahb_reset);
797
798 if (is_ipq) {
799 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
800 if (IS_ERR(res->phy_ahb_reset))
801 return PTR_ERR(res->phy_ahb_reset);
802 }
803
804 return 0;
805}
806
807static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
808{
809 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
810
811 reset_control_assert(res->axi_m_reset);
812 reset_control_assert(res->axi_s_reset);
813 reset_control_assert(res->pipe_reset);
814 reset_control_assert(res->pipe_sticky_reset);
815 reset_control_assert(res->phy_reset);
816 reset_control_assert(res->phy_ahb_reset);
817 reset_control_assert(res->axi_m_sticky_reset);
818 reset_control_assert(res->pwr_reset);
819 reset_control_assert(res->ahb_reset);
820 clk_bulk_disable_unprepare(res->num_clks, res->clks);
821}
822
823static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
824{
825 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
826 struct dw_pcie *pci = pcie->pci;
827 struct device *dev = pci->dev;
828 int ret;
829
830 ret = reset_control_assert(res->axi_m_reset);
831 if (ret) {
832 dev_err(dev, "cannot assert axi master reset\n");
833 return ret;
834 }
835
836 ret = reset_control_assert(res->axi_s_reset);
837 if (ret) {
838 dev_err(dev, "cannot assert axi slave reset\n");
839 return ret;
840 }
841
842 usleep_range(10000, 12000);
843
844 ret = reset_control_assert(res->pipe_reset);
845 if (ret) {
846 dev_err(dev, "cannot assert pipe reset\n");
847 return ret;
848 }
849
850 ret = reset_control_assert(res->pipe_sticky_reset);
851 if (ret) {
852 dev_err(dev, "cannot assert pipe sticky reset\n");
853 return ret;
854 }
855
856 ret = reset_control_assert(res->phy_reset);
857 if (ret) {
858 dev_err(dev, "cannot assert phy reset\n");
859 return ret;
860 }
861
862 ret = reset_control_assert(res->phy_ahb_reset);
863 if (ret) {
864 dev_err(dev, "cannot assert phy ahb reset\n");
865 return ret;
866 }
867
868 usleep_range(10000, 12000);
869
870 ret = reset_control_assert(res->axi_m_sticky_reset);
871 if (ret) {
872 dev_err(dev, "cannot assert axi master sticky reset\n");
873 return ret;
874 }
875
876 ret = reset_control_assert(res->pwr_reset);
877 if (ret) {
878 dev_err(dev, "cannot assert power reset\n");
879 return ret;
880 }
881
882 ret = reset_control_assert(res->ahb_reset);
883 if (ret) {
884 dev_err(dev, "cannot assert ahb reset\n");
885 return ret;
886 }
887
888 usleep_range(10000, 12000);
889
890 ret = reset_control_deassert(res->phy_ahb_reset);
891 if (ret) {
892 dev_err(dev, "cannot deassert phy ahb reset\n");
893 return ret;
894 }
895
896 ret = reset_control_deassert(res->phy_reset);
897 if (ret) {
898 dev_err(dev, "cannot deassert phy reset\n");
899 goto err_rst_phy;
900 }
901
902 ret = reset_control_deassert(res->pipe_reset);
903 if (ret) {
904 dev_err(dev, "cannot deassert pipe reset\n");
905 goto err_rst_pipe;
906 }
907
908 ret = reset_control_deassert(res->pipe_sticky_reset);
909 if (ret) {
910 dev_err(dev, "cannot deassert pipe sticky reset\n");
911 goto err_rst_pipe_sticky;
912 }
913
914 usleep_range(10000, 12000);
915
916 ret = reset_control_deassert(res->axi_m_reset);
917 if (ret) {
918 dev_err(dev, "cannot deassert axi master reset\n");
919 goto err_rst_axi_m;
920 }
921
922 ret = reset_control_deassert(res->axi_m_sticky_reset);
923 if (ret) {
924 dev_err(dev, "cannot deassert axi master sticky reset\n");
925 goto err_rst_axi_m_sticky;
926 }
927
928 ret = reset_control_deassert(res->axi_s_reset);
929 if (ret) {
930 dev_err(dev, "cannot deassert axi slave reset\n");
931 goto err_rst_axi_s;
932 }
933
934 ret = reset_control_deassert(res->pwr_reset);
935 if (ret) {
936 dev_err(dev, "cannot deassert power reset\n");
937 goto err_rst_pwr;
938 }
939
940 ret = reset_control_deassert(res->ahb_reset);
941 if (ret) {
942 dev_err(dev, "cannot deassert ahb reset\n");
943 goto err_rst_ahb;
944 }
945
946 usleep_range(10000, 12000);
947
948 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
949 if (ret)
950 goto err_clks;
951
952 return 0;
953
954err_clks:
955 reset_control_assert(res->ahb_reset);
956err_rst_ahb:
957 reset_control_assert(res->pwr_reset);
958err_rst_pwr:
959 reset_control_assert(res->axi_s_reset);
960err_rst_axi_s:
961 reset_control_assert(res->axi_m_sticky_reset);
962err_rst_axi_m_sticky:
963 reset_control_assert(res->axi_m_reset);
964err_rst_axi_m:
965 reset_control_assert(res->pipe_sticky_reset);
966err_rst_pipe_sticky:
967 reset_control_assert(res->pipe_reset);
968err_rst_pipe:
969 reset_control_assert(res->phy_reset);
970err_rst_phy:
971 reset_control_assert(res->phy_ahb_reset);
972 return ret;
973}
974
975static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie)
976{
977 u32 val;
978
979 /* enable PCIe clocks and resets */
980 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
981 val &= ~BIT(0);
982 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
983
984 /* change DBI base address */
985 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
986
987 /* MAC PHY_POWERDOWN MUX DISABLE */
988 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
989 val &= ~BIT(29);
990 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
991
992 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
993 val |= BIT(4);
994 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
995
996 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
997 val |= BIT(31);
998 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
999
1000 return 0;
1001}
1002
1003static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
1004{
1005 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1006 struct dw_pcie *pci = pcie->pci;
1007 struct device *dev = pci->dev;
1008 int i;
1009 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
1010 "axi_m_sticky", "sticky",
1011 "ahb", "sleep", };
1012
1013 res->iface = devm_clk_get(dev, "iface");
1014 if (IS_ERR(res->iface))
1015 return PTR_ERR(res->iface);
1016
1017 res->axi_m_clk = devm_clk_get(dev, "axi_m");
1018 if (IS_ERR(res->axi_m_clk))
1019 return PTR_ERR(res->axi_m_clk);
1020
1021 res->axi_s_clk = devm_clk_get(dev, "axi_s");
1022 if (IS_ERR(res->axi_s_clk))
1023 return PTR_ERR(res->axi_s_clk);
1024
1025 res->ahb_clk = devm_clk_get(dev, "ahb");
1026 if (IS_ERR(res->ahb_clk))
1027 return PTR_ERR(res->ahb_clk);
1028
1029 res->aux_clk = devm_clk_get(dev, "aux");
1030 if (IS_ERR(res->aux_clk))
1031 return PTR_ERR(res->aux_clk);
1032
1033 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
1034 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
1035 if (IS_ERR(res->rst[i]))
1036 return PTR_ERR(res->rst[i]);
1037 }
1038
1039 return 0;
1040}
1041
1042static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
1043{
1044 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1045
1046 clk_disable_unprepare(res->iface);
1047 clk_disable_unprepare(res->axi_m_clk);
1048 clk_disable_unprepare(res->axi_s_clk);
1049 clk_disable_unprepare(res->ahb_clk);
1050 clk_disable_unprepare(res->aux_clk);
1051}
1052
1053static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
1054{
1055 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1056 struct dw_pcie *pci = pcie->pci;
1057 struct device *dev = pci->dev;
1058 int i, ret;
1059
1060 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1061 ret = reset_control_assert(res->rst[i]);
1062 if (ret) {
1063 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
1064 return ret;
1065 }
1066 }
1067
1068 usleep_range(2000, 2500);
1069
1070 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1071 ret = reset_control_deassert(res->rst[i]);
1072 if (ret) {
1073 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
1074 ret);
1075 return ret;
1076 }
1077 }
1078
1079 /*
1080 * Don't have a way to see if the reset has completed.
1081 * Wait for some time.
1082 */
1083 usleep_range(2000, 2500);
1084
1085 ret = clk_prepare_enable(res->iface);
1086 if (ret) {
1087 dev_err(dev, "cannot prepare/enable core clock\n");
1088 goto err_clk_iface;
1089 }
1090
1091 ret = clk_prepare_enable(res->axi_m_clk);
1092 if (ret) {
1093 dev_err(dev, "cannot prepare/enable core clock\n");
1094 goto err_clk_axi_m;
1095 }
1096
1097 ret = clk_prepare_enable(res->axi_s_clk);
1098 if (ret) {
1099 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1100 goto err_clk_axi_s;
1101 }
1102
1103 ret = clk_prepare_enable(res->ahb_clk);
1104 if (ret) {
1105 dev_err(dev, "cannot prepare/enable ahb clock\n");
1106 goto err_clk_ahb;
1107 }
1108
1109 ret = clk_prepare_enable(res->aux_clk);
1110 if (ret) {
1111 dev_err(dev, "cannot prepare/enable aux clock\n");
1112 goto err_clk_aux;
1113 }
1114
1115 return 0;
1116
1117err_clk_aux:
1118 clk_disable_unprepare(res->ahb_clk);
1119err_clk_ahb:
1120 clk_disable_unprepare(res->axi_s_clk);
1121err_clk_axi_s:
1122 clk_disable_unprepare(res->axi_m_clk);
1123err_clk_axi_m:
1124 clk_disable_unprepare(res->iface);
1125err_clk_iface:
1126 /*
1127 * Not checking for failure, will anyway return
1128 * the original failure in 'ret'.
1129 */
1130 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1131 reset_control_assert(res->rst[i]);
1132
1133 return ret;
1134}
1135
1136static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
1137{
1138 struct dw_pcie *pci = pcie->pci;
1139 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1140 u32 val;
1141
1142 writel(SLV_ADDR_SPACE_SZ,
1143 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1144
1145 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1146 val &= ~BIT(0);
1147 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1148
1149 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1150
1151 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1152 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1153 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1154 pcie->parf + PCIE20_PARF_SYS_CTRL);
1155 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1156
1157 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
1158 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1159 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1160
1161 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1162 val &= ~PCI_EXP_LNKCAP_ASPMS;
1163 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1164
1165 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1166 PCI_EXP_DEVCTL2);
1167
1168 return 0;
1169}
1170
1171static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
1172{
1173 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1174 struct dw_pcie *pci = pcie->pci;
1175 struct device *dev = pci->dev;
1176 unsigned int num_clks, num_opt_clks;
1177 unsigned int idx;
1178 int ret;
1179
1180 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
1181 if (IS_ERR(res->pci_reset))
1182 return PTR_ERR(res->pci_reset);
1183
1184 res->supplies[0].supply = "vdda";
1185 res->supplies[1].supply = "vddpe-3v3";
1186 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
1187 res->supplies);
1188 if (ret)
1189 return ret;
1190
1191 idx = 0;
1192 res->clks[idx++].id = "aux";
1193 res->clks[idx++].id = "cfg";
1194 res->clks[idx++].id = "bus_master";
1195 res->clks[idx++].id = "bus_slave";
1196 res->clks[idx++].id = "slave_q2a";
1197
1198 num_clks = idx;
1199
1200 ret = devm_clk_bulk_get(dev, num_clks, res->clks);
1201 if (ret < 0)
1202 return ret;
1203
1204 res->clks[idx++].id = "tbu";
1205 res->clks[idx++].id = "ddrss_sf_tbu";
1206 res->clks[idx++].id = "aggre0";
1207 res->clks[idx++].id = "aggre1";
1208 res->clks[idx++].id = "noc_aggr_4";
1209 res->clks[idx++].id = "noc_aggr_south_sf";
1210 res->clks[idx++].id = "cnoc_qx";
1211
1212 num_opt_clks = idx - num_clks;
1213 res->num_clks = idx;
1214
1215 ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks);
1216 if (ret < 0)
1217 return ret;
1218
1219 return 0;
1220}
1221
1222static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
1223{
1224 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1225 struct dw_pcie *pci = pcie->pci;
1226 struct device *dev = pci->dev;
1227 u32 val;
1228 int ret;
1229
1230 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
1231 if (ret < 0) {
1232 dev_err(dev, "cannot enable regulators\n");
1233 return ret;
1234 }
1235
1236 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
1237 if (ret < 0)
1238 goto err_disable_regulators;
1239
1240 ret = reset_control_assert(res->pci_reset);
1241 if (ret < 0) {
1242 dev_err(dev, "cannot assert pci reset\n");
1243 goto err_disable_clocks;
1244 }
1245
1246 usleep_range(1000, 1500);
1247
1248 ret = reset_control_deassert(res->pci_reset);
1249 if (ret < 0) {
1250 dev_err(dev, "cannot deassert pci reset\n");
1251 goto err_disable_clocks;
1252 }
1253
1254 /* Wait for reset to complete, required on SM8450 */
1255 usleep_range(1000, 1500);
1256
1257 /* configure PCIe to RC mode */
1258 writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
1259
1260 /* enable PCIe clocks and resets */
1261 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1262 val &= ~BIT(0);
1263 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1264
1265 /* change DBI base address */
1266 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1267
1268 /* MAC PHY_POWERDOWN MUX DISABLE */
1269 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
1270 val &= ~BIT(29);
1271 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
1272
1273 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1274 val |= BIT(4);
1275 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1276
1277 /* Enable L1 and L1SS */
1278 val = readl(pcie->parf + PCIE20_PARF_PM_CTRL);
1279 val &= ~REQ_NOT_ENTR_L1;
1280 writel(val, pcie->parf + PCIE20_PARF_PM_CTRL);
1281
1282 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1283 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1284 val |= BIT(31);
1285 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1286 }
1287
1288 return 0;
1289err_disable_clocks:
1290 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1291err_disable_regulators:
1292 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1293
1294 return ret;
1295}
1296
1297static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1298{
1299 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1300
1301 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1302
1303 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1304}
1305
1306static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
1307{
1308 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1309 struct dw_pcie *pci = pcie->pci;
1310 struct device *dev = pci->dev;
1311 int ret;
1312
1313 res->clks[0].id = "iface";
1314 res->clks[1].id = "axi_m";
1315 res->clks[2].id = "axi_s";
1316 res->clks[3].id = "axi_bridge";
1317 res->clks[4].id = "rchng";
1318
1319 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
1320 if (ret < 0)
1321 return ret;
1322
1323 res->rst = devm_reset_control_array_get_exclusive(dev);
1324 if (IS_ERR(res->rst))
1325 return PTR_ERR(res->rst);
1326
1327 return 0;
1328}
1329
1330static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
1331{
1332 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1333
1334 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1335}
1336
1337static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
1338{
1339 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1340 struct device *dev = pcie->pci->dev;
1341 int ret;
1342
1343 ret = reset_control_assert(res->rst);
1344 if (ret) {
1345 dev_err(dev, "reset assert failed (%d)\n", ret);
1346 return ret;
1347 }
1348
1349 /*
1350 * Delay periods before and after reset deassert are working values
1351 * from downstream Codeaurora kernel
1352 */
1353 usleep_range(2000, 2500);
1354
1355 ret = reset_control_deassert(res->rst);
1356 if (ret) {
1357 dev_err(dev, "reset deassert failed (%d)\n", ret);
1358 return ret;
1359 }
1360
1361 usleep_range(2000, 2500);
1362
1363 return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
1364}
1365
1366static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
1367{
1368 struct dw_pcie *pci = pcie->pci;
1369 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1370 u32 val;
1371 int i;
1372
1373 writel(SLV_ADDR_SPACE_SZ,
1374 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1375
1376 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1377 val &= ~BIT(0);
1378 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1379
1380 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1381
1382 writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
1383 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
1384 pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1385 writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
1386 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
1387 pci->dbi_base + GEN3_RELATED_OFF);
1388
1389 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
1390 SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1391 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1392 pcie->parf + PCIE20_PARF_SYS_CTRL);
1393
1394 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1395
1396 dw_pcie_dbi_ro_wr_en(pci);
1397 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1398
1399 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1400 val &= ~PCI_EXP_LNKCAP_ASPMS;
1401 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1402
1403 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1404 PCI_EXP_DEVCTL2);
1405
1406 for (i = 0; i < 256; i++)
1407 writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
1408
1409 return 0;
1410}
1411
1412static int qcom_pcie_link_up(struct dw_pcie *pci)
1413{
1414 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1415 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1416
1417 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1418}
1419
1420static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
1421{
1422 /* iommu map structure */
1423 struct {
1424 u32 bdf;
1425 u32 phandle;
1426 u32 smmu_sid;
1427 u32 smmu_sid_len;
1428 } *map;
1429 void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N;
1430 struct device *dev = pcie->pci->dev;
1431 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
1432 int i, nr_map, size = 0;
1433 u32 smmu_sid_base;
1434
1435 of_get_property(dev->of_node, "iommu-map", &size);
1436 if (!size)
1437 return 0;
1438
1439 map = kzalloc(size, GFP_KERNEL);
1440 if (!map)
1441 return -ENOMEM;
1442
1443 of_property_read_u32_array(dev->of_node,
1444 "iommu-map", (u32 *)map, size / sizeof(u32));
1445
1446 nr_map = size / (sizeof(*map));
1447
1448 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
1449
1450 /* Registers need to be zero out first */
1451 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
1452
1453 /* Extract the SMMU SID base from the first entry of iommu-map */
1454 smmu_sid_base = map[0].smmu_sid;
1455
1456 /* Look for an available entry to hold the mapping */
1457 for (i = 0; i < nr_map; i++) {
1458 __be16 bdf_be = cpu_to_be16(map[i].bdf);
1459 u32 val;
1460 u8 hash;
1461
1462 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be),
1463 0);
1464
1465 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1466
1467 /* If the register is already populated, look for next available entry */
1468 while (val) {
1469 u8 current_hash = hash++;
1470 u8 next_mask = 0xff;
1471
1472 /* If NEXT field is NULL then update it with next hash */
1473 if (!(val & next_mask)) {
1474 val |= (u32)hash;
1475 writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
1476 }
1477
1478 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1479 }
1480
1481 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
1482 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
1483 writel(val, bdf_to_sid_base + hash * sizeof(u32));
1484 }
1485
1486 kfree(map);
1487
1488 return 0;
1489}
1490
1491static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
1492{
1493 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1494 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1495 int ret;
1496
1497 qcom_ep_reset_assert(pcie);
1498
1499 ret = pcie->cfg->ops->init(pcie);
1500 if (ret)
1501 return ret;
1502
1503 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
1504 if (ret)
1505 goto err_deinit;
1506
1507 ret = phy_power_on(pcie->phy);
1508 if (ret)
1509 goto err_deinit;
1510
1511 if (pcie->cfg->ops->post_init) {
1512 ret = pcie->cfg->ops->post_init(pcie);
1513 if (ret)
1514 goto err_disable_phy;
1515 }
1516
1517 qcom_ep_reset_deassert(pcie);
1518
1519 if (pcie->cfg->ops->config_sid) {
1520 ret = pcie->cfg->ops->config_sid(pcie);
1521 if (ret)
1522 goto err_assert_reset;
1523 }
1524
1525 return 0;
1526
1527err_assert_reset:
1528 qcom_ep_reset_assert(pcie);
1529err_disable_phy:
1530 phy_power_off(pcie->phy);
1531err_deinit:
1532 pcie->cfg->ops->deinit(pcie);
1533
1534 return ret;
1535}
1536
1537static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1538 .host_init = qcom_pcie_host_init,
1539};
1540
1541/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1542static const struct qcom_pcie_ops ops_2_1_0 = {
1543 .get_resources = qcom_pcie_get_resources_2_1_0,
1544 .init = qcom_pcie_init_2_1_0,
1545 .post_init = qcom_pcie_post_init_2_1_0,
1546 .deinit = qcom_pcie_deinit_2_1_0,
1547 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1548};
1549
1550/* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1551static const struct qcom_pcie_ops ops_1_0_0 = {
1552 .get_resources = qcom_pcie_get_resources_1_0_0,
1553 .init = qcom_pcie_init_1_0_0,
1554 .post_init = qcom_pcie_post_init_1_0_0,
1555 .deinit = qcom_pcie_deinit_1_0_0,
1556 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1557};
1558
1559/* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1560static const struct qcom_pcie_ops ops_2_3_2 = {
1561 .get_resources = qcom_pcie_get_resources_2_3_2,
1562 .init = qcom_pcie_init_2_3_2,
1563 .post_init = qcom_pcie_post_init_2_3_2,
1564 .deinit = qcom_pcie_deinit_2_3_2,
1565 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1566};
1567
1568/* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1569static const struct qcom_pcie_ops ops_2_4_0 = {
1570 .get_resources = qcom_pcie_get_resources_2_4_0,
1571 .init = qcom_pcie_init_2_4_0,
1572 .post_init = qcom_pcie_post_init_2_4_0,
1573 .deinit = qcom_pcie_deinit_2_4_0,
1574 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1575};
1576
1577/* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1578static const struct qcom_pcie_ops ops_2_3_3 = {
1579 .get_resources = qcom_pcie_get_resources_2_3_3,
1580 .init = qcom_pcie_init_2_3_3,
1581 .post_init = qcom_pcie_post_init_2_3_3,
1582 .deinit = qcom_pcie_deinit_2_3_3,
1583 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1584};
1585
1586/* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1587static const struct qcom_pcie_ops ops_2_7_0 = {
1588 .get_resources = qcom_pcie_get_resources_2_7_0,
1589 .init = qcom_pcie_init_2_7_0,
1590 .deinit = qcom_pcie_deinit_2_7_0,
1591 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1592};
1593
1594/* Qcom IP rev.: 1.9.0 */
1595static const struct qcom_pcie_ops ops_1_9_0 = {
1596 .get_resources = qcom_pcie_get_resources_2_7_0,
1597 .init = qcom_pcie_init_2_7_0,
1598 .deinit = qcom_pcie_deinit_2_7_0,
1599 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1600 .config_sid = qcom_pcie_config_sid_sm8250,
1601};
1602
1603/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
1604static const struct qcom_pcie_ops ops_2_9_0 = {
1605 .get_resources = qcom_pcie_get_resources_2_9_0,
1606 .init = qcom_pcie_init_2_9_0,
1607 .post_init = qcom_pcie_post_init_2_9_0,
1608 .deinit = qcom_pcie_deinit_2_9_0,
1609 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1610};
1611
1612static const struct qcom_pcie_cfg cfg_1_0_0 = {
1613 .ops = &ops_1_0_0,
1614};
1615
1616static const struct qcom_pcie_cfg cfg_1_9_0 = {
1617 .ops = &ops_1_9_0,
1618};
1619
1620static const struct qcom_pcie_cfg cfg_2_1_0 = {
1621 .ops = &ops_2_1_0,
1622};
1623
1624static const struct qcom_pcie_cfg cfg_2_3_2 = {
1625 .ops = &ops_2_3_2,
1626};
1627
1628static const struct qcom_pcie_cfg cfg_2_3_3 = {
1629 .ops = &ops_2_3_3,
1630};
1631
1632static const struct qcom_pcie_cfg cfg_2_4_0 = {
1633 .ops = &ops_2_4_0,
1634};
1635
1636static const struct qcom_pcie_cfg cfg_2_7_0 = {
1637 .ops = &ops_2_7_0,
1638};
1639
1640static const struct qcom_pcie_cfg cfg_2_9_0 = {
1641 .ops = &ops_2_9_0,
1642};
1643
1644static const struct dw_pcie_ops dw_pcie_ops = {
1645 .link_up = qcom_pcie_link_up,
1646 .start_link = qcom_pcie_start_link,
1647};
1648
1649static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
1650{
1651 struct dw_pcie *pci = pcie->pci;
1652 int ret;
1653
1654 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem");
1655 if (IS_ERR(pcie->icc_mem))
1656 return PTR_ERR(pcie->icc_mem);
1657
1658 /*
1659 * Some Qualcomm platforms require interconnect bandwidth constraints
1660 * to be set before enabling interconnect clocks.
1661 *
1662 * Set an initial peak bandwidth corresponding to single-lane Gen 1
1663 * for the pcie-mem path.
1664 */
1665 ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
1666 if (ret) {
1667 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
1668 ret);
1669 return ret;
1670 }
1671
1672 return 0;
1673}
1674
1675static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
1676{
1677 struct dw_pcie *pci = pcie->pci;
1678 u32 offset, status, bw;
1679 int speed, width;
1680 int ret;
1681
1682 if (!pcie->icc_mem)
1683 return;
1684
1685 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1686 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1687
1688 /* Only update constraints if link is up. */
1689 if (!(status & PCI_EXP_LNKSTA_DLLLA))
1690 return;
1691
1692 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
1693 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
1694
1695 switch (speed) {
1696 case 1:
1697 bw = MBps_to_icc(250);
1698 break;
1699 case 2:
1700 bw = MBps_to_icc(500);
1701 break;
1702 default:
1703 WARN_ON_ONCE(1);
1704 fallthrough;
1705 case 3:
1706 bw = MBps_to_icc(985);
1707 break;
1708 }
1709
1710 ret = icc_set_bw(pcie->icc_mem, 0, width * bw);
1711 if (ret) {
1712 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
1713 ret);
1714 }
1715}
1716
1717static int qcom_pcie_probe(struct platform_device *pdev)
1718{
1719 struct device *dev = &pdev->dev;
1720 struct dw_pcie_rp *pp;
1721 struct dw_pcie *pci;
1722 struct qcom_pcie *pcie;
1723 const struct qcom_pcie_cfg *pcie_cfg;
1724 int ret;
1725
1726 pcie_cfg = of_device_get_match_data(dev);
1727 if (!pcie_cfg || !pcie_cfg->ops) {
1728 dev_err(dev, "Invalid platform data\n");
1729 return -EINVAL;
1730 }
1731
1732 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1733 if (!pcie)
1734 return -ENOMEM;
1735
1736 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1737 if (!pci)
1738 return -ENOMEM;
1739
1740 pm_runtime_enable(dev);
1741 ret = pm_runtime_get_sync(dev);
1742 if (ret < 0)
1743 goto err_pm_runtime_put;
1744
1745 pci->dev = dev;
1746 pci->ops = &dw_pcie_ops;
1747 pp = &pci->pp;
1748
1749 pcie->pci = pci;
1750
1751 pcie->cfg = pcie_cfg;
1752
1753 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1754 if (IS_ERR(pcie->reset)) {
1755 ret = PTR_ERR(pcie->reset);
1756 goto err_pm_runtime_put;
1757 }
1758
1759 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1760 if (IS_ERR(pcie->parf)) {
1761 ret = PTR_ERR(pcie->parf);
1762 goto err_pm_runtime_put;
1763 }
1764
1765 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1766 if (IS_ERR(pcie->elbi)) {
1767 ret = PTR_ERR(pcie->elbi);
1768 goto err_pm_runtime_put;
1769 }
1770
1771 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1772 if (IS_ERR(pcie->phy)) {
1773 ret = PTR_ERR(pcie->phy);
1774 goto err_pm_runtime_put;
1775 }
1776
1777 ret = qcom_pcie_icc_init(pcie);
1778 if (ret)
1779 goto err_pm_runtime_put;
1780
1781 ret = pcie->cfg->ops->get_resources(pcie);
1782 if (ret)
1783 goto err_pm_runtime_put;
1784
1785 pp->ops = &qcom_pcie_dw_ops;
1786
1787 ret = phy_init(pcie->phy);
1788 if (ret)
1789 goto err_pm_runtime_put;
1790
1791 platform_set_drvdata(pdev, pcie);
1792
1793 ret = dw_pcie_host_init(pp);
1794 if (ret) {
1795 dev_err(dev, "cannot initialize host\n");
1796 goto err_phy_exit;
1797 }
1798
1799 qcom_pcie_icc_update(pcie);
1800
1801 return 0;
1802
1803err_phy_exit:
1804 phy_exit(pcie->phy);
1805err_pm_runtime_put:
1806 pm_runtime_put(dev);
1807 pm_runtime_disable(dev);
1808
1809 return ret;
1810}
1811
1812static const struct of_device_id qcom_pcie_match[] = {
1813 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1814 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1815 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1816 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1817 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1818 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1819 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1820 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1821 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1822 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
1823 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1824 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1825 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
1826 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1827 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1828 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1829 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1830 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1831 { }
1832};
1833
1834static void qcom_fixup_class(struct pci_dev *dev)
1835{
1836 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
1837}
1838DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1839DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1840DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1841DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1842DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1843DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1844DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1845
1846static struct platform_driver qcom_pcie_driver = {
1847 .probe = qcom_pcie_probe,
1848 .driver = {
1849 .name = "qcom-pcie",
1850 .suppress_bind_attrs = true,
1851 .of_match_table = qcom_pcie_match,
1852 },
1853};
1854builtin_platform_driver(qcom_pcie_driver);