Loading...
1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT76_CONNAC_H
5#define __MT76_CONNAC_H
6
7#include "mt76.h"
8
9enum rx_pkt_type {
10 PKT_TYPE_TXS,
11 PKT_TYPE_TXRXV,
12 PKT_TYPE_NORMAL,
13 PKT_TYPE_RX_DUP_RFB,
14 PKT_TYPE_RX_TMR,
15 PKT_TYPE_RETRIEVE,
16 PKT_TYPE_TXRX_NOTIFY,
17 PKT_TYPE_RX_EVENT,
18 PKT_TYPE_NORMAL_MCU,
19 PKT_TYPE_RX_FW_MONITOR = 0x0c,
20 PKT_TYPE_TXRX_NOTIFY_V0 = 0x18,
21};
22
23#define MT76_CONNAC_SCAN_IE_LEN 600
24#define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL 10
25#define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX
26#define MT76_CONNAC_MAX_SCHED_SCAN_SSID 10
27#define MT76_CONNAC_MAX_SCAN_MATCH 16
28
29#define MT76_CONNAC_MAX_WMM_SETS 4
30
31#define MT76_CONNAC_COREDUMP_TIMEOUT (HZ / 20)
32#define MT76_CONNAC_COREDUMP_SZ (1300 * 1024)
33
34#define MT_TXD_SIZE (8 * 4)
35
36#define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4)
37#define MT_USB_HDR_SIZE 4
38#define MT_USB_TAIL_SIZE 4
39
40#define MT_SDIO_TXD_SIZE (MT_TXD_SIZE + 8 * 4)
41#define MT_SDIO_TAIL_SIZE 8
42#define MT_SDIO_HDR_SIZE 4
43
44#define MT_MSDU_ID_VALID BIT(15)
45
46#define MT_TXD_LEN_LAST BIT(15)
47#define MT_TXD_LEN_MASK GENMASK(11, 0)
48#define MT_TXD_LEN_MSDU_LAST BIT(14)
49#define MT_TXD_LEN_AMSDU_LAST BIT(15)
50
51enum {
52 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
53 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
54 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
55 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
56 CMD_CBW_10MHZ,
57 CMD_CBW_5MHZ,
58 CMD_CBW_8080MHZ,
59 CMD_CBW_320MHZ,
60
61 CMD_HE_MCS_BW80 = 0,
62 CMD_HE_MCS_BW160,
63 CMD_HE_MCS_BW8080,
64 CMD_HE_MCS_BW_NUM
65};
66
67enum {
68 HW_BSSID_0 = 0x0,
69 HW_BSSID_1,
70 HW_BSSID_2,
71 HW_BSSID_3,
72 HW_BSSID_MAX = HW_BSSID_3,
73 EXT_BSSID_START = 0x10,
74 EXT_BSSID_1,
75 EXT_BSSID_15 = 0x1f,
76 EXT_BSSID_MAX = EXT_BSSID_15,
77 REPEATER_BSSID_START = 0x20,
78 REPEATER_BSSID_MAX = 0x3f,
79};
80
81struct mt76_connac_reg_map {
82 u32 phys;
83 u32 maps;
84 u32 size;
85};
86
87struct mt76_connac_pm {
88 bool enable:1;
89 bool enable_user:1;
90 bool ds_enable:1;
91 bool ds_enable_user:1;
92 bool suspended:1;
93
94 spinlock_t txq_lock;
95 struct {
96 struct mt76_wcid *wcid;
97 struct sk_buff *skb;
98 } tx_q[IEEE80211_NUM_ACS];
99
100 struct work_struct wake_work;
101 wait_queue_head_t wait;
102
103 struct {
104 spinlock_t lock;
105 u32 count;
106 } wake;
107 struct mutex mutex;
108
109 struct delayed_work ps_work;
110 unsigned long last_activity;
111 unsigned long idle_timeout;
112
113 struct {
114 unsigned long last_wake_event;
115 unsigned long awake_time;
116 unsigned long last_doze_event;
117 unsigned long doze_time;
118 unsigned int lp_wake;
119 } stats;
120};
121
122struct mt76_connac_coredump {
123 struct sk_buff_head msg_list;
124 struct delayed_work work;
125 unsigned long last_activity;
126};
127
128struct mt76_connac_sta_key_conf {
129 s8 keyidx;
130 u8 key[16];
131};
132
133#define MT_TXP_MAX_BUF_NUM 6
134
135struct mt76_connac_fw_txp {
136 __le16 flags;
137 __le16 token;
138 u8 bss_idx;
139 __le16 rept_wds_wcid;
140 u8 nbuf;
141 __le32 buf[MT_TXP_MAX_BUF_NUM];
142 __le16 len[MT_TXP_MAX_BUF_NUM];
143} __packed __aligned(4);
144
145#define MT_HW_TXP_MAX_MSDU_NUM 4
146#define MT_HW_TXP_MAX_BUF_NUM 4
147
148struct mt76_connac_txp_ptr {
149 __le32 buf0;
150 __le16 len0;
151 __le16 len1;
152 __le32 buf1;
153} __packed __aligned(4);
154
155struct mt76_connac_hw_txp {
156 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
157 struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
158} __packed __aligned(4);
159
160struct mt76_connac_txp_common {
161 union {
162 struct mt76_connac_fw_txp fw;
163 struct mt76_connac_hw_txp hw;
164 };
165};
166
167struct mt76_connac_tx_free {
168 __le16 rx_byte_cnt;
169 __le16 ctrl;
170 __le32 txd;
171} __packed __aligned(4);
172
173extern const struct wiphy_wowlan_support mt76_connac_wowlan_support;
174
175static inline bool is_mt7925(struct mt76_dev *dev)
176{
177 return mt76_chip(dev) == 0x7925;
178}
179
180static inline bool is_mt7920(struct mt76_dev *dev)
181{
182 return mt76_chip(dev) == 0x7920;
183}
184
185static inline bool is_mt7922(struct mt76_dev *dev)
186{
187 return mt76_chip(dev) == 0x7922;
188}
189
190static inline bool is_mt7921(struct mt76_dev *dev)
191{
192 return mt76_chip(dev) == 0x7961 || is_mt7922(dev) || is_mt7920(dev);
193}
194
195static inline bool is_mt7663(struct mt76_dev *dev)
196{
197 return mt76_chip(dev) == 0x7663;
198}
199
200static inline bool is_mt7915(struct mt76_dev *dev)
201{
202 return mt76_chip(dev) == 0x7915;
203}
204
205static inline bool is_mt7916(struct mt76_dev *dev)
206{
207 return mt76_chip(dev) == 0x7906;
208}
209
210static inline bool is_mt7981(struct mt76_dev *dev)
211{
212 return mt76_chip(dev) == 0x7981;
213}
214
215static inline bool is_mt7986(struct mt76_dev *dev)
216{
217 return mt76_chip(dev) == 0x7986;
218}
219
220static inline bool is_mt798x(struct mt76_dev *dev)
221{
222 return is_mt7981(dev) || is_mt7986(dev);
223}
224
225static inline bool is_mt7996(struct mt76_dev *dev)
226{
227 return mt76_chip(dev) == 0x7990;
228}
229
230static inline bool is_mt7992(struct mt76_dev *dev)
231{
232 return mt76_chip(dev) == 0x7992;
233}
234
235static inline bool is_mt799x(struct mt76_dev *dev)
236{
237 return is_mt7996(dev) || is_mt7992(dev);
238}
239
240static inline bool is_mt7622(struct mt76_dev *dev)
241{
242 if (!IS_ENABLED(CONFIG_MT7622_WMAC))
243 return false;
244
245 return mt76_chip(dev) == 0x7622;
246}
247
248static inline bool is_mt7615(struct mt76_dev *dev)
249{
250 return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611;
251}
252
253static inline bool is_mt7611(struct mt76_dev *dev)
254{
255 return mt76_chip(dev) == 0x7611;
256}
257
258static inline bool is_connac_v1(struct mt76_dev *dev)
259{
260 return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev);
261}
262
263static inline bool is_mt76_fw_txp(struct mt76_dev *dev)
264{
265 switch (mt76_chip(dev)) {
266 case 0x7961:
267 case 0x7920:
268 case 0x7922:
269 case 0x7925:
270 case 0x7663:
271 case 0x7622:
272 return false;
273 default:
274 return true;
275 }
276}
277
278static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef)
279{
280 static const u8 width_to_bw[] = {
281 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
282 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
283 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
284 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
285 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
286 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
287 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
288 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
289 [NL80211_CHAN_WIDTH_320] = CMD_CBW_320MHZ,
290 };
291
292 if (chandef->width >= ARRAY_SIZE(width_to_bw))
293 return 0;
294
295 return width_to_bw[chandef->width];
296}
297
298static inline u8 mt76_connac_lmac_mapping(u8 ac)
299{
300 /* LMAC uses the reverse order of mac80211 AC indexes */
301 return 3 - ac;
302}
303
304static inline void *
305mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
306{
307 u8 *txwi;
308
309 if (!t)
310 return NULL;
311
312 txwi = mt76_get_txwi_ptr(dev, t);
313
314 return (void *)(txwi + MT_TXD_SIZE);
315}
316
317static inline u8 mt76_connac_spe_idx(u8 antenna_mask)
318{
319 static const u8 ant_to_spe[] = {0, 0, 1, 0, 3, 2, 4, 0,
320 9, 8, 6, 10, 16, 12, 18, 0};
321
322 if (antenna_mask >= sizeof(ant_to_spe))
323 return 0;
324
325 return ant_to_spe[antenna_mask];
326}
327
328static inline void mt76_connac_irq_enable(struct mt76_dev *dev, u32 mask)
329{
330 mt76_set_irq_mask(dev, 0, 0, mask);
331 tasklet_schedule(&dev->irq_tasklet);
332}
333
334int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm);
335void mt76_connac_power_save_sched(struct mt76_phy *phy,
336 struct mt76_connac_pm *pm);
337void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm,
338 struct mt76_wcid *wcid);
339
340static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev)
341{
342 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false);
343 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false);
344}
345
346static inline bool
347mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
348{
349 bool ret = false;
350
351 spin_lock_bh(&pm->wake.lock);
352 if (test_bit(MT76_STATE_PM, &phy->state))
353 goto out;
354
355 pm->wake.count++;
356 ret = true;
357out:
358 spin_unlock_bh(&pm->wake.lock);
359
360 return ret;
361}
362
363static inline void
364mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
365{
366 spin_lock_bh(&pm->wake.lock);
367
368 pm->last_activity = jiffies;
369 if (--pm->wake.count == 0 &&
370 test_bit(MT76_STATE_MCU_RUNNING, &phy->state))
371 mt76_connac_power_save_sched(phy, pm);
372
373 spin_unlock_bh(&pm->wake.lock);
374}
375
376static inline bool
377mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm)
378{
379 struct mt76_dev *dev = phy->dev;
380 bool ret;
381
382 if (dev->token_count)
383 return true;
384
385 spin_lock_bh(&pm->wake.lock);
386 ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state);
387 spin_unlock_bh(&pm->wake.lock);
388
389 return ret;
390}
391
392static inline void
393mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm)
394 __acquires(&dev->mutex)
395{
396 mutex_lock(&dev->mutex);
397 mt76_connac_pm_wake(&dev->phy, pm);
398}
399
400static inline void
401mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm)
402 __releases(&dev->mutex)
403{
404 mt76_connac_power_save_sched(&dev->phy, pm);
405 mutex_unlock(&dev->mutex);
406}
407
408void mt76_connac_gen_ppe_thresh(u8 *he_ppet, int nss);
409int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,
410 int ring_base, void *wed, u32 flags);
411
412void mt76_connac_write_hw_txp(struct mt76_dev *dev,
413 struct mt76_tx_info *tx_info,
414 void *txp_ptr, u32 id);
415void mt76_connac_txp_skb_unmap(struct mt76_dev *dev,
416 struct mt76_txwi_cache *txwi);
417void mt76_connac_tx_complete_skb(struct mt76_dev *mdev,
418 struct mt76_queue_entry *e);
419void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw,
420 struct mt76_connac_pm *pm,
421 struct mt76_wcid *wcid,
422 struct sk_buff *skb);
423void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy,
424 struct mt76_connac_pm *pm);
425void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
426 struct sk_buff *skb, struct mt76_wcid *wcid,
427 struct ieee80211_key_conf *key, int pid,
428 enum mt76_txq_id qid, u32 changed);
429u16 mt76_connac2_mac_tx_rate_val(struct mt76_phy *mphy,
430 struct ieee80211_vif *vif,
431 bool beacon, bool mcast);
432bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid,
433 __le32 *txs_data);
434bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid,
435 int pid, __le32 *txs_data);
436void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev,
437 struct sk_buff *skb,
438 __le32 *rxv, u32 mode);
439int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif,
440 struct sk_buff *skb, u16 hdr_offset);
441int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev,
442 struct mt76_rx_status *status,
443 struct ieee80211_supported_band *sband,
444 __le32 *rxv, u8 *mode);
445void mt76_connac2_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi);
446void mt76_connac2_txwi_free(struct mt76_dev *dev, struct mt76_txwi_cache *t,
447 struct ieee80211_sta *sta,
448 struct list_head *free_list);
449void mt76_connac2_tx_token_put(struct mt76_dev *dev);
450
451/* connac3 */
452void mt76_connac3_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv,
453 u8 mode);
454void mt76_connac3_mac_decode_eht_radiotap(struct sk_buff *skb, __le32 *rxv,
455 u8 mode);
456#endif /* __MT76_CONNAC_H */
1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT76_CONNAC_H
5#define __MT76_CONNAC_H
6
7#include "mt76.h"
8
9#define MT76_CONNAC_SCAN_IE_LEN 600
10#define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL 10
11#define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX
12#define MT76_CONNAC_MAX_SCHED_SCAN_SSID 10
13#define MT76_CONNAC_MAX_SCAN_MATCH 16
14
15#define MT76_CONNAC_MAX_WMM_SETS 4
16
17#define MT76_CONNAC_COREDUMP_TIMEOUT (HZ / 20)
18#define MT76_CONNAC_COREDUMP_SZ (1300 * 1024)
19
20#define MT_TXD_SIZE (8 * 4)
21
22#define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4)
23#define MT_USB_HDR_SIZE 4
24#define MT_USB_TAIL_SIZE 4
25
26#define MT_SDIO_TXD_SIZE (MT_TXD_SIZE + 8 * 4)
27#define MT_SDIO_TAIL_SIZE 8
28#define MT_SDIO_HDR_SIZE 4
29
30#define MT_MSDU_ID_VALID BIT(15)
31
32#define MT_TXD_LEN_LAST BIT(15)
33#define MT_TXD_LEN_MASK GENMASK(11, 0)
34#define MT_TXD_LEN_MSDU_LAST BIT(14)
35#define MT_TXD_LEN_AMSDU_LAST BIT(15)
36
37enum {
38 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
39 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
40 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
41 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
42 CMD_CBW_10MHZ,
43 CMD_CBW_5MHZ,
44 CMD_CBW_8080MHZ,
45
46 CMD_HE_MCS_BW80 = 0,
47 CMD_HE_MCS_BW160,
48 CMD_HE_MCS_BW8080,
49 CMD_HE_MCS_BW_NUM
50};
51
52enum {
53 HW_BSSID_0 = 0x0,
54 HW_BSSID_1,
55 HW_BSSID_2,
56 HW_BSSID_3,
57 HW_BSSID_MAX = HW_BSSID_3,
58 EXT_BSSID_START = 0x10,
59 EXT_BSSID_1,
60 EXT_BSSID_15 = 0x1f,
61 EXT_BSSID_MAX = EXT_BSSID_15,
62 REPEATER_BSSID_START = 0x20,
63 REPEATER_BSSID_MAX = 0x3f,
64};
65
66struct mt76_connac_reg_map {
67 u32 phys;
68 u32 maps;
69 u32 size;
70};
71
72struct mt76_connac_pm {
73 bool enable:1;
74 bool enable_user:1;
75 bool ds_enable:1;
76 bool ds_enable_user:1;
77 bool suspended:1;
78
79 spinlock_t txq_lock;
80 struct {
81 struct mt76_wcid *wcid;
82 struct sk_buff *skb;
83 } tx_q[IEEE80211_NUM_ACS];
84
85 struct work_struct wake_work;
86 wait_queue_head_t wait;
87
88 struct {
89 spinlock_t lock;
90 u32 count;
91 } wake;
92 struct mutex mutex;
93
94 struct delayed_work ps_work;
95 unsigned long last_activity;
96 unsigned long idle_timeout;
97
98 struct {
99 unsigned long last_wake_event;
100 unsigned long awake_time;
101 unsigned long last_doze_event;
102 unsigned long doze_time;
103 unsigned int lp_wake;
104 } stats;
105};
106
107struct mt76_connac_coredump {
108 struct sk_buff_head msg_list;
109 struct delayed_work work;
110 unsigned long last_activity;
111};
112
113struct mt76_connac_sta_key_conf {
114 s8 keyidx;
115 u8 key[16];
116};
117
118#define MT_TXP_MAX_BUF_NUM 6
119
120struct mt76_connac_fw_txp {
121 __le16 flags;
122 __le16 token;
123 u8 bss_idx;
124 __le16 rept_wds_wcid;
125 u8 nbuf;
126 __le32 buf[MT_TXP_MAX_BUF_NUM];
127 __le16 len[MT_TXP_MAX_BUF_NUM];
128} __packed __aligned(4);
129
130#define MT_HW_TXP_MAX_MSDU_NUM 4
131#define MT_HW_TXP_MAX_BUF_NUM 4
132
133struct mt76_connac_txp_ptr {
134 __le32 buf0;
135 __le16 len0;
136 __le16 len1;
137 __le32 buf1;
138} __packed __aligned(4);
139
140struct mt76_connac_hw_txp {
141 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
142 struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
143} __packed __aligned(4);
144
145struct mt76_connac_txp_common {
146 union {
147 struct mt76_connac_fw_txp fw;
148 struct mt76_connac_hw_txp hw;
149 };
150};
151
152struct mt76_connac_tx_free {
153 __le16 rx_byte_cnt;
154 __le16 ctrl;
155 __le32 txd;
156} __packed __aligned(4);
157
158extern const struct wiphy_wowlan_support mt76_connac_wowlan_support;
159
160static inline bool is_mt7922(struct mt76_dev *dev)
161{
162 return mt76_chip(dev) == 0x7922;
163}
164
165static inline bool is_mt7921(struct mt76_dev *dev)
166{
167 return mt76_chip(dev) == 0x7961 || is_mt7922(dev);
168}
169
170static inline bool is_mt7663(struct mt76_dev *dev)
171{
172 return mt76_chip(dev) == 0x7663;
173}
174
175static inline bool is_mt7915(struct mt76_dev *dev)
176{
177 return mt76_chip(dev) == 0x7915;
178}
179
180static inline bool is_mt7916(struct mt76_dev *dev)
181{
182 return mt76_chip(dev) == 0x7906;
183}
184
185static inline bool is_mt7986(struct mt76_dev *dev)
186{
187 return mt76_chip(dev) == 0x7986;
188}
189
190static inline bool is_mt7996(struct mt76_dev *dev)
191{
192 return mt76_chip(dev) == 0x7990;
193}
194
195static inline bool is_mt7622(struct mt76_dev *dev)
196{
197 if (!IS_ENABLED(CONFIG_MT7622_WMAC))
198 return false;
199
200 return mt76_chip(dev) == 0x7622;
201}
202
203static inline bool is_mt7615(struct mt76_dev *dev)
204{
205 return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611;
206}
207
208static inline bool is_mt7611(struct mt76_dev *dev)
209{
210 return mt76_chip(dev) == 0x7611;
211}
212
213static inline bool is_connac_v1(struct mt76_dev *dev)
214{
215 return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev);
216}
217
218static inline bool is_mt76_fw_txp(struct mt76_dev *dev)
219{
220 switch (mt76_chip(dev)) {
221 case 0x7961:
222 case 0x7922:
223 case 0x7663:
224 case 0x7622:
225 return false;
226 default:
227 return true;
228 }
229}
230
231static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef)
232{
233 static const u8 width_to_bw[] = {
234 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
235 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
236 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
237 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
238 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
239 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
240 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
241 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
242 };
243
244 if (chandef->width >= ARRAY_SIZE(width_to_bw))
245 return 0;
246
247 return width_to_bw[chandef->width];
248}
249
250static inline u8 mt76_connac_lmac_mapping(u8 ac)
251{
252 /* LMAC uses the reverse order of mac80211 AC indexes */
253 return 3 - ac;
254}
255
256static inline void *
257mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
258{
259 u8 *txwi;
260
261 if (!t)
262 return NULL;
263
264 txwi = mt76_get_txwi_ptr(dev, t);
265
266 return (void *)(txwi + MT_TXD_SIZE);
267}
268
269static inline u8 mt76_connac_spe_idx(u8 antenna_mask)
270{
271 static const u8 ant_to_spe[] = {0, 0, 1, 0, 3, 2, 4, 0,
272 9, 8, 6, 10, 16, 12, 18, 0};
273
274 if (antenna_mask >= sizeof(ant_to_spe))
275 return 0;
276
277 return ant_to_spe[antenna_mask];
278}
279
280int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm);
281void mt76_connac_power_save_sched(struct mt76_phy *phy,
282 struct mt76_connac_pm *pm);
283void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm,
284 struct mt76_wcid *wcid);
285
286static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev)
287{
288 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false);
289 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false);
290}
291
292static inline bool
293mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
294{
295 bool ret = false;
296
297 spin_lock_bh(&pm->wake.lock);
298 if (test_bit(MT76_STATE_PM, &phy->state))
299 goto out;
300
301 pm->wake.count++;
302 ret = true;
303out:
304 spin_unlock_bh(&pm->wake.lock);
305
306 return ret;
307}
308
309static inline void
310mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
311{
312 spin_lock_bh(&pm->wake.lock);
313
314 pm->last_activity = jiffies;
315 if (--pm->wake.count == 0 &&
316 test_bit(MT76_STATE_MCU_RUNNING, &phy->state))
317 mt76_connac_power_save_sched(phy, pm);
318
319 spin_unlock_bh(&pm->wake.lock);
320}
321
322static inline bool
323mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm)
324{
325 struct mt76_dev *dev = phy->dev;
326 bool ret;
327
328 if (dev->token_count)
329 return true;
330
331 spin_lock_bh(&pm->wake.lock);
332 ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state);
333 spin_unlock_bh(&pm->wake.lock);
334
335 return ret;
336}
337
338static inline void
339mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm)
340 __acquires(&dev->mutex)
341{
342 mutex_lock(&dev->mutex);
343 mt76_connac_pm_wake(&dev->phy, pm);
344}
345
346static inline void
347mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm)
348 __releases(&dev->mutex)
349{
350 mt76_connac_power_save_sched(&dev->phy, pm);
351 mutex_unlock(&dev->mutex);
352}
353
354int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,
355 int ring_base, u32 flags);
356void mt76_connac_write_hw_txp(struct mt76_dev *dev,
357 struct mt76_tx_info *tx_info,
358 void *txp_ptr, u32 id);
359void mt76_connac_txp_skb_unmap(struct mt76_dev *dev,
360 struct mt76_txwi_cache *txwi);
361void mt76_connac_tx_complete_skb(struct mt76_dev *mdev,
362 struct mt76_queue_entry *e);
363void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw,
364 struct mt76_connac_pm *pm,
365 struct mt76_wcid *wcid,
366 struct sk_buff *skb);
367void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy,
368 struct mt76_connac_pm *pm);
369void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
370 struct sk_buff *skb, struct mt76_wcid *wcid,
371 struct ieee80211_key_conf *key, int pid,
372 enum mt76_txq_id qid, u32 changed);
373bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid,
374 __le32 *txs_data);
375bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid,
376 int pid, __le32 *txs_data);
377void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev,
378 struct sk_buff *skb,
379 __le32 *rxv, u32 mode);
380int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif,
381 struct sk_buff *skb, u16 hdr_offset);
382int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev,
383 struct mt76_rx_status *status,
384 struct ieee80211_supported_band *sband,
385 __le32 *rxv, u8 *mode);
386
387#endif /* __MT76_CONNAC_H */