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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/marvell.c
4 *
5 * Driver for Marvell PHYs
6 *
7 * Author: Andy Fleming
8 *
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 *
11 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12 */
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/ctype.h>
16#include <linux/errno.h>
17#include <linux/unistd.h>
18#include <linux/hwmon.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/spinlock.h>
26#include <linux/mm.h>
27#include <linux/module.h>
28#include <linux/mii.h>
29#include <linux/ethtool.h>
30#include <linux/ethtool_netlink.h>
31#include <linux/phy.h>
32#include <linux/marvell_phy.h>
33#include <linux/bitfield.h>
34#include <linux/of.h>
35#include <linux/sfp.h>
36
37#include <linux/io.h>
38#include <asm/irq.h>
39#include <linux/uaccess.h>
40
41#define MII_MARVELL_PHY_PAGE 22
42#define MII_MARVELL_COPPER_PAGE 0x00
43#define MII_MARVELL_FIBER_PAGE 0x01
44#define MII_MARVELL_MSCR_PAGE 0x02
45#define MII_MARVELL_LED_PAGE 0x03
46#define MII_MARVELL_VCT5_PAGE 0x05
47#define MII_MARVELL_MISC_TEST_PAGE 0x06
48#define MII_MARVELL_VCT7_PAGE 0x07
49#define MII_MARVELL_WOL_PAGE 0x11
50#define MII_MARVELL_MODE_PAGE 0x12
51
52#define MII_M1011_IEVENT 0x13
53#define MII_M1011_IEVENT_CLEAR 0x0000
54
55#define MII_M1011_IMASK 0x12
56#define MII_M1011_IMASK_INIT 0x6400
57#define MII_M1011_IMASK_CLEAR 0x0000
58
59#define MII_M1011_PHY_SCR 0x10
60#define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
61#define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
62#define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
63#define MII_M1011_PHY_SCR_MDI (0x0 << 5)
64#define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
65#define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
66
67#define MII_M1011_PHY_SSR 0x11
68#define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
69
70#define MII_M1111_PHY_LED_CONTROL 0x18
71#define MII_M1111_PHY_LED_DIRECT 0x4100
72#define MII_M1111_PHY_LED_COMBINE 0x411c
73#define MII_M1111_PHY_EXT_CR 0x14
74#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
75#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
76#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
77#define MII_M1111_RGMII_RX_DELAY BIT(7)
78#define MII_M1111_RGMII_TX_DELAY BIT(1)
79#define MII_M1111_PHY_EXT_SR 0x1b
80
81#define MII_M1111_HWCFG_MODE_MASK 0xf
82#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
83#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
84#define MII_M1111_HWCFG_MODE_RTBI 0x7
85#define MII_M1111_HWCFG_MODE_COPPER_1000X_AN 0x8
86#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
87#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
88#define MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN 0xc
89#define MII_M1111_HWCFG_SERIAL_AN_BYPASS BIT(12)
90#define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
91#define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
92
93#define MII_88E1121_PHY_MSCR_REG 21
94#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
95#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
96#define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
97
98#define MII_88E1121_MISC_TEST 0x1a
99#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
100#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
101#define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
102#define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
103#define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
104#define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
105
106#define MII_88E1510_TEMP_SENSOR 0x1b
107#define MII_88E1510_TEMP_SENSOR_MASK 0xff
108
109#define MII_88E1540_COPPER_CTRL3 0x1a
110#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
111#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
112#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
113#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
114#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
115#define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
116
117#define MII_88E6390_MISC_TEST 0x1b
118#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S (0x0 << 14)
119#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE (0x1 << 14)
120#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_ONESHOT (0x2 << 14)
121#define MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE (0x3 << 14)
122#define MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK (0x3 << 14)
123#define MII_88E6393_MISC_TEST_SAMPLES_2048 (0x0 << 11)
124#define MII_88E6393_MISC_TEST_SAMPLES_4096 (0x1 << 11)
125#define MII_88E6393_MISC_TEST_SAMPLES_8192 (0x2 << 11)
126#define MII_88E6393_MISC_TEST_SAMPLES_16384 (0x3 << 11)
127#define MII_88E6393_MISC_TEST_SAMPLES_MASK (0x3 << 11)
128#define MII_88E6393_MISC_TEST_RATE_2_3MS (0x5 << 8)
129#define MII_88E6393_MISC_TEST_RATE_6_4MS (0x6 << 8)
130#define MII_88E6393_MISC_TEST_RATE_11_9MS (0x7 << 8)
131#define MII_88E6393_MISC_TEST_RATE_MASK (0x7 << 8)
132
133#define MII_88E6390_TEMP_SENSOR 0x1c
134#define MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK 0xff00
135#define MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT 8
136#define MII_88E6390_TEMP_SENSOR_MASK 0xff
137#define MII_88E6390_TEMP_SENSOR_SAMPLES 10
138
139#define MII_88E1318S_PHY_MSCR1_REG 16
140#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
141
142/* Copper Specific Interrupt Enable Register */
143#define MII_88E1318S_PHY_CSIER 0x12
144/* WOL Event Interrupt Enable */
145#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
146
147#define MII_88E1318S_PHY_LED_FUNC 0x10
148#define MII_88E1318S_PHY_LED_FUNC_OFF (0x8)
149#define MII_88E1318S_PHY_LED_FUNC_ON (0x9)
150#define MII_88E1318S_PHY_LED_FUNC_HI_Z (0xa)
151#define MII_88E1318S_PHY_LED_FUNC_BLINK (0xb)
152#define MII_88E1318S_PHY_LED_TCR 0x12
153#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
154#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
155#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
156
157/* Magic Packet MAC address registers */
158#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
159#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
160#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
161
162#define MII_88E1318S_PHY_WOL_CTRL 0x10
163#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
164#define MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE BIT(13)
165#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
166
167#define MII_PHY_LED_CTRL 16
168#define MII_88E1121_PHY_LED_DEF 0x0030
169#define MII_88E1510_PHY_LED_DEF 0x1177
170#define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
171
172#define MII_M1011_PHY_STATUS 0x11
173#define MII_M1011_PHY_STATUS_1000 0x8000
174#define MII_M1011_PHY_STATUS_100 0x4000
175#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
176#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
177#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
178#define MII_M1011_PHY_STATUS_LINK 0x0400
179#define MII_M1011_PHY_STATUS_MDIX BIT(6)
180
181#define MII_88E3016_PHY_SPEC_CTRL 0x10
182#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
183#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
184
185#define MII_88E1510_GEN_CTRL_REG_1 0x14
186#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
187#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII 0x0 /* RGMII to copper */
188#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
189/* RGMII to 1000BASE-X */
190#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X 0x2
191/* RGMII to 100BASE-FX */
192#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX 0x3
193/* RGMII to SGMII */
194#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII 0x4
195#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
196
197#define MII_88E1510_MSCR_2 0x15
198
199#define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
200#define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
201#define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
202#define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
203#define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
204#define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
205#define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
206
207#define MII_VCT5_CTRL 0x17
208#define MII_VCT5_CTRL_ENABLE BIT(15)
209#define MII_VCT5_CTRL_COMPLETE BIT(14)
210#define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
211#define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
212#define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
213#define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
214#define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
215#define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
216#define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
217#define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
218#define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
219#define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
220#define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
221#define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
222#define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
223#define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
224#define MII_VCT5_CTRL_SAMPLES_SHIFT 8
225#define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
226#define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
227#define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
228#define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
229#define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
230
231#define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
232#define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
233#define MII_VCT5_TX_PULSE_CTRL 0x1c
234#define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
235#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
236#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
237#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
238#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
239#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
240#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
241#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
242#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
243#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
244#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
245#define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
246#define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
247
248/* For TDR measurements less than 11 meters, a short pulse should be
249 * used.
250 */
251#define TDR_SHORT_CABLE_LENGTH 11
252
253#define MII_VCT7_PAIR_0_DISTANCE 0x10
254#define MII_VCT7_PAIR_1_DISTANCE 0x11
255#define MII_VCT7_PAIR_2_DISTANCE 0x12
256#define MII_VCT7_PAIR_3_DISTANCE 0x13
257
258#define MII_VCT7_RESULTS 0x14
259#define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
260#define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
261#define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
262#define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
263#define MII_VCT7_RESULTS_PAIR3_SHIFT 12
264#define MII_VCT7_RESULTS_PAIR2_SHIFT 8
265#define MII_VCT7_RESULTS_PAIR1_SHIFT 4
266#define MII_VCT7_RESULTS_PAIR0_SHIFT 0
267#define MII_VCT7_RESULTS_INVALID 0
268#define MII_VCT7_RESULTS_OK 1
269#define MII_VCT7_RESULTS_OPEN 2
270#define MII_VCT7_RESULTS_SAME_SHORT 3
271#define MII_VCT7_RESULTS_CROSS_SHORT 4
272#define MII_VCT7_RESULTS_BUSY 9
273
274#define MII_VCT7_CTRL 0x15
275#define MII_VCT7_CTRL_RUN_NOW BIT(15)
276#define MII_VCT7_CTRL_RUN_ANEG BIT(14)
277#define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
278#define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
279#define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
280#define MII_VCT7_CTRL_METERS BIT(10)
281#define MII_VCT7_CTRL_CENTIMETERS 0
282
283#define MII_VCT_TXPINS 0x1A
284#define MII_VCT_RXPINS 0x1B
285#define MII_VCT_SR 0x1C
286#define MII_VCT_TXPINS_ENVCT BIT(15)
287#define MII_VCT_TXRXPINS_VCTTST GENMASK(14, 13)
288#define MII_VCT_TXRXPINS_VCTTST_SHIFT 13
289#define MII_VCT_TXRXPINS_VCTTST_OK 0
290#define MII_VCT_TXRXPINS_VCTTST_SHORT 1
291#define MII_VCT_TXRXPINS_VCTTST_OPEN 2
292#define MII_VCT_TXRXPINS_VCTTST_FAIL 3
293#define MII_VCT_TXRXPINS_AMPRFLN GENMASK(12, 8)
294#define MII_VCT_TXRXPINS_AMPRFLN_SHIFT 8
295#define MII_VCT_TXRXPINS_DISTRFLN GENMASK(7, 0)
296#define MII_VCT_TXRXPINS_DISTRFLN_MAX 0xff
297
298#define M88E3082_PAIR_A BIT(0)
299#define M88E3082_PAIR_B BIT(1)
300
301#define LPA_PAUSE_FIBER 0x180
302#define LPA_PAUSE_ASYM_FIBER 0x100
303
304#define NB_FIBER_STATS 1
305#define NB_STAT_MAX 3
306
307MODULE_DESCRIPTION("Marvell PHY driver");
308MODULE_AUTHOR("Andy Fleming");
309MODULE_LICENSE("GPL");
310
311struct marvell_hw_stat {
312 const char *string;
313 u8 page;
314 u8 reg;
315 u8 bits;
316};
317
318static const struct marvell_hw_stat marvell_hw_stats[] = {
319 { "phy_receive_errors_copper", 0, 21, 16},
320 { "phy_idle_errors", 0, 10, 8 },
321 { "phy_receive_errors_fiber", 1, 21, 16},
322};
323
324static_assert(ARRAY_SIZE(marvell_hw_stats) <= NB_STAT_MAX);
325
326/* "simple" stat list + corresponding marvell_get_*_simple functions are used
327 * on PHYs without a page register
328 */
329struct marvell_hw_stat_simple {
330 const char *string;
331 u8 reg;
332 u8 bits;
333};
334
335static const struct marvell_hw_stat_simple marvell_hw_stats_simple[] = {
336 { "phy_receive_errors", 21, 16},
337};
338
339static_assert(ARRAY_SIZE(marvell_hw_stats_simple) <= NB_STAT_MAX);
340
341enum {
342 M88E3082_VCT_OFF,
343 M88E3082_VCT_PHASE1,
344 M88E3082_VCT_PHASE2,
345};
346
347struct marvell_priv {
348 u64 stats[NB_STAT_MAX];
349 char *hwmon_name;
350 struct device *hwmon_dev;
351 bool cable_test_tdr;
352 u32 first;
353 u32 last;
354 u32 step;
355 s8 pair;
356 u8 vct_phase;
357};
358
359static int marvell_read_page(struct phy_device *phydev)
360{
361 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
362}
363
364static int marvell_write_page(struct phy_device *phydev, int page)
365{
366 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
367}
368
369static int marvell_set_page(struct phy_device *phydev, int page)
370{
371 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
372}
373
374static int marvell_ack_interrupt(struct phy_device *phydev)
375{
376 int err;
377
378 /* Clear the interrupts by reading the reg */
379 err = phy_read(phydev, MII_M1011_IEVENT);
380
381 if (err < 0)
382 return err;
383
384 return 0;
385}
386
387static int marvell_config_intr(struct phy_device *phydev)
388{
389 int err;
390
391 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
392 err = marvell_ack_interrupt(phydev);
393 if (err)
394 return err;
395
396 err = phy_write(phydev, MII_M1011_IMASK,
397 MII_M1011_IMASK_INIT);
398 } else {
399 err = phy_write(phydev, MII_M1011_IMASK,
400 MII_M1011_IMASK_CLEAR);
401 if (err)
402 return err;
403
404 err = marvell_ack_interrupt(phydev);
405 }
406
407 return err;
408}
409
410static irqreturn_t marvell_handle_interrupt(struct phy_device *phydev)
411{
412 int irq_status;
413
414 irq_status = phy_read(phydev, MII_M1011_IEVENT);
415 if (irq_status < 0) {
416 phy_error(phydev);
417 return IRQ_NONE;
418 }
419
420 if (!(irq_status & MII_M1011_IMASK_INIT))
421 return IRQ_NONE;
422
423 phy_trigger_machine(phydev);
424
425 return IRQ_HANDLED;
426}
427
428static int marvell_set_polarity(struct phy_device *phydev, int polarity)
429{
430 u16 val;
431
432 switch (polarity) {
433 case ETH_TP_MDI:
434 val = MII_M1011_PHY_SCR_MDI;
435 break;
436 case ETH_TP_MDI_X:
437 val = MII_M1011_PHY_SCR_MDI_X;
438 break;
439 case ETH_TP_MDI_AUTO:
440 case ETH_TP_MDI_INVALID:
441 default:
442 val = MII_M1011_PHY_SCR_AUTO_CROSS;
443 break;
444 }
445
446 return phy_modify_changed(phydev, MII_M1011_PHY_SCR,
447 MII_M1011_PHY_SCR_AUTO_CROSS, val);
448}
449
450static int marvell_config_aneg(struct phy_device *phydev)
451{
452 int changed = 0;
453 int err;
454
455 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
456 if (err < 0)
457 return err;
458
459 changed = err;
460
461 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
462 MII_M1111_PHY_LED_DIRECT);
463 if (err < 0)
464 return err;
465
466 err = genphy_config_aneg(phydev);
467 if (err < 0)
468 return err;
469
470 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
471 /* A write to speed/duplex bits (that is performed by
472 * genphy_config_aneg() call above) must be followed by
473 * a software reset. Otherwise, the write has no effect.
474 */
475 err = genphy_soft_reset(phydev);
476 if (err < 0)
477 return err;
478 }
479
480 return 0;
481}
482
483static int m88e1101_config_aneg(struct phy_device *phydev)
484{
485 int err;
486
487 /* This Marvell PHY has an errata which requires
488 * that certain registers get written in order
489 * to restart autonegotiation
490 */
491 err = genphy_soft_reset(phydev);
492 if (err < 0)
493 return err;
494
495 err = phy_write(phydev, 0x1d, 0x1f);
496 if (err < 0)
497 return err;
498
499 err = phy_write(phydev, 0x1e, 0x200c);
500 if (err < 0)
501 return err;
502
503 err = phy_write(phydev, 0x1d, 0x5);
504 if (err < 0)
505 return err;
506
507 err = phy_write(phydev, 0x1e, 0);
508 if (err < 0)
509 return err;
510
511 err = phy_write(phydev, 0x1e, 0x100);
512 if (err < 0)
513 return err;
514
515 return marvell_config_aneg(phydev);
516}
517
518#if IS_ENABLED(CONFIG_OF_MDIO)
519/* Set and/or override some configuration registers based on the
520 * marvell,reg-init property stored in the of_node for the phydev.
521 *
522 * marvell,reg-init = <reg-page reg mask value>,...;
523 *
524 * There may be one or more sets of <reg-page reg mask value>:
525 *
526 * reg-page: which register bank to use.
527 * reg: the register.
528 * mask: if non-zero, ANDed with existing register value.
529 * value: ORed with the masked value and written to the regiser.
530 *
531 */
532static int marvell_of_reg_init(struct phy_device *phydev)
533{
534 const __be32 *paddr;
535 int len, i, saved_page, current_page, ret = 0;
536
537 if (!phydev->mdio.dev.of_node)
538 return 0;
539
540 paddr = of_get_property(phydev->mdio.dev.of_node,
541 "marvell,reg-init", &len);
542 if (!paddr || len < (4 * sizeof(*paddr)))
543 return 0;
544
545 saved_page = phy_save_page(phydev);
546 if (saved_page < 0)
547 goto err;
548 current_page = saved_page;
549
550 len /= sizeof(*paddr);
551 for (i = 0; i < len - 3; i += 4) {
552 u16 page = be32_to_cpup(paddr + i);
553 u16 reg = be32_to_cpup(paddr + i + 1);
554 u16 mask = be32_to_cpup(paddr + i + 2);
555 u16 val_bits = be32_to_cpup(paddr + i + 3);
556 int val;
557
558 if (page != current_page) {
559 current_page = page;
560 ret = marvell_write_page(phydev, page);
561 if (ret < 0)
562 goto err;
563 }
564
565 val = 0;
566 if (mask) {
567 val = __phy_read(phydev, reg);
568 if (val < 0) {
569 ret = val;
570 goto err;
571 }
572 val &= mask;
573 }
574 val |= val_bits;
575
576 ret = __phy_write(phydev, reg, val);
577 if (ret < 0)
578 goto err;
579 }
580err:
581 return phy_restore_page(phydev, saved_page, ret);
582}
583#else
584static int marvell_of_reg_init(struct phy_device *phydev)
585{
586 return 0;
587}
588#endif /* CONFIG_OF_MDIO */
589
590static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
591{
592 int mscr;
593
594 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
595 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
596 MII_88E1121_PHY_MSCR_TX_DELAY;
597 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
598 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
599 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
600 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
601 else
602 mscr = 0;
603
604 return phy_modify_paged_changed(phydev, MII_MARVELL_MSCR_PAGE,
605 MII_88E1121_PHY_MSCR_REG,
606 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
607}
608
609static int m88e1121_config_aneg(struct phy_device *phydev)
610{
611 int changed = 0;
612 int err = 0;
613
614 if (phy_interface_is_rgmii(phydev)) {
615 err = m88e1121_config_aneg_rgmii_delays(phydev);
616 if (err < 0)
617 return err;
618 }
619
620 changed = err;
621
622 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
623 if (err < 0)
624 return err;
625
626 changed |= err;
627
628 err = genphy_config_aneg(phydev);
629 if (err < 0)
630 return err;
631
632 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
633 /* A software reset is used to ensure a "commit" of the
634 * changes is done.
635 */
636 err = genphy_soft_reset(phydev);
637 if (err < 0)
638 return err;
639 }
640
641 return 0;
642}
643
644static int m88e1318_config_aneg(struct phy_device *phydev)
645{
646 int err;
647
648 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
649 MII_88E1318S_PHY_MSCR1_REG,
650 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
651 if (err < 0)
652 return err;
653
654 return m88e1121_config_aneg(phydev);
655}
656
657/**
658 * linkmode_adv_to_fiber_adv_t
659 * @advertise: the linkmode advertisement settings
660 *
661 * A small helper function that translates linkmode advertisement
662 * settings to phy autonegotiation advertisements for the MII_ADV
663 * register for fiber link.
664 */
665static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
666{
667 u32 result = 0;
668
669 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
670 result |= ADVERTISE_1000XHALF;
671 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
672 result |= ADVERTISE_1000XFULL;
673
674 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
675 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
676 result |= ADVERTISE_1000XPSE_ASYM;
677 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
678 result |= ADVERTISE_1000XPAUSE;
679
680 return result;
681}
682
683/**
684 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
685 * @phydev: target phy_device struct
686 *
687 * Description: If auto-negotiation is enabled, we configure the
688 * advertising, and then restart auto-negotiation. If it is not
689 * enabled, then we write the BMCR. Adapted for fiber link in
690 * some Marvell's devices.
691 */
692static int marvell_config_aneg_fiber(struct phy_device *phydev)
693{
694 int changed = 0;
695 int err;
696 u16 adv;
697
698 if (phydev->autoneg != AUTONEG_ENABLE)
699 return genphy_setup_forced(phydev);
700
701 /* Only allow advertising what this PHY supports */
702 linkmode_and(phydev->advertising, phydev->advertising,
703 phydev->supported);
704
705 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
706
707 /* Setup fiber advertisement */
708 err = phy_modify_changed(phydev, MII_ADVERTISE,
709 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
710 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
711 adv);
712 if (err < 0)
713 return err;
714 if (err > 0)
715 changed = 1;
716
717 return genphy_check_and_restart_aneg(phydev, changed);
718}
719
720static int m88e1111_config_aneg(struct phy_device *phydev)
721{
722 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
723 int err;
724
725 if (extsr < 0)
726 return extsr;
727
728 /* If not using SGMII or copper 1000BaseX modes, use normal process.
729 * Steps below are only required for these modes.
730 */
731 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
732 (extsr & MII_M1111_HWCFG_MODE_MASK) !=
733 MII_M1111_HWCFG_MODE_COPPER_1000X_AN)
734 return marvell_config_aneg(phydev);
735
736 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
737 if (err < 0)
738 goto error;
739
740 /* Configure the copper link first */
741 err = marvell_config_aneg(phydev);
742 if (err < 0)
743 goto error;
744
745 /* Then the fiber link */
746 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
747 if (err < 0)
748 goto error;
749
750 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
751 /* Do not touch the fiber advertisement if we're in copper->sgmii mode.
752 * Just ensure that SGMII-side autonegotiation is enabled.
753 * If we switched from some other mode to SGMII it may not be.
754 */
755 err = genphy_check_and_restart_aneg(phydev, false);
756 else
757 err = marvell_config_aneg_fiber(phydev);
758 if (err < 0)
759 goto error;
760
761 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
762
763error:
764 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
765 return err;
766}
767
768static int m88e1510_config_aneg(struct phy_device *phydev)
769{
770 int err;
771
772 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
773 if (err < 0)
774 goto error;
775
776 /* Configure the copper link first */
777 err = m88e1318_config_aneg(phydev);
778 if (err < 0)
779 goto error;
780
781 /* Do not touch the fiber page if we're in copper->sgmii mode */
782 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
783 return 0;
784
785 /* Then the fiber link */
786 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
787 if (err < 0)
788 goto error;
789
790 err = marvell_config_aneg_fiber(phydev);
791 if (err < 0)
792 goto error;
793
794 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
795
796error:
797 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
798 return err;
799}
800
801static void marvell_config_led(struct phy_device *phydev)
802{
803 u16 def_config;
804 int err;
805
806 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
807 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
808 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
809 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
810 def_config = MII_88E1121_PHY_LED_DEF;
811 break;
812 /* Default PHY LED config:
813 * LED[0] .. 1000Mbps Link
814 * LED[1] .. 100Mbps Link
815 * LED[2] .. Blink, Activity
816 */
817 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
818 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
819 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
820 else
821 def_config = MII_88E1510_PHY_LED_DEF;
822 break;
823 default:
824 return;
825 }
826
827 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
828 def_config);
829 if (err < 0)
830 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
831}
832
833static int marvell_config_init(struct phy_device *phydev)
834{
835 /* Set default LED */
836 marvell_config_led(phydev);
837
838 /* Set registers from marvell,reg-init DT property */
839 return marvell_of_reg_init(phydev);
840}
841
842static int m88e3016_config_init(struct phy_device *phydev)
843{
844 int ret;
845
846 /* Enable Scrambler and Auto-Crossover */
847 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
848 MII_88E3016_DISABLE_SCRAMBLER,
849 MII_88E3016_AUTO_MDIX_CROSSOVER);
850 if (ret < 0)
851 return ret;
852
853 return marvell_config_init(phydev);
854}
855
856static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
857 u16 mode,
858 int fibre_copper_auto)
859{
860 if (fibre_copper_auto)
861 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
862
863 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
864 MII_M1111_HWCFG_MODE_MASK |
865 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
866 MII_M1111_HWCFG_FIBER_COPPER_RES,
867 mode);
868}
869
870static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
871{
872 int delay;
873
874 switch (phydev->interface) {
875 case PHY_INTERFACE_MODE_RGMII_ID:
876 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
877 break;
878 case PHY_INTERFACE_MODE_RGMII_RXID:
879 delay = MII_M1111_RGMII_RX_DELAY;
880 break;
881 case PHY_INTERFACE_MODE_RGMII_TXID:
882 delay = MII_M1111_RGMII_TX_DELAY;
883 break;
884 default:
885 delay = 0;
886 break;
887 }
888
889 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
890 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
891 delay);
892}
893
894static int m88e1111_config_init_rgmii(struct phy_device *phydev)
895{
896 int temp;
897 int err;
898
899 err = m88e1111_config_init_rgmii_delays(phydev);
900 if (err < 0)
901 return err;
902
903 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
904 if (temp < 0)
905 return temp;
906
907 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
908
909 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
910 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
911 else
912 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
913
914 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
915}
916
917static int m88e1111_config_init_sgmii(struct phy_device *phydev)
918{
919 int err;
920
921 err = m88e1111_config_init_hwcfg_mode(
922 phydev,
923 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
924 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
925 if (err < 0)
926 return err;
927
928 /* make sure copper is selected */
929 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
930}
931
932static int m88e1111_config_init_rtbi(struct phy_device *phydev)
933{
934 int err;
935
936 err = m88e1111_config_init_rgmii_delays(phydev);
937 if (err < 0)
938 return err;
939
940 err = m88e1111_config_init_hwcfg_mode(
941 phydev,
942 MII_M1111_HWCFG_MODE_RTBI,
943 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
944 if (err < 0)
945 return err;
946
947 /* soft reset */
948 err = genphy_soft_reset(phydev);
949 if (err < 0)
950 return err;
951
952 return m88e1111_config_init_hwcfg_mode(
953 phydev,
954 MII_M1111_HWCFG_MODE_RTBI,
955 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
956}
957
958static int m88e1111_config_init_1000basex(struct phy_device *phydev)
959{
960 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
961 int err, mode;
962
963 if (extsr < 0)
964 return extsr;
965
966 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled.
967 * FIXME: this does not actually enable 1000BaseX auto-negotiation if
968 * it was previously disabled in the Fiber BMCR!
969 */
970 mode = extsr & MII_M1111_HWCFG_MODE_MASK;
971 if (mode == MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN) {
972 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
973 MII_M1111_HWCFG_MODE_MASK |
974 MII_M1111_HWCFG_SERIAL_AN_BYPASS,
975 MII_M1111_HWCFG_MODE_COPPER_1000X_AN |
976 MII_M1111_HWCFG_SERIAL_AN_BYPASS);
977 if (err < 0)
978 return err;
979 }
980 return 0;
981}
982
983static int m88e1111_config_init(struct phy_device *phydev)
984{
985 int err;
986
987 if (phy_interface_is_rgmii(phydev)) {
988 err = m88e1111_config_init_rgmii(phydev);
989 if (err < 0)
990 return err;
991 }
992
993 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
994 err = m88e1111_config_init_sgmii(phydev);
995 if (err < 0)
996 return err;
997 }
998
999 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
1000 err = m88e1111_config_init_rtbi(phydev);
1001 if (err < 0)
1002 return err;
1003 }
1004
1005 if (phydev->interface == PHY_INTERFACE_MODE_1000BASEX) {
1006 err = m88e1111_config_init_1000basex(phydev);
1007 if (err < 0)
1008 return err;
1009 }
1010
1011 err = marvell_of_reg_init(phydev);
1012 if (err < 0)
1013 return err;
1014
1015 err = genphy_soft_reset(phydev);
1016 if (err < 0)
1017 return err;
1018
1019 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1020 /* If the HWCFG_MODE was changed from another mode (such as
1021 * 1000BaseX) to SGMII, the state of the support bits may have
1022 * also changed now that the PHY has been reset.
1023 * Update the PHY abilities accordingly.
1024 */
1025 err = genphy_read_abilities(phydev);
1026 linkmode_or(phydev->advertising, phydev->advertising,
1027 phydev->supported);
1028 }
1029 return err;
1030}
1031
1032static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
1033{
1034 int val, cnt, enable;
1035
1036 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
1037 if (val < 0)
1038 return val;
1039
1040 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
1041 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
1042
1043 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1044
1045 return 0;
1046}
1047
1048static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
1049{
1050 int val, err;
1051
1052 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
1053 return -E2BIG;
1054
1055 if (!cnt) {
1056 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
1057 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
1058 } else {
1059 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
1060 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
1061
1062 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
1063 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
1064 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
1065 val);
1066 }
1067
1068 if (err < 0)
1069 return err;
1070
1071 return genphy_soft_reset(phydev);
1072}
1073
1074static int m88e1111_get_tunable(struct phy_device *phydev,
1075 struct ethtool_tunable *tuna, void *data)
1076{
1077 switch (tuna->id) {
1078 case ETHTOOL_PHY_DOWNSHIFT:
1079 return m88e1111_get_downshift(phydev, data);
1080 default:
1081 return -EOPNOTSUPP;
1082 }
1083}
1084
1085static int m88e1111_set_tunable(struct phy_device *phydev,
1086 struct ethtool_tunable *tuna, const void *data)
1087{
1088 switch (tuna->id) {
1089 case ETHTOOL_PHY_DOWNSHIFT:
1090 return m88e1111_set_downshift(phydev, *(const u8 *)data);
1091 default:
1092 return -EOPNOTSUPP;
1093 }
1094}
1095
1096static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
1097{
1098 int val, cnt, enable;
1099
1100 val = phy_read(phydev, MII_M1011_PHY_SCR);
1101 if (val < 0)
1102 return val;
1103
1104 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
1105 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
1106
1107 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1108
1109 return 0;
1110}
1111
1112static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
1113{
1114 int val, err;
1115
1116 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
1117 return -E2BIG;
1118
1119 if (!cnt) {
1120 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
1121 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
1122 } else {
1123 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
1124 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
1125
1126 err = phy_modify(phydev, MII_M1011_PHY_SCR,
1127 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
1128 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
1129 val);
1130 }
1131
1132 if (err < 0)
1133 return err;
1134
1135 return genphy_soft_reset(phydev);
1136}
1137
1138static int m88e1011_get_tunable(struct phy_device *phydev,
1139 struct ethtool_tunable *tuna, void *data)
1140{
1141 switch (tuna->id) {
1142 case ETHTOOL_PHY_DOWNSHIFT:
1143 return m88e1011_get_downshift(phydev, data);
1144 default:
1145 return -EOPNOTSUPP;
1146 }
1147}
1148
1149static int m88e1011_set_tunable(struct phy_device *phydev,
1150 struct ethtool_tunable *tuna, const void *data)
1151{
1152 switch (tuna->id) {
1153 case ETHTOOL_PHY_DOWNSHIFT:
1154 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1155 default:
1156 return -EOPNOTSUPP;
1157 }
1158}
1159
1160static int m88e1112_config_init(struct phy_device *phydev)
1161{
1162 int err;
1163
1164 err = m88e1011_set_downshift(phydev, 3);
1165 if (err < 0)
1166 return err;
1167
1168 return m88e1111_config_init(phydev);
1169}
1170
1171static int m88e1111gbe_config_init(struct phy_device *phydev)
1172{
1173 int err;
1174
1175 err = m88e1111_set_downshift(phydev, 3);
1176 if (err < 0)
1177 return err;
1178
1179 return m88e1111_config_init(phydev);
1180}
1181
1182static int marvell_1011gbe_config_init(struct phy_device *phydev)
1183{
1184 int err;
1185
1186 err = m88e1011_set_downshift(phydev, 3);
1187 if (err < 0)
1188 return err;
1189
1190 return marvell_config_init(phydev);
1191}
1192static int m88e1116r_config_init(struct phy_device *phydev)
1193{
1194 int err;
1195
1196 err = genphy_soft_reset(phydev);
1197 if (err < 0)
1198 return err;
1199
1200 msleep(500);
1201
1202 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1203 if (err < 0)
1204 return err;
1205
1206 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1207 if (err < 0)
1208 return err;
1209
1210 err = m88e1011_set_downshift(phydev, 8);
1211 if (err < 0)
1212 return err;
1213
1214 if (phy_interface_is_rgmii(phydev)) {
1215 err = m88e1121_config_aneg_rgmii_delays(phydev);
1216 if (err < 0)
1217 return err;
1218 }
1219
1220 err = genphy_soft_reset(phydev);
1221 if (err < 0)
1222 return err;
1223
1224 return marvell_config_init(phydev);
1225}
1226
1227static int m88e1318_config_init(struct phy_device *phydev)
1228{
1229 if (phy_interrupt_is_valid(phydev)) {
1230 int err = phy_modify_paged(
1231 phydev, MII_MARVELL_LED_PAGE,
1232 MII_88E1318S_PHY_LED_TCR,
1233 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1234 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1235 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1236 if (err < 0)
1237 return err;
1238 }
1239
1240 return marvell_config_init(phydev);
1241}
1242
1243static int m88e1510_config_init(struct phy_device *phydev)
1244{
1245 static const struct {
1246 u16 reg17, reg16;
1247 } errata_vals[] = {
1248 { 0x214b, 0x2144 },
1249 { 0x0c28, 0x2146 },
1250 { 0xb233, 0x214d },
1251 { 0xcc0c, 0x2159 },
1252 };
1253 int err;
1254 int i;
1255
1256 /* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/
1257 * 88E1514 Rev A0, Errata Section 5.1:
1258 * If EEE is intended to be used, the following register writes
1259 * must be done once after every hardware reset.
1260 */
1261 err = marvell_set_page(phydev, 0x00FF);
1262 if (err < 0)
1263 return err;
1264
1265 for (i = 0; i < ARRAY_SIZE(errata_vals); ++i) {
1266 err = phy_write(phydev, 17, errata_vals[i].reg17);
1267 if (err)
1268 return err;
1269 err = phy_write(phydev, 16, errata_vals[i].reg16);
1270 if (err)
1271 return err;
1272 }
1273
1274 err = marvell_set_page(phydev, 0x00FB);
1275 if (err < 0)
1276 return err;
1277 err = phy_write(phydev, 07, 0xC00D);
1278 if (err < 0)
1279 return err;
1280 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1281 if (err < 0)
1282 return err;
1283
1284 /* SGMII-to-Copper mode initialization */
1285 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1286 /* Select page 18 */
1287 err = marvell_set_page(phydev, 18);
1288 if (err < 0)
1289 return err;
1290
1291 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1292 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1293 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1294 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1295 if (err < 0)
1296 return err;
1297
1298 /* PHY reset is necessary after changing MODE[2:0] */
1299 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
1300 MII_88E1510_GEN_CTRL_REG_1_RESET);
1301 if (err < 0)
1302 return err;
1303
1304 /* Reset page selection */
1305 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1306 if (err < 0)
1307 return err;
1308 }
1309 err = m88e1011_set_downshift(phydev, 3);
1310 if (err < 0)
1311 return err;
1312
1313 return m88e1318_config_init(phydev);
1314}
1315
1316static int m88e1118_config_aneg(struct phy_device *phydev)
1317{
1318 int err;
1319
1320 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1321 if (err < 0)
1322 return err;
1323
1324 err = genphy_config_aneg(phydev);
1325 if (err < 0)
1326 return err;
1327
1328 return genphy_soft_reset(phydev);
1329}
1330
1331static int m88e1118_config_init(struct phy_device *phydev)
1332{
1333 u16 leds;
1334 int err;
1335
1336 /* Enable 1000 Mbit */
1337 err = phy_write_paged(phydev, MII_MARVELL_MSCR_PAGE,
1338 MII_88E1121_PHY_MSCR_REG, 0x1070);
1339 if (err < 0)
1340 return err;
1341
1342 if (phy_interface_is_rgmii(phydev)) {
1343 err = m88e1121_config_aneg_rgmii_delays(phydev);
1344 if (err < 0)
1345 return err;
1346 }
1347
1348 /* Adjust LED Control */
1349 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1350 leds = 0x1100;
1351 else
1352 leds = 0x021e;
1353
1354 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, 0x10, leds);
1355 if (err < 0)
1356 return err;
1357
1358 err = marvell_of_reg_init(phydev);
1359 if (err < 0)
1360 return err;
1361
1362 /* Reset page register */
1363 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1364 if (err < 0)
1365 return err;
1366
1367 return genphy_soft_reset(phydev);
1368}
1369
1370static int m88e1149_config_init(struct phy_device *phydev)
1371{
1372 int err;
1373
1374 /* Change address */
1375 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1376 if (err < 0)
1377 return err;
1378
1379 /* Enable 1000 Mbit */
1380 err = phy_write(phydev, 0x15, 0x1048);
1381 if (err < 0)
1382 return err;
1383
1384 err = marvell_of_reg_init(phydev);
1385 if (err < 0)
1386 return err;
1387
1388 /* Reset address */
1389 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1390 if (err < 0)
1391 return err;
1392
1393 return genphy_soft_reset(phydev);
1394}
1395
1396static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1397{
1398 int err;
1399
1400 err = m88e1111_config_init_rgmii_delays(phydev);
1401 if (err < 0)
1402 return err;
1403
1404 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1405 err = phy_write(phydev, 0x1d, 0x0012);
1406 if (err < 0)
1407 return err;
1408
1409 err = phy_modify(phydev, 0x1e, 0x0fc0,
1410 2 << 9 | /* 36 ohm */
1411 2 << 6); /* 39 ohm */
1412 if (err < 0)
1413 return err;
1414
1415 err = phy_write(phydev, 0x1d, 0x3);
1416 if (err < 0)
1417 return err;
1418
1419 err = phy_write(phydev, 0x1e, 0x8000);
1420 }
1421 return err;
1422}
1423
1424static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1425{
1426 return m88e1111_config_init_hwcfg_mode(
1427 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1428 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1429}
1430
1431static int m88e1145_config_init(struct phy_device *phydev)
1432{
1433 int err;
1434
1435 /* Take care of errata E0 & E1 */
1436 err = phy_write(phydev, 0x1d, 0x001b);
1437 if (err < 0)
1438 return err;
1439
1440 err = phy_write(phydev, 0x1e, 0x418f);
1441 if (err < 0)
1442 return err;
1443
1444 err = phy_write(phydev, 0x1d, 0x0016);
1445 if (err < 0)
1446 return err;
1447
1448 err = phy_write(phydev, 0x1e, 0xa2da);
1449 if (err < 0)
1450 return err;
1451
1452 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1453 err = m88e1145_config_init_rgmii(phydev);
1454 if (err < 0)
1455 return err;
1456 }
1457
1458 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1459 err = m88e1145_config_init_sgmii(phydev);
1460 if (err < 0)
1461 return err;
1462 }
1463 err = m88e1111_set_downshift(phydev, 3);
1464 if (err < 0)
1465 return err;
1466
1467 err = marvell_of_reg_init(phydev);
1468 if (err < 0)
1469 return err;
1470
1471 return 0;
1472}
1473
1474static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1475{
1476 int val;
1477
1478 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1479 if (val < 0)
1480 return val;
1481
1482 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1483 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1484 return 0;
1485 }
1486
1487 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1488
1489 switch (val) {
1490 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1491 *msecs = 0;
1492 break;
1493 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1494 *msecs = 10;
1495 break;
1496 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1497 *msecs = 20;
1498 break;
1499 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1500 *msecs = 40;
1501 break;
1502 default:
1503 return -EINVAL;
1504 }
1505
1506 return 0;
1507}
1508
1509static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1510{
1511 struct ethtool_keee eee;
1512 int val, ret;
1513
1514 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1515 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1516 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1517
1518 /* According to the Marvell data sheet EEE must be disabled for
1519 * Fast Link Down detection to work properly
1520 */
1521 ret = genphy_c45_ethtool_get_eee(phydev, &eee);
1522 if (!ret && eee.eee_enabled) {
1523 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1524 return -EBUSY;
1525 }
1526
1527 if (*msecs <= 5)
1528 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1529 else if (*msecs <= 15)
1530 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1531 else if (*msecs <= 30)
1532 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1533 else
1534 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1535
1536 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1537
1538 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1539 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1540 if (ret)
1541 return ret;
1542
1543 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1544 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1545}
1546
1547static int m88e1540_get_tunable(struct phy_device *phydev,
1548 struct ethtool_tunable *tuna, void *data)
1549{
1550 switch (tuna->id) {
1551 case ETHTOOL_PHY_FAST_LINK_DOWN:
1552 return m88e1540_get_fld(phydev, data);
1553 case ETHTOOL_PHY_DOWNSHIFT:
1554 return m88e1011_get_downshift(phydev, data);
1555 default:
1556 return -EOPNOTSUPP;
1557 }
1558}
1559
1560static int m88e1540_set_tunable(struct phy_device *phydev,
1561 struct ethtool_tunable *tuna, const void *data)
1562{
1563 switch (tuna->id) {
1564 case ETHTOOL_PHY_FAST_LINK_DOWN:
1565 return m88e1540_set_fld(phydev, data);
1566 case ETHTOOL_PHY_DOWNSHIFT:
1567 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1568 default:
1569 return -EOPNOTSUPP;
1570 }
1571}
1572
1573/* The VOD can be out of specification on link up. Poke an
1574 * undocumented register, in an undocumented page, with a magic value
1575 * to fix this.
1576 */
1577static int m88e6390_errata(struct phy_device *phydev)
1578{
1579 int err;
1580
1581 err = phy_write(phydev, MII_BMCR,
1582 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1583 if (err)
1584 return err;
1585
1586 usleep_range(300, 400);
1587
1588 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1589 if (err)
1590 return err;
1591
1592 return genphy_soft_reset(phydev);
1593}
1594
1595static int m88e6390_config_aneg(struct phy_device *phydev)
1596{
1597 int err;
1598
1599 err = m88e6390_errata(phydev);
1600 if (err)
1601 return err;
1602
1603 return m88e1510_config_aneg(phydev);
1604}
1605
1606/**
1607 * fiber_lpa_mod_linkmode_lpa_t
1608 * @advertising: the linkmode advertisement settings
1609 * @lpa: value of the MII_LPA register for fiber link
1610 *
1611 * A small helper function that translates MII_LPA bits to linkmode LP
1612 * advertisement settings. Other bits in advertising are left
1613 * unchanged.
1614 */
1615static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1616{
1617 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1618 advertising, lpa & LPA_1000XHALF);
1619
1620 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1621 advertising, lpa & LPA_1000XFULL);
1622}
1623
1624static int marvell_read_status_page_an(struct phy_device *phydev,
1625 int fiber, int status)
1626{
1627 int lpa;
1628 int err;
1629
1630 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1631 phydev->link = 0;
1632 return 0;
1633 }
1634
1635 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1636 phydev->duplex = DUPLEX_FULL;
1637 else
1638 phydev->duplex = DUPLEX_HALF;
1639
1640 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1641 case MII_M1011_PHY_STATUS_1000:
1642 phydev->speed = SPEED_1000;
1643 break;
1644
1645 case MII_M1011_PHY_STATUS_100:
1646 phydev->speed = SPEED_100;
1647 break;
1648
1649 default:
1650 phydev->speed = SPEED_10;
1651 break;
1652 }
1653
1654 if (!fiber) {
1655 err = genphy_read_lpa(phydev);
1656 if (err < 0)
1657 return err;
1658
1659 phy_resolve_aneg_pause(phydev);
1660 } else {
1661 lpa = phy_read(phydev, MII_LPA);
1662 if (lpa < 0)
1663 return lpa;
1664
1665 /* The fiber link is only 1000M capable */
1666 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1667
1668 if (phydev->duplex == DUPLEX_FULL) {
1669 if (!(lpa & LPA_PAUSE_FIBER)) {
1670 phydev->pause = 0;
1671 phydev->asym_pause = 0;
1672 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1673 phydev->pause = 1;
1674 phydev->asym_pause = 1;
1675 } else {
1676 phydev->pause = 1;
1677 phydev->asym_pause = 0;
1678 }
1679 }
1680 }
1681
1682 return 0;
1683}
1684
1685/* marvell_read_status_page
1686 *
1687 * Description:
1688 * Check the link, then figure out the current state
1689 * by comparing what we advertise with what the link partner
1690 * advertises. Start by checking the gigabit possibilities,
1691 * then move on to 10/100.
1692 */
1693static int marvell_read_status_page(struct phy_device *phydev, int page)
1694{
1695 int status;
1696 int fiber;
1697 int err;
1698
1699 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1700 if (status < 0)
1701 return status;
1702
1703 /* Use the generic register for copper link status,
1704 * and the PHY status register for fiber link status.
1705 */
1706 if (page == MII_MARVELL_FIBER_PAGE) {
1707 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1708 } else {
1709 err = genphy_update_link(phydev);
1710 if (err)
1711 return err;
1712 }
1713
1714 if (page == MII_MARVELL_FIBER_PAGE)
1715 fiber = 1;
1716 else
1717 fiber = 0;
1718
1719 linkmode_zero(phydev->lp_advertising);
1720 phydev->pause = 0;
1721 phydev->asym_pause = 0;
1722 phydev->speed = SPEED_UNKNOWN;
1723 phydev->duplex = DUPLEX_UNKNOWN;
1724 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1725
1726 if (fiber) {
1727 phydev->mdix = ETH_TP_MDI_INVALID;
1728 } else {
1729 /* The MDI-X state is set regardless of Autoneg being enabled
1730 * and reflects forced MDI-X state as well as auto resolution
1731 */
1732 if (status & MII_M1011_PHY_STATUS_RESOLVED)
1733 phydev->mdix = status & MII_M1011_PHY_STATUS_MDIX ?
1734 ETH_TP_MDI_X : ETH_TP_MDI;
1735 else
1736 phydev->mdix = ETH_TP_MDI_INVALID;
1737 }
1738
1739 if (phydev->autoneg == AUTONEG_ENABLE)
1740 err = marvell_read_status_page_an(phydev, fiber, status);
1741 else
1742 err = genphy_read_status_fixed(phydev);
1743
1744 return err;
1745}
1746
1747/* marvell_read_status
1748 *
1749 * Some Marvell's phys have two modes: fiber and copper.
1750 * Both need status checked.
1751 * Description:
1752 * First, check the fiber link and status.
1753 * If the fiber link is down, check the copper link and status which
1754 * will be the default value if both link are down.
1755 */
1756static int marvell_read_status(struct phy_device *phydev)
1757{
1758 int err;
1759
1760 /* Check the fiber mode first */
1761 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1762 phydev->supported) &&
1763 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1764 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1765 if (err < 0)
1766 goto error;
1767
1768 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1769 if (err < 0)
1770 goto error;
1771
1772 /* If the fiber link is up, it is the selected and
1773 * used link. In this case, we need to stay in the
1774 * fiber page. Please to be careful about that, avoid
1775 * to restore Copper page in other functions which
1776 * could break the behaviour for some fiber phy like
1777 * 88E1512.
1778 */
1779 if (phydev->link)
1780 return 0;
1781
1782 /* If fiber link is down, check and save copper mode state */
1783 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1784 if (err < 0)
1785 goto error;
1786 }
1787
1788 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1789
1790error:
1791 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1792 return err;
1793}
1794
1795/* marvell_suspend
1796 *
1797 * Some Marvell's phys have two modes: fiber and copper.
1798 * Both need to be suspended
1799 */
1800static int marvell_suspend(struct phy_device *phydev)
1801{
1802 int err;
1803
1804 /* Suspend the fiber mode first */
1805 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1806 phydev->supported)) {
1807 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1808 if (err < 0)
1809 goto error;
1810
1811 /* With the page set, use the generic suspend */
1812 err = genphy_suspend(phydev);
1813 if (err < 0)
1814 goto error;
1815
1816 /* Then, the copper link */
1817 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1818 if (err < 0)
1819 goto error;
1820 }
1821
1822 /* With the page set, use the generic suspend */
1823 return genphy_suspend(phydev);
1824
1825error:
1826 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1827 return err;
1828}
1829
1830/* marvell_resume
1831 *
1832 * Some Marvell's phys have two modes: fiber and copper.
1833 * Both need to be resumed
1834 */
1835static int marvell_resume(struct phy_device *phydev)
1836{
1837 int err;
1838
1839 /* Resume the fiber mode first */
1840 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1841 phydev->supported)) {
1842 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1843 if (err < 0)
1844 goto error;
1845
1846 /* With the page set, use the generic resume */
1847 err = genphy_resume(phydev);
1848 if (err < 0)
1849 goto error;
1850
1851 /* Then, the copper link */
1852 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1853 if (err < 0)
1854 goto error;
1855 }
1856
1857 /* With the page set, use the generic resume */
1858 return genphy_resume(phydev);
1859
1860error:
1861 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1862 return err;
1863}
1864
1865static int marvell_aneg_done(struct phy_device *phydev)
1866{
1867 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1868
1869 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1870}
1871
1872static void m88e1318_get_wol(struct phy_device *phydev,
1873 struct ethtool_wolinfo *wol)
1874{
1875 int ret;
1876
1877 wol->supported = WAKE_MAGIC | WAKE_PHY;
1878 wol->wolopts = 0;
1879
1880 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1881 MII_88E1318S_PHY_WOL_CTRL);
1882 if (ret < 0)
1883 return;
1884
1885 if (ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1886 wol->wolopts |= WAKE_MAGIC;
1887
1888 if (ret & MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE)
1889 wol->wolopts |= WAKE_PHY;
1890}
1891
1892static int m88e1318_set_wol(struct phy_device *phydev,
1893 struct ethtool_wolinfo *wol)
1894{
1895 int err = 0, oldpage;
1896
1897 oldpage = phy_save_page(phydev);
1898 if (oldpage < 0)
1899 goto error;
1900
1901 if (wol->wolopts & (WAKE_MAGIC | WAKE_PHY)) {
1902 /* Explicitly switch to page 0x00, just to be sure */
1903 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1904 if (err < 0)
1905 goto error;
1906
1907 /* If WOL event happened once, the LED[2] interrupt pin
1908 * will not be cleared unless we reading the interrupt status
1909 * register. If interrupts are in use, the normal interrupt
1910 * handling will clear the WOL event. Clear the WOL event
1911 * before enabling it if !phy_interrupt_is_valid()
1912 */
1913 if (!phy_interrupt_is_valid(phydev))
1914 __phy_read(phydev, MII_M1011_IEVENT);
1915
1916 /* Enable the WOL interrupt */
1917 err = __phy_set_bits(phydev, MII_88E1318S_PHY_CSIER,
1918 MII_88E1318S_PHY_CSIER_WOL_EIE);
1919 if (err < 0)
1920 goto error;
1921
1922 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1923 if (err < 0)
1924 goto error;
1925
1926 /* Setup LED[2] as interrupt pin (active low) */
1927 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1928 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1929 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1930 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1931 if (err < 0)
1932 goto error;
1933 }
1934
1935 if (wol->wolopts & WAKE_MAGIC) {
1936 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1937 if (err < 0)
1938 goto error;
1939
1940 /* Store the device address for the magic packet */
1941 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1942 ((phydev->attached_dev->dev_addr[5] << 8) |
1943 phydev->attached_dev->dev_addr[4]));
1944 if (err < 0)
1945 goto error;
1946 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1947 ((phydev->attached_dev->dev_addr[3] << 8) |
1948 phydev->attached_dev->dev_addr[2]));
1949 if (err < 0)
1950 goto error;
1951 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1952 ((phydev->attached_dev->dev_addr[1] << 8) |
1953 phydev->attached_dev->dev_addr[0]));
1954 if (err < 0)
1955 goto error;
1956
1957 /* Clear WOL status and enable magic packet matching */
1958 err = __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
1959 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1960 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1961 if (err < 0)
1962 goto error;
1963 } else {
1964 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1965 if (err < 0)
1966 goto error;
1967
1968 /* Clear WOL status and disable magic packet matching */
1969 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1970 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1971 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1972 if (err < 0)
1973 goto error;
1974 }
1975
1976 if (wol->wolopts & WAKE_PHY) {
1977 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1978 if (err < 0)
1979 goto error;
1980
1981 /* Clear WOL status and enable link up event */
1982 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL, 0,
1983 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1984 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE);
1985 if (err < 0)
1986 goto error;
1987 } else {
1988 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1989 if (err < 0)
1990 goto error;
1991
1992 /* Clear WOL status and disable link up event */
1993 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1994 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE,
1995 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1996 if (err < 0)
1997 goto error;
1998 }
1999
2000error:
2001 return phy_restore_page(phydev, oldpage, err);
2002}
2003
2004static int marvell_get_sset_count(struct phy_device *phydev)
2005{
2006 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2007 phydev->supported))
2008 return ARRAY_SIZE(marvell_hw_stats);
2009 else
2010 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
2011}
2012
2013static int marvell_get_sset_count_simple(struct phy_device *phydev)
2014{
2015 return ARRAY_SIZE(marvell_hw_stats_simple);
2016}
2017
2018static void marvell_get_strings(struct phy_device *phydev, u8 *data)
2019{
2020 int count = marvell_get_sset_count(phydev);
2021 int i;
2022
2023 for (i = 0; i < count; i++)
2024 ethtool_puts(&data, marvell_hw_stats[i].string);
2025}
2026
2027static void marvell_get_strings_simple(struct phy_device *phydev, u8 *data)
2028{
2029 int count = marvell_get_sset_count_simple(phydev);
2030 int i;
2031
2032 for (i = 0; i < count; i++)
2033 ethtool_puts(&data, marvell_hw_stats_simple[i].string);
2034}
2035
2036static u64 marvell_get_stat(struct phy_device *phydev, int i)
2037{
2038 struct marvell_hw_stat stat = marvell_hw_stats[i];
2039 struct marvell_priv *priv = phydev->priv;
2040 int val;
2041 u64 ret;
2042
2043 val = phy_read_paged(phydev, stat.page, stat.reg);
2044 if (val < 0) {
2045 ret = U64_MAX;
2046 } else {
2047 val = val & ((1 << stat.bits) - 1);
2048 priv->stats[i] += val;
2049 ret = priv->stats[i];
2050 }
2051
2052 return ret;
2053}
2054
2055static u64 marvell_get_stat_simple(struct phy_device *phydev, int i)
2056{
2057 struct marvell_hw_stat_simple stat = marvell_hw_stats_simple[i];
2058 struct marvell_priv *priv = phydev->priv;
2059 int val;
2060 u64 ret;
2061
2062 val = phy_read(phydev, stat.reg);
2063 if (val < 0) {
2064 ret = U64_MAX;
2065 } else {
2066 val = val & ((1 << stat.bits) - 1);
2067 priv->stats[i] += val;
2068 ret = priv->stats[i];
2069 }
2070
2071 return ret;
2072}
2073
2074static void marvell_get_stats(struct phy_device *phydev,
2075 struct ethtool_stats *stats, u64 *data)
2076{
2077 int count = marvell_get_sset_count(phydev);
2078 int i;
2079
2080 for (i = 0; i < count; i++)
2081 data[i] = marvell_get_stat(phydev, i);
2082}
2083
2084static void marvell_get_stats_simple(struct phy_device *phydev,
2085 struct ethtool_stats *stats, u64 *data)
2086{
2087 int count = marvell_get_sset_count_simple(phydev);
2088 int i;
2089
2090 for (i = 0; i < count; i++)
2091 data[i] = marvell_get_stat_simple(phydev, i);
2092}
2093
2094static int m88e1510_loopback(struct phy_device *phydev, bool enable)
2095{
2096 int err;
2097
2098 if (enable) {
2099 u16 bmcr_ctl, mscr2_ctl = 0;
2100
2101 bmcr_ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
2102
2103 err = phy_write(phydev, MII_BMCR, bmcr_ctl);
2104 if (err < 0)
2105 return err;
2106
2107 if (phydev->speed == SPEED_1000)
2108 mscr2_ctl = BMCR_SPEED1000;
2109 else if (phydev->speed == SPEED_100)
2110 mscr2_ctl = BMCR_SPEED100;
2111
2112 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
2113 MII_88E1510_MSCR_2, BMCR_SPEED1000 |
2114 BMCR_SPEED100, mscr2_ctl);
2115 if (err < 0)
2116 return err;
2117
2118 /* Need soft reset to have speed configuration takes effect */
2119 err = genphy_soft_reset(phydev);
2120 if (err < 0)
2121 return err;
2122
2123 err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
2124 BMCR_LOOPBACK);
2125
2126 if (!err) {
2127 /* It takes some time for PHY device to switch
2128 * into/out-of loopback mode.
2129 */
2130 msleep(1000);
2131 }
2132 return err;
2133 } else {
2134 err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
2135 if (err < 0)
2136 return err;
2137
2138 return phy_config_aneg(phydev);
2139 }
2140}
2141
2142static int marvell_vct5_wait_complete(struct phy_device *phydev)
2143{
2144 int i;
2145 int val;
2146
2147 for (i = 0; i < 32; i++) {
2148 val = __phy_read(phydev, MII_VCT5_CTRL);
2149 if (val < 0)
2150 return val;
2151
2152 if (val & MII_VCT5_CTRL_COMPLETE)
2153 return 0;
2154 }
2155
2156 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
2157 return -ETIMEDOUT;
2158}
2159
2160static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
2161{
2162 int amplitude;
2163 int val;
2164 int reg;
2165
2166 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
2167 val = __phy_read(phydev, reg);
2168
2169 if (val < 0)
2170 return 0;
2171
2172 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
2173 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
2174
2175 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
2176 amplitude = -amplitude;
2177
2178 return 1000 * amplitude / 128;
2179}
2180
2181static u32 marvell_vct5_distance2cm(int distance)
2182{
2183 return distance * 805 / 10;
2184}
2185
2186static u32 marvell_vct5_cm2distance(int cm)
2187{
2188 return cm * 10 / 805;
2189}
2190
2191static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
2192 int distance, int pair)
2193{
2194 u16 reg;
2195 int err;
2196 int mV;
2197 int i;
2198
2199 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
2200 distance);
2201 if (err)
2202 return err;
2203
2204 reg = MII_VCT5_CTRL_ENABLE |
2205 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2206 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2207 MII_VCT5_CTRL_SAMPLE_POINT |
2208 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
2209 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
2210 if (err)
2211 return err;
2212
2213 err = marvell_vct5_wait_complete(phydev);
2214 if (err)
2215 return err;
2216
2217 for (i = 0; i < 4; i++) {
2218 if (pair != PHY_PAIR_ALL && i != pair)
2219 continue;
2220
2221 mV = marvell_vct5_amplitude(phydev, i);
2222 ethnl_cable_test_amplitude(phydev, i, mV);
2223 }
2224
2225 return 0;
2226}
2227
2228static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
2229{
2230 struct marvell_priv *priv = phydev->priv;
2231 int distance;
2232 u16 width;
2233 int page;
2234 int err;
2235 u16 reg;
2236
2237 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
2238 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
2239 else
2240 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2241
2242 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2243 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2244 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2245
2246 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2247 MII_VCT5_TX_PULSE_CTRL, reg);
2248 if (err)
2249 return err;
2250
2251 /* Reading the TDR data is very MDIO heavy. We need to optimize
2252 * access to keep the time to a minimum. So lock the bus once,
2253 * and don't release it until complete. We can then avoid having
2254 * to change the page for every access, greatly speeding things
2255 * up.
2256 */
2257 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
2258 if (page < 0)
2259 goto restore_page;
2260
2261 for (distance = priv->first;
2262 distance <= priv->last;
2263 distance += priv->step) {
2264 err = marvell_vct5_amplitude_distance(phydev, distance,
2265 priv->pair);
2266 if (err)
2267 goto restore_page;
2268
2269 if (distance > TDR_SHORT_CABLE_LENGTH &&
2270 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
2271 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2272 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2273 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2274 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2275 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
2276 if (err)
2277 goto restore_page;
2278 }
2279 }
2280
2281restore_page:
2282 return phy_restore_page(phydev, page, err);
2283}
2284
2285static int marvell_cable_test_start_common(struct phy_device *phydev)
2286{
2287 int bmcr, bmsr, ret;
2288
2289 /* If auto-negotiation is enabled, but not complete, the cable
2290 * test never completes. So disable auto-neg.
2291 */
2292 bmcr = phy_read(phydev, MII_BMCR);
2293 if (bmcr < 0)
2294 return bmcr;
2295
2296 bmsr = phy_read(phydev, MII_BMSR);
2297
2298 if (bmsr < 0)
2299 return bmsr;
2300
2301 if (bmcr & BMCR_ANENABLE) {
2302 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
2303 if (ret < 0)
2304 return ret;
2305 ret = genphy_soft_reset(phydev);
2306 if (ret < 0)
2307 return ret;
2308 }
2309
2310 /* If the link is up, allow it some time to go down */
2311 if (bmsr & BMSR_LSTATUS)
2312 msleep(1500);
2313
2314 return 0;
2315}
2316
2317static int marvell_vct7_cable_test_start(struct phy_device *phydev)
2318{
2319 struct marvell_priv *priv = phydev->priv;
2320 int ret;
2321
2322 ret = marvell_cable_test_start_common(phydev);
2323 if (ret)
2324 return ret;
2325
2326 priv->cable_test_tdr = false;
2327
2328 /* Reset the VCT5 API control to defaults, otherwise
2329 * VCT7 does not work correctly.
2330 */
2331 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2332 MII_VCT5_CTRL,
2333 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2334 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2335 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
2336 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
2337 if (ret)
2338 return ret;
2339
2340 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2341 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
2342 if (ret)
2343 return ret;
2344
2345 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2346 MII_VCT7_CTRL,
2347 MII_VCT7_CTRL_RUN_NOW |
2348 MII_VCT7_CTRL_CENTIMETERS);
2349}
2350
2351static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
2352 const struct phy_tdr_config *cfg)
2353{
2354 struct marvell_priv *priv = phydev->priv;
2355 int ret;
2356
2357 priv->cable_test_tdr = true;
2358 priv->first = marvell_vct5_cm2distance(cfg->first);
2359 priv->last = marvell_vct5_cm2distance(cfg->last);
2360 priv->step = marvell_vct5_cm2distance(cfg->step);
2361 priv->pair = cfg->pair;
2362
2363 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2364 return -EINVAL;
2365
2366 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2367 return -EINVAL;
2368
2369 /* Disable VCT7 */
2370 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2371 MII_VCT7_CTRL, 0);
2372 if (ret)
2373 return ret;
2374
2375 ret = marvell_cable_test_start_common(phydev);
2376 if (ret)
2377 return ret;
2378
2379 ret = ethnl_cable_test_pulse(phydev, 1000);
2380 if (ret)
2381 return ret;
2382
2383 return ethnl_cable_test_step(phydev,
2384 marvell_vct5_distance2cm(priv->first),
2385 marvell_vct5_distance2cm(priv->last),
2386 marvell_vct5_distance2cm(priv->step));
2387}
2388
2389static int marvell_vct7_distance_to_length(int distance, bool meter)
2390{
2391 if (meter)
2392 distance *= 100;
2393
2394 return distance;
2395}
2396
2397static bool marvell_vct7_distance_valid(int result)
2398{
2399 switch (result) {
2400 case MII_VCT7_RESULTS_OPEN:
2401 case MII_VCT7_RESULTS_SAME_SHORT:
2402 case MII_VCT7_RESULTS_CROSS_SHORT:
2403 return true;
2404 }
2405 return false;
2406}
2407
2408static int marvell_vct7_report_length(struct phy_device *phydev,
2409 int pair, bool meter)
2410{
2411 int length;
2412 int ret;
2413
2414 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2415 MII_VCT7_PAIR_0_DISTANCE + pair);
2416 if (ret < 0)
2417 return ret;
2418
2419 length = marvell_vct7_distance_to_length(ret, meter);
2420
2421 ethnl_cable_test_fault_length(phydev, pair, length);
2422
2423 return 0;
2424}
2425
2426static int marvell_vct7_cable_test_report_trans(int result)
2427{
2428 switch (result) {
2429 case MII_VCT7_RESULTS_OK:
2430 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2431 case MII_VCT7_RESULTS_OPEN:
2432 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2433 case MII_VCT7_RESULTS_SAME_SHORT:
2434 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2435 case MII_VCT7_RESULTS_CROSS_SHORT:
2436 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2437 default:
2438 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2439 }
2440}
2441
2442static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2443{
2444 int pair0, pair1, pair2, pair3;
2445 bool meter;
2446 int ret;
2447
2448 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2449 MII_VCT7_RESULTS);
2450 if (ret < 0)
2451 return ret;
2452
2453 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2454 MII_VCT7_RESULTS_PAIR3_SHIFT;
2455 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2456 MII_VCT7_RESULTS_PAIR2_SHIFT;
2457 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2458 MII_VCT7_RESULTS_PAIR1_SHIFT;
2459 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2460 MII_VCT7_RESULTS_PAIR0_SHIFT;
2461
2462 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2463 marvell_vct7_cable_test_report_trans(pair0));
2464 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2465 marvell_vct7_cable_test_report_trans(pair1));
2466 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2467 marvell_vct7_cable_test_report_trans(pair2));
2468 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2469 marvell_vct7_cable_test_report_trans(pair3));
2470
2471 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2472 if (ret < 0)
2473 return ret;
2474
2475 meter = ret & MII_VCT7_CTRL_METERS;
2476
2477 if (marvell_vct7_distance_valid(pair0))
2478 marvell_vct7_report_length(phydev, 0, meter);
2479 if (marvell_vct7_distance_valid(pair1))
2480 marvell_vct7_report_length(phydev, 1, meter);
2481 if (marvell_vct7_distance_valid(pair2))
2482 marvell_vct7_report_length(phydev, 2, meter);
2483 if (marvell_vct7_distance_valid(pair3))
2484 marvell_vct7_report_length(phydev, 3, meter);
2485
2486 return 0;
2487}
2488
2489static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2490 bool *finished)
2491{
2492 struct marvell_priv *priv = phydev->priv;
2493 int ret;
2494
2495 if (priv->cable_test_tdr) {
2496 ret = marvell_vct5_amplitude_graph(phydev);
2497 *finished = true;
2498 return ret;
2499 }
2500
2501 *finished = false;
2502
2503 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2504 MII_VCT7_CTRL);
2505
2506 if (ret < 0)
2507 return ret;
2508
2509 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2510 *finished = true;
2511
2512 return marvell_vct7_cable_test_report(phydev);
2513 }
2514
2515 return 0;
2516}
2517
2518static int m88e3082_vct_cable_test_start(struct phy_device *phydev)
2519{
2520 struct marvell_priv *priv = phydev->priv;
2521 int ret;
2522
2523 /* It needs some magic workarounds described in VCT manual for this PHY.
2524 */
2525 ret = phy_write(phydev, 29, 0x0003);
2526 if (ret < 0)
2527 return ret;
2528
2529 ret = phy_write(phydev, 30, 0x6440);
2530 if (ret < 0)
2531 return ret;
2532
2533 if (priv->vct_phase == M88E3082_VCT_PHASE1) {
2534 ret = phy_write(phydev, 29, 0x000a);
2535 if (ret < 0)
2536 return ret;
2537
2538 ret = phy_write(phydev, 30, 0x0002);
2539 if (ret < 0)
2540 return ret;
2541 }
2542
2543 ret = phy_write(phydev, MII_BMCR,
2544 BMCR_RESET | BMCR_SPEED100 | BMCR_FULLDPLX);
2545 if (ret < 0)
2546 return ret;
2547
2548 ret = phy_write(phydev, MII_VCT_TXPINS, MII_VCT_TXPINS_ENVCT);
2549 if (ret < 0)
2550 return ret;
2551
2552 ret = phy_write(phydev, 29, 0x0003);
2553 if (ret < 0)
2554 return ret;
2555
2556 ret = phy_write(phydev, 30, 0x0);
2557 if (ret < 0)
2558 return ret;
2559
2560 if (priv->vct_phase == M88E3082_VCT_OFF) {
2561 priv->vct_phase = M88E3082_VCT_PHASE1;
2562 priv->pair = 0;
2563
2564 return 0;
2565 }
2566
2567 ret = phy_write(phydev, 29, 0x000a);
2568 if (ret < 0)
2569 return ret;
2570
2571 ret = phy_write(phydev, 30, 0x0);
2572 if (ret < 0)
2573 return ret;
2574
2575 priv->vct_phase = M88E3082_VCT_PHASE2;
2576
2577 return 0;
2578}
2579
2580static int m88e3082_vct_cable_test_report_trans(int result, u8 distance)
2581{
2582 switch (result) {
2583 case MII_VCT_TXRXPINS_VCTTST_OK:
2584 if (distance == MII_VCT_TXRXPINS_DISTRFLN_MAX)
2585 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2586 return ETHTOOL_A_CABLE_RESULT_CODE_IMPEDANCE_MISMATCH;
2587 case MII_VCT_TXRXPINS_VCTTST_SHORT:
2588 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2589 case MII_VCT_TXRXPINS_VCTTST_OPEN:
2590 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2591 default:
2592 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2593 }
2594}
2595
2596static u32 m88e3082_vct_distrfln_2_cm(u8 distrfln)
2597{
2598 if (distrfln < 24)
2599 return 0;
2600
2601 /* Original function for meters: y = 0.7861x - 18.862 */
2602 return (7861 * distrfln - 188620) / 100;
2603}
2604
2605static int m88e3082_vct_cable_test_get_status(struct phy_device *phydev,
2606 bool *finished)
2607{
2608 u8 tx_vcttst_res, rx_vcttst_res, tx_distrfln, rx_distrfln;
2609 struct marvell_priv *priv = phydev->priv;
2610 int ret, tx_result, rx_result;
2611 bool done_phase = true;
2612
2613 *finished = false;
2614
2615 ret = phy_read(phydev, MII_VCT_TXPINS);
2616 if (ret < 0)
2617 return ret;
2618 else if (ret & MII_VCT_TXPINS_ENVCT)
2619 return 0;
2620
2621 tx_distrfln = ret & MII_VCT_TXRXPINS_DISTRFLN;
2622 tx_vcttst_res = (ret & MII_VCT_TXRXPINS_VCTTST) >>
2623 MII_VCT_TXRXPINS_VCTTST_SHIFT;
2624
2625 ret = phy_read(phydev, MII_VCT_RXPINS);
2626 if (ret < 0)
2627 return ret;
2628
2629 rx_distrfln = ret & MII_VCT_TXRXPINS_DISTRFLN;
2630 rx_vcttst_res = (ret & MII_VCT_TXRXPINS_VCTTST) >>
2631 MII_VCT_TXRXPINS_VCTTST_SHIFT;
2632
2633 *finished = true;
2634
2635 switch (priv->vct_phase) {
2636 case M88E3082_VCT_PHASE1:
2637 tx_result = m88e3082_vct_cable_test_report_trans(tx_vcttst_res,
2638 tx_distrfln);
2639 rx_result = m88e3082_vct_cable_test_report_trans(rx_vcttst_res,
2640 rx_distrfln);
2641
2642 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2643 tx_result);
2644 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2645 rx_result);
2646
2647 if (tx_vcttst_res == MII_VCT_TXRXPINS_VCTTST_OPEN) {
2648 done_phase = false;
2649 priv->pair |= M88E3082_PAIR_A;
2650 } else if (tx_distrfln < MII_VCT_TXRXPINS_DISTRFLN_MAX) {
2651 u8 pair = ETHTOOL_A_CABLE_PAIR_A;
2652 u32 cm = m88e3082_vct_distrfln_2_cm(tx_distrfln);
2653
2654 ethnl_cable_test_fault_length(phydev, pair, cm);
2655 }
2656
2657 if (rx_vcttst_res == MII_VCT_TXRXPINS_VCTTST_OPEN) {
2658 done_phase = false;
2659 priv->pair |= M88E3082_PAIR_B;
2660 } else if (rx_distrfln < MII_VCT_TXRXPINS_DISTRFLN_MAX) {
2661 u8 pair = ETHTOOL_A_CABLE_PAIR_B;
2662 u32 cm = m88e3082_vct_distrfln_2_cm(rx_distrfln);
2663
2664 ethnl_cable_test_fault_length(phydev, pair, cm);
2665 }
2666
2667 break;
2668 case M88E3082_VCT_PHASE2:
2669 if (priv->pair & M88E3082_PAIR_A &&
2670 tx_vcttst_res == MII_VCT_TXRXPINS_VCTTST_OPEN &&
2671 tx_distrfln < MII_VCT_TXRXPINS_DISTRFLN_MAX) {
2672 u8 pair = ETHTOOL_A_CABLE_PAIR_A;
2673 u32 cm = m88e3082_vct_distrfln_2_cm(tx_distrfln);
2674
2675 ethnl_cable_test_fault_length(phydev, pair, cm);
2676 }
2677 if (priv->pair & M88E3082_PAIR_B &&
2678 rx_vcttst_res == MII_VCT_TXRXPINS_VCTTST_OPEN &&
2679 rx_distrfln < MII_VCT_TXRXPINS_DISTRFLN_MAX) {
2680 u8 pair = ETHTOOL_A_CABLE_PAIR_B;
2681 u32 cm = m88e3082_vct_distrfln_2_cm(rx_distrfln);
2682
2683 ethnl_cable_test_fault_length(phydev, pair, cm);
2684 }
2685
2686 break;
2687 default:
2688 return -EINVAL;
2689 }
2690
2691 if (!done_phase) {
2692 *finished = false;
2693 return m88e3082_vct_cable_test_start(phydev);
2694 }
2695 if (*finished)
2696 priv->vct_phase = M88E3082_VCT_OFF;
2697 return 0;
2698}
2699
2700static int m88e1111_vct_cable_test_start(struct phy_device *phydev)
2701{
2702 int ret;
2703
2704 ret = marvell_cable_test_start_common(phydev);
2705 if (ret)
2706 return ret;
2707
2708 /* It needs some magic workarounds described in VCT manual for this PHY.
2709 */
2710 ret = phy_write(phydev, 29, 0x0018);
2711 if (ret < 0)
2712 return ret;
2713
2714 ret = phy_write(phydev, 30, 0x00c2);
2715 if (ret < 0)
2716 return ret;
2717
2718 ret = phy_write(phydev, 30, 0x00ca);
2719 if (ret < 0)
2720 return ret;
2721
2722 ret = phy_write(phydev, 30, 0x00c2);
2723 if (ret < 0)
2724 return ret;
2725
2726 ret = phy_write_paged(phydev, MII_MARVELL_COPPER_PAGE, MII_VCT_SR,
2727 MII_VCT_TXPINS_ENVCT);
2728 if (ret < 0)
2729 return ret;
2730
2731 ret = phy_write(phydev, 29, 0x0018);
2732 if (ret < 0)
2733 return ret;
2734
2735 ret = phy_write(phydev, 30, 0x0042);
2736 if (ret < 0)
2737 return ret;
2738
2739 return 0;
2740}
2741
2742static u32 m88e1111_vct_distrfln_2_cm(u8 distrfln)
2743{
2744 if (distrfln < 36)
2745 return 0;
2746
2747 /* Original function for meters: y = 0.8018x - 28.751 */
2748 return (8018 * distrfln - 287510) / 100;
2749}
2750
2751static int m88e1111_vct_cable_test_get_status(struct phy_device *phydev,
2752 bool *finished)
2753{
2754 u8 vcttst_res, distrfln;
2755 int ret, result;
2756
2757 *finished = false;
2758
2759 /* Each pair use one page: A-0, B-1, C-2, D-3 */
2760 for (u8 i = 0; i < 4; i++) {
2761 ret = phy_read_paged(phydev, i, MII_VCT_SR);
2762 if (ret < 0)
2763 return ret;
2764 else if (i == 0 && ret & MII_VCT_TXPINS_ENVCT)
2765 return 0;
2766
2767 distrfln = ret & MII_VCT_TXRXPINS_DISTRFLN;
2768 vcttst_res = (ret & MII_VCT_TXRXPINS_VCTTST) >>
2769 MII_VCT_TXRXPINS_VCTTST_SHIFT;
2770
2771 result = m88e3082_vct_cable_test_report_trans(vcttst_res,
2772 distrfln);
2773 ethnl_cable_test_result(phydev, i, result);
2774
2775 if (distrfln < MII_VCT_TXRXPINS_DISTRFLN_MAX) {
2776 u32 cm = m88e1111_vct_distrfln_2_cm(distrfln);
2777
2778 ethnl_cable_test_fault_length(phydev, i, cm);
2779 }
2780 }
2781
2782 *finished = true;
2783 return 0;
2784}
2785
2786#ifdef CONFIG_HWMON
2787struct marvell_hwmon_ops {
2788 int (*config)(struct phy_device *phydev);
2789 int (*get_temp)(struct phy_device *phydev, long *temp);
2790 int (*get_temp_critical)(struct phy_device *phydev, long *temp);
2791 int (*set_temp_critical)(struct phy_device *phydev, long temp);
2792 int (*get_temp_alarm)(struct phy_device *phydev, long *alarm);
2793};
2794
2795static const struct marvell_hwmon_ops *
2796to_marvell_hwmon_ops(const struct phy_device *phydev)
2797{
2798 return phydev->drv->driver_data;
2799}
2800
2801static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2802{
2803 int oldpage;
2804 int ret = 0;
2805 int val;
2806
2807 *temp = 0;
2808
2809 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2810 if (oldpage < 0)
2811 goto error;
2812
2813 /* Enable temperature sensor */
2814 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2815 if (ret < 0)
2816 goto error;
2817
2818 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2819 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2820 if (ret < 0)
2821 goto error;
2822
2823 /* Wait for temperature to stabilize */
2824 usleep_range(10000, 12000);
2825
2826 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2827 if (val < 0) {
2828 ret = val;
2829 goto error;
2830 }
2831
2832 /* Disable temperature sensor */
2833 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2834 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2835 if (ret < 0)
2836 goto error;
2837
2838 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2839
2840error:
2841 return phy_restore_page(phydev, oldpage, ret);
2842}
2843
2844static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2845{
2846 int ret;
2847
2848 *temp = 0;
2849
2850 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2851 MII_88E1510_TEMP_SENSOR);
2852 if (ret < 0)
2853 return ret;
2854
2855 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2856
2857 return 0;
2858}
2859
2860static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2861{
2862 int ret;
2863
2864 *temp = 0;
2865
2866 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2867 MII_88E1121_MISC_TEST);
2868 if (ret < 0)
2869 return ret;
2870
2871 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2872 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2873 /* convert to mC */
2874 *temp *= 1000;
2875
2876 return 0;
2877}
2878
2879static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2880{
2881 temp = temp / 1000;
2882 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2883
2884 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2885 MII_88E1121_MISC_TEST,
2886 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2887 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2888}
2889
2890static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2891{
2892 int ret;
2893
2894 *alarm = false;
2895
2896 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2897 MII_88E1121_MISC_TEST);
2898 if (ret < 0)
2899 return ret;
2900
2901 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2902
2903 return 0;
2904}
2905
2906static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2907{
2908 int sum = 0;
2909 int oldpage;
2910 int ret = 0;
2911 int i;
2912
2913 *temp = 0;
2914
2915 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2916 if (oldpage < 0)
2917 goto error;
2918
2919 /* Enable temperature sensor */
2920 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2921 if (ret < 0)
2922 goto error;
2923
2924 ret &= ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2925 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S;
2926
2927 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2928 if (ret < 0)
2929 goto error;
2930
2931 /* Wait for temperature to stabilize */
2932 usleep_range(10000, 12000);
2933
2934 /* Reading the temperature sense has an errata. You need to read
2935 * a number of times and take an average.
2936 */
2937 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2938 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2939 if (ret < 0)
2940 goto error;
2941 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2942 }
2943
2944 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2945 *temp = (sum - 75) * 1000;
2946
2947 /* Disable temperature sensor */
2948 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2949 if (ret < 0)
2950 goto error;
2951
2952 ret = ret & ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2953 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE;
2954
2955 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2956
2957error:
2958 phy_restore_page(phydev, oldpage, ret);
2959
2960 return ret;
2961}
2962
2963static int m88e6393_get_temp(struct phy_device *phydev, long *temp)
2964{
2965 int err;
2966
2967 err = m88e1510_get_temp(phydev, temp);
2968
2969 /* 88E1510 measures T + 25, while the PHY on 88E6393X switch
2970 * T + 75, so we have to subtract another 50
2971 */
2972 *temp -= 50000;
2973
2974 return err;
2975}
2976
2977static int m88e6393_get_temp_critical(struct phy_device *phydev, long *temp)
2978{
2979 int ret;
2980
2981 *temp = 0;
2982
2983 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2984 MII_88E6390_TEMP_SENSOR);
2985 if (ret < 0)
2986 return ret;
2987
2988 *temp = (((ret & MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK) >>
2989 MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT) - 75) * 1000;
2990
2991 return 0;
2992}
2993
2994static int m88e6393_set_temp_critical(struct phy_device *phydev, long temp)
2995{
2996 temp = (temp / 1000) + 75;
2997
2998 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2999 MII_88E6390_TEMP_SENSOR,
3000 MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK,
3001 temp << MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT);
3002}
3003
3004static int m88e6393_hwmon_config(struct phy_device *phydev)
3005{
3006 int err;
3007
3008 err = m88e6393_set_temp_critical(phydev, 100000);
3009 if (err)
3010 return err;
3011
3012 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
3013 MII_88E6390_MISC_TEST,
3014 MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK |
3015 MII_88E6393_MISC_TEST_SAMPLES_MASK |
3016 MII_88E6393_MISC_TEST_RATE_MASK,
3017 MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE |
3018 MII_88E6393_MISC_TEST_SAMPLES_2048 |
3019 MII_88E6393_MISC_TEST_RATE_2_3MS);
3020}
3021
3022static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
3023 u32 attr, int channel, long *temp)
3024{
3025 struct phy_device *phydev = dev_get_drvdata(dev);
3026 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
3027 int err = -EOPNOTSUPP;
3028
3029 switch (attr) {
3030 case hwmon_temp_input:
3031 if (ops->get_temp)
3032 err = ops->get_temp(phydev, temp);
3033 break;
3034 case hwmon_temp_crit:
3035 if (ops->get_temp_critical)
3036 err = ops->get_temp_critical(phydev, temp);
3037 break;
3038 case hwmon_temp_max_alarm:
3039 if (ops->get_temp_alarm)
3040 err = ops->get_temp_alarm(phydev, temp);
3041 break;
3042 }
3043
3044 return err;
3045}
3046
3047static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
3048 u32 attr, int channel, long temp)
3049{
3050 struct phy_device *phydev = dev_get_drvdata(dev);
3051 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
3052 int err = -EOPNOTSUPP;
3053
3054 switch (attr) {
3055 case hwmon_temp_crit:
3056 if (ops->set_temp_critical)
3057 err = ops->set_temp_critical(phydev, temp);
3058 break;
3059 }
3060
3061 return err;
3062}
3063
3064static umode_t marvell_hwmon_is_visible(const void *data,
3065 enum hwmon_sensor_types type,
3066 u32 attr, int channel)
3067{
3068 const struct phy_device *phydev = data;
3069 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
3070
3071 if (type != hwmon_temp)
3072 return 0;
3073
3074 switch (attr) {
3075 case hwmon_temp_input:
3076 return ops->get_temp ? 0444 : 0;
3077 case hwmon_temp_max_alarm:
3078 return ops->get_temp_alarm ? 0444 : 0;
3079 case hwmon_temp_crit:
3080 return (ops->get_temp_critical ? 0444 : 0) |
3081 (ops->set_temp_critical ? 0200 : 0);
3082 default:
3083 return 0;
3084 }
3085}
3086
3087static u32 marvell_hwmon_chip_config[] = {
3088 HWMON_C_REGISTER_TZ,
3089 0
3090};
3091
3092static const struct hwmon_channel_info marvell_hwmon_chip = {
3093 .type = hwmon_chip,
3094 .config = marvell_hwmon_chip_config,
3095};
3096
3097/* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not
3098 * defined for all PHYs, because the hwmon code checks whether the attributes
3099 * exists via the .is_visible method
3100 */
3101static u32 marvell_hwmon_temp_config[] = {
3102 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
3103 0
3104};
3105
3106static const struct hwmon_channel_info marvell_hwmon_temp = {
3107 .type = hwmon_temp,
3108 .config = marvell_hwmon_temp_config,
3109};
3110
3111static const struct hwmon_channel_info * const marvell_hwmon_info[] = {
3112 &marvell_hwmon_chip,
3113 &marvell_hwmon_temp,
3114 NULL
3115};
3116
3117static const struct hwmon_ops marvell_hwmon_hwmon_ops = {
3118 .is_visible = marvell_hwmon_is_visible,
3119 .read = marvell_hwmon_read,
3120 .write = marvell_hwmon_write,
3121};
3122
3123static const struct hwmon_chip_info marvell_hwmon_chip_info = {
3124 .ops = &marvell_hwmon_hwmon_ops,
3125 .info = marvell_hwmon_info,
3126};
3127
3128static int marvell_hwmon_name(struct phy_device *phydev)
3129{
3130 struct marvell_priv *priv = phydev->priv;
3131 struct device *dev = &phydev->mdio.dev;
3132 const char *devname = dev_name(dev);
3133 size_t len = strlen(devname);
3134 int i, j;
3135
3136 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
3137 if (!priv->hwmon_name)
3138 return -ENOMEM;
3139
3140 for (i = j = 0; i < len && devname[i]; i++) {
3141 if (isalnum(devname[i]))
3142 priv->hwmon_name[j++] = devname[i];
3143 }
3144
3145 return 0;
3146}
3147
3148static int marvell_hwmon_probe(struct phy_device *phydev)
3149{
3150 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
3151 struct marvell_priv *priv = phydev->priv;
3152 struct device *dev = &phydev->mdio.dev;
3153 int err;
3154
3155 if (!ops)
3156 return 0;
3157
3158 err = marvell_hwmon_name(phydev);
3159 if (err)
3160 return err;
3161
3162 priv->hwmon_dev = devm_hwmon_device_register_with_info(
3163 dev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL);
3164 if (IS_ERR(priv->hwmon_dev))
3165 return PTR_ERR(priv->hwmon_dev);
3166
3167 if (ops->config)
3168 err = ops->config(phydev);
3169
3170 return err;
3171}
3172
3173static const struct marvell_hwmon_ops m88e1121_hwmon_ops = {
3174 .get_temp = m88e1121_get_temp,
3175};
3176
3177static const struct marvell_hwmon_ops m88e1510_hwmon_ops = {
3178 .get_temp = m88e1510_get_temp,
3179 .get_temp_critical = m88e1510_get_temp_critical,
3180 .set_temp_critical = m88e1510_set_temp_critical,
3181 .get_temp_alarm = m88e1510_get_temp_alarm,
3182};
3183
3184static const struct marvell_hwmon_ops m88e6390_hwmon_ops = {
3185 .get_temp = m88e6390_get_temp,
3186};
3187
3188static const struct marvell_hwmon_ops m88e6393_hwmon_ops = {
3189 .config = m88e6393_hwmon_config,
3190 .get_temp = m88e6393_get_temp,
3191 .get_temp_critical = m88e6393_get_temp_critical,
3192 .set_temp_critical = m88e6393_set_temp_critical,
3193 .get_temp_alarm = m88e1510_get_temp_alarm,
3194};
3195
3196#define DEF_MARVELL_HWMON_OPS(s) (&(s))
3197
3198#else
3199
3200#define DEF_MARVELL_HWMON_OPS(s) NULL
3201
3202static int marvell_hwmon_probe(struct phy_device *phydev)
3203{
3204 return 0;
3205}
3206#endif
3207
3208static int m88e1318_led_brightness_set(struct phy_device *phydev,
3209 u8 index, enum led_brightness value)
3210{
3211 int reg;
3212
3213 reg = phy_read_paged(phydev, MII_MARVELL_LED_PAGE,
3214 MII_88E1318S_PHY_LED_FUNC);
3215 if (reg < 0)
3216 return reg;
3217
3218 switch (index) {
3219 case 0:
3220 case 1:
3221 case 2:
3222 reg &= ~(0xf << (4 * index));
3223 if (value == LED_OFF)
3224 reg |= MII_88E1318S_PHY_LED_FUNC_OFF << (4 * index);
3225 else
3226 reg |= MII_88E1318S_PHY_LED_FUNC_ON << (4 * index);
3227 break;
3228 default:
3229 return -EINVAL;
3230 }
3231
3232 return phy_write_paged(phydev, MII_MARVELL_LED_PAGE,
3233 MII_88E1318S_PHY_LED_FUNC, reg);
3234}
3235
3236static int m88e1318_led_blink_set(struct phy_device *phydev, u8 index,
3237 unsigned long *delay_on,
3238 unsigned long *delay_off)
3239{
3240 int reg;
3241
3242 reg = phy_read_paged(phydev, MII_MARVELL_LED_PAGE,
3243 MII_88E1318S_PHY_LED_FUNC);
3244 if (reg < 0)
3245 return reg;
3246
3247 switch (index) {
3248 case 0:
3249 case 1:
3250 case 2:
3251 reg &= ~(0xf << (4 * index));
3252 reg |= MII_88E1318S_PHY_LED_FUNC_BLINK << (4 * index);
3253 /* Reset default is 84ms */
3254 *delay_on = 84 / 2;
3255 *delay_off = 84 / 2;
3256 break;
3257 default:
3258 return -EINVAL;
3259 }
3260
3261 return phy_write_paged(phydev, MII_MARVELL_LED_PAGE,
3262 MII_88E1318S_PHY_LED_FUNC, reg);
3263}
3264
3265struct marvell_led_rules {
3266 int mode;
3267 unsigned long rules;
3268};
3269
3270static const struct marvell_led_rules marvell_led0[] = {
3271 {
3272 .mode = 0,
3273 .rules = BIT(TRIGGER_NETDEV_LINK),
3274 },
3275 {
3276 .mode = 1,
3277 .rules = (BIT(TRIGGER_NETDEV_LINK) |
3278 BIT(TRIGGER_NETDEV_RX) |
3279 BIT(TRIGGER_NETDEV_TX)),
3280 },
3281 {
3282 .mode = 3,
3283 .rules = (BIT(TRIGGER_NETDEV_RX) |
3284 BIT(TRIGGER_NETDEV_TX)),
3285 },
3286 {
3287 .mode = 4,
3288 .rules = (BIT(TRIGGER_NETDEV_RX) |
3289 BIT(TRIGGER_NETDEV_TX)),
3290 },
3291 {
3292 .mode = 5,
3293 .rules = BIT(TRIGGER_NETDEV_TX),
3294 },
3295 {
3296 .mode = 6,
3297 .rules = BIT(TRIGGER_NETDEV_LINK),
3298 },
3299 {
3300 .mode = 7,
3301 .rules = BIT(TRIGGER_NETDEV_LINK_1000),
3302 },
3303 {
3304 .mode = 8,
3305 .rules = 0,
3306 },
3307};
3308
3309static const struct marvell_led_rules marvell_led1[] = {
3310 {
3311 .mode = 1,
3312 .rules = (BIT(TRIGGER_NETDEV_LINK) |
3313 BIT(TRIGGER_NETDEV_RX) |
3314 BIT(TRIGGER_NETDEV_TX)),
3315 },
3316 {
3317 .mode = 2,
3318 .rules = (BIT(TRIGGER_NETDEV_LINK) |
3319 BIT(TRIGGER_NETDEV_RX)),
3320 },
3321 {
3322 .mode = 3,
3323 .rules = (BIT(TRIGGER_NETDEV_RX) |
3324 BIT(TRIGGER_NETDEV_TX)),
3325 },
3326 {
3327 .mode = 4,
3328 .rules = (BIT(TRIGGER_NETDEV_RX) |
3329 BIT(TRIGGER_NETDEV_TX)),
3330 },
3331 {
3332 .mode = 6,
3333 .rules = (BIT(TRIGGER_NETDEV_LINK_100) |
3334 BIT(TRIGGER_NETDEV_LINK_1000)),
3335 },
3336 {
3337 .mode = 7,
3338 .rules = BIT(TRIGGER_NETDEV_LINK_100),
3339 },
3340 {
3341 .mode = 8,
3342 .rules = 0,
3343 },
3344};
3345
3346static const struct marvell_led_rules marvell_led2[] = {
3347 {
3348 .mode = 0,
3349 .rules = BIT(TRIGGER_NETDEV_LINK),
3350 },
3351 {
3352 .mode = 1,
3353 .rules = (BIT(TRIGGER_NETDEV_LINK) |
3354 BIT(TRIGGER_NETDEV_RX) |
3355 BIT(TRIGGER_NETDEV_TX)),
3356 },
3357 {
3358 .mode = 3,
3359 .rules = (BIT(TRIGGER_NETDEV_RX) |
3360 BIT(TRIGGER_NETDEV_TX)),
3361 },
3362 {
3363 .mode = 4,
3364 .rules = (BIT(TRIGGER_NETDEV_RX) |
3365 BIT(TRIGGER_NETDEV_TX)),
3366 },
3367 {
3368 .mode = 5,
3369 .rules = BIT(TRIGGER_NETDEV_TX),
3370 },
3371 {
3372 .mode = 6,
3373 .rules = (BIT(TRIGGER_NETDEV_LINK_10) |
3374 BIT(TRIGGER_NETDEV_LINK_1000)),
3375 },
3376 {
3377 .mode = 7,
3378 .rules = BIT(TRIGGER_NETDEV_LINK_10),
3379 },
3380 {
3381 .mode = 8,
3382 .rules = 0,
3383 },
3384};
3385
3386static int marvell_find_led_mode(unsigned long rules,
3387 const struct marvell_led_rules *marvell_rules,
3388 int count,
3389 int *mode)
3390{
3391 int i;
3392
3393 for (i = 0; i < count; i++) {
3394 if (marvell_rules[i].rules == rules) {
3395 *mode = marvell_rules[i].mode;
3396 return 0;
3397 }
3398 }
3399 return -EOPNOTSUPP;
3400}
3401
3402static int marvell_get_led_mode(u8 index, unsigned long rules, int *mode)
3403{
3404 int ret;
3405
3406 switch (index) {
3407 case 0:
3408 ret = marvell_find_led_mode(rules, marvell_led0,
3409 ARRAY_SIZE(marvell_led0), mode);
3410 break;
3411 case 1:
3412 ret = marvell_find_led_mode(rules, marvell_led1,
3413 ARRAY_SIZE(marvell_led1), mode);
3414 break;
3415 case 2:
3416 ret = marvell_find_led_mode(rules, marvell_led2,
3417 ARRAY_SIZE(marvell_led2), mode);
3418 break;
3419 default:
3420 ret = -EINVAL;
3421 }
3422
3423 return ret;
3424}
3425
3426static int marvell_find_led_rules(unsigned long *rules,
3427 const struct marvell_led_rules *marvell_rules,
3428 int count,
3429 int mode)
3430{
3431 int i;
3432
3433 for (i = 0; i < count; i++) {
3434 if (marvell_rules[i].mode == mode) {
3435 *rules = marvell_rules[i].rules;
3436 return 0;
3437 }
3438 }
3439 return -EOPNOTSUPP;
3440}
3441
3442static int marvell_get_led_rules(u8 index, unsigned long *rules, int mode)
3443{
3444 int ret;
3445
3446 switch (index) {
3447 case 0:
3448 ret = marvell_find_led_rules(rules, marvell_led0,
3449 ARRAY_SIZE(marvell_led0), mode);
3450 break;
3451 case 1:
3452 ret = marvell_find_led_rules(rules, marvell_led1,
3453 ARRAY_SIZE(marvell_led1), mode);
3454 break;
3455 case 2:
3456 ret = marvell_find_led_rules(rules, marvell_led2,
3457 ARRAY_SIZE(marvell_led2), mode);
3458 break;
3459 default:
3460 ret = -EOPNOTSUPP;
3461 }
3462
3463 return ret;
3464}
3465
3466static int m88e1318_led_hw_is_supported(struct phy_device *phydev, u8 index,
3467 unsigned long rules)
3468{
3469 int mode, ret;
3470
3471 switch (index) {
3472 case 0:
3473 case 1:
3474 case 2:
3475 ret = marvell_get_led_mode(index, rules, &mode);
3476 break;
3477 default:
3478 ret = -EINVAL;
3479 }
3480
3481 return ret;
3482}
3483
3484static int m88e1318_led_hw_control_set(struct phy_device *phydev, u8 index,
3485 unsigned long rules)
3486{
3487 int mode, ret, reg;
3488
3489 switch (index) {
3490 case 0:
3491 case 1:
3492 case 2:
3493 ret = marvell_get_led_mode(index, rules, &mode);
3494 break;
3495 default:
3496 ret = -EINVAL;
3497 }
3498
3499 if (ret < 0)
3500 return ret;
3501
3502 reg = phy_read_paged(phydev, MII_MARVELL_LED_PAGE,
3503 MII_88E1318S_PHY_LED_FUNC);
3504 if (reg < 0)
3505 return reg;
3506
3507 reg &= ~(0xf << (4 * index));
3508 reg |= mode << (4 * index);
3509 return phy_write_paged(phydev, MII_MARVELL_LED_PAGE,
3510 MII_88E1318S_PHY_LED_FUNC, reg);
3511}
3512
3513static int m88e1318_led_hw_control_get(struct phy_device *phydev, u8 index,
3514 unsigned long *rules)
3515{
3516 int mode, reg;
3517
3518 if (index > 2)
3519 return -EINVAL;
3520
3521 reg = phy_read_paged(phydev, MII_MARVELL_LED_PAGE,
3522 MII_88E1318S_PHY_LED_FUNC);
3523 if (reg < 0)
3524 return reg;
3525
3526 mode = (reg >> (4 * index)) & 0xf;
3527
3528 return marvell_get_led_rules(index, rules, mode);
3529}
3530
3531static int marvell_probe(struct phy_device *phydev)
3532{
3533 struct marvell_priv *priv;
3534
3535 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3536 if (!priv)
3537 return -ENOMEM;
3538
3539 phydev->priv = priv;
3540
3541 return marvell_hwmon_probe(phydev);
3542}
3543
3544static int m88e1510_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3545{
3546 DECLARE_PHY_INTERFACE_MASK(interfaces);
3547 struct phy_device *phydev = upstream;
3548 phy_interface_t interface;
3549 struct device *dev;
3550 int oldpage;
3551 int ret = 0;
3552 u16 mode;
3553
3554 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
3555
3556 dev = &phydev->mdio.dev;
3557
3558 sfp_parse_support(phydev->sfp_bus, id, supported, interfaces);
3559 interface = sfp_select_interface(phydev->sfp_bus, supported);
3560
3561 dev_info(dev, "%s SFP module inserted\n", phy_modes(interface));
3562
3563 switch (interface) {
3564 case PHY_INTERFACE_MODE_1000BASEX:
3565 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X;
3566
3567 break;
3568 case PHY_INTERFACE_MODE_100BASEX:
3569 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX;
3570
3571 break;
3572 case PHY_INTERFACE_MODE_SGMII:
3573 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII;
3574
3575 break;
3576 default:
3577 dev_err(dev, "Incompatible SFP module inserted\n");
3578
3579 return -EINVAL;
3580 }
3581
3582 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
3583 if (oldpage < 0)
3584 goto error;
3585
3586 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
3587 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK, mode);
3588 if (ret < 0)
3589 goto error;
3590
3591 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
3592 MII_88E1510_GEN_CTRL_REG_1_RESET);
3593
3594error:
3595 return phy_restore_page(phydev, oldpage, ret);
3596}
3597
3598static void m88e1510_sfp_remove(void *upstream)
3599{
3600 struct phy_device *phydev = upstream;
3601 int oldpage;
3602 int ret = 0;
3603
3604 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
3605 if (oldpage < 0)
3606 goto error;
3607
3608 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
3609 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
3610 MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII);
3611 if (ret < 0)
3612 goto error;
3613
3614 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
3615 MII_88E1510_GEN_CTRL_REG_1_RESET);
3616
3617error:
3618 phy_restore_page(phydev, oldpage, ret);
3619}
3620
3621static const struct sfp_upstream_ops m88e1510_sfp_ops = {
3622 .module_insert = m88e1510_sfp_insert,
3623 .module_remove = m88e1510_sfp_remove,
3624 .attach = phy_sfp_attach,
3625 .detach = phy_sfp_detach,
3626 .connect_phy = phy_sfp_connect_phy,
3627 .disconnect_phy = phy_sfp_disconnect_phy,
3628};
3629
3630static int m88e1510_probe(struct phy_device *phydev)
3631{
3632 int err;
3633
3634 err = marvell_probe(phydev);
3635 if (err)
3636 return err;
3637
3638 return phy_sfp_probe(phydev, &m88e1510_sfp_ops);
3639}
3640
3641static struct phy_driver marvell_drivers[] = {
3642 {
3643 .phy_id = MARVELL_PHY_ID_88E1101,
3644 .phy_id_mask = MARVELL_PHY_ID_MASK,
3645 .name = "Marvell 88E1101",
3646 /* PHY_GBIT_FEATURES */
3647 .probe = marvell_probe,
3648 .config_init = marvell_config_init,
3649 .config_aneg = m88e1101_config_aneg,
3650 .config_intr = marvell_config_intr,
3651 .handle_interrupt = marvell_handle_interrupt,
3652 .resume = genphy_resume,
3653 .suspend = genphy_suspend,
3654 .read_page = marvell_read_page,
3655 .write_page = marvell_write_page,
3656 .get_sset_count = marvell_get_sset_count,
3657 .get_strings = marvell_get_strings,
3658 .get_stats = marvell_get_stats,
3659 },
3660 {
3661 .phy_id = MARVELL_PHY_ID_88E3082,
3662 .phy_id_mask = MARVELL_PHY_ID_MASK,
3663 .name = "Marvell 88E308X/88E609X Family",
3664 /* PHY_BASIC_FEATURES */
3665 .probe = marvell_probe,
3666 .config_init = marvell_config_init,
3667 .aneg_done = marvell_aneg_done,
3668 .read_status = marvell_read_status,
3669 .resume = genphy_resume,
3670 .suspend = genphy_suspend,
3671 .cable_test_start = m88e3082_vct_cable_test_start,
3672 .cable_test_get_status = m88e3082_vct_cable_test_get_status,
3673 },
3674 {
3675 .phy_id = MARVELL_PHY_ID_88E1112,
3676 .phy_id_mask = MARVELL_PHY_ID_MASK,
3677 .name = "Marvell 88E1112",
3678 /* PHY_GBIT_FEATURES */
3679 .probe = marvell_probe,
3680 .config_init = m88e1112_config_init,
3681 .config_aneg = marvell_config_aneg,
3682 .config_intr = marvell_config_intr,
3683 .handle_interrupt = marvell_handle_interrupt,
3684 .resume = genphy_resume,
3685 .suspend = genphy_suspend,
3686 .read_page = marvell_read_page,
3687 .write_page = marvell_write_page,
3688 .get_sset_count = marvell_get_sset_count,
3689 .get_strings = marvell_get_strings,
3690 .get_stats = marvell_get_stats,
3691 .get_tunable = m88e1011_get_tunable,
3692 .set_tunable = m88e1011_set_tunable,
3693 },
3694 {
3695 .phy_id = MARVELL_PHY_ID_88E1111,
3696 .phy_id_mask = MARVELL_PHY_ID_MASK,
3697 .name = "Marvell 88E1111",
3698 /* PHY_GBIT_FEATURES */
3699 .flags = PHY_POLL_CABLE_TEST,
3700 .probe = marvell_probe,
3701 .config_init = m88e1111gbe_config_init,
3702 .config_aneg = m88e1111_config_aneg,
3703 .read_status = marvell_read_status,
3704 .config_intr = marvell_config_intr,
3705 .handle_interrupt = marvell_handle_interrupt,
3706 .resume = genphy_resume,
3707 .suspend = genphy_suspend,
3708 .read_page = marvell_read_page,
3709 .write_page = marvell_write_page,
3710 .get_sset_count = marvell_get_sset_count,
3711 .get_strings = marvell_get_strings,
3712 .get_stats = marvell_get_stats,
3713 .get_tunable = m88e1111_get_tunable,
3714 .set_tunable = m88e1111_set_tunable,
3715 .cable_test_start = m88e1111_vct_cable_test_start,
3716 .cable_test_get_status = m88e1111_vct_cable_test_get_status,
3717 },
3718 {
3719 .phy_id = MARVELL_PHY_ID_88E1111_FINISAR,
3720 .phy_id_mask = MARVELL_PHY_ID_MASK,
3721 .name = "Marvell 88E1111 (Finisar)",
3722 /* PHY_GBIT_FEATURES */
3723 .probe = marvell_probe,
3724 .config_init = m88e1111gbe_config_init,
3725 .config_aneg = m88e1111_config_aneg,
3726 .read_status = marvell_read_status,
3727 .config_intr = marvell_config_intr,
3728 .handle_interrupt = marvell_handle_interrupt,
3729 .resume = genphy_resume,
3730 .suspend = genphy_suspend,
3731 .read_page = marvell_read_page,
3732 .write_page = marvell_write_page,
3733 .get_sset_count = marvell_get_sset_count,
3734 .get_strings = marvell_get_strings,
3735 .get_stats = marvell_get_stats,
3736 .get_tunable = m88e1111_get_tunable,
3737 .set_tunable = m88e1111_set_tunable,
3738 },
3739 {
3740 .phy_id = MARVELL_PHY_ID_88E1118,
3741 .phy_id_mask = MARVELL_PHY_ID_MASK,
3742 .name = "Marvell 88E1118",
3743 /* PHY_GBIT_FEATURES */
3744 .probe = marvell_probe,
3745 .config_init = m88e1118_config_init,
3746 .config_aneg = m88e1118_config_aneg,
3747 .config_intr = marvell_config_intr,
3748 .handle_interrupt = marvell_handle_interrupt,
3749 .resume = genphy_resume,
3750 .suspend = genphy_suspend,
3751 .read_page = marvell_read_page,
3752 .write_page = marvell_write_page,
3753 .get_sset_count = marvell_get_sset_count,
3754 .get_strings = marvell_get_strings,
3755 .get_stats = marvell_get_stats,
3756 },
3757 {
3758 .phy_id = MARVELL_PHY_ID_88E1121R,
3759 .phy_id_mask = MARVELL_PHY_ID_MASK,
3760 .name = "Marvell 88E1121R",
3761 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops),
3762 /* PHY_GBIT_FEATURES */
3763 .probe = marvell_probe,
3764 .config_init = marvell_1011gbe_config_init,
3765 .config_aneg = m88e1121_config_aneg,
3766 .read_status = marvell_read_status,
3767 .config_intr = marvell_config_intr,
3768 .handle_interrupt = marvell_handle_interrupt,
3769 .resume = genphy_resume,
3770 .suspend = genphy_suspend,
3771 .read_page = marvell_read_page,
3772 .write_page = marvell_write_page,
3773 .get_sset_count = marvell_get_sset_count,
3774 .get_strings = marvell_get_strings,
3775 .get_stats = marvell_get_stats,
3776 .get_tunable = m88e1011_get_tunable,
3777 .set_tunable = m88e1011_set_tunable,
3778 },
3779 {
3780 .phy_id = MARVELL_PHY_ID_88E1318S,
3781 .phy_id_mask = MARVELL_PHY_ID_MASK,
3782 .name = "Marvell 88E1318S",
3783 /* PHY_GBIT_FEATURES */
3784 .probe = marvell_probe,
3785 .config_init = m88e1318_config_init,
3786 .config_aneg = m88e1318_config_aneg,
3787 .read_status = marvell_read_status,
3788 .config_intr = marvell_config_intr,
3789 .handle_interrupt = marvell_handle_interrupt,
3790 .get_wol = m88e1318_get_wol,
3791 .set_wol = m88e1318_set_wol,
3792 .resume = genphy_resume,
3793 .suspend = genphy_suspend,
3794 .read_page = marvell_read_page,
3795 .write_page = marvell_write_page,
3796 .get_sset_count = marvell_get_sset_count,
3797 .get_strings = marvell_get_strings,
3798 .get_stats = marvell_get_stats,
3799 .led_brightness_set = m88e1318_led_brightness_set,
3800 .led_blink_set = m88e1318_led_blink_set,
3801 .led_hw_is_supported = m88e1318_led_hw_is_supported,
3802 .led_hw_control_set = m88e1318_led_hw_control_set,
3803 .led_hw_control_get = m88e1318_led_hw_control_get,
3804 },
3805 {
3806 .phy_id = MARVELL_PHY_ID_88E1145,
3807 .phy_id_mask = MARVELL_PHY_ID_MASK,
3808 .name = "Marvell 88E1145",
3809 /* PHY_GBIT_FEATURES */
3810 .flags = PHY_POLL_CABLE_TEST,
3811 .probe = marvell_probe,
3812 .config_init = m88e1145_config_init,
3813 .config_aneg = m88e1101_config_aneg,
3814 .config_intr = marvell_config_intr,
3815 .handle_interrupt = marvell_handle_interrupt,
3816 .resume = genphy_resume,
3817 .suspend = genphy_suspend,
3818 .read_page = marvell_read_page,
3819 .write_page = marvell_write_page,
3820 .get_sset_count = marvell_get_sset_count,
3821 .get_strings = marvell_get_strings,
3822 .get_stats = marvell_get_stats,
3823 .get_tunable = m88e1111_get_tunable,
3824 .set_tunable = m88e1111_set_tunable,
3825 .cable_test_start = m88e1111_vct_cable_test_start,
3826 .cable_test_get_status = m88e1111_vct_cable_test_get_status,
3827 },
3828 {
3829 .phy_id = MARVELL_PHY_ID_88E1149R,
3830 .phy_id_mask = MARVELL_PHY_ID_MASK,
3831 .name = "Marvell 88E1149R",
3832 /* PHY_GBIT_FEATURES */
3833 .probe = marvell_probe,
3834 .config_init = m88e1149_config_init,
3835 .config_aneg = m88e1118_config_aneg,
3836 .config_intr = marvell_config_intr,
3837 .handle_interrupt = marvell_handle_interrupt,
3838 .resume = genphy_resume,
3839 .suspend = genphy_suspend,
3840 .read_page = marvell_read_page,
3841 .write_page = marvell_write_page,
3842 .get_sset_count = marvell_get_sset_count,
3843 .get_strings = marvell_get_strings,
3844 .get_stats = marvell_get_stats,
3845 },
3846 {
3847 .phy_id = MARVELL_PHY_ID_88E1240,
3848 .phy_id_mask = MARVELL_PHY_ID_MASK,
3849 .name = "Marvell 88E1240",
3850 /* PHY_GBIT_FEATURES */
3851 .probe = marvell_probe,
3852 .config_init = m88e1112_config_init,
3853 .config_aneg = marvell_config_aneg,
3854 .config_intr = marvell_config_intr,
3855 .handle_interrupt = marvell_handle_interrupt,
3856 .resume = genphy_resume,
3857 .suspend = genphy_suspend,
3858 .read_page = marvell_read_page,
3859 .write_page = marvell_write_page,
3860 .get_sset_count = marvell_get_sset_count,
3861 .get_strings = marvell_get_strings,
3862 .get_stats = marvell_get_stats,
3863 .get_tunable = m88e1011_get_tunable,
3864 .set_tunable = m88e1011_set_tunable,
3865 },
3866 {
3867 .phy_id = MARVELL_PHY_ID_88E1116R,
3868 .phy_id_mask = MARVELL_PHY_ID_MASK,
3869 .name = "Marvell 88E1116R",
3870 /* PHY_GBIT_FEATURES */
3871 .probe = marvell_probe,
3872 .config_init = m88e1116r_config_init,
3873 .config_intr = marvell_config_intr,
3874 .handle_interrupt = marvell_handle_interrupt,
3875 .resume = genphy_resume,
3876 .suspend = genphy_suspend,
3877 .read_page = marvell_read_page,
3878 .write_page = marvell_write_page,
3879 .get_sset_count = marvell_get_sset_count,
3880 .get_strings = marvell_get_strings,
3881 .get_stats = marvell_get_stats,
3882 .get_tunable = m88e1011_get_tunable,
3883 .set_tunable = m88e1011_set_tunable,
3884 },
3885 {
3886 .phy_id = MARVELL_PHY_ID_88E1510,
3887 .phy_id_mask = MARVELL_PHY_ID_MASK,
3888 .name = "Marvell 88E1510",
3889 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3890 .features = PHY_GBIT_FIBRE_FEATURES,
3891 .flags = PHY_POLL_CABLE_TEST,
3892 .probe = m88e1510_probe,
3893 .config_init = m88e1510_config_init,
3894 .config_aneg = m88e1510_config_aneg,
3895 .read_status = marvell_read_status,
3896 .config_intr = marvell_config_intr,
3897 .handle_interrupt = marvell_handle_interrupt,
3898 .get_wol = m88e1318_get_wol,
3899 .set_wol = m88e1318_set_wol,
3900 .resume = marvell_resume,
3901 .suspend = marvell_suspend,
3902 .read_page = marvell_read_page,
3903 .write_page = marvell_write_page,
3904 .get_sset_count = marvell_get_sset_count,
3905 .get_strings = marvell_get_strings,
3906 .get_stats = marvell_get_stats,
3907 .set_loopback = m88e1510_loopback,
3908 .get_tunable = m88e1011_get_tunable,
3909 .set_tunable = m88e1011_set_tunable,
3910 .cable_test_start = marvell_vct7_cable_test_start,
3911 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3912 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3913 .led_brightness_set = m88e1318_led_brightness_set,
3914 .led_blink_set = m88e1318_led_blink_set,
3915 .led_hw_is_supported = m88e1318_led_hw_is_supported,
3916 .led_hw_control_set = m88e1318_led_hw_control_set,
3917 .led_hw_control_get = m88e1318_led_hw_control_get,
3918 },
3919 {
3920 .phy_id = MARVELL_PHY_ID_88E1540,
3921 .phy_id_mask = MARVELL_PHY_ID_MASK,
3922 .name = "Marvell 88E1540",
3923 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3924 /* PHY_GBIT_FEATURES */
3925 .flags = PHY_POLL_CABLE_TEST,
3926 .probe = marvell_probe,
3927 .config_init = marvell_1011gbe_config_init,
3928 .config_aneg = m88e1510_config_aneg,
3929 .read_status = marvell_read_status,
3930 .config_intr = marvell_config_intr,
3931 .handle_interrupt = marvell_handle_interrupt,
3932 .resume = genphy_resume,
3933 .suspend = genphy_suspend,
3934 .read_page = marvell_read_page,
3935 .write_page = marvell_write_page,
3936 .get_sset_count = marvell_get_sset_count,
3937 .get_strings = marvell_get_strings,
3938 .get_stats = marvell_get_stats,
3939 .get_tunable = m88e1540_get_tunable,
3940 .set_tunable = m88e1540_set_tunable,
3941 .cable_test_start = marvell_vct7_cable_test_start,
3942 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3943 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3944 .led_brightness_set = m88e1318_led_brightness_set,
3945 .led_blink_set = m88e1318_led_blink_set,
3946 .led_hw_is_supported = m88e1318_led_hw_is_supported,
3947 .led_hw_control_set = m88e1318_led_hw_control_set,
3948 .led_hw_control_get = m88e1318_led_hw_control_get,
3949 },
3950 {
3951 .phy_id = MARVELL_PHY_ID_88E1545,
3952 .phy_id_mask = MARVELL_PHY_ID_MASK,
3953 .name = "Marvell 88E1545",
3954 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3955 .probe = marvell_probe,
3956 /* PHY_GBIT_FEATURES */
3957 .flags = PHY_POLL_CABLE_TEST,
3958 .config_init = marvell_1011gbe_config_init,
3959 .config_aneg = m88e1510_config_aneg,
3960 .read_status = marvell_read_status,
3961 .config_intr = marvell_config_intr,
3962 .handle_interrupt = marvell_handle_interrupt,
3963 .resume = genphy_resume,
3964 .suspend = genphy_suspend,
3965 .read_page = marvell_read_page,
3966 .write_page = marvell_write_page,
3967 .get_sset_count = marvell_get_sset_count,
3968 .get_strings = marvell_get_strings,
3969 .get_stats = marvell_get_stats,
3970 .get_tunable = m88e1540_get_tunable,
3971 .set_tunable = m88e1540_set_tunable,
3972 .cable_test_start = marvell_vct7_cable_test_start,
3973 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3974 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3975 .led_brightness_set = m88e1318_led_brightness_set,
3976 .led_blink_set = m88e1318_led_blink_set,
3977 .led_hw_is_supported = m88e1318_led_hw_is_supported,
3978 .led_hw_control_set = m88e1318_led_hw_control_set,
3979 .led_hw_control_get = m88e1318_led_hw_control_get,
3980 },
3981 {
3982 .phy_id = MARVELL_PHY_ID_88E3016,
3983 .phy_id_mask = MARVELL_PHY_ID_MASK,
3984 .name = "Marvell 88E3016",
3985 /* PHY_BASIC_FEATURES */
3986 .probe = marvell_probe,
3987 .config_init = m88e3016_config_init,
3988 .aneg_done = marvell_aneg_done,
3989 .read_status = marvell_read_status,
3990 .config_intr = marvell_config_intr,
3991 .handle_interrupt = marvell_handle_interrupt,
3992 .resume = genphy_resume,
3993 .suspend = genphy_suspend,
3994 .read_page = marvell_read_page,
3995 .write_page = marvell_write_page,
3996 .get_sset_count = marvell_get_sset_count,
3997 .get_strings = marvell_get_strings,
3998 .get_stats = marvell_get_stats,
3999 },
4000 {
4001 .phy_id = MARVELL_PHY_ID_88E6250_FAMILY,
4002 .phy_id_mask = MARVELL_PHY_ID_MASK,
4003 .name = "Marvell 88E6250 Family",
4004 /* PHY_BASIC_FEATURES */
4005 .probe = marvell_probe,
4006 .aneg_done = marvell_aneg_done,
4007 .config_intr = marvell_config_intr,
4008 .handle_interrupt = marvell_handle_interrupt,
4009 .resume = genphy_resume,
4010 .suspend = genphy_suspend,
4011 .get_sset_count = marvell_get_sset_count_simple,
4012 .get_strings = marvell_get_strings_simple,
4013 .get_stats = marvell_get_stats_simple,
4014 },
4015 {
4016 .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
4017 .phy_id_mask = MARVELL_PHY_ID_MASK,
4018 .name = "Marvell 88E6341 Family",
4019 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
4020 /* PHY_GBIT_FEATURES */
4021 .flags = PHY_POLL_CABLE_TEST,
4022 .probe = marvell_probe,
4023 .config_init = marvell_1011gbe_config_init,
4024 .config_aneg = m88e6390_config_aneg,
4025 .read_status = marvell_read_status,
4026 .config_intr = marvell_config_intr,
4027 .handle_interrupt = marvell_handle_interrupt,
4028 .resume = genphy_resume,
4029 .suspend = genphy_suspend,
4030 .read_page = marvell_read_page,
4031 .write_page = marvell_write_page,
4032 .get_sset_count = marvell_get_sset_count,
4033 .get_strings = marvell_get_strings,
4034 .get_stats = marvell_get_stats,
4035 .get_tunable = m88e1540_get_tunable,
4036 .set_tunable = m88e1540_set_tunable,
4037 .cable_test_start = marvell_vct7_cable_test_start,
4038 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
4039 .cable_test_get_status = marvell_vct7_cable_test_get_status,
4040 },
4041 {
4042 .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
4043 .phy_id_mask = MARVELL_PHY_ID_MASK,
4044 .name = "Marvell 88E6390 Family",
4045 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops),
4046 /* PHY_GBIT_FEATURES */
4047 .flags = PHY_POLL_CABLE_TEST,
4048 .probe = marvell_probe,
4049 .config_init = marvell_1011gbe_config_init,
4050 .config_aneg = m88e6390_config_aneg,
4051 .read_status = marvell_read_status,
4052 .config_intr = marvell_config_intr,
4053 .handle_interrupt = marvell_handle_interrupt,
4054 .resume = genphy_resume,
4055 .suspend = genphy_suspend,
4056 .read_page = marvell_read_page,
4057 .write_page = marvell_write_page,
4058 .get_sset_count = marvell_get_sset_count,
4059 .get_strings = marvell_get_strings,
4060 .get_stats = marvell_get_stats,
4061 .get_tunable = m88e1540_get_tunable,
4062 .set_tunable = m88e1540_set_tunable,
4063 .cable_test_start = marvell_vct7_cable_test_start,
4064 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
4065 .cable_test_get_status = marvell_vct7_cable_test_get_status,
4066 },
4067 {
4068 .phy_id = MARVELL_PHY_ID_88E6393_FAMILY,
4069 .phy_id_mask = MARVELL_PHY_ID_MASK,
4070 .name = "Marvell 88E6393 Family",
4071 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6393_hwmon_ops),
4072 /* PHY_GBIT_FEATURES */
4073 .flags = PHY_POLL_CABLE_TEST,
4074 .probe = marvell_probe,
4075 .config_init = marvell_1011gbe_config_init,
4076 .config_aneg = m88e1510_config_aneg,
4077 .read_status = marvell_read_status,
4078 .config_intr = marvell_config_intr,
4079 .handle_interrupt = marvell_handle_interrupt,
4080 .resume = genphy_resume,
4081 .suspend = genphy_suspend,
4082 .read_page = marvell_read_page,
4083 .write_page = marvell_write_page,
4084 .get_sset_count = marvell_get_sset_count,
4085 .get_strings = marvell_get_strings,
4086 .get_stats = marvell_get_stats,
4087 .get_tunable = m88e1540_get_tunable,
4088 .set_tunable = m88e1540_set_tunable,
4089 .cable_test_start = marvell_vct7_cable_test_start,
4090 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
4091 .cable_test_get_status = marvell_vct7_cable_test_get_status,
4092 },
4093 {
4094 .phy_id = MARVELL_PHY_ID_88E1340S,
4095 .phy_id_mask = MARVELL_PHY_ID_MASK,
4096 .name = "Marvell 88E1340S",
4097 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
4098 .probe = marvell_probe,
4099 /* PHY_GBIT_FEATURES */
4100 .config_init = marvell_1011gbe_config_init,
4101 .config_aneg = m88e1510_config_aneg,
4102 .read_status = marvell_read_status,
4103 .config_intr = marvell_config_intr,
4104 .handle_interrupt = marvell_handle_interrupt,
4105 .resume = genphy_resume,
4106 .suspend = genphy_suspend,
4107 .read_page = marvell_read_page,
4108 .write_page = marvell_write_page,
4109 .get_sset_count = marvell_get_sset_count,
4110 .get_strings = marvell_get_strings,
4111 .get_stats = marvell_get_stats,
4112 .get_tunable = m88e1540_get_tunable,
4113 .set_tunable = m88e1540_set_tunable,
4114 },
4115 {
4116 .phy_id = MARVELL_PHY_ID_88E1548P,
4117 .phy_id_mask = MARVELL_PHY_ID_MASK,
4118 .name = "Marvell 88E1548P",
4119 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
4120 .probe = marvell_probe,
4121 .features = PHY_GBIT_FIBRE_FEATURES,
4122 .config_init = marvell_1011gbe_config_init,
4123 .config_aneg = m88e1510_config_aneg,
4124 .read_status = marvell_read_status,
4125 .config_intr = marvell_config_intr,
4126 .handle_interrupt = marvell_handle_interrupt,
4127 .resume = genphy_resume,
4128 .suspend = genphy_suspend,
4129 .read_page = marvell_read_page,
4130 .write_page = marvell_write_page,
4131 .get_sset_count = marvell_get_sset_count,
4132 .get_strings = marvell_get_strings,
4133 .get_stats = marvell_get_stats,
4134 .get_tunable = m88e1540_get_tunable,
4135 .set_tunable = m88e1540_set_tunable,
4136 .led_brightness_set = m88e1318_led_brightness_set,
4137 .led_blink_set = m88e1318_led_blink_set,
4138 .led_hw_is_supported = m88e1318_led_hw_is_supported,
4139 .led_hw_control_set = m88e1318_led_hw_control_set,
4140 .led_hw_control_get = m88e1318_led_hw_control_get,
4141 },
4142};
4143
4144module_phy_driver(marvell_drivers);
4145
4146static struct mdio_device_id __maybe_unused marvell_tbl[] = {
4147 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
4148 { MARVELL_PHY_ID_88E3082, MARVELL_PHY_ID_MASK },
4149 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
4150 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
4151 { MARVELL_PHY_ID_88E1111_FINISAR, MARVELL_PHY_ID_MASK },
4152 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
4153 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
4154 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
4155 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
4156 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
4157 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
4158 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
4159 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
4160 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
4161 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
4162 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
4163 { MARVELL_PHY_ID_88E6250_FAMILY, MARVELL_PHY_ID_MASK },
4164 { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
4165 { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
4166 { MARVELL_PHY_ID_88E6393_FAMILY, MARVELL_PHY_ID_MASK },
4167 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
4168 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
4169 { }
4170};
4171
4172MODULE_DEVICE_TABLE(mdio, marvell_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/marvell.c
4 *
5 * Driver for Marvell PHYs
6 *
7 * Author: Andy Fleming
8 *
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 *
11 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12 */
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/ctype.h>
16#include <linux/errno.h>
17#include <linux/unistd.h>
18#include <linux/hwmon.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/spinlock.h>
26#include <linux/mm.h>
27#include <linux/module.h>
28#include <linux/mii.h>
29#include <linux/ethtool.h>
30#include <linux/ethtool_netlink.h>
31#include <linux/phy.h>
32#include <linux/marvell_phy.h>
33#include <linux/bitfield.h>
34#include <linux/of.h>
35#include <linux/sfp.h>
36
37#include <linux/io.h>
38#include <asm/irq.h>
39#include <linux/uaccess.h>
40
41#define MII_MARVELL_PHY_PAGE 22
42#define MII_MARVELL_COPPER_PAGE 0x00
43#define MII_MARVELL_FIBER_PAGE 0x01
44#define MII_MARVELL_MSCR_PAGE 0x02
45#define MII_MARVELL_LED_PAGE 0x03
46#define MII_MARVELL_VCT5_PAGE 0x05
47#define MII_MARVELL_MISC_TEST_PAGE 0x06
48#define MII_MARVELL_VCT7_PAGE 0x07
49#define MII_MARVELL_WOL_PAGE 0x11
50#define MII_MARVELL_MODE_PAGE 0x12
51
52#define MII_M1011_IEVENT 0x13
53#define MII_M1011_IEVENT_CLEAR 0x0000
54
55#define MII_M1011_IMASK 0x12
56#define MII_M1011_IMASK_INIT 0x6400
57#define MII_M1011_IMASK_CLEAR 0x0000
58
59#define MII_M1011_PHY_SCR 0x10
60#define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
61#define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
62#define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
63#define MII_M1011_PHY_SCR_MDI (0x0 << 5)
64#define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
65#define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
66
67#define MII_M1011_PHY_SSR 0x11
68#define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
69
70#define MII_M1111_PHY_LED_CONTROL 0x18
71#define MII_M1111_PHY_LED_DIRECT 0x4100
72#define MII_M1111_PHY_LED_COMBINE 0x411c
73#define MII_M1111_PHY_EXT_CR 0x14
74#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
75#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
76#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
77#define MII_M1111_RGMII_RX_DELAY BIT(7)
78#define MII_M1111_RGMII_TX_DELAY BIT(1)
79#define MII_M1111_PHY_EXT_SR 0x1b
80
81#define MII_M1111_HWCFG_MODE_MASK 0xf
82#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
83#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
84#define MII_M1111_HWCFG_MODE_RTBI 0x7
85#define MII_M1111_HWCFG_MODE_COPPER_1000X_AN 0x8
86#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
87#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
88#define MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN 0xc
89#define MII_M1111_HWCFG_SERIAL_AN_BYPASS BIT(12)
90#define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
91#define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
92
93#define MII_88E1121_PHY_MSCR_REG 21
94#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
95#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
96#define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
97
98#define MII_88E1121_MISC_TEST 0x1a
99#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
100#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
101#define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
102#define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
103#define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
104#define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
105
106#define MII_88E1510_TEMP_SENSOR 0x1b
107#define MII_88E1510_TEMP_SENSOR_MASK 0xff
108
109#define MII_88E1540_COPPER_CTRL3 0x1a
110#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
111#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
112#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
113#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
114#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
115#define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
116
117#define MII_88E6390_MISC_TEST 0x1b
118#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S (0x0 << 14)
119#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE (0x1 << 14)
120#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_ONESHOT (0x2 << 14)
121#define MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE (0x3 << 14)
122#define MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK (0x3 << 14)
123#define MII_88E6393_MISC_TEST_SAMPLES_2048 (0x0 << 11)
124#define MII_88E6393_MISC_TEST_SAMPLES_4096 (0x1 << 11)
125#define MII_88E6393_MISC_TEST_SAMPLES_8192 (0x2 << 11)
126#define MII_88E6393_MISC_TEST_SAMPLES_16384 (0x3 << 11)
127#define MII_88E6393_MISC_TEST_SAMPLES_MASK (0x3 << 11)
128#define MII_88E6393_MISC_TEST_RATE_2_3MS (0x5 << 8)
129#define MII_88E6393_MISC_TEST_RATE_6_4MS (0x6 << 8)
130#define MII_88E6393_MISC_TEST_RATE_11_9MS (0x7 << 8)
131#define MII_88E6393_MISC_TEST_RATE_MASK (0x7 << 8)
132
133#define MII_88E6390_TEMP_SENSOR 0x1c
134#define MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK 0xff00
135#define MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT 8
136#define MII_88E6390_TEMP_SENSOR_MASK 0xff
137#define MII_88E6390_TEMP_SENSOR_SAMPLES 10
138
139#define MII_88E1318S_PHY_MSCR1_REG 16
140#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
141
142/* Copper Specific Interrupt Enable Register */
143#define MII_88E1318S_PHY_CSIER 0x12
144/* WOL Event Interrupt Enable */
145#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
146
147/* LED Timer Control Register */
148#define MII_88E1318S_PHY_LED_TCR 0x12
149#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
150#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
151#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
152
153/* Magic Packet MAC address registers */
154#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
155#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
156#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
157
158#define MII_88E1318S_PHY_WOL_CTRL 0x10
159#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
160#define MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE BIT(13)
161#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
162
163#define MII_PHY_LED_CTRL 16
164#define MII_88E1121_PHY_LED_DEF 0x0030
165#define MII_88E1510_PHY_LED_DEF 0x1177
166#define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
167
168#define MII_M1011_PHY_STATUS 0x11
169#define MII_M1011_PHY_STATUS_1000 0x8000
170#define MII_M1011_PHY_STATUS_100 0x4000
171#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
172#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
173#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
174#define MII_M1011_PHY_STATUS_LINK 0x0400
175
176#define MII_88E3016_PHY_SPEC_CTRL 0x10
177#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
178#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
179
180#define MII_88E1510_GEN_CTRL_REG_1 0x14
181#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
182#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII 0x0 /* RGMII to copper */
183#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
184/* RGMII to 1000BASE-X */
185#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X 0x2
186/* RGMII to 100BASE-FX */
187#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX 0x3
188/* RGMII to SGMII */
189#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII 0x4
190#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
191
192#define MII_88E1510_MSCR_2 0x15
193
194#define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
195#define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
196#define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
197#define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
198#define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
199#define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
200#define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
201
202#define MII_VCT5_CTRL 0x17
203#define MII_VCT5_CTRL_ENABLE BIT(15)
204#define MII_VCT5_CTRL_COMPLETE BIT(14)
205#define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
206#define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
207#define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
208#define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
209#define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
210#define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
211#define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
212#define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
213#define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
214#define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
215#define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
216#define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
217#define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
218#define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
219#define MII_VCT5_CTRL_SAMPLES_SHIFT 8
220#define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
221#define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
222#define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
223#define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
224#define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
225
226#define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
227#define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
228#define MII_VCT5_TX_PULSE_CTRL 0x1c
229#define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
230#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
231#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
232#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
233#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
234#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
235#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
236#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
237#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
238#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
239#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
240#define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
241#define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
242
243/* For TDR measurements less than 11 meters, a short pulse should be
244 * used.
245 */
246#define TDR_SHORT_CABLE_LENGTH 11
247
248#define MII_VCT7_PAIR_0_DISTANCE 0x10
249#define MII_VCT7_PAIR_1_DISTANCE 0x11
250#define MII_VCT7_PAIR_2_DISTANCE 0x12
251#define MII_VCT7_PAIR_3_DISTANCE 0x13
252
253#define MII_VCT7_RESULTS 0x14
254#define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
255#define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
256#define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
257#define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
258#define MII_VCT7_RESULTS_PAIR3_SHIFT 12
259#define MII_VCT7_RESULTS_PAIR2_SHIFT 8
260#define MII_VCT7_RESULTS_PAIR1_SHIFT 4
261#define MII_VCT7_RESULTS_PAIR0_SHIFT 0
262#define MII_VCT7_RESULTS_INVALID 0
263#define MII_VCT7_RESULTS_OK 1
264#define MII_VCT7_RESULTS_OPEN 2
265#define MII_VCT7_RESULTS_SAME_SHORT 3
266#define MII_VCT7_RESULTS_CROSS_SHORT 4
267#define MII_VCT7_RESULTS_BUSY 9
268
269#define MII_VCT7_CTRL 0x15
270#define MII_VCT7_CTRL_RUN_NOW BIT(15)
271#define MII_VCT7_CTRL_RUN_ANEG BIT(14)
272#define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
273#define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
274#define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
275#define MII_VCT7_CTRL_METERS BIT(10)
276#define MII_VCT7_CTRL_CENTIMETERS 0
277
278#define LPA_PAUSE_FIBER 0x180
279#define LPA_PAUSE_ASYM_FIBER 0x100
280
281#define NB_FIBER_STATS 1
282
283MODULE_DESCRIPTION("Marvell PHY driver");
284MODULE_AUTHOR("Andy Fleming");
285MODULE_LICENSE("GPL");
286
287struct marvell_hw_stat {
288 const char *string;
289 u8 page;
290 u8 reg;
291 u8 bits;
292};
293
294static struct marvell_hw_stat marvell_hw_stats[] = {
295 { "phy_receive_errors_copper", 0, 21, 16},
296 { "phy_idle_errors", 0, 10, 8 },
297 { "phy_receive_errors_fiber", 1, 21, 16},
298};
299
300struct marvell_priv {
301 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
302 char *hwmon_name;
303 struct device *hwmon_dev;
304 bool cable_test_tdr;
305 u32 first;
306 u32 last;
307 u32 step;
308 s8 pair;
309};
310
311static int marvell_read_page(struct phy_device *phydev)
312{
313 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
314}
315
316static int marvell_write_page(struct phy_device *phydev, int page)
317{
318 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
319}
320
321static int marvell_set_page(struct phy_device *phydev, int page)
322{
323 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
324}
325
326static int marvell_ack_interrupt(struct phy_device *phydev)
327{
328 int err;
329
330 /* Clear the interrupts by reading the reg */
331 err = phy_read(phydev, MII_M1011_IEVENT);
332
333 if (err < 0)
334 return err;
335
336 return 0;
337}
338
339static int marvell_config_intr(struct phy_device *phydev)
340{
341 int err;
342
343 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
344 err = marvell_ack_interrupt(phydev);
345 if (err)
346 return err;
347
348 err = phy_write(phydev, MII_M1011_IMASK,
349 MII_M1011_IMASK_INIT);
350 } else {
351 err = phy_write(phydev, MII_M1011_IMASK,
352 MII_M1011_IMASK_CLEAR);
353 if (err)
354 return err;
355
356 err = marvell_ack_interrupt(phydev);
357 }
358
359 return err;
360}
361
362static irqreturn_t marvell_handle_interrupt(struct phy_device *phydev)
363{
364 int irq_status;
365
366 irq_status = phy_read(phydev, MII_M1011_IEVENT);
367 if (irq_status < 0) {
368 phy_error(phydev);
369 return IRQ_NONE;
370 }
371
372 if (!(irq_status & MII_M1011_IMASK_INIT))
373 return IRQ_NONE;
374
375 phy_trigger_machine(phydev);
376
377 return IRQ_HANDLED;
378}
379
380static int marvell_set_polarity(struct phy_device *phydev, int polarity)
381{
382 u16 val;
383
384 switch (polarity) {
385 case ETH_TP_MDI:
386 val = MII_M1011_PHY_SCR_MDI;
387 break;
388 case ETH_TP_MDI_X:
389 val = MII_M1011_PHY_SCR_MDI_X;
390 break;
391 case ETH_TP_MDI_AUTO:
392 case ETH_TP_MDI_INVALID:
393 default:
394 val = MII_M1011_PHY_SCR_AUTO_CROSS;
395 break;
396 }
397
398 return phy_modify_changed(phydev, MII_M1011_PHY_SCR,
399 MII_M1011_PHY_SCR_AUTO_CROSS, val);
400}
401
402static int marvell_config_aneg(struct phy_device *phydev)
403{
404 int changed = 0;
405 int err;
406
407 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
408 if (err < 0)
409 return err;
410
411 changed = err;
412
413 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
414 MII_M1111_PHY_LED_DIRECT);
415 if (err < 0)
416 return err;
417
418 err = genphy_config_aneg(phydev);
419 if (err < 0)
420 return err;
421
422 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
423 /* A write to speed/duplex bits (that is performed by
424 * genphy_config_aneg() call above) must be followed by
425 * a software reset. Otherwise, the write has no effect.
426 */
427 err = genphy_soft_reset(phydev);
428 if (err < 0)
429 return err;
430 }
431
432 return 0;
433}
434
435static int m88e1101_config_aneg(struct phy_device *phydev)
436{
437 int err;
438
439 /* This Marvell PHY has an errata which requires
440 * that certain registers get written in order
441 * to restart autonegotiation
442 */
443 err = genphy_soft_reset(phydev);
444 if (err < 0)
445 return err;
446
447 err = phy_write(phydev, 0x1d, 0x1f);
448 if (err < 0)
449 return err;
450
451 err = phy_write(phydev, 0x1e, 0x200c);
452 if (err < 0)
453 return err;
454
455 err = phy_write(phydev, 0x1d, 0x5);
456 if (err < 0)
457 return err;
458
459 err = phy_write(phydev, 0x1e, 0);
460 if (err < 0)
461 return err;
462
463 err = phy_write(phydev, 0x1e, 0x100);
464 if (err < 0)
465 return err;
466
467 return marvell_config_aneg(phydev);
468}
469
470#if IS_ENABLED(CONFIG_OF_MDIO)
471/* Set and/or override some configuration registers based on the
472 * marvell,reg-init property stored in the of_node for the phydev.
473 *
474 * marvell,reg-init = <reg-page reg mask value>,...;
475 *
476 * There may be one or more sets of <reg-page reg mask value>:
477 *
478 * reg-page: which register bank to use.
479 * reg: the register.
480 * mask: if non-zero, ANDed with existing register value.
481 * value: ORed with the masked value and written to the regiser.
482 *
483 */
484static int marvell_of_reg_init(struct phy_device *phydev)
485{
486 const __be32 *paddr;
487 int len, i, saved_page, current_page, ret = 0;
488
489 if (!phydev->mdio.dev.of_node)
490 return 0;
491
492 paddr = of_get_property(phydev->mdio.dev.of_node,
493 "marvell,reg-init", &len);
494 if (!paddr || len < (4 * sizeof(*paddr)))
495 return 0;
496
497 saved_page = phy_save_page(phydev);
498 if (saved_page < 0)
499 goto err;
500 current_page = saved_page;
501
502 len /= sizeof(*paddr);
503 for (i = 0; i < len - 3; i += 4) {
504 u16 page = be32_to_cpup(paddr + i);
505 u16 reg = be32_to_cpup(paddr + i + 1);
506 u16 mask = be32_to_cpup(paddr + i + 2);
507 u16 val_bits = be32_to_cpup(paddr + i + 3);
508 int val;
509
510 if (page != current_page) {
511 current_page = page;
512 ret = marvell_write_page(phydev, page);
513 if (ret < 0)
514 goto err;
515 }
516
517 val = 0;
518 if (mask) {
519 val = __phy_read(phydev, reg);
520 if (val < 0) {
521 ret = val;
522 goto err;
523 }
524 val &= mask;
525 }
526 val |= val_bits;
527
528 ret = __phy_write(phydev, reg, val);
529 if (ret < 0)
530 goto err;
531 }
532err:
533 return phy_restore_page(phydev, saved_page, ret);
534}
535#else
536static int marvell_of_reg_init(struct phy_device *phydev)
537{
538 return 0;
539}
540#endif /* CONFIG_OF_MDIO */
541
542static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
543{
544 int mscr;
545
546 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
547 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
548 MII_88E1121_PHY_MSCR_TX_DELAY;
549 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
550 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
551 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
552 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
553 else
554 mscr = 0;
555
556 return phy_modify_paged_changed(phydev, MII_MARVELL_MSCR_PAGE,
557 MII_88E1121_PHY_MSCR_REG,
558 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
559}
560
561static int m88e1121_config_aneg(struct phy_device *phydev)
562{
563 int changed = 0;
564 int err = 0;
565
566 if (phy_interface_is_rgmii(phydev)) {
567 err = m88e1121_config_aneg_rgmii_delays(phydev);
568 if (err < 0)
569 return err;
570 }
571
572 changed = err;
573
574 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
575 if (err < 0)
576 return err;
577
578 changed |= err;
579
580 err = genphy_config_aneg(phydev);
581 if (err < 0)
582 return err;
583
584 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
585 /* A software reset is used to ensure a "commit" of the
586 * changes is done.
587 */
588 err = genphy_soft_reset(phydev);
589 if (err < 0)
590 return err;
591 }
592
593 return 0;
594}
595
596static int m88e1318_config_aneg(struct phy_device *phydev)
597{
598 int err;
599
600 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
601 MII_88E1318S_PHY_MSCR1_REG,
602 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
603 if (err < 0)
604 return err;
605
606 return m88e1121_config_aneg(phydev);
607}
608
609/**
610 * linkmode_adv_to_fiber_adv_t
611 * @advertise: the linkmode advertisement settings
612 *
613 * A small helper function that translates linkmode advertisement
614 * settings to phy autonegotiation advertisements for the MII_ADV
615 * register for fiber link.
616 */
617static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
618{
619 u32 result = 0;
620
621 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
622 result |= ADVERTISE_1000XHALF;
623 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
624 result |= ADVERTISE_1000XFULL;
625
626 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
627 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
628 result |= ADVERTISE_1000XPSE_ASYM;
629 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
630 result |= ADVERTISE_1000XPAUSE;
631
632 return result;
633}
634
635/**
636 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
637 * @phydev: target phy_device struct
638 *
639 * Description: If auto-negotiation is enabled, we configure the
640 * advertising, and then restart auto-negotiation. If it is not
641 * enabled, then we write the BMCR. Adapted for fiber link in
642 * some Marvell's devices.
643 */
644static int marvell_config_aneg_fiber(struct phy_device *phydev)
645{
646 int changed = 0;
647 int err;
648 u16 adv;
649
650 if (phydev->autoneg != AUTONEG_ENABLE)
651 return genphy_setup_forced(phydev);
652
653 /* Only allow advertising what this PHY supports */
654 linkmode_and(phydev->advertising, phydev->advertising,
655 phydev->supported);
656
657 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
658
659 /* Setup fiber advertisement */
660 err = phy_modify_changed(phydev, MII_ADVERTISE,
661 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
662 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
663 adv);
664 if (err < 0)
665 return err;
666 if (err > 0)
667 changed = 1;
668
669 return genphy_check_and_restart_aneg(phydev, changed);
670}
671
672static int m88e1111_config_aneg(struct phy_device *phydev)
673{
674 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
675 int err;
676
677 if (extsr < 0)
678 return extsr;
679
680 /* If not using SGMII or copper 1000BaseX modes, use normal process.
681 * Steps below are only required for these modes.
682 */
683 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
684 (extsr & MII_M1111_HWCFG_MODE_MASK) !=
685 MII_M1111_HWCFG_MODE_COPPER_1000X_AN)
686 return marvell_config_aneg(phydev);
687
688 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
689 if (err < 0)
690 goto error;
691
692 /* Configure the copper link first */
693 err = marvell_config_aneg(phydev);
694 if (err < 0)
695 goto error;
696
697 /* Then the fiber link */
698 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
699 if (err < 0)
700 goto error;
701
702 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
703 /* Do not touch the fiber advertisement if we're in copper->sgmii mode.
704 * Just ensure that SGMII-side autonegotiation is enabled.
705 * If we switched from some other mode to SGMII it may not be.
706 */
707 err = genphy_check_and_restart_aneg(phydev, false);
708 else
709 err = marvell_config_aneg_fiber(phydev);
710 if (err < 0)
711 goto error;
712
713 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
714
715error:
716 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
717 return err;
718}
719
720static int m88e1510_config_aneg(struct phy_device *phydev)
721{
722 int err;
723
724 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
725 if (err < 0)
726 goto error;
727
728 /* Configure the copper link first */
729 err = m88e1318_config_aneg(phydev);
730 if (err < 0)
731 goto error;
732
733 /* Do not touch the fiber page if we're in copper->sgmii mode */
734 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
735 return 0;
736
737 /* Then the fiber link */
738 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
739 if (err < 0)
740 goto error;
741
742 err = marvell_config_aneg_fiber(phydev);
743 if (err < 0)
744 goto error;
745
746 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
747
748error:
749 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
750 return err;
751}
752
753static void marvell_config_led(struct phy_device *phydev)
754{
755 u16 def_config;
756 int err;
757
758 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
759 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
760 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
761 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
762 def_config = MII_88E1121_PHY_LED_DEF;
763 break;
764 /* Default PHY LED config:
765 * LED[0] .. 1000Mbps Link
766 * LED[1] .. 100Mbps Link
767 * LED[2] .. Blink, Activity
768 */
769 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
770 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
771 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
772 else
773 def_config = MII_88E1510_PHY_LED_DEF;
774 break;
775 default:
776 return;
777 }
778
779 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
780 def_config);
781 if (err < 0)
782 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
783}
784
785static int marvell_config_init(struct phy_device *phydev)
786{
787 /* Set default LED */
788 marvell_config_led(phydev);
789
790 /* Set registers from marvell,reg-init DT property */
791 return marvell_of_reg_init(phydev);
792}
793
794static int m88e3016_config_init(struct phy_device *phydev)
795{
796 int ret;
797
798 /* Enable Scrambler and Auto-Crossover */
799 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
800 MII_88E3016_DISABLE_SCRAMBLER,
801 MII_88E3016_AUTO_MDIX_CROSSOVER);
802 if (ret < 0)
803 return ret;
804
805 return marvell_config_init(phydev);
806}
807
808static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
809 u16 mode,
810 int fibre_copper_auto)
811{
812 if (fibre_copper_auto)
813 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
814
815 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
816 MII_M1111_HWCFG_MODE_MASK |
817 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
818 MII_M1111_HWCFG_FIBER_COPPER_RES,
819 mode);
820}
821
822static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
823{
824 int delay;
825
826 switch (phydev->interface) {
827 case PHY_INTERFACE_MODE_RGMII_ID:
828 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
829 break;
830 case PHY_INTERFACE_MODE_RGMII_RXID:
831 delay = MII_M1111_RGMII_RX_DELAY;
832 break;
833 case PHY_INTERFACE_MODE_RGMII_TXID:
834 delay = MII_M1111_RGMII_TX_DELAY;
835 break;
836 default:
837 delay = 0;
838 break;
839 }
840
841 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
842 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
843 delay);
844}
845
846static int m88e1111_config_init_rgmii(struct phy_device *phydev)
847{
848 int temp;
849 int err;
850
851 err = m88e1111_config_init_rgmii_delays(phydev);
852 if (err < 0)
853 return err;
854
855 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
856 if (temp < 0)
857 return temp;
858
859 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
860
861 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
862 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
863 else
864 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
865
866 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
867}
868
869static int m88e1111_config_init_sgmii(struct phy_device *phydev)
870{
871 int err;
872
873 err = m88e1111_config_init_hwcfg_mode(
874 phydev,
875 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
876 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
877 if (err < 0)
878 return err;
879
880 /* make sure copper is selected */
881 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
882}
883
884static int m88e1111_config_init_rtbi(struct phy_device *phydev)
885{
886 int err;
887
888 err = m88e1111_config_init_rgmii_delays(phydev);
889 if (err < 0)
890 return err;
891
892 err = m88e1111_config_init_hwcfg_mode(
893 phydev,
894 MII_M1111_HWCFG_MODE_RTBI,
895 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
896 if (err < 0)
897 return err;
898
899 /* soft reset */
900 err = genphy_soft_reset(phydev);
901 if (err < 0)
902 return err;
903
904 return m88e1111_config_init_hwcfg_mode(
905 phydev,
906 MII_M1111_HWCFG_MODE_RTBI,
907 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
908}
909
910static int m88e1111_config_init_1000basex(struct phy_device *phydev)
911{
912 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
913 int err, mode;
914
915 if (extsr < 0)
916 return extsr;
917
918 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled */
919 mode = extsr & MII_M1111_HWCFG_MODE_MASK;
920 if (mode == MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN) {
921 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
922 MII_M1111_HWCFG_MODE_MASK |
923 MII_M1111_HWCFG_SERIAL_AN_BYPASS,
924 MII_M1111_HWCFG_MODE_COPPER_1000X_AN |
925 MII_M1111_HWCFG_SERIAL_AN_BYPASS);
926 if (err < 0)
927 return err;
928 }
929 return 0;
930}
931
932static int m88e1111_config_init(struct phy_device *phydev)
933{
934 int err;
935
936 if (phy_interface_is_rgmii(phydev)) {
937 err = m88e1111_config_init_rgmii(phydev);
938 if (err < 0)
939 return err;
940 }
941
942 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
943 err = m88e1111_config_init_sgmii(phydev);
944 if (err < 0)
945 return err;
946 }
947
948 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
949 err = m88e1111_config_init_rtbi(phydev);
950 if (err < 0)
951 return err;
952 }
953
954 if (phydev->interface == PHY_INTERFACE_MODE_1000BASEX) {
955 err = m88e1111_config_init_1000basex(phydev);
956 if (err < 0)
957 return err;
958 }
959
960 err = marvell_of_reg_init(phydev);
961 if (err < 0)
962 return err;
963
964 err = genphy_soft_reset(phydev);
965 if (err < 0)
966 return err;
967
968 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
969 /* If the HWCFG_MODE was changed from another mode (such as
970 * 1000BaseX) to SGMII, the state of the support bits may have
971 * also changed now that the PHY has been reset.
972 * Update the PHY abilities accordingly.
973 */
974 err = genphy_read_abilities(phydev);
975 linkmode_or(phydev->advertising, phydev->advertising,
976 phydev->supported);
977 }
978 return err;
979}
980
981static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
982{
983 int val, cnt, enable;
984
985 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
986 if (val < 0)
987 return val;
988
989 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
990 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
991
992 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
993
994 return 0;
995}
996
997static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
998{
999 int val, err;
1000
1001 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
1002 return -E2BIG;
1003
1004 if (!cnt) {
1005 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
1006 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
1007 } else {
1008 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
1009 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
1010
1011 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
1012 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
1013 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
1014 val);
1015 }
1016
1017 if (err < 0)
1018 return err;
1019
1020 return genphy_soft_reset(phydev);
1021}
1022
1023static int m88e1111_get_tunable(struct phy_device *phydev,
1024 struct ethtool_tunable *tuna, void *data)
1025{
1026 switch (tuna->id) {
1027 case ETHTOOL_PHY_DOWNSHIFT:
1028 return m88e1111_get_downshift(phydev, data);
1029 default:
1030 return -EOPNOTSUPP;
1031 }
1032}
1033
1034static int m88e1111_set_tunable(struct phy_device *phydev,
1035 struct ethtool_tunable *tuna, const void *data)
1036{
1037 switch (tuna->id) {
1038 case ETHTOOL_PHY_DOWNSHIFT:
1039 return m88e1111_set_downshift(phydev, *(const u8 *)data);
1040 default:
1041 return -EOPNOTSUPP;
1042 }
1043}
1044
1045static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
1046{
1047 int val, cnt, enable;
1048
1049 val = phy_read(phydev, MII_M1011_PHY_SCR);
1050 if (val < 0)
1051 return val;
1052
1053 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
1054 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
1055
1056 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1057
1058 return 0;
1059}
1060
1061static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
1062{
1063 int val, err;
1064
1065 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
1066 return -E2BIG;
1067
1068 if (!cnt) {
1069 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
1070 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
1071 } else {
1072 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
1073 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
1074
1075 err = phy_modify(phydev, MII_M1011_PHY_SCR,
1076 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
1077 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
1078 val);
1079 }
1080
1081 if (err < 0)
1082 return err;
1083
1084 return genphy_soft_reset(phydev);
1085}
1086
1087static int m88e1011_get_tunable(struct phy_device *phydev,
1088 struct ethtool_tunable *tuna, void *data)
1089{
1090 switch (tuna->id) {
1091 case ETHTOOL_PHY_DOWNSHIFT:
1092 return m88e1011_get_downshift(phydev, data);
1093 default:
1094 return -EOPNOTSUPP;
1095 }
1096}
1097
1098static int m88e1011_set_tunable(struct phy_device *phydev,
1099 struct ethtool_tunable *tuna, const void *data)
1100{
1101 switch (tuna->id) {
1102 case ETHTOOL_PHY_DOWNSHIFT:
1103 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1104 default:
1105 return -EOPNOTSUPP;
1106 }
1107}
1108
1109static int m88e1112_config_init(struct phy_device *phydev)
1110{
1111 int err;
1112
1113 err = m88e1011_set_downshift(phydev, 3);
1114 if (err < 0)
1115 return err;
1116
1117 return m88e1111_config_init(phydev);
1118}
1119
1120static int m88e1111gbe_config_init(struct phy_device *phydev)
1121{
1122 int err;
1123
1124 err = m88e1111_set_downshift(phydev, 3);
1125 if (err < 0)
1126 return err;
1127
1128 return m88e1111_config_init(phydev);
1129}
1130
1131static int marvell_1011gbe_config_init(struct phy_device *phydev)
1132{
1133 int err;
1134
1135 err = m88e1011_set_downshift(phydev, 3);
1136 if (err < 0)
1137 return err;
1138
1139 return marvell_config_init(phydev);
1140}
1141static int m88e1116r_config_init(struct phy_device *phydev)
1142{
1143 int err;
1144
1145 err = genphy_soft_reset(phydev);
1146 if (err < 0)
1147 return err;
1148
1149 msleep(500);
1150
1151 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1152 if (err < 0)
1153 return err;
1154
1155 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1156 if (err < 0)
1157 return err;
1158
1159 err = m88e1011_set_downshift(phydev, 8);
1160 if (err < 0)
1161 return err;
1162
1163 if (phy_interface_is_rgmii(phydev)) {
1164 err = m88e1121_config_aneg_rgmii_delays(phydev);
1165 if (err < 0)
1166 return err;
1167 }
1168
1169 err = genphy_soft_reset(phydev);
1170 if (err < 0)
1171 return err;
1172
1173 return marvell_config_init(phydev);
1174}
1175
1176static int m88e1318_config_init(struct phy_device *phydev)
1177{
1178 if (phy_interrupt_is_valid(phydev)) {
1179 int err = phy_modify_paged(
1180 phydev, MII_MARVELL_LED_PAGE,
1181 MII_88E1318S_PHY_LED_TCR,
1182 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1183 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1184 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1185 if (err < 0)
1186 return err;
1187 }
1188
1189 return marvell_config_init(phydev);
1190}
1191
1192static int m88e1510_config_init(struct phy_device *phydev)
1193{
1194 static const struct {
1195 u16 reg17, reg16;
1196 } errata_vals[] = {
1197 { 0x214b, 0x2144 },
1198 { 0x0c28, 0x2146 },
1199 { 0xb233, 0x214d },
1200 { 0xcc0c, 0x2159 },
1201 };
1202 int err;
1203 int i;
1204
1205 /* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/
1206 * 88E1514 Rev A0, Errata Section 5.1:
1207 * If EEE is intended to be used, the following register writes
1208 * must be done once after every hardware reset.
1209 */
1210 err = marvell_set_page(phydev, 0x00FF);
1211 if (err < 0)
1212 return err;
1213
1214 for (i = 0; i < ARRAY_SIZE(errata_vals); ++i) {
1215 err = phy_write(phydev, 17, errata_vals[i].reg17);
1216 if (err)
1217 return err;
1218 err = phy_write(phydev, 16, errata_vals[i].reg16);
1219 if (err)
1220 return err;
1221 }
1222
1223 err = marvell_set_page(phydev, 0x00FB);
1224 if (err < 0)
1225 return err;
1226 err = phy_write(phydev, 07, 0xC00D);
1227 if (err < 0)
1228 return err;
1229 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1230 if (err < 0)
1231 return err;
1232
1233 /* SGMII-to-Copper mode initialization */
1234 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1235 /* Select page 18 */
1236 err = marvell_set_page(phydev, 18);
1237 if (err < 0)
1238 return err;
1239
1240 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1241 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1242 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1243 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1244 if (err < 0)
1245 return err;
1246
1247 /* PHY reset is necessary after changing MODE[2:0] */
1248 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
1249 MII_88E1510_GEN_CTRL_REG_1_RESET);
1250 if (err < 0)
1251 return err;
1252
1253 /* Reset page selection */
1254 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1255 if (err < 0)
1256 return err;
1257 }
1258 err = m88e1011_set_downshift(phydev, 3);
1259 if (err < 0)
1260 return err;
1261
1262 return m88e1318_config_init(phydev);
1263}
1264
1265static int m88e1118_config_aneg(struct phy_device *phydev)
1266{
1267 int err;
1268
1269 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1270 if (err < 0)
1271 return err;
1272
1273 err = genphy_config_aneg(phydev);
1274 if (err < 0)
1275 return err;
1276
1277 return genphy_soft_reset(phydev);
1278}
1279
1280static int m88e1118_config_init(struct phy_device *phydev)
1281{
1282 u16 leds;
1283 int err;
1284
1285 /* Enable 1000 Mbit */
1286 err = phy_write_paged(phydev, MII_MARVELL_MSCR_PAGE,
1287 MII_88E1121_PHY_MSCR_REG, 0x1070);
1288 if (err < 0)
1289 return err;
1290
1291 if (phy_interface_is_rgmii(phydev)) {
1292 err = m88e1121_config_aneg_rgmii_delays(phydev);
1293 if (err < 0)
1294 return err;
1295 }
1296
1297 /* Adjust LED Control */
1298 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1299 leds = 0x1100;
1300 else
1301 leds = 0x021e;
1302
1303 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, 0x10, leds);
1304 if (err < 0)
1305 return err;
1306
1307 err = marvell_of_reg_init(phydev);
1308 if (err < 0)
1309 return err;
1310
1311 /* Reset page register */
1312 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1313 if (err < 0)
1314 return err;
1315
1316 return genphy_soft_reset(phydev);
1317}
1318
1319static int m88e1149_config_init(struct phy_device *phydev)
1320{
1321 int err;
1322
1323 /* Change address */
1324 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1325 if (err < 0)
1326 return err;
1327
1328 /* Enable 1000 Mbit */
1329 err = phy_write(phydev, 0x15, 0x1048);
1330 if (err < 0)
1331 return err;
1332
1333 err = marvell_of_reg_init(phydev);
1334 if (err < 0)
1335 return err;
1336
1337 /* Reset address */
1338 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1339 if (err < 0)
1340 return err;
1341
1342 return genphy_soft_reset(phydev);
1343}
1344
1345static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1346{
1347 int err;
1348
1349 err = m88e1111_config_init_rgmii_delays(phydev);
1350 if (err < 0)
1351 return err;
1352
1353 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1354 err = phy_write(phydev, 0x1d, 0x0012);
1355 if (err < 0)
1356 return err;
1357
1358 err = phy_modify(phydev, 0x1e, 0x0fc0,
1359 2 << 9 | /* 36 ohm */
1360 2 << 6); /* 39 ohm */
1361 if (err < 0)
1362 return err;
1363
1364 err = phy_write(phydev, 0x1d, 0x3);
1365 if (err < 0)
1366 return err;
1367
1368 err = phy_write(phydev, 0x1e, 0x8000);
1369 }
1370 return err;
1371}
1372
1373static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1374{
1375 return m88e1111_config_init_hwcfg_mode(
1376 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1377 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1378}
1379
1380static int m88e1145_config_init(struct phy_device *phydev)
1381{
1382 int err;
1383
1384 /* Take care of errata E0 & E1 */
1385 err = phy_write(phydev, 0x1d, 0x001b);
1386 if (err < 0)
1387 return err;
1388
1389 err = phy_write(phydev, 0x1e, 0x418f);
1390 if (err < 0)
1391 return err;
1392
1393 err = phy_write(phydev, 0x1d, 0x0016);
1394 if (err < 0)
1395 return err;
1396
1397 err = phy_write(phydev, 0x1e, 0xa2da);
1398 if (err < 0)
1399 return err;
1400
1401 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1402 err = m88e1145_config_init_rgmii(phydev);
1403 if (err < 0)
1404 return err;
1405 }
1406
1407 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1408 err = m88e1145_config_init_sgmii(phydev);
1409 if (err < 0)
1410 return err;
1411 }
1412 err = m88e1111_set_downshift(phydev, 3);
1413 if (err < 0)
1414 return err;
1415
1416 err = marvell_of_reg_init(phydev);
1417 if (err < 0)
1418 return err;
1419
1420 return 0;
1421}
1422
1423static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1424{
1425 int val;
1426
1427 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1428 if (val < 0)
1429 return val;
1430
1431 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1432 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1433 return 0;
1434 }
1435
1436 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1437
1438 switch (val) {
1439 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1440 *msecs = 0;
1441 break;
1442 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1443 *msecs = 10;
1444 break;
1445 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1446 *msecs = 20;
1447 break;
1448 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1449 *msecs = 40;
1450 break;
1451 default:
1452 return -EINVAL;
1453 }
1454
1455 return 0;
1456}
1457
1458static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1459{
1460 struct ethtool_eee eee;
1461 int val, ret;
1462
1463 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1464 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1465 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1466
1467 /* According to the Marvell data sheet EEE must be disabled for
1468 * Fast Link Down detection to work properly
1469 */
1470 ret = phy_ethtool_get_eee(phydev, &eee);
1471 if (!ret && eee.eee_enabled) {
1472 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1473 return -EBUSY;
1474 }
1475
1476 if (*msecs <= 5)
1477 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1478 else if (*msecs <= 15)
1479 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1480 else if (*msecs <= 30)
1481 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1482 else
1483 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1484
1485 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1486
1487 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1488 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1489 if (ret)
1490 return ret;
1491
1492 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1493 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1494}
1495
1496static int m88e1540_get_tunable(struct phy_device *phydev,
1497 struct ethtool_tunable *tuna, void *data)
1498{
1499 switch (tuna->id) {
1500 case ETHTOOL_PHY_FAST_LINK_DOWN:
1501 return m88e1540_get_fld(phydev, data);
1502 case ETHTOOL_PHY_DOWNSHIFT:
1503 return m88e1011_get_downshift(phydev, data);
1504 default:
1505 return -EOPNOTSUPP;
1506 }
1507}
1508
1509static int m88e1540_set_tunable(struct phy_device *phydev,
1510 struct ethtool_tunable *tuna, const void *data)
1511{
1512 switch (tuna->id) {
1513 case ETHTOOL_PHY_FAST_LINK_DOWN:
1514 return m88e1540_set_fld(phydev, data);
1515 case ETHTOOL_PHY_DOWNSHIFT:
1516 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1517 default:
1518 return -EOPNOTSUPP;
1519 }
1520}
1521
1522/* The VOD can be out of specification on link up. Poke an
1523 * undocumented register, in an undocumented page, with a magic value
1524 * to fix this.
1525 */
1526static int m88e6390_errata(struct phy_device *phydev)
1527{
1528 int err;
1529
1530 err = phy_write(phydev, MII_BMCR,
1531 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1532 if (err)
1533 return err;
1534
1535 usleep_range(300, 400);
1536
1537 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1538 if (err)
1539 return err;
1540
1541 return genphy_soft_reset(phydev);
1542}
1543
1544static int m88e6390_config_aneg(struct phy_device *phydev)
1545{
1546 int err;
1547
1548 err = m88e6390_errata(phydev);
1549 if (err)
1550 return err;
1551
1552 return m88e1510_config_aneg(phydev);
1553}
1554
1555/**
1556 * fiber_lpa_mod_linkmode_lpa_t
1557 * @advertising: the linkmode advertisement settings
1558 * @lpa: value of the MII_LPA register for fiber link
1559 *
1560 * A small helper function that translates MII_LPA bits to linkmode LP
1561 * advertisement settings. Other bits in advertising are left
1562 * unchanged.
1563 */
1564static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1565{
1566 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1567 advertising, lpa & LPA_1000XHALF);
1568
1569 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1570 advertising, lpa & LPA_1000XFULL);
1571}
1572
1573static int marvell_read_status_page_an(struct phy_device *phydev,
1574 int fiber, int status)
1575{
1576 int lpa;
1577 int err;
1578
1579 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1580 phydev->link = 0;
1581 return 0;
1582 }
1583
1584 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1585 phydev->duplex = DUPLEX_FULL;
1586 else
1587 phydev->duplex = DUPLEX_HALF;
1588
1589 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1590 case MII_M1011_PHY_STATUS_1000:
1591 phydev->speed = SPEED_1000;
1592 break;
1593
1594 case MII_M1011_PHY_STATUS_100:
1595 phydev->speed = SPEED_100;
1596 break;
1597
1598 default:
1599 phydev->speed = SPEED_10;
1600 break;
1601 }
1602
1603 if (!fiber) {
1604 err = genphy_read_lpa(phydev);
1605 if (err < 0)
1606 return err;
1607
1608 phy_resolve_aneg_pause(phydev);
1609 } else {
1610 lpa = phy_read(phydev, MII_LPA);
1611 if (lpa < 0)
1612 return lpa;
1613
1614 /* The fiber link is only 1000M capable */
1615 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1616
1617 if (phydev->duplex == DUPLEX_FULL) {
1618 if (!(lpa & LPA_PAUSE_FIBER)) {
1619 phydev->pause = 0;
1620 phydev->asym_pause = 0;
1621 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1622 phydev->pause = 1;
1623 phydev->asym_pause = 1;
1624 } else {
1625 phydev->pause = 1;
1626 phydev->asym_pause = 0;
1627 }
1628 }
1629 }
1630
1631 return 0;
1632}
1633
1634/* marvell_read_status_page
1635 *
1636 * Description:
1637 * Check the link, then figure out the current state
1638 * by comparing what we advertise with what the link partner
1639 * advertises. Start by checking the gigabit possibilities,
1640 * then move on to 10/100.
1641 */
1642static int marvell_read_status_page(struct phy_device *phydev, int page)
1643{
1644 int status;
1645 int fiber;
1646 int err;
1647
1648 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1649 if (status < 0)
1650 return status;
1651
1652 /* Use the generic register for copper link status,
1653 * and the PHY status register for fiber link status.
1654 */
1655 if (page == MII_MARVELL_FIBER_PAGE) {
1656 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1657 } else {
1658 err = genphy_update_link(phydev);
1659 if (err)
1660 return err;
1661 }
1662
1663 if (page == MII_MARVELL_FIBER_PAGE)
1664 fiber = 1;
1665 else
1666 fiber = 0;
1667
1668 linkmode_zero(phydev->lp_advertising);
1669 phydev->pause = 0;
1670 phydev->asym_pause = 0;
1671 phydev->speed = SPEED_UNKNOWN;
1672 phydev->duplex = DUPLEX_UNKNOWN;
1673 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1674
1675 if (phydev->autoneg == AUTONEG_ENABLE)
1676 err = marvell_read_status_page_an(phydev, fiber, status);
1677 else
1678 err = genphy_read_status_fixed(phydev);
1679
1680 return err;
1681}
1682
1683/* marvell_read_status
1684 *
1685 * Some Marvell's phys have two modes: fiber and copper.
1686 * Both need status checked.
1687 * Description:
1688 * First, check the fiber link and status.
1689 * If the fiber link is down, check the copper link and status which
1690 * will be the default value if both link are down.
1691 */
1692static int marvell_read_status(struct phy_device *phydev)
1693{
1694 int err;
1695
1696 /* Check the fiber mode first */
1697 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1698 phydev->supported) &&
1699 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1700 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1701 if (err < 0)
1702 goto error;
1703
1704 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1705 if (err < 0)
1706 goto error;
1707
1708 /* If the fiber link is up, it is the selected and
1709 * used link. In this case, we need to stay in the
1710 * fiber page. Please to be careful about that, avoid
1711 * to restore Copper page in other functions which
1712 * could break the behaviour for some fiber phy like
1713 * 88E1512.
1714 */
1715 if (phydev->link)
1716 return 0;
1717
1718 /* If fiber link is down, check and save copper mode state */
1719 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1720 if (err < 0)
1721 goto error;
1722 }
1723
1724 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1725
1726error:
1727 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1728 return err;
1729}
1730
1731/* marvell_suspend
1732 *
1733 * Some Marvell's phys have two modes: fiber and copper.
1734 * Both need to be suspended
1735 */
1736static int marvell_suspend(struct phy_device *phydev)
1737{
1738 int err;
1739
1740 /* Suspend the fiber mode first */
1741 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1742 phydev->supported)) {
1743 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1744 if (err < 0)
1745 goto error;
1746
1747 /* With the page set, use the generic suspend */
1748 err = genphy_suspend(phydev);
1749 if (err < 0)
1750 goto error;
1751
1752 /* Then, the copper link */
1753 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1754 if (err < 0)
1755 goto error;
1756 }
1757
1758 /* With the page set, use the generic suspend */
1759 return genphy_suspend(phydev);
1760
1761error:
1762 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1763 return err;
1764}
1765
1766/* marvell_resume
1767 *
1768 * Some Marvell's phys have two modes: fiber and copper.
1769 * Both need to be resumed
1770 */
1771static int marvell_resume(struct phy_device *phydev)
1772{
1773 int err;
1774
1775 /* Resume the fiber mode first */
1776 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1777 phydev->supported)) {
1778 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1779 if (err < 0)
1780 goto error;
1781
1782 /* With the page set, use the generic resume */
1783 err = genphy_resume(phydev);
1784 if (err < 0)
1785 goto error;
1786
1787 /* Then, the copper link */
1788 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1789 if (err < 0)
1790 goto error;
1791 }
1792
1793 /* With the page set, use the generic resume */
1794 return genphy_resume(phydev);
1795
1796error:
1797 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1798 return err;
1799}
1800
1801static int marvell_aneg_done(struct phy_device *phydev)
1802{
1803 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1804
1805 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1806}
1807
1808static void m88e1318_get_wol(struct phy_device *phydev,
1809 struct ethtool_wolinfo *wol)
1810{
1811 int ret;
1812
1813 wol->supported = WAKE_MAGIC | WAKE_PHY;
1814 wol->wolopts = 0;
1815
1816 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1817 MII_88E1318S_PHY_WOL_CTRL);
1818 if (ret < 0)
1819 return;
1820
1821 if (ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1822 wol->wolopts |= WAKE_MAGIC;
1823
1824 if (ret & MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE)
1825 wol->wolopts |= WAKE_PHY;
1826}
1827
1828static int m88e1318_set_wol(struct phy_device *phydev,
1829 struct ethtool_wolinfo *wol)
1830{
1831 int err = 0, oldpage;
1832
1833 oldpage = phy_save_page(phydev);
1834 if (oldpage < 0)
1835 goto error;
1836
1837 if (wol->wolopts & (WAKE_MAGIC | WAKE_PHY)) {
1838 /* Explicitly switch to page 0x00, just to be sure */
1839 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1840 if (err < 0)
1841 goto error;
1842
1843 /* If WOL event happened once, the LED[2] interrupt pin
1844 * will not be cleared unless we reading the interrupt status
1845 * register. If interrupts are in use, the normal interrupt
1846 * handling will clear the WOL event. Clear the WOL event
1847 * before enabling it if !phy_interrupt_is_valid()
1848 */
1849 if (!phy_interrupt_is_valid(phydev))
1850 __phy_read(phydev, MII_M1011_IEVENT);
1851
1852 /* Enable the WOL interrupt */
1853 err = __phy_set_bits(phydev, MII_88E1318S_PHY_CSIER,
1854 MII_88E1318S_PHY_CSIER_WOL_EIE);
1855 if (err < 0)
1856 goto error;
1857
1858 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1859 if (err < 0)
1860 goto error;
1861
1862 /* Setup LED[2] as interrupt pin (active low) */
1863 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1864 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1865 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1866 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1867 if (err < 0)
1868 goto error;
1869 }
1870
1871 if (wol->wolopts & WAKE_MAGIC) {
1872 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1873 if (err < 0)
1874 goto error;
1875
1876 /* Store the device address for the magic packet */
1877 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1878 ((phydev->attached_dev->dev_addr[5] << 8) |
1879 phydev->attached_dev->dev_addr[4]));
1880 if (err < 0)
1881 goto error;
1882 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1883 ((phydev->attached_dev->dev_addr[3] << 8) |
1884 phydev->attached_dev->dev_addr[2]));
1885 if (err < 0)
1886 goto error;
1887 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1888 ((phydev->attached_dev->dev_addr[1] << 8) |
1889 phydev->attached_dev->dev_addr[0]));
1890 if (err < 0)
1891 goto error;
1892
1893 /* Clear WOL status and enable magic packet matching */
1894 err = __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
1895 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1896 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1897 if (err < 0)
1898 goto error;
1899 } else {
1900 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1901 if (err < 0)
1902 goto error;
1903
1904 /* Clear WOL status and disable magic packet matching */
1905 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1906 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1907 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1908 if (err < 0)
1909 goto error;
1910 }
1911
1912 if (wol->wolopts & WAKE_PHY) {
1913 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1914 if (err < 0)
1915 goto error;
1916
1917 /* Clear WOL status and enable link up event */
1918 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL, 0,
1919 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1920 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE);
1921 if (err < 0)
1922 goto error;
1923 } else {
1924 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1925 if (err < 0)
1926 goto error;
1927
1928 /* Clear WOL status and disable link up event */
1929 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1930 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE,
1931 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1932 if (err < 0)
1933 goto error;
1934 }
1935
1936error:
1937 return phy_restore_page(phydev, oldpage, err);
1938}
1939
1940static int marvell_get_sset_count(struct phy_device *phydev)
1941{
1942 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1943 phydev->supported))
1944 return ARRAY_SIZE(marvell_hw_stats);
1945 else
1946 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1947}
1948
1949static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1950{
1951 int count = marvell_get_sset_count(phydev);
1952 int i;
1953
1954 for (i = 0; i < count; i++) {
1955 strscpy(data + i * ETH_GSTRING_LEN,
1956 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1957 }
1958}
1959
1960static u64 marvell_get_stat(struct phy_device *phydev, int i)
1961{
1962 struct marvell_hw_stat stat = marvell_hw_stats[i];
1963 struct marvell_priv *priv = phydev->priv;
1964 int val;
1965 u64 ret;
1966
1967 val = phy_read_paged(phydev, stat.page, stat.reg);
1968 if (val < 0) {
1969 ret = U64_MAX;
1970 } else {
1971 val = val & ((1 << stat.bits) - 1);
1972 priv->stats[i] += val;
1973 ret = priv->stats[i];
1974 }
1975
1976 return ret;
1977}
1978
1979static void marvell_get_stats(struct phy_device *phydev,
1980 struct ethtool_stats *stats, u64 *data)
1981{
1982 int count = marvell_get_sset_count(phydev);
1983 int i;
1984
1985 for (i = 0; i < count; i++)
1986 data[i] = marvell_get_stat(phydev, i);
1987}
1988
1989static int m88e1510_loopback(struct phy_device *phydev, bool enable)
1990{
1991 int err;
1992
1993 if (enable) {
1994 u16 bmcr_ctl, mscr2_ctl = 0;
1995
1996 bmcr_ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
1997
1998 err = phy_write(phydev, MII_BMCR, bmcr_ctl);
1999 if (err < 0)
2000 return err;
2001
2002 if (phydev->speed == SPEED_1000)
2003 mscr2_ctl = BMCR_SPEED1000;
2004 else if (phydev->speed == SPEED_100)
2005 mscr2_ctl = BMCR_SPEED100;
2006
2007 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
2008 MII_88E1510_MSCR_2, BMCR_SPEED1000 |
2009 BMCR_SPEED100, mscr2_ctl);
2010 if (err < 0)
2011 return err;
2012
2013 /* Need soft reset to have speed configuration takes effect */
2014 err = genphy_soft_reset(phydev);
2015 if (err < 0)
2016 return err;
2017
2018 err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
2019 BMCR_LOOPBACK);
2020
2021 if (!err) {
2022 /* It takes some time for PHY device to switch
2023 * into/out-of loopback mode.
2024 */
2025 msleep(1000);
2026 }
2027 return err;
2028 } else {
2029 err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
2030 if (err < 0)
2031 return err;
2032
2033 return phy_config_aneg(phydev);
2034 }
2035}
2036
2037static int marvell_vct5_wait_complete(struct phy_device *phydev)
2038{
2039 int i;
2040 int val;
2041
2042 for (i = 0; i < 32; i++) {
2043 val = __phy_read(phydev, MII_VCT5_CTRL);
2044 if (val < 0)
2045 return val;
2046
2047 if (val & MII_VCT5_CTRL_COMPLETE)
2048 return 0;
2049 }
2050
2051 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
2052 return -ETIMEDOUT;
2053}
2054
2055static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
2056{
2057 int amplitude;
2058 int val;
2059 int reg;
2060
2061 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
2062 val = __phy_read(phydev, reg);
2063
2064 if (val < 0)
2065 return 0;
2066
2067 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
2068 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
2069
2070 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
2071 amplitude = -amplitude;
2072
2073 return 1000 * amplitude / 128;
2074}
2075
2076static u32 marvell_vct5_distance2cm(int distance)
2077{
2078 return distance * 805 / 10;
2079}
2080
2081static u32 marvell_vct5_cm2distance(int cm)
2082{
2083 return cm * 10 / 805;
2084}
2085
2086static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
2087 int distance, int pair)
2088{
2089 u16 reg;
2090 int err;
2091 int mV;
2092 int i;
2093
2094 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
2095 distance);
2096 if (err)
2097 return err;
2098
2099 reg = MII_VCT5_CTRL_ENABLE |
2100 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2101 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2102 MII_VCT5_CTRL_SAMPLE_POINT |
2103 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
2104 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
2105 if (err)
2106 return err;
2107
2108 err = marvell_vct5_wait_complete(phydev);
2109 if (err)
2110 return err;
2111
2112 for (i = 0; i < 4; i++) {
2113 if (pair != PHY_PAIR_ALL && i != pair)
2114 continue;
2115
2116 mV = marvell_vct5_amplitude(phydev, i);
2117 ethnl_cable_test_amplitude(phydev, i, mV);
2118 }
2119
2120 return 0;
2121}
2122
2123static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
2124{
2125 struct marvell_priv *priv = phydev->priv;
2126 int distance;
2127 u16 width;
2128 int page;
2129 int err;
2130 u16 reg;
2131
2132 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
2133 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
2134 else
2135 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2136
2137 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2138 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2139 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2140
2141 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2142 MII_VCT5_TX_PULSE_CTRL, reg);
2143 if (err)
2144 return err;
2145
2146 /* Reading the TDR data is very MDIO heavy. We need to optimize
2147 * access to keep the time to a minimum. So lock the bus once,
2148 * and don't release it until complete. We can then avoid having
2149 * to change the page for every access, greatly speeding things
2150 * up.
2151 */
2152 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
2153 if (page < 0)
2154 goto restore_page;
2155
2156 for (distance = priv->first;
2157 distance <= priv->last;
2158 distance += priv->step) {
2159 err = marvell_vct5_amplitude_distance(phydev, distance,
2160 priv->pair);
2161 if (err)
2162 goto restore_page;
2163
2164 if (distance > TDR_SHORT_CABLE_LENGTH &&
2165 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
2166 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2167 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2168 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2169 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2170 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
2171 if (err)
2172 goto restore_page;
2173 }
2174 }
2175
2176restore_page:
2177 return phy_restore_page(phydev, page, err);
2178}
2179
2180static int marvell_cable_test_start_common(struct phy_device *phydev)
2181{
2182 int bmcr, bmsr, ret;
2183
2184 /* If auto-negotiation is enabled, but not complete, the cable
2185 * test never completes. So disable auto-neg.
2186 */
2187 bmcr = phy_read(phydev, MII_BMCR);
2188 if (bmcr < 0)
2189 return bmcr;
2190
2191 bmsr = phy_read(phydev, MII_BMSR);
2192
2193 if (bmsr < 0)
2194 return bmsr;
2195
2196 if (bmcr & BMCR_ANENABLE) {
2197 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
2198 if (ret < 0)
2199 return ret;
2200 ret = genphy_soft_reset(phydev);
2201 if (ret < 0)
2202 return ret;
2203 }
2204
2205 /* If the link is up, allow it some time to go down */
2206 if (bmsr & BMSR_LSTATUS)
2207 msleep(1500);
2208
2209 return 0;
2210}
2211
2212static int marvell_vct7_cable_test_start(struct phy_device *phydev)
2213{
2214 struct marvell_priv *priv = phydev->priv;
2215 int ret;
2216
2217 ret = marvell_cable_test_start_common(phydev);
2218 if (ret)
2219 return ret;
2220
2221 priv->cable_test_tdr = false;
2222
2223 /* Reset the VCT5 API control to defaults, otherwise
2224 * VCT7 does not work correctly.
2225 */
2226 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2227 MII_VCT5_CTRL,
2228 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2229 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2230 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
2231 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
2232 if (ret)
2233 return ret;
2234
2235 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2236 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
2237 if (ret)
2238 return ret;
2239
2240 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2241 MII_VCT7_CTRL,
2242 MII_VCT7_CTRL_RUN_NOW |
2243 MII_VCT7_CTRL_CENTIMETERS);
2244}
2245
2246static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
2247 const struct phy_tdr_config *cfg)
2248{
2249 struct marvell_priv *priv = phydev->priv;
2250 int ret;
2251
2252 priv->cable_test_tdr = true;
2253 priv->first = marvell_vct5_cm2distance(cfg->first);
2254 priv->last = marvell_vct5_cm2distance(cfg->last);
2255 priv->step = marvell_vct5_cm2distance(cfg->step);
2256 priv->pair = cfg->pair;
2257
2258 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2259 return -EINVAL;
2260
2261 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2262 return -EINVAL;
2263
2264 /* Disable VCT7 */
2265 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2266 MII_VCT7_CTRL, 0);
2267 if (ret)
2268 return ret;
2269
2270 ret = marvell_cable_test_start_common(phydev);
2271 if (ret)
2272 return ret;
2273
2274 ret = ethnl_cable_test_pulse(phydev, 1000);
2275 if (ret)
2276 return ret;
2277
2278 return ethnl_cable_test_step(phydev,
2279 marvell_vct5_distance2cm(priv->first),
2280 marvell_vct5_distance2cm(priv->last),
2281 marvell_vct5_distance2cm(priv->step));
2282}
2283
2284static int marvell_vct7_distance_to_length(int distance, bool meter)
2285{
2286 if (meter)
2287 distance *= 100;
2288
2289 return distance;
2290}
2291
2292static bool marvell_vct7_distance_valid(int result)
2293{
2294 switch (result) {
2295 case MII_VCT7_RESULTS_OPEN:
2296 case MII_VCT7_RESULTS_SAME_SHORT:
2297 case MII_VCT7_RESULTS_CROSS_SHORT:
2298 return true;
2299 }
2300 return false;
2301}
2302
2303static int marvell_vct7_report_length(struct phy_device *phydev,
2304 int pair, bool meter)
2305{
2306 int length;
2307 int ret;
2308
2309 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2310 MII_VCT7_PAIR_0_DISTANCE + pair);
2311 if (ret < 0)
2312 return ret;
2313
2314 length = marvell_vct7_distance_to_length(ret, meter);
2315
2316 ethnl_cable_test_fault_length(phydev, pair, length);
2317
2318 return 0;
2319}
2320
2321static int marvell_vct7_cable_test_report_trans(int result)
2322{
2323 switch (result) {
2324 case MII_VCT7_RESULTS_OK:
2325 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2326 case MII_VCT7_RESULTS_OPEN:
2327 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2328 case MII_VCT7_RESULTS_SAME_SHORT:
2329 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2330 case MII_VCT7_RESULTS_CROSS_SHORT:
2331 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2332 default:
2333 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2334 }
2335}
2336
2337static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2338{
2339 int pair0, pair1, pair2, pair3;
2340 bool meter;
2341 int ret;
2342
2343 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2344 MII_VCT7_RESULTS);
2345 if (ret < 0)
2346 return ret;
2347
2348 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2349 MII_VCT7_RESULTS_PAIR3_SHIFT;
2350 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2351 MII_VCT7_RESULTS_PAIR2_SHIFT;
2352 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2353 MII_VCT7_RESULTS_PAIR1_SHIFT;
2354 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2355 MII_VCT7_RESULTS_PAIR0_SHIFT;
2356
2357 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2358 marvell_vct7_cable_test_report_trans(pair0));
2359 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2360 marvell_vct7_cable_test_report_trans(pair1));
2361 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2362 marvell_vct7_cable_test_report_trans(pair2));
2363 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2364 marvell_vct7_cable_test_report_trans(pair3));
2365
2366 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2367 if (ret < 0)
2368 return ret;
2369
2370 meter = ret & MII_VCT7_CTRL_METERS;
2371
2372 if (marvell_vct7_distance_valid(pair0))
2373 marvell_vct7_report_length(phydev, 0, meter);
2374 if (marvell_vct7_distance_valid(pair1))
2375 marvell_vct7_report_length(phydev, 1, meter);
2376 if (marvell_vct7_distance_valid(pair2))
2377 marvell_vct7_report_length(phydev, 2, meter);
2378 if (marvell_vct7_distance_valid(pair3))
2379 marvell_vct7_report_length(phydev, 3, meter);
2380
2381 return 0;
2382}
2383
2384static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2385 bool *finished)
2386{
2387 struct marvell_priv *priv = phydev->priv;
2388 int ret;
2389
2390 if (priv->cable_test_tdr) {
2391 ret = marvell_vct5_amplitude_graph(phydev);
2392 *finished = true;
2393 return ret;
2394 }
2395
2396 *finished = false;
2397
2398 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2399 MII_VCT7_CTRL);
2400
2401 if (ret < 0)
2402 return ret;
2403
2404 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2405 *finished = true;
2406
2407 return marvell_vct7_cable_test_report(phydev);
2408 }
2409
2410 return 0;
2411}
2412
2413#ifdef CONFIG_HWMON
2414struct marvell_hwmon_ops {
2415 int (*config)(struct phy_device *phydev);
2416 int (*get_temp)(struct phy_device *phydev, long *temp);
2417 int (*get_temp_critical)(struct phy_device *phydev, long *temp);
2418 int (*set_temp_critical)(struct phy_device *phydev, long temp);
2419 int (*get_temp_alarm)(struct phy_device *phydev, long *alarm);
2420};
2421
2422static const struct marvell_hwmon_ops *
2423to_marvell_hwmon_ops(const struct phy_device *phydev)
2424{
2425 return phydev->drv->driver_data;
2426}
2427
2428static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2429{
2430 int oldpage;
2431 int ret = 0;
2432 int val;
2433
2434 *temp = 0;
2435
2436 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2437 if (oldpage < 0)
2438 goto error;
2439
2440 /* Enable temperature sensor */
2441 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2442 if (ret < 0)
2443 goto error;
2444
2445 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2446 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2447 if (ret < 0)
2448 goto error;
2449
2450 /* Wait for temperature to stabilize */
2451 usleep_range(10000, 12000);
2452
2453 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2454 if (val < 0) {
2455 ret = val;
2456 goto error;
2457 }
2458
2459 /* Disable temperature sensor */
2460 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2461 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2462 if (ret < 0)
2463 goto error;
2464
2465 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2466
2467error:
2468 return phy_restore_page(phydev, oldpage, ret);
2469}
2470
2471static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2472{
2473 int ret;
2474
2475 *temp = 0;
2476
2477 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2478 MII_88E1510_TEMP_SENSOR);
2479 if (ret < 0)
2480 return ret;
2481
2482 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2483
2484 return 0;
2485}
2486
2487static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2488{
2489 int ret;
2490
2491 *temp = 0;
2492
2493 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2494 MII_88E1121_MISC_TEST);
2495 if (ret < 0)
2496 return ret;
2497
2498 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2499 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2500 /* convert to mC */
2501 *temp *= 1000;
2502
2503 return 0;
2504}
2505
2506static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2507{
2508 temp = temp / 1000;
2509 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2510
2511 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2512 MII_88E1121_MISC_TEST,
2513 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2514 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2515}
2516
2517static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2518{
2519 int ret;
2520
2521 *alarm = false;
2522
2523 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2524 MII_88E1121_MISC_TEST);
2525 if (ret < 0)
2526 return ret;
2527
2528 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2529
2530 return 0;
2531}
2532
2533static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2534{
2535 int sum = 0;
2536 int oldpage;
2537 int ret = 0;
2538 int i;
2539
2540 *temp = 0;
2541
2542 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2543 if (oldpage < 0)
2544 goto error;
2545
2546 /* Enable temperature sensor */
2547 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2548 if (ret < 0)
2549 goto error;
2550
2551 ret &= ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2552 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S;
2553
2554 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2555 if (ret < 0)
2556 goto error;
2557
2558 /* Wait for temperature to stabilize */
2559 usleep_range(10000, 12000);
2560
2561 /* Reading the temperature sense has an errata. You need to read
2562 * a number of times and take an average.
2563 */
2564 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2565 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2566 if (ret < 0)
2567 goto error;
2568 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2569 }
2570
2571 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2572 *temp = (sum - 75) * 1000;
2573
2574 /* Disable temperature sensor */
2575 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2576 if (ret < 0)
2577 goto error;
2578
2579 ret = ret & ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2580 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE;
2581
2582 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2583
2584error:
2585 phy_restore_page(phydev, oldpage, ret);
2586
2587 return ret;
2588}
2589
2590static int m88e6393_get_temp(struct phy_device *phydev, long *temp)
2591{
2592 int err;
2593
2594 err = m88e1510_get_temp(phydev, temp);
2595
2596 /* 88E1510 measures T + 25, while the PHY on 88E6393X switch
2597 * T + 75, so we have to subtract another 50
2598 */
2599 *temp -= 50000;
2600
2601 return err;
2602}
2603
2604static int m88e6393_get_temp_critical(struct phy_device *phydev, long *temp)
2605{
2606 int ret;
2607
2608 *temp = 0;
2609
2610 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2611 MII_88E6390_TEMP_SENSOR);
2612 if (ret < 0)
2613 return ret;
2614
2615 *temp = (((ret & MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK) >>
2616 MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT) - 75) * 1000;
2617
2618 return 0;
2619}
2620
2621static int m88e6393_set_temp_critical(struct phy_device *phydev, long temp)
2622{
2623 temp = (temp / 1000) + 75;
2624
2625 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2626 MII_88E6390_TEMP_SENSOR,
2627 MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK,
2628 temp << MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT);
2629}
2630
2631static int m88e6393_hwmon_config(struct phy_device *phydev)
2632{
2633 int err;
2634
2635 err = m88e6393_set_temp_critical(phydev, 100000);
2636 if (err)
2637 return err;
2638
2639 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2640 MII_88E6390_MISC_TEST,
2641 MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK |
2642 MII_88E6393_MISC_TEST_SAMPLES_MASK |
2643 MII_88E6393_MISC_TEST_RATE_MASK,
2644 MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE |
2645 MII_88E6393_MISC_TEST_SAMPLES_2048 |
2646 MII_88E6393_MISC_TEST_RATE_2_3MS);
2647}
2648
2649static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
2650 u32 attr, int channel, long *temp)
2651{
2652 struct phy_device *phydev = dev_get_drvdata(dev);
2653 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2654 int err = -EOPNOTSUPP;
2655
2656 switch (attr) {
2657 case hwmon_temp_input:
2658 if (ops->get_temp)
2659 err = ops->get_temp(phydev, temp);
2660 break;
2661 case hwmon_temp_crit:
2662 if (ops->get_temp_critical)
2663 err = ops->get_temp_critical(phydev, temp);
2664 break;
2665 case hwmon_temp_max_alarm:
2666 if (ops->get_temp_alarm)
2667 err = ops->get_temp_alarm(phydev, temp);
2668 break;
2669 }
2670
2671 return err;
2672}
2673
2674static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
2675 u32 attr, int channel, long temp)
2676{
2677 struct phy_device *phydev = dev_get_drvdata(dev);
2678 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2679 int err = -EOPNOTSUPP;
2680
2681 switch (attr) {
2682 case hwmon_temp_crit:
2683 if (ops->set_temp_critical)
2684 err = ops->set_temp_critical(phydev, temp);
2685 break;
2686 }
2687
2688 return err;
2689}
2690
2691static umode_t marvell_hwmon_is_visible(const void *data,
2692 enum hwmon_sensor_types type,
2693 u32 attr, int channel)
2694{
2695 const struct phy_device *phydev = data;
2696 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2697
2698 if (type != hwmon_temp)
2699 return 0;
2700
2701 switch (attr) {
2702 case hwmon_temp_input:
2703 return ops->get_temp ? 0444 : 0;
2704 case hwmon_temp_max_alarm:
2705 return ops->get_temp_alarm ? 0444 : 0;
2706 case hwmon_temp_crit:
2707 return (ops->get_temp_critical ? 0444 : 0) |
2708 (ops->set_temp_critical ? 0200 : 0);
2709 default:
2710 return 0;
2711 }
2712}
2713
2714static u32 marvell_hwmon_chip_config[] = {
2715 HWMON_C_REGISTER_TZ,
2716 0
2717};
2718
2719static const struct hwmon_channel_info marvell_hwmon_chip = {
2720 .type = hwmon_chip,
2721 .config = marvell_hwmon_chip_config,
2722};
2723
2724/* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not
2725 * defined for all PHYs, because the hwmon code checks whether the attributes
2726 * exists via the .is_visible method
2727 */
2728static u32 marvell_hwmon_temp_config[] = {
2729 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2730 0
2731};
2732
2733static const struct hwmon_channel_info marvell_hwmon_temp = {
2734 .type = hwmon_temp,
2735 .config = marvell_hwmon_temp_config,
2736};
2737
2738static const struct hwmon_channel_info *marvell_hwmon_info[] = {
2739 &marvell_hwmon_chip,
2740 &marvell_hwmon_temp,
2741 NULL
2742};
2743
2744static const struct hwmon_ops marvell_hwmon_hwmon_ops = {
2745 .is_visible = marvell_hwmon_is_visible,
2746 .read = marvell_hwmon_read,
2747 .write = marvell_hwmon_write,
2748};
2749
2750static const struct hwmon_chip_info marvell_hwmon_chip_info = {
2751 .ops = &marvell_hwmon_hwmon_ops,
2752 .info = marvell_hwmon_info,
2753};
2754
2755static int marvell_hwmon_name(struct phy_device *phydev)
2756{
2757 struct marvell_priv *priv = phydev->priv;
2758 struct device *dev = &phydev->mdio.dev;
2759 const char *devname = dev_name(dev);
2760 size_t len = strlen(devname);
2761 int i, j;
2762
2763 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2764 if (!priv->hwmon_name)
2765 return -ENOMEM;
2766
2767 for (i = j = 0; i < len && devname[i]; i++) {
2768 if (isalnum(devname[i]))
2769 priv->hwmon_name[j++] = devname[i];
2770 }
2771
2772 return 0;
2773}
2774
2775static int marvell_hwmon_probe(struct phy_device *phydev)
2776{
2777 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2778 struct marvell_priv *priv = phydev->priv;
2779 struct device *dev = &phydev->mdio.dev;
2780 int err;
2781
2782 if (!ops)
2783 return 0;
2784
2785 err = marvell_hwmon_name(phydev);
2786 if (err)
2787 return err;
2788
2789 priv->hwmon_dev = devm_hwmon_device_register_with_info(
2790 dev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL);
2791 if (IS_ERR(priv->hwmon_dev))
2792 return PTR_ERR(priv->hwmon_dev);
2793
2794 if (ops->config)
2795 err = ops->config(phydev);
2796
2797 return err;
2798}
2799
2800static const struct marvell_hwmon_ops m88e1121_hwmon_ops = {
2801 .get_temp = m88e1121_get_temp,
2802};
2803
2804static const struct marvell_hwmon_ops m88e1510_hwmon_ops = {
2805 .get_temp = m88e1510_get_temp,
2806 .get_temp_critical = m88e1510_get_temp_critical,
2807 .set_temp_critical = m88e1510_set_temp_critical,
2808 .get_temp_alarm = m88e1510_get_temp_alarm,
2809};
2810
2811static const struct marvell_hwmon_ops m88e6390_hwmon_ops = {
2812 .get_temp = m88e6390_get_temp,
2813};
2814
2815static const struct marvell_hwmon_ops m88e6393_hwmon_ops = {
2816 .config = m88e6393_hwmon_config,
2817 .get_temp = m88e6393_get_temp,
2818 .get_temp_critical = m88e6393_get_temp_critical,
2819 .set_temp_critical = m88e6393_set_temp_critical,
2820 .get_temp_alarm = m88e1510_get_temp_alarm,
2821};
2822
2823#define DEF_MARVELL_HWMON_OPS(s) (&(s))
2824
2825#else
2826
2827#define DEF_MARVELL_HWMON_OPS(s) NULL
2828
2829static int marvell_hwmon_probe(struct phy_device *phydev)
2830{
2831 return 0;
2832}
2833#endif
2834
2835static int marvell_probe(struct phy_device *phydev)
2836{
2837 struct marvell_priv *priv;
2838
2839 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2840 if (!priv)
2841 return -ENOMEM;
2842
2843 phydev->priv = priv;
2844
2845 return marvell_hwmon_probe(phydev);
2846}
2847
2848static int m88e1510_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
2849{
2850 DECLARE_PHY_INTERFACE_MASK(interfaces);
2851 struct phy_device *phydev = upstream;
2852 phy_interface_t interface;
2853 struct device *dev;
2854 int oldpage;
2855 int ret = 0;
2856 u16 mode;
2857
2858 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
2859
2860 dev = &phydev->mdio.dev;
2861
2862 sfp_parse_support(phydev->sfp_bus, id, supported, interfaces);
2863 interface = sfp_select_interface(phydev->sfp_bus, supported);
2864
2865 dev_info(dev, "%s SFP module inserted\n", phy_modes(interface));
2866
2867 switch (interface) {
2868 case PHY_INTERFACE_MODE_1000BASEX:
2869 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X;
2870
2871 break;
2872 case PHY_INTERFACE_MODE_100BASEX:
2873 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX;
2874
2875 break;
2876 case PHY_INTERFACE_MODE_SGMII:
2877 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII;
2878
2879 break;
2880 default:
2881 dev_err(dev, "Incompatible SFP module inserted\n");
2882
2883 return -EINVAL;
2884 }
2885
2886 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
2887 if (oldpage < 0)
2888 goto error;
2889
2890 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
2891 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK, mode);
2892 if (ret < 0)
2893 goto error;
2894
2895 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
2896 MII_88E1510_GEN_CTRL_REG_1_RESET);
2897
2898error:
2899 return phy_restore_page(phydev, oldpage, ret);
2900}
2901
2902static void m88e1510_sfp_remove(void *upstream)
2903{
2904 struct phy_device *phydev = upstream;
2905 int oldpage;
2906 int ret = 0;
2907
2908 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
2909 if (oldpage < 0)
2910 goto error;
2911
2912 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
2913 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
2914 MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII);
2915 if (ret < 0)
2916 goto error;
2917
2918 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
2919 MII_88E1510_GEN_CTRL_REG_1_RESET);
2920
2921error:
2922 phy_restore_page(phydev, oldpage, ret);
2923}
2924
2925static const struct sfp_upstream_ops m88e1510_sfp_ops = {
2926 .module_insert = m88e1510_sfp_insert,
2927 .module_remove = m88e1510_sfp_remove,
2928 .attach = phy_sfp_attach,
2929 .detach = phy_sfp_detach,
2930};
2931
2932static int m88e1510_probe(struct phy_device *phydev)
2933{
2934 int err;
2935
2936 err = marvell_probe(phydev);
2937 if (err)
2938 return err;
2939
2940 return phy_sfp_probe(phydev, &m88e1510_sfp_ops);
2941}
2942
2943static struct phy_driver marvell_drivers[] = {
2944 {
2945 .phy_id = MARVELL_PHY_ID_88E1101,
2946 .phy_id_mask = MARVELL_PHY_ID_MASK,
2947 .name = "Marvell 88E1101",
2948 /* PHY_GBIT_FEATURES */
2949 .probe = marvell_probe,
2950 .config_init = marvell_config_init,
2951 .config_aneg = m88e1101_config_aneg,
2952 .config_intr = marvell_config_intr,
2953 .handle_interrupt = marvell_handle_interrupt,
2954 .resume = genphy_resume,
2955 .suspend = genphy_suspend,
2956 .read_page = marvell_read_page,
2957 .write_page = marvell_write_page,
2958 .get_sset_count = marvell_get_sset_count,
2959 .get_strings = marvell_get_strings,
2960 .get_stats = marvell_get_stats,
2961 },
2962 {
2963 .phy_id = MARVELL_PHY_ID_88E1112,
2964 .phy_id_mask = MARVELL_PHY_ID_MASK,
2965 .name = "Marvell 88E1112",
2966 /* PHY_GBIT_FEATURES */
2967 .probe = marvell_probe,
2968 .config_init = m88e1112_config_init,
2969 .config_aneg = marvell_config_aneg,
2970 .config_intr = marvell_config_intr,
2971 .handle_interrupt = marvell_handle_interrupt,
2972 .resume = genphy_resume,
2973 .suspend = genphy_suspend,
2974 .read_page = marvell_read_page,
2975 .write_page = marvell_write_page,
2976 .get_sset_count = marvell_get_sset_count,
2977 .get_strings = marvell_get_strings,
2978 .get_stats = marvell_get_stats,
2979 .get_tunable = m88e1011_get_tunable,
2980 .set_tunable = m88e1011_set_tunable,
2981 },
2982 {
2983 .phy_id = MARVELL_PHY_ID_88E1111,
2984 .phy_id_mask = MARVELL_PHY_ID_MASK,
2985 .name = "Marvell 88E1111",
2986 /* PHY_GBIT_FEATURES */
2987 .probe = marvell_probe,
2988 .config_init = m88e1111gbe_config_init,
2989 .config_aneg = m88e1111_config_aneg,
2990 .read_status = marvell_read_status,
2991 .config_intr = marvell_config_intr,
2992 .handle_interrupt = marvell_handle_interrupt,
2993 .resume = genphy_resume,
2994 .suspend = genphy_suspend,
2995 .read_page = marvell_read_page,
2996 .write_page = marvell_write_page,
2997 .get_sset_count = marvell_get_sset_count,
2998 .get_strings = marvell_get_strings,
2999 .get_stats = marvell_get_stats,
3000 .get_tunable = m88e1111_get_tunable,
3001 .set_tunable = m88e1111_set_tunable,
3002 },
3003 {
3004 .phy_id = MARVELL_PHY_ID_88E1111_FINISAR,
3005 .phy_id_mask = MARVELL_PHY_ID_MASK,
3006 .name = "Marvell 88E1111 (Finisar)",
3007 /* PHY_GBIT_FEATURES */
3008 .probe = marvell_probe,
3009 .config_init = m88e1111gbe_config_init,
3010 .config_aneg = m88e1111_config_aneg,
3011 .read_status = marvell_read_status,
3012 .config_intr = marvell_config_intr,
3013 .handle_interrupt = marvell_handle_interrupt,
3014 .resume = genphy_resume,
3015 .suspend = genphy_suspend,
3016 .read_page = marvell_read_page,
3017 .write_page = marvell_write_page,
3018 .get_sset_count = marvell_get_sset_count,
3019 .get_strings = marvell_get_strings,
3020 .get_stats = marvell_get_stats,
3021 .get_tunable = m88e1111_get_tunable,
3022 .set_tunable = m88e1111_set_tunable,
3023 },
3024 {
3025 .phy_id = MARVELL_PHY_ID_88E1118,
3026 .phy_id_mask = MARVELL_PHY_ID_MASK,
3027 .name = "Marvell 88E1118",
3028 /* PHY_GBIT_FEATURES */
3029 .probe = marvell_probe,
3030 .config_init = m88e1118_config_init,
3031 .config_aneg = m88e1118_config_aneg,
3032 .config_intr = marvell_config_intr,
3033 .handle_interrupt = marvell_handle_interrupt,
3034 .resume = genphy_resume,
3035 .suspend = genphy_suspend,
3036 .read_page = marvell_read_page,
3037 .write_page = marvell_write_page,
3038 .get_sset_count = marvell_get_sset_count,
3039 .get_strings = marvell_get_strings,
3040 .get_stats = marvell_get_stats,
3041 },
3042 {
3043 .phy_id = MARVELL_PHY_ID_88E1121R,
3044 .phy_id_mask = MARVELL_PHY_ID_MASK,
3045 .name = "Marvell 88E1121R",
3046 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops),
3047 /* PHY_GBIT_FEATURES */
3048 .probe = marvell_probe,
3049 .config_init = marvell_1011gbe_config_init,
3050 .config_aneg = m88e1121_config_aneg,
3051 .read_status = marvell_read_status,
3052 .config_intr = marvell_config_intr,
3053 .handle_interrupt = marvell_handle_interrupt,
3054 .resume = genphy_resume,
3055 .suspend = genphy_suspend,
3056 .read_page = marvell_read_page,
3057 .write_page = marvell_write_page,
3058 .get_sset_count = marvell_get_sset_count,
3059 .get_strings = marvell_get_strings,
3060 .get_stats = marvell_get_stats,
3061 .get_tunable = m88e1011_get_tunable,
3062 .set_tunable = m88e1011_set_tunable,
3063 },
3064 {
3065 .phy_id = MARVELL_PHY_ID_88E1318S,
3066 .phy_id_mask = MARVELL_PHY_ID_MASK,
3067 .name = "Marvell 88E1318S",
3068 /* PHY_GBIT_FEATURES */
3069 .probe = marvell_probe,
3070 .config_init = m88e1318_config_init,
3071 .config_aneg = m88e1318_config_aneg,
3072 .read_status = marvell_read_status,
3073 .config_intr = marvell_config_intr,
3074 .handle_interrupt = marvell_handle_interrupt,
3075 .get_wol = m88e1318_get_wol,
3076 .set_wol = m88e1318_set_wol,
3077 .resume = genphy_resume,
3078 .suspend = genphy_suspend,
3079 .read_page = marvell_read_page,
3080 .write_page = marvell_write_page,
3081 .get_sset_count = marvell_get_sset_count,
3082 .get_strings = marvell_get_strings,
3083 .get_stats = marvell_get_stats,
3084 },
3085 {
3086 .phy_id = MARVELL_PHY_ID_88E1145,
3087 .phy_id_mask = MARVELL_PHY_ID_MASK,
3088 .name = "Marvell 88E1145",
3089 /* PHY_GBIT_FEATURES */
3090 .probe = marvell_probe,
3091 .config_init = m88e1145_config_init,
3092 .config_aneg = m88e1101_config_aneg,
3093 .config_intr = marvell_config_intr,
3094 .handle_interrupt = marvell_handle_interrupt,
3095 .resume = genphy_resume,
3096 .suspend = genphy_suspend,
3097 .read_page = marvell_read_page,
3098 .write_page = marvell_write_page,
3099 .get_sset_count = marvell_get_sset_count,
3100 .get_strings = marvell_get_strings,
3101 .get_stats = marvell_get_stats,
3102 .get_tunable = m88e1111_get_tunable,
3103 .set_tunable = m88e1111_set_tunable,
3104 },
3105 {
3106 .phy_id = MARVELL_PHY_ID_88E1149R,
3107 .phy_id_mask = MARVELL_PHY_ID_MASK,
3108 .name = "Marvell 88E1149R",
3109 /* PHY_GBIT_FEATURES */
3110 .probe = marvell_probe,
3111 .config_init = m88e1149_config_init,
3112 .config_aneg = m88e1118_config_aneg,
3113 .config_intr = marvell_config_intr,
3114 .handle_interrupt = marvell_handle_interrupt,
3115 .resume = genphy_resume,
3116 .suspend = genphy_suspend,
3117 .read_page = marvell_read_page,
3118 .write_page = marvell_write_page,
3119 .get_sset_count = marvell_get_sset_count,
3120 .get_strings = marvell_get_strings,
3121 .get_stats = marvell_get_stats,
3122 },
3123 {
3124 .phy_id = MARVELL_PHY_ID_88E1240,
3125 .phy_id_mask = MARVELL_PHY_ID_MASK,
3126 .name = "Marvell 88E1240",
3127 /* PHY_GBIT_FEATURES */
3128 .probe = marvell_probe,
3129 .config_init = m88e1112_config_init,
3130 .config_aneg = marvell_config_aneg,
3131 .config_intr = marvell_config_intr,
3132 .handle_interrupt = marvell_handle_interrupt,
3133 .resume = genphy_resume,
3134 .suspend = genphy_suspend,
3135 .read_page = marvell_read_page,
3136 .write_page = marvell_write_page,
3137 .get_sset_count = marvell_get_sset_count,
3138 .get_strings = marvell_get_strings,
3139 .get_stats = marvell_get_stats,
3140 .get_tunable = m88e1011_get_tunable,
3141 .set_tunable = m88e1011_set_tunable,
3142 },
3143 {
3144 .phy_id = MARVELL_PHY_ID_88E1116R,
3145 .phy_id_mask = MARVELL_PHY_ID_MASK,
3146 .name = "Marvell 88E1116R",
3147 /* PHY_GBIT_FEATURES */
3148 .probe = marvell_probe,
3149 .config_init = m88e1116r_config_init,
3150 .config_intr = marvell_config_intr,
3151 .handle_interrupt = marvell_handle_interrupt,
3152 .resume = genphy_resume,
3153 .suspend = genphy_suspend,
3154 .read_page = marvell_read_page,
3155 .write_page = marvell_write_page,
3156 .get_sset_count = marvell_get_sset_count,
3157 .get_strings = marvell_get_strings,
3158 .get_stats = marvell_get_stats,
3159 .get_tunable = m88e1011_get_tunable,
3160 .set_tunable = m88e1011_set_tunable,
3161 },
3162 {
3163 .phy_id = MARVELL_PHY_ID_88E1510,
3164 .phy_id_mask = MARVELL_PHY_ID_MASK,
3165 .name = "Marvell 88E1510",
3166 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3167 .features = PHY_GBIT_FIBRE_FEATURES,
3168 .flags = PHY_POLL_CABLE_TEST,
3169 .probe = m88e1510_probe,
3170 .config_init = m88e1510_config_init,
3171 .config_aneg = m88e1510_config_aneg,
3172 .read_status = marvell_read_status,
3173 .config_intr = marvell_config_intr,
3174 .handle_interrupt = marvell_handle_interrupt,
3175 .get_wol = m88e1318_get_wol,
3176 .set_wol = m88e1318_set_wol,
3177 .resume = marvell_resume,
3178 .suspend = marvell_suspend,
3179 .read_page = marvell_read_page,
3180 .write_page = marvell_write_page,
3181 .get_sset_count = marvell_get_sset_count,
3182 .get_strings = marvell_get_strings,
3183 .get_stats = marvell_get_stats,
3184 .set_loopback = m88e1510_loopback,
3185 .get_tunable = m88e1011_get_tunable,
3186 .set_tunable = m88e1011_set_tunable,
3187 .cable_test_start = marvell_vct7_cable_test_start,
3188 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3189 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3190 },
3191 {
3192 .phy_id = MARVELL_PHY_ID_88E1540,
3193 .phy_id_mask = MARVELL_PHY_ID_MASK,
3194 .name = "Marvell 88E1540",
3195 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3196 /* PHY_GBIT_FEATURES */
3197 .flags = PHY_POLL_CABLE_TEST,
3198 .probe = marvell_probe,
3199 .config_init = marvell_1011gbe_config_init,
3200 .config_aneg = m88e1510_config_aneg,
3201 .read_status = marvell_read_status,
3202 .config_intr = marvell_config_intr,
3203 .handle_interrupt = marvell_handle_interrupt,
3204 .resume = genphy_resume,
3205 .suspend = genphy_suspend,
3206 .read_page = marvell_read_page,
3207 .write_page = marvell_write_page,
3208 .get_sset_count = marvell_get_sset_count,
3209 .get_strings = marvell_get_strings,
3210 .get_stats = marvell_get_stats,
3211 .get_tunable = m88e1540_get_tunable,
3212 .set_tunable = m88e1540_set_tunable,
3213 .cable_test_start = marvell_vct7_cable_test_start,
3214 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3215 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3216 },
3217 {
3218 .phy_id = MARVELL_PHY_ID_88E1545,
3219 .phy_id_mask = MARVELL_PHY_ID_MASK,
3220 .name = "Marvell 88E1545",
3221 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3222 .probe = marvell_probe,
3223 /* PHY_GBIT_FEATURES */
3224 .flags = PHY_POLL_CABLE_TEST,
3225 .config_init = marvell_1011gbe_config_init,
3226 .config_aneg = m88e1510_config_aneg,
3227 .read_status = marvell_read_status,
3228 .config_intr = marvell_config_intr,
3229 .handle_interrupt = marvell_handle_interrupt,
3230 .resume = genphy_resume,
3231 .suspend = genphy_suspend,
3232 .read_page = marvell_read_page,
3233 .write_page = marvell_write_page,
3234 .get_sset_count = marvell_get_sset_count,
3235 .get_strings = marvell_get_strings,
3236 .get_stats = marvell_get_stats,
3237 .get_tunable = m88e1540_get_tunable,
3238 .set_tunable = m88e1540_set_tunable,
3239 .cable_test_start = marvell_vct7_cable_test_start,
3240 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3241 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3242 },
3243 {
3244 .phy_id = MARVELL_PHY_ID_88E3016,
3245 .phy_id_mask = MARVELL_PHY_ID_MASK,
3246 .name = "Marvell 88E3016",
3247 /* PHY_BASIC_FEATURES */
3248 .probe = marvell_probe,
3249 .config_init = m88e3016_config_init,
3250 .aneg_done = marvell_aneg_done,
3251 .read_status = marvell_read_status,
3252 .config_intr = marvell_config_intr,
3253 .handle_interrupt = marvell_handle_interrupt,
3254 .resume = genphy_resume,
3255 .suspend = genphy_suspend,
3256 .read_page = marvell_read_page,
3257 .write_page = marvell_write_page,
3258 .get_sset_count = marvell_get_sset_count,
3259 .get_strings = marvell_get_strings,
3260 .get_stats = marvell_get_stats,
3261 },
3262 {
3263 .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
3264 .phy_id_mask = MARVELL_PHY_ID_MASK,
3265 .name = "Marvell 88E6341 Family",
3266 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3267 /* PHY_GBIT_FEATURES */
3268 .flags = PHY_POLL_CABLE_TEST,
3269 .probe = marvell_probe,
3270 .config_init = marvell_1011gbe_config_init,
3271 .config_aneg = m88e6390_config_aneg,
3272 .read_status = marvell_read_status,
3273 .config_intr = marvell_config_intr,
3274 .handle_interrupt = marvell_handle_interrupt,
3275 .resume = genphy_resume,
3276 .suspend = genphy_suspend,
3277 .read_page = marvell_read_page,
3278 .write_page = marvell_write_page,
3279 .get_sset_count = marvell_get_sset_count,
3280 .get_strings = marvell_get_strings,
3281 .get_stats = marvell_get_stats,
3282 .get_tunable = m88e1540_get_tunable,
3283 .set_tunable = m88e1540_set_tunable,
3284 .cable_test_start = marvell_vct7_cable_test_start,
3285 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3286 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3287 },
3288 {
3289 .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
3290 .phy_id_mask = MARVELL_PHY_ID_MASK,
3291 .name = "Marvell 88E6390 Family",
3292 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops),
3293 /* PHY_GBIT_FEATURES */
3294 .flags = PHY_POLL_CABLE_TEST,
3295 .probe = marvell_probe,
3296 .config_init = marvell_1011gbe_config_init,
3297 .config_aneg = m88e6390_config_aneg,
3298 .read_status = marvell_read_status,
3299 .config_intr = marvell_config_intr,
3300 .handle_interrupt = marvell_handle_interrupt,
3301 .resume = genphy_resume,
3302 .suspend = genphy_suspend,
3303 .read_page = marvell_read_page,
3304 .write_page = marvell_write_page,
3305 .get_sset_count = marvell_get_sset_count,
3306 .get_strings = marvell_get_strings,
3307 .get_stats = marvell_get_stats,
3308 .get_tunable = m88e1540_get_tunable,
3309 .set_tunable = m88e1540_set_tunable,
3310 .cable_test_start = marvell_vct7_cable_test_start,
3311 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3312 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3313 },
3314 {
3315 .phy_id = MARVELL_PHY_ID_88E6393_FAMILY,
3316 .phy_id_mask = MARVELL_PHY_ID_MASK,
3317 .name = "Marvell 88E6393 Family",
3318 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6393_hwmon_ops),
3319 /* PHY_GBIT_FEATURES */
3320 .flags = PHY_POLL_CABLE_TEST,
3321 .probe = marvell_probe,
3322 .config_init = marvell_1011gbe_config_init,
3323 .config_aneg = m88e1510_config_aneg,
3324 .read_status = marvell_read_status,
3325 .config_intr = marvell_config_intr,
3326 .handle_interrupt = marvell_handle_interrupt,
3327 .resume = genphy_resume,
3328 .suspend = genphy_suspend,
3329 .read_page = marvell_read_page,
3330 .write_page = marvell_write_page,
3331 .get_sset_count = marvell_get_sset_count,
3332 .get_strings = marvell_get_strings,
3333 .get_stats = marvell_get_stats,
3334 .get_tunable = m88e1540_get_tunable,
3335 .set_tunable = m88e1540_set_tunable,
3336 .cable_test_start = marvell_vct7_cable_test_start,
3337 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3338 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3339 },
3340 {
3341 .phy_id = MARVELL_PHY_ID_88E1340S,
3342 .phy_id_mask = MARVELL_PHY_ID_MASK,
3343 .name = "Marvell 88E1340S",
3344 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3345 .probe = marvell_probe,
3346 /* PHY_GBIT_FEATURES */
3347 .config_init = marvell_1011gbe_config_init,
3348 .config_aneg = m88e1510_config_aneg,
3349 .read_status = marvell_read_status,
3350 .config_intr = marvell_config_intr,
3351 .handle_interrupt = marvell_handle_interrupt,
3352 .resume = genphy_resume,
3353 .suspend = genphy_suspend,
3354 .read_page = marvell_read_page,
3355 .write_page = marvell_write_page,
3356 .get_sset_count = marvell_get_sset_count,
3357 .get_strings = marvell_get_strings,
3358 .get_stats = marvell_get_stats,
3359 .get_tunable = m88e1540_get_tunable,
3360 .set_tunable = m88e1540_set_tunable,
3361 },
3362 {
3363 .phy_id = MARVELL_PHY_ID_88E1548P,
3364 .phy_id_mask = MARVELL_PHY_ID_MASK,
3365 .name = "Marvell 88E1548P",
3366 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3367 .probe = marvell_probe,
3368 .features = PHY_GBIT_FIBRE_FEATURES,
3369 .config_init = marvell_1011gbe_config_init,
3370 .config_aneg = m88e1510_config_aneg,
3371 .read_status = marvell_read_status,
3372 .config_intr = marvell_config_intr,
3373 .handle_interrupt = marvell_handle_interrupt,
3374 .resume = genphy_resume,
3375 .suspend = genphy_suspend,
3376 .read_page = marvell_read_page,
3377 .write_page = marvell_write_page,
3378 .get_sset_count = marvell_get_sset_count,
3379 .get_strings = marvell_get_strings,
3380 .get_stats = marvell_get_stats,
3381 .get_tunable = m88e1540_get_tunable,
3382 .set_tunable = m88e1540_set_tunable,
3383 },
3384};
3385
3386module_phy_driver(marvell_drivers);
3387
3388static struct mdio_device_id __maybe_unused marvell_tbl[] = {
3389 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3390 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3391 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
3392 { MARVELL_PHY_ID_88E1111_FINISAR, MARVELL_PHY_ID_MASK },
3393 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3394 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3395 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3396 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3397 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3398 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3399 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
3400 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
3401 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
3402 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
3403 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
3404 { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
3405 { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
3406 { MARVELL_PHY_ID_88E6393_FAMILY, MARVELL_PHY_ID_MASK },
3407 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
3408 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
3409 { }
3410};
3411
3412MODULE_DEVICE_TABLE(mdio, marvell_tbl);