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1// SPDX-License-Identifier: GPL-2.0
2/* Driver for the Texas Instruments DP83869 PHY
3 * Copyright (C) 2019 Texas Instruments Inc.
4 */
5
6#include <linux/ethtool.h>
7#include <linux/etherdevice.h>
8#include <linux/kernel.h>
9#include <linux/mii.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/phy.h>
13#include <linux/delay.h>
14#include <linux/bitfield.h>
15
16#include <dt-bindings/net/ti-dp83869.h>
17
18#define DP83869_PHY_ID 0x2000a0f1
19#define DP83561_PHY_ID 0x2000a1a4
20#define DP83869_DEVADDR 0x1f
21
22#define MII_DP83869_PHYCTRL 0x10
23#define MII_DP83869_MICR 0x12
24#define MII_DP83869_ISR 0x13
25#define DP83869_CFG2 0x14
26#define DP83869_CTRL 0x1f
27#define DP83869_CFG4 0x1e
28
29/* Extended Registers */
30#define DP83869_GEN_CFG3 0x0031
31#define DP83869_RGMIICTL 0x0032
32#define DP83869_STRAP_STS1 0x006e
33#define DP83869_RGMIIDCTL 0x0086
34#define DP83869_RXFCFG 0x0134
35#define DP83869_RXFPMD1 0x0136
36#define DP83869_RXFPMD2 0x0137
37#define DP83869_RXFPMD3 0x0138
38#define DP83869_RXFSOP1 0x0139
39#define DP83869_RXFSOP2 0x013A
40#define DP83869_RXFSOP3 0x013B
41#define DP83869_IO_MUX_CFG 0x0170
42#define DP83869_OP_MODE 0x01df
43#define DP83869_FX_CTRL 0x0c00
44
45#define DP83869_SW_RESET BIT(15)
46#define DP83869_SW_RESTART BIT(14)
47
48/* MICR Interrupt bits */
49#define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15)
50#define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14)
51#define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
52#define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12)
53#define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11)
54#define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10)
55#define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8)
56#define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
57#define MII_DP83869_MICR_WOL_INT_EN BIT(3)
58#define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2)
59#define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1)
60#define MII_DP83869_MICR_JABBER_INT_EN BIT(0)
61
62#define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \
63 BMCR_FULLDPLX | \
64 BMCR_SPEED1000)
65
66#define MII_DP83869_FIBER_ADVERTISE (ADVERTISED_FIBRE | \
67 ADVERTISED_Pause | \
68 ADVERTISED_Asym_Pause)
69
70/* This is the same bit mask as the BMCR so re-use the BMCR default */
71#define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
72
73/* CFG1 bits */
74#define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \
75 ADVERTISE_1000FULL | \
76 CTL1000_AS_MASTER)
77
78/* RGMIICTL bits */
79#define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1)
80#define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0)
81
82/* RGMIIDCTL */
83#define DP83869_RGMII_CLK_DELAY_SHIFT 4
84#define DP83869_CLK_DELAY_DEF 7
85
86/* STRAP_STS1 bits */
87#define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0)
88#define DP83869_STRAP_STS1_RESERVED BIT(11)
89#define DP83869_STRAP_MIRROR_ENABLED BIT(12)
90
91/* PHYCTRL bits */
92#define DP83869_RX_FIFO_SHIFT 12
93#define DP83869_TX_FIFO_SHIFT 14
94
95/* PHY_CTRL lower bytes 0x48 are declared as reserved */
96#define DP83869_PHY_CTRL_DEFAULT 0x48
97#define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12)
98#define DP83869_PHYCR_RESERVED_MASK BIT(11)
99
100/* IO_MUX_CFG bits */
101#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
102
103#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
104#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
105#define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
106#define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
107
108/* CFG3 bits */
109#define DP83869_CFG3_PORT_MIRROR_EN BIT(0)
110
111/* CFG4 bits */
112#define DP83869_INT_OE BIT(7)
113
114/* OP MODE */
115#define DP83869_OP_MODE_MII BIT(5)
116#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
117
118/* RXFCFG bits*/
119#define DP83869_WOL_MAGIC_EN BIT(0)
120#define DP83869_WOL_PATTERN_EN BIT(1)
121#define DP83869_WOL_BCAST_EN BIT(2)
122#define DP83869_WOL_UCAST_EN BIT(4)
123#define DP83869_WOL_SEC_EN BIT(5)
124#define DP83869_WOL_ENH_MAC BIT(7)
125
126/* CFG2 bits */
127#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
128#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
129#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
130#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
131#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
132#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
133#define DP83869_DOWNSHIFT_1_COUNT 1
134#define DP83869_DOWNSHIFT_2_COUNT 2
135#define DP83869_DOWNSHIFT_4_COUNT 4
136#define DP83869_DOWNSHIFT_8_COUNT 8
137
138enum {
139 DP83869_PORT_MIRRORING_KEEP,
140 DP83869_PORT_MIRRORING_EN,
141 DP83869_PORT_MIRRORING_DIS,
142};
143
144struct dp83869_private {
145 int tx_fifo_depth;
146 int rx_fifo_depth;
147 s32 rx_int_delay;
148 s32 tx_int_delay;
149 int io_impedance;
150 int port_mirroring;
151 bool rxctrl_strap_quirk;
152 int clk_output_sel;
153 int mode;
154};
155
156static int dp83869_config_aneg(struct phy_device *phydev)
157{
158 struct dp83869_private *dp83869 = phydev->priv;
159
160 if (dp83869->mode != DP83869_RGMII_1000_BASE)
161 return genphy_config_aneg(phydev);
162
163 return genphy_c37_config_aneg(phydev);
164}
165
166static int dp83869_read_status(struct phy_device *phydev)
167{
168 struct dp83869_private *dp83869 = phydev->priv;
169 bool changed;
170 int ret;
171
172 if (dp83869->mode == DP83869_RGMII_1000_BASE)
173 return genphy_c37_read_status(phydev, &changed);
174
175 ret = genphy_read_status(phydev);
176 if (ret)
177 return ret;
178
179 if (dp83869->mode == DP83869_RGMII_100_BASE) {
180 if (phydev->link) {
181 phydev->speed = SPEED_100;
182 } else {
183 phydev->speed = SPEED_UNKNOWN;
184 phydev->duplex = DUPLEX_UNKNOWN;
185 }
186 }
187
188 return 0;
189}
190
191static int dp83869_ack_interrupt(struct phy_device *phydev)
192{
193 int err = phy_read(phydev, MII_DP83869_ISR);
194
195 if (err < 0)
196 return err;
197
198 return 0;
199}
200
201static int dp83869_config_intr(struct phy_device *phydev)
202{
203 int micr_status = 0, err;
204
205 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
206 err = dp83869_ack_interrupt(phydev);
207 if (err)
208 return err;
209
210 micr_status = phy_read(phydev, MII_DP83869_MICR);
211 if (micr_status < 0)
212 return micr_status;
213
214 micr_status |=
215 (MII_DP83869_MICR_AN_ERR_INT_EN |
216 MII_DP83869_MICR_SPEED_CHNG_INT_EN |
217 MII_DP83869_MICR_AUTONEG_COMP_INT_EN |
218 MII_DP83869_MICR_LINK_STS_CHNG_INT_EN |
219 MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN |
220 MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN);
221
222 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
223 } else {
224 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
225 if (err)
226 return err;
227
228 err = dp83869_ack_interrupt(phydev);
229 }
230
231 return err;
232}
233
234static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev)
235{
236 int irq_status, irq_enabled;
237
238 irq_status = phy_read(phydev, MII_DP83869_ISR);
239 if (irq_status < 0) {
240 phy_error(phydev);
241 return IRQ_NONE;
242 }
243
244 irq_enabled = phy_read(phydev, MII_DP83869_MICR);
245 if (irq_enabled < 0) {
246 phy_error(phydev);
247 return IRQ_NONE;
248 }
249
250 if (!(irq_status & irq_enabled))
251 return IRQ_NONE;
252
253 phy_trigger_machine(phydev);
254
255 return IRQ_HANDLED;
256}
257
258static int dp83869_set_wol(struct phy_device *phydev,
259 struct ethtool_wolinfo *wol)
260{
261 struct net_device *ndev = phydev->attached_dev;
262 int val_rxcfg, val_micr;
263 const u8 *mac;
264 int ret;
265
266 val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
267 if (val_rxcfg < 0)
268 return val_rxcfg;
269
270 val_micr = phy_read(phydev, MII_DP83869_MICR);
271 if (val_micr < 0)
272 return val_micr;
273
274 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
275 WAKE_BCAST)) {
276 val_rxcfg |= DP83869_WOL_ENH_MAC;
277 val_micr |= MII_DP83869_MICR_WOL_INT_EN;
278
279 if (wol->wolopts & WAKE_MAGIC ||
280 wol->wolopts & WAKE_MAGICSECURE) {
281 mac = (const u8 *)ndev->dev_addr;
282
283 if (!is_valid_ether_addr(mac))
284 return -EINVAL;
285
286 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
287 DP83869_RXFPMD1,
288 mac[1] << 8 | mac[0]);
289 if (ret)
290 return ret;
291
292 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
293 DP83869_RXFPMD2,
294 mac[3] << 8 | mac[2]);
295 if (ret)
296 return ret;
297
298 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
299 DP83869_RXFPMD3,
300 mac[5] << 8 | mac[4]);
301 if (ret)
302 return ret;
303
304 val_rxcfg |= DP83869_WOL_MAGIC_EN;
305 } else {
306 val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
307 }
308
309 if (wol->wolopts & WAKE_MAGICSECURE) {
310 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
311 DP83869_RXFSOP1,
312 (wol->sopass[1] << 8) | wol->sopass[0]);
313 if (ret)
314 return ret;
315
316 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
317 DP83869_RXFSOP2,
318 (wol->sopass[3] << 8) | wol->sopass[2]);
319 if (ret)
320 return ret;
321 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
322 DP83869_RXFSOP3,
323 (wol->sopass[5] << 8) | wol->sopass[4]);
324 if (ret)
325 return ret;
326
327 val_rxcfg |= DP83869_WOL_SEC_EN;
328 } else {
329 val_rxcfg &= ~DP83869_WOL_SEC_EN;
330 }
331
332 if (wol->wolopts & WAKE_UCAST)
333 val_rxcfg |= DP83869_WOL_UCAST_EN;
334 else
335 val_rxcfg &= ~DP83869_WOL_UCAST_EN;
336
337 if (wol->wolopts & WAKE_BCAST)
338 val_rxcfg |= DP83869_WOL_BCAST_EN;
339 else
340 val_rxcfg &= ~DP83869_WOL_BCAST_EN;
341 } else {
342 val_rxcfg &= ~DP83869_WOL_ENH_MAC;
343 val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
344 }
345
346 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
347 if (ret)
348 return ret;
349
350 return phy_write(phydev, MII_DP83869_MICR, val_micr);
351}
352
353static void dp83869_get_wol(struct phy_device *phydev,
354 struct ethtool_wolinfo *wol)
355{
356 int value, sopass_val;
357
358 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
359 WAKE_MAGICSECURE);
360 wol->wolopts = 0;
361
362 value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
363 if (value < 0) {
364 phydev_err(phydev, "Failed to read RX CFG\n");
365 return;
366 }
367
368 if (value & DP83869_WOL_UCAST_EN)
369 wol->wolopts |= WAKE_UCAST;
370
371 if (value & DP83869_WOL_BCAST_EN)
372 wol->wolopts |= WAKE_BCAST;
373
374 if (value & DP83869_WOL_MAGIC_EN)
375 wol->wolopts |= WAKE_MAGIC;
376
377 if (value & DP83869_WOL_SEC_EN) {
378 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
379 DP83869_RXFSOP1);
380 if (sopass_val < 0) {
381 phydev_err(phydev, "Failed to read RX SOP 1\n");
382 return;
383 }
384
385 wol->sopass[0] = (sopass_val & 0xff);
386 wol->sopass[1] = (sopass_val >> 8);
387
388 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
389 DP83869_RXFSOP2);
390 if (sopass_val < 0) {
391 phydev_err(phydev, "Failed to read RX SOP 2\n");
392 return;
393 }
394
395 wol->sopass[2] = (sopass_val & 0xff);
396 wol->sopass[3] = (sopass_val >> 8);
397
398 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
399 DP83869_RXFSOP3);
400 if (sopass_val < 0) {
401 phydev_err(phydev, "Failed to read RX SOP 3\n");
402 return;
403 }
404
405 wol->sopass[4] = (sopass_val & 0xff);
406 wol->sopass[5] = (sopass_val >> 8);
407
408 wol->wolopts |= WAKE_MAGICSECURE;
409 }
410
411 if (!(value & DP83869_WOL_ENH_MAC))
412 wol->wolopts = 0;
413}
414
415static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
416{
417 int val, cnt, enable, count;
418
419 val = phy_read(phydev, DP83869_CFG2);
420 if (val < 0)
421 return val;
422
423 enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
424 cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
425
426 switch (cnt) {
427 case DP83869_DOWNSHIFT_1_COUNT_VAL:
428 count = DP83869_DOWNSHIFT_1_COUNT;
429 break;
430 case DP83869_DOWNSHIFT_2_COUNT_VAL:
431 count = DP83869_DOWNSHIFT_2_COUNT;
432 break;
433 case DP83869_DOWNSHIFT_4_COUNT_VAL:
434 count = DP83869_DOWNSHIFT_4_COUNT;
435 break;
436 case DP83869_DOWNSHIFT_8_COUNT_VAL:
437 count = DP83869_DOWNSHIFT_8_COUNT;
438 break;
439 default:
440 return -EINVAL;
441 }
442
443 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
444
445 return 0;
446}
447
448static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
449{
450 int val, count;
451
452 if (cnt > DP83869_DOWNSHIFT_8_COUNT)
453 return -EINVAL;
454
455 if (!cnt)
456 return phy_clear_bits(phydev, DP83869_CFG2,
457 DP83869_DOWNSHIFT_EN);
458
459 switch (cnt) {
460 case DP83869_DOWNSHIFT_1_COUNT:
461 count = DP83869_DOWNSHIFT_1_COUNT_VAL;
462 break;
463 case DP83869_DOWNSHIFT_2_COUNT:
464 count = DP83869_DOWNSHIFT_2_COUNT_VAL;
465 break;
466 case DP83869_DOWNSHIFT_4_COUNT:
467 count = DP83869_DOWNSHIFT_4_COUNT_VAL;
468 break;
469 case DP83869_DOWNSHIFT_8_COUNT:
470 count = DP83869_DOWNSHIFT_8_COUNT_VAL;
471 break;
472 default:
473 phydev_err(phydev,
474 "Downshift count must be 1, 2, 4 or 8\n");
475 return -EINVAL;
476 }
477
478 val = DP83869_DOWNSHIFT_EN;
479 val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
480
481 return phy_modify(phydev, DP83869_CFG2,
482 DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
483 val);
484}
485
486static int dp83869_get_tunable(struct phy_device *phydev,
487 struct ethtool_tunable *tuna, void *data)
488{
489 switch (tuna->id) {
490 case ETHTOOL_PHY_DOWNSHIFT:
491 return dp83869_get_downshift(phydev, data);
492 default:
493 return -EOPNOTSUPP;
494 }
495}
496
497static int dp83869_set_tunable(struct phy_device *phydev,
498 struct ethtool_tunable *tuna, const void *data)
499{
500 switch (tuna->id) {
501 case ETHTOOL_PHY_DOWNSHIFT:
502 return dp83869_set_downshift(phydev, *(const u8 *)data);
503 default:
504 return -EOPNOTSUPP;
505 }
506}
507
508static int dp83869_config_port_mirroring(struct phy_device *phydev)
509{
510 struct dp83869_private *dp83869 = phydev->priv;
511
512 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
513 return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
514 DP83869_GEN_CFG3,
515 DP83869_CFG3_PORT_MIRROR_EN);
516 else
517 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR,
518 DP83869_GEN_CFG3,
519 DP83869_CFG3_PORT_MIRROR_EN);
520}
521
522static int dp83869_set_strapped_mode(struct phy_device *phydev)
523{
524 struct dp83869_private *dp83869 = phydev->priv;
525 int val;
526
527 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
528 if (val < 0)
529 return val;
530
531 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK;
532
533 return 0;
534}
535
536#if IS_ENABLED(CONFIG_OF_MDIO)
537static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
538 1750, 2000, 2250, 2500, 2750, 3000,
539 3250, 3500, 3750, 4000};
540
541static int dp83869_of_init(struct phy_device *phydev)
542{
543 struct dp83869_private *dp83869 = phydev->priv;
544 struct device *dev = &phydev->mdio.dev;
545 struct device_node *of_node = dev->of_node;
546 int delay_size = ARRAY_SIZE(dp83869_internal_delay);
547 int ret;
548
549 if (!of_node)
550 return -ENODEV;
551
552 dp83869->io_impedance = -EINVAL;
553
554 /* Optional configuration */
555 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
556 &dp83869->clk_output_sel);
557 if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK)
558 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
559
560 ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode);
561 if (ret == 0) {
562 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
563 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
564 return -EINVAL;
565 } else {
566 ret = dp83869_set_strapped_mode(phydev);
567 if (ret)
568 return ret;
569 }
570
571 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
572 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
573 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
574 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
575
576 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) {
577 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
578 } else {
579 /* If the lane swap is not in the DT then check the straps */
580 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
581 if (ret < 0)
582 return ret;
583
584 if (ret & DP83869_STRAP_MIRROR_ENABLED)
585 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
586 else
587 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
588
589 ret = 0;
590 }
591
592 if (of_property_read_u32(of_node, "rx-fifo-depth",
593 &dp83869->rx_fifo_depth))
594 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
595
596 if (of_property_read_u32(of_node, "tx-fifo-depth",
597 &dp83869->tx_fifo_depth))
598 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
599
600 dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev,
601 &dp83869_internal_delay[0],
602 delay_size, true);
603 if (dp83869->rx_int_delay < 0)
604 dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF;
605
606 dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev,
607 &dp83869_internal_delay[0],
608 delay_size, false);
609 if (dp83869->tx_int_delay < 0)
610 dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF;
611
612 return ret;
613}
614#else
615static int dp83869_of_init(struct phy_device *phydev)
616{
617 return dp83869_set_strapped_mode(phydev);
618}
619#endif /* CONFIG_OF_MDIO */
620
621static int dp83869_configure_rgmii(struct phy_device *phydev,
622 struct dp83869_private *dp83869)
623{
624 int ret = 0, val;
625
626 if (phy_interface_is_rgmii(phydev)) {
627 val = phy_read(phydev, MII_DP83869_PHYCTRL);
628 if (val < 0)
629 return val;
630
631 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK;
632 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT);
633 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT);
634
635 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
636 if (ret)
637 return ret;
638 }
639
640 if (dp83869->io_impedance >= 0)
641 ret = phy_modify_mmd(phydev, DP83869_DEVADDR,
642 DP83869_IO_MUX_CFG,
643 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
644 dp83869->io_impedance &
645 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
646
647 return ret;
648}
649
650static int dp83869_configure_fiber(struct phy_device *phydev,
651 struct dp83869_private *dp83869)
652{
653 int bmcr;
654 int ret;
655
656 /* Only allow advertising what this PHY supports */
657 linkmode_and(phydev->advertising, phydev->advertising,
658 phydev->supported);
659
660 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
661
662 if (dp83869->mode == DP83869_RGMII_1000_BASE) {
663 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
664 phydev->supported);
665 } else {
666 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
667 phydev->supported);
668 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
669 phydev->supported);
670
671 /* Auto neg is not supported in 100base FX mode */
672 bmcr = phy_read(phydev, MII_BMCR);
673 if (bmcr < 0)
674 return bmcr;
675
676 phydev->autoneg = AUTONEG_DISABLE;
677 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
678 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
679
680 if (bmcr & BMCR_ANENABLE) {
681 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
682 if (ret < 0)
683 return ret;
684 }
685 }
686
687 /* Update advertising from supported */
688 linkmode_or(phydev->advertising, phydev->advertising,
689 phydev->supported);
690
691 return 0;
692}
693
694static int dp83869_configure_mode(struct phy_device *phydev,
695 struct dp83869_private *dp83869)
696{
697 int phy_ctrl_val;
698 int ret;
699
700 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
701 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
702 return -EINVAL;
703
704 /* Below init sequence for each operational mode is defined in
705 * section 9.4.8 of the datasheet.
706 */
707 phy_ctrl_val = dp83869->mode;
708 if (phydev->interface == PHY_INTERFACE_MODE_MII) {
709 if (dp83869->mode == DP83869_100M_MEDIA_CONVERT ||
710 dp83869->mode == DP83869_RGMII_100_BASE ||
711 dp83869->mode == DP83869_RGMII_COPPER_ETHERNET) {
712 phy_ctrl_val |= DP83869_OP_MODE_MII;
713 } else {
714 phydev_err(phydev, "selected op-mode is not valid with MII mode\n");
715 return -EINVAL;
716 }
717 }
718
719 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
720 phy_ctrl_val);
721 if (ret)
722 return ret;
723
724 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
725 if (ret)
726 return ret;
727
728 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
729 dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
730 DP83869_PHY_CTRL_DEFAULT);
731
732 switch (dp83869->mode) {
733 case DP83869_RGMII_COPPER_ETHERNET:
734 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
735 phy_ctrl_val);
736 if (ret)
737 return ret;
738
739 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
740 if (ret)
741 return ret;
742
743 ret = dp83869_configure_rgmii(phydev, dp83869);
744 if (ret)
745 return ret;
746 break;
747 case DP83869_RGMII_SGMII_BRIDGE:
748 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
749 DP83869_SGMII_RGMII_BRIDGE,
750 DP83869_SGMII_RGMII_BRIDGE);
751 if (ret)
752 return ret;
753
754 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
755 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
756 if (ret)
757 return ret;
758
759 break;
760 case DP83869_1000M_MEDIA_CONVERT:
761 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
762 phy_ctrl_val);
763 if (ret)
764 return ret;
765
766 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
767 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
768 if (ret)
769 return ret;
770 break;
771 case DP83869_100M_MEDIA_CONVERT:
772 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
773 phy_ctrl_val);
774 if (ret)
775 return ret;
776 break;
777 case DP83869_SGMII_COPPER_ETHERNET:
778 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
779 phy_ctrl_val);
780 if (ret)
781 return ret;
782
783 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
784 if (ret)
785 return ret;
786
787 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
788 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
789 if (ret)
790 return ret;
791
792 break;
793 case DP83869_RGMII_1000_BASE:
794 case DP83869_RGMII_100_BASE:
795 ret = dp83869_configure_fiber(phydev, dp83869);
796 break;
797 default:
798 return -EINVAL;
799 }
800
801 return ret;
802}
803
804static int dp83869_config_init(struct phy_device *phydev)
805{
806 struct dp83869_private *dp83869 = phydev->priv;
807 int ret, val;
808
809 /* Force speed optimization for the PHY even if it strapped */
810 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
811 DP83869_DOWNSHIFT_EN);
812 if (ret)
813 return ret;
814
815 ret = dp83869_configure_mode(phydev, dp83869);
816 if (ret)
817 return ret;
818
819 /* Enable Interrupt output INT_OE in CFG4 register */
820 if (phy_interrupt_is_valid(phydev)) {
821 val = phy_read(phydev, DP83869_CFG4);
822 val |= DP83869_INT_OE;
823 phy_write(phydev, DP83869_CFG4, val);
824 }
825
826 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
827 dp83869_config_port_mirroring(phydev);
828
829 /* Clock output selection if muxing property is set */
830 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
831 ret = phy_modify_mmd(phydev,
832 DP83869_DEVADDR, DP83869_IO_MUX_CFG,
833 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
834 dp83869->clk_output_sel <<
835 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
836
837 if (phy_interface_is_rgmii(phydev)) {
838 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
839 dp83869->rx_int_delay |
840 dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT);
841 if (ret)
842 return ret;
843
844 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
845 val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
846 DP83869_RGMII_RX_CLK_DELAY_EN);
847
848 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
849 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
850 DP83869_RGMII_RX_CLK_DELAY_EN);
851
852 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
853 val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
854
855 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
856 val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
857
858 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
859 val);
860 }
861
862 return ret;
863}
864
865static int dp83869_probe(struct phy_device *phydev)
866{
867 struct dp83869_private *dp83869;
868 int ret;
869
870 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
871 GFP_KERNEL);
872 if (!dp83869)
873 return -ENOMEM;
874
875 phydev->priv = dp83869;
876
877 ret = dp83869_of_init(phydev);
878 if (ret)
879 return ret;
880
881 if (dp83869->mode == DP83869_RGMII_100_BASE ||
882 dp83869->mode == DP83869_RGMII_1000_BASE)
883 phydev->port = PORT_FIBRE;
884
885 return dp83869_config_init(phydev);
886}
887
888static int dp83869_phy_reset(struct phy_device *phydev)
889{
890 int ret;
891
892 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
893 if (ret < 0)
894 return ret;
895
896 usleep_range(10, 20);
897
898 /* Global sw reset sets all registers to default.
899 * Need to set the registers in the PHY to the right config.
900 */
901 return dp83869_config_init(phydev);
902}
903
904
905#define DP83869_PHY_DRIVER(_id, _name) \
906{ \
907 PHY_ID_MATCH_MODEL(_id), \
908 .name = (_name), \
909 .probe = dp83869_probe, \
910 .config_init = dp83869_config_init, \
911 .soft_reset = dp83869_phy_reset, \
912 .config_intr = dp83869_config_intr, \
913 .handle_interrupt = dp83869_handle_interrupt, \
914 .config_aneg = dp83869_config_aneg, \
915 .read_status = dp83869_read_status, \
916 .get_tunable = dp83869_get_tunable, \
917 .set_tunable = dp83869_set_tunable, \
918 .get_wol = dp83869_get_wol, \
919 .set_wol = dp83869_set_wol, \
920 .suspend = genphy_suspend, \
921 .resume = genphy_resume, \
922}
923
924static struct phy_driver dp83869_driver[] = {
925 DP83869_PHY_DRIVER(DP83869_PHY_ID, "TI DP83869"),
926 DP83869_PHY_DRIVER(DP83561_PHY_ID, "TI DP83561-SP"),
927
928};
929module_phy_driver(dp83869_driver);
930
931static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
932 { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) },
933 { PHY_ID_MATCH_MODEL(DP83561_PHY_ID) },
934 { }
935};
936MODULE_DEVICE_TABLE(mdio, dp83869_tbl);
937
938MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver");
939MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
940MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/* Driver for the Texas Instruments DP83869 PHY
3 * Copyright (C) 2019 Texas Instruments Inc.
4 */
5
6#include <linux/ethtool.h>
7#include <linux/etherdevice.h>
8#include <linux/kernel.h>
9#include <linux/mii.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/phy.h>
13#include <linux/delay.h>
14#include <linux/bitfield.h>
15
16#include <dt-bindings/net/ti-dp83869.h>
17
18#define DP83869_PHY_ID 0x2000a0f1
19#define DP83561_PHY_ID 0x2000a1a4
20#define DP83869_DEVADDR 0x1f
21
22#define MII_DP83869_PHYCTRL 0x10
23#define MII_DP83869_MICR 0x12
24#define MII_DP83869_ISR 0x13
25#define DP83869_CFG2 0x14
26#define DP83869_CTRL 0x1f
27#define DP83869_CFG4 0x1e
28
29/* Extended Registers */
30#define DP83869_GEN_CFG3 0x0031
31#define DP83869_RGMIICTL 0x0032
32#define DP83869_STRAP_STS1 0x006e
33#define DP83869_RGMIIDCTL 0x0086
34#define DP83869_RXFCFG 0x0134
35#define DP83869_RXFPMD1 0x0136
36#define DP83869_RXFPMD2 0x0137
37#define DP83869_RXFPMD3 0x0138
38#define DP83869_RXFSOP1 0x0139
39#define DP83869_RXFSOP2 0x013A
40#define DP83869_RXFSOP3 0x013B
41#define DP83869_IO_MUX_CFG 0x0170
42#define DP83869_OP_MODE 0x01df
43#define DP83869_FX_CTRL 0x0c00
44
45#define DP83869_SW_RESET BIT(15)
46#define DP83869_SW_RESTART BIT(14)
47
48/* MICR Interrupt bits */
49#define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15)
50#define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14)
51#define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
52#define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12)
53#define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11)
54#define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10)
55#define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8)
56#define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
57#define MII_DP83869_MICR_WOL_INT_EN BIT(3)
58#define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2)
59#define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1)
60#define MII_DP83869_MICR_JABBER_INT_EN BIT(0)
61
62#define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \
63 BMCR_FULLDPLX | \
64 BMCR_SPEED1000)
65
66#define MII_DP83869_FIBER_ADVERTISE (ADVERTISED_FIBRE | \
67 ADVERTISED_Pause | \
68 ADVERTISED_Asym_Pause)
69
70/* This is the same bit mask as the BMCR so re-use the BMCR default */
71#define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
72
73/* CFG1 bits */
74#define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \
75 ADVERTISE_1000FULL | \
76 CTL1000_AS_MASTER)
77
78/* RGMIICTL bits */
79#define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1)
80#define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0)
81
82/* RGMIIDCTL */
83#define DP83869_RGMII_CLK_DELAY_SHIFT 4
84#define DP83869_CLK_DELAY_DEF 7
85
86/* STRAP_STS1 bits */
87#define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0)
88#define DP83869_STRAP_STS1_RESERVED BIT(11)
89#define DP83869_STRAP_MIRROR_ENABLED BIT(12)
90
91/* PHYCTRL bits */
92#define DP83869_RX_FIFO_SHIFT 12
93#define DP83869_TX_FIFO_SHIFT 14
94
95/* PHY_CTRL lower bytes 0x48 are declared as reserved */
96#define DP83869_PHY_CTRL_DEFAULT 0x48
97#define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12)
98#define DP83869_PHYCR_RESERVED_MASK BIT(11)
99
100/* IO_MUX_CFG bits */
101#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
102
103#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
104#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
105#define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
106#define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
107
108/* CFG3 bits */
109#define DP83869_CFG3_PORT_MIRROR_EN BIT(0)
110
111/* CFG4 bits */
112#define DP83869_INT_OE BIT(7)
113
114/* OP MODE */
115#define DP83869_OP_MODE_MII BIT(5)
116#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
117
118/* RXFCFG bits*/
119#define DP83869_WOL_MAGIC_EN BIT(0)
120#define DP83869_WOL_PATTERN_EN BIT(1)
121#define DP83869_WOL_BCAST_EN BIT(2)
122#define DP83869_WOL_UCAST_EN BIT(4)
123#define DP83869_WOL_SEC_EN BIT(5)
124#define DP83869_WOL_ENH_MAC BIT(7)
125
126/* CFG2 bits */
127#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
128#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
129#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
130#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
131#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
132#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
133#define DP83869_DOWNSHIFT_1_COUNT 1
134#define DP83869_DOWNSHIFT_2_COUNT 2
135#define DP83869_DOWNSHIFT_4_COUNT 4
136#define DP83869_DOWNSHIFT_8_COUNT 8
137
138enum {
139 DP83869_PORT_MIRRORING_KEEP,
140 DP83869_PORT_MIRRORING_EN,
141 DP83869_PORT_MIRRORING_DIS,
142};
143
144struct dp83869_private {
145 int tx_fifo_depth;
146 int rx_fifo_depth;
147 s32 rx_int_delay;
148 s32 tx_int_delay;
149 int io_impedance;
150 int port_mirroring;
151 bool rxctrl_strap_quirk;
152 int clk_output_sel;
153 int mode;
154};
155
156static int dp83869_read_status(struct phy_device *phydev)
157{
158 struct dp83869_private *dp83869 = phydev->priv;
159 int ret;
160
161 ret = genphy_read_status(phydev);
162 if (ret)
163 return ret;
164
165 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
166 if (phydev->link) {
167 if (dp83869->mode == DP83869_RGMII_100_BASE)
168 phydev->speed = SPEED_100;
169 } else {
170 phydev->speed = SPEED_UNKNOWN;
171 phydev->duplex = DUPLEX_UNKNOWN;
172 }
173 }
174
175 return 0;
176}
177
178static int dp83869_ack_interrupt(struct phy_device *phydev)
179{
180 int err = phy_read(phydev, MII_DP83869_ISR);
181
182 if (err < 0)
183 return err;
184
185 return 0;
186}
187
188static int dp83869_config_intr(struct phy_device *phydev)
189{
190 int micr_status = 0, err;
191
192 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
193 err = dp83869_ack_interrupt(phydev);
194 if (err)
195 return err;
196
197 micr_status = phy_read(phydev, MII_DP83869_MICR);
198 if (micr_status < 0)
199 return micr_status;
200
201 micr_status |=
202 (MII_DP83869_MICR_AN_ERR_INT_EN |
203 MII_DP83869_MICR_SPEED_CHNG_INT_EN |
204 MII_DP83869_MICR_AUTONEG_COMP_INT_EN |
205 MII_DP83869_MICR_LINK_STS_CHNG_INT_EN |
206 MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN |
207 MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN);
208
209 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
210 } else {
211 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
212 if (err)
213 return err;
214
215 err = dp83869_ack_interrupt(phydev);
216 }
217
218 return err;
219}
220
221static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev)
222{
223 int irq_status, irq_enabled;
224
225 irq_status = phy_read(phydev, MII_DP83869_ISR);
226 if (irq_status < 0) {
227 phy_error(phydev);
228 return IRQ_NONE;
229 }
230
231 irq_enabled = phy_read(phydev, MII_DP83869_MICR);
232 if (irq_enabled < 0) {
233 phy_error(phydev);
234 return IRQ_NONE;
235 }
236
237 if (!(irq_status & irq_enabled))
238 return IRQ_NONE;
239
240 phy_trigger_machine(phydev);
241
242 return IRQ_HANDLED;
243}
244
245static int dp83869_set_wol(struct phy_device *phydev,
246 struct ethtool_wolinfo *wol)
247{
248 struct net_device *ndev = phydev->attached_dev;
249 int val_rxcfg, val_micr;
250 const u8 *mac;
251 int ret;
252
253 val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
254 if (val_rxcfg < 0)
255 return val_rxcfg;
256
257 val_micr = phy_read(phydev, MII_DP83869_MICR);
258 if (val_micr < 0)
259 return val_micr;
260
261 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
262 WAKE_BCAST)) {
263 val_rxcfg |= DP83869_WOL_ENH_MAC;
264 val_micr |= MII_DP83869_MICR_WOL_INT_EN;
265
266 if (wol->wolopts & WAKE_MAGIC ||
267 wol->wolopts & WAKE_MAGICSECURE) {
268 mac = (const u8 *)ndev->dev_addr;
269
270 if (!is_valid_ether_addr(mac))
271 return -EINVAL;
272
273 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
274 DP83869_RXFPMD1,
275 mac[1] << 8 | mac[0]);
276 if (ret)
277 return ret;
278
279 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
280 DP83869_RXFPMD2,
281 mac[3] << 8 | mac[2]);
282 if (ret)
283 return ret;
284
285 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
286 DP83869_RXFPMD3,
287 mac[5] << 8 | mac[4]);
288 if (ret)
289 return ret;
290
291 val_rxcfg |= DP83869_WOL_MAGIC_EN;
292 } else {
293 val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
294 }
295
296 if (wol->wolopts & WAKE_MAGICSECURE) {
297 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
298 DP83869_RXFSOP1,
299 (wol->sopass[1] << 8) | wol->sopass[0]);
300 if (ret)
301 return ret;
302
303 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
304 DP83869_RXFSOP2,
305 (wol->sopass[3] << 8) | wol->sopass[2]);
306 if (ret)
307 return ret;
308 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
309 DP83869_RXFSOP3,
310 (wol->sopass[5] << 8) | wol->sopass[4]);
311 if (ret)
312 return ret;
313
314 val_rxcfg |= DP83869_WOL_SEC_EN;
315 } else {
316 val_rxcfg &= ~DP83869_WOL_SEC_EN;
317 }
318
319 if (wol->wolopts & WAKE_UCAST)
320 val_rxcfg |= DP83869_WOL_UCAST_EN;
321 else
322 val_rxcfg &= ~DP83869_WOL_UCAST_EN;
323
324 if (wol->wolopts & WAKE_BCAST)
325 val_rxcfg |= DP83869_WOL_BCAST_EN;
326 else
327 val_rxcfg &= ~DP83869_WOL_BCAST_EN;
328 } else {
329 val_rxcfg &= ~DP83869_WOL_ENH_MAC;
330 val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
331 }
332
333 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
334 if (ret)
335 return ret;
336
337 return phy_write(phydev, MII_DP83869_MICR, val_micr);
338}
339
340static void dp83869_get_wol(struct phy_device *phydev,
341 struct ethtool_wolinfo *wol)
342{
343 int value, sopass_val;
344
345 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
346 WAKE_MAGICSECURE);
347 wol->wolopts = 0;
348
349 value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
350 if (value < 0) {
351 phydev_err(phydev, "Failed to read RX CFG\n");
352 return;
353 }
354
355 if (value & DP83869_WOL_UCAST_EN)
356 wol->wolopts |= WAKE_UCAST;
357
358 if (value & DP83869_WOL_BCAST_EN)
359 wol->wolopts |= WAKE_BCAST;
360
361 if (value & DP83869_WOL_MAGIC_EN)
362 wol->wolopts |= WAKE_MAGIC;
363
364 if (value & DP83869_WOL_SEC_EN) {
365 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
366 DP83869_RXFSOP1);
367 if (sopass_val < 0) {
368 phydev_err(phydev, "Failed to read RX SOP 1\n");
369 return;
370 }
371
372 wol->sopass[0] = (sopass_val & 0xff);
373 wol->sopass[1] = (sopass_val >> 8);
374
375 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
376 DP83869_RXFSOP2);
377 if (sopass_val < 0) {
378 phydev_err(phydev, "Failed to read RX SOP 2\n");
379 return;
380 }
381
382 wol->sopass[2] = (sopass_val & 0xff);
383 wol->sopass[3] = (sopass_val >> 8);
384
385 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
386 DP83869_RXFSOP3);
387 if (sopass_val < 0) {
388 phydev_err(phydev, "Failed to read RX SOP 3\n");
389 return;
390 }
391
392 wol->sopass[4] = (sopass_val & 0xff);
393 wol->sopass[5] = (sopass_val >> 8);
394
395 wol->wolopts |= WAKE_MAGICSECURE;
396 }
397
398 if (!(value & DP83869_WOL_ENH_MAC))
399 wol->wolopts = 0;
400}
401
402static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
403{
404 int val, cnt, enable, count;
405
406 val = phy_read(phydev, DP83869_CFG2);
407 if (val < 0)
408 return val;
409
410 enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
411 cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
412
413 switch (cnt) {
414 case DP83869_DOWNSHIFT_1_COUNT_VAL:
415 count = DP83869_DOWNSHIFT_1_COUNT;
416 break;
417 case DP83869_DOWNSHIFT_2_COUNT_VAL:
418 count = DP83869_DOWNSHIFT_2_COUNT;
419 break;
420 case DP83869_DOWNSHIFT_4_COUNT_VAL:
421 count = DP83869_DOWNSHIFT_4_COUNT;
422 break;
423 case DP83869_DOWNSHIFT_8_COUNT_VAL:
424 count = DP83869_DOWNSHIFT_8_COUNT;
425 break;
426 default:
427 return -EINVAL;
428 }
429
430 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
431
432 return 0;
433}
434
435static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
436{
437 int val, count;
438
439 if (cnt > DP83869_DOWNSHIFT_8_COUNT)
440 return -EINVAL;
441
442 if (!cnt)
443 return phy_clear_bits(phydev, DP83869_CFG2,
444 DP83869_DOWNSHIFT_EN);
445
446 switch (cnt) {
447 case DP83869_DOWNSHIFT_1_COUNT:
448 count = DP83869_DOWNSHIFT_1_COUNT_VAL;
449 break;
450 case DP83869_DOWNSHIFT_2_COUNT:
451 count = DP83869_DOWNSHIFT_2_COUNT_VAL;
452 break;
453 case DP83869_DOWNSHIFT_4_COUNT:
454 count = DP83869_DOWNSHIFT_4_COUNT_VAL;
455 break;
456 case DP83869_DOWNSHIFT_8_COUNT:
457 count = DP83869_DOWNSHIFT_8_COUNT_VAL;
458 break;
459 default:
460 phydev_err(phydev,
461 "Downshift count must be 1, 2, 4 or 8\n");
462 return -EINVAL;
463 }
464
465 val = DP83869_DOWNSHIFT_EN;
466 val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
467
468 return phy_modify(phydev, DP83869_CFG2,
469 DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
470 val);
471}
472
473static int dp83869_get_tunable(struct phy_device *phydev,
474 struct ethtool_tunable *tuna, void *data)
475{
476 switch (tuna->id) {
477 case ETHTOOL_PHY_DOWNSHIFT:
478 return dp83869_get_downshift(phydev, data);
479 default:
480 return -EOPNOTSUPP;
481 }
482}
483
484static int dp83869_set_tunable(struct phy_device *phydev,
485 struct ethtool_tunable *tuna, const void *data)
486{
487 switch (tuna->id) {
488 case ETHTOOL_PHY_DOWNSHIFT:
489 return dp83869_set_downshift(phydev, *(const u8 *)data);
490 default:
491 return -EOPNOTSUPP;
492 }
493}
494
495static int dp83869_config_port_mirroring(struct phy_device *phydev)
496{
497 struct dp83869_private *dp83869 = phydev->priv;
498
499 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
500 return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
501 DP83869_GEN_CFG3,
502 DP83869_CFG3_PORT_MIRROR_EN);
503 else
504 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR,
505 DP83869_GEN_CFG3,
506 DP83869_CFG3_PORT_MIRROR_EN);
507}
508
509static int dp83869_set_strapped_mode(struct phy_device *phydev)
510{
511 struct dp83869_private *dp83869 = phydev->priv;
512 int val;
513
514 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
515 if (val < 0)
516 return val;
517
518 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK;
519
520 return 0;
521}
522
523#if IS_ENABLED(CONFIG_OF_MDIO)
524static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
525 1750, 2000, 2250, 2500, 2750, 3000,
526 3250, 3500, 3750, 4000};
527
528static int dp83869_of_init(struct phy_device *phydev)
529{
530 struct dp83869_private *dp83869 = phydev->priv;
531 struct device *dev = &phydev->mdio.dev;
532 struct device_node *of_node = dev->of_node;
533 int delay_size = ARRAY_SIZE(dp83869_internal_delay);
534 int ret;
535
536 if (!of_node)
537 return -ENODEV;
538
539 dp83869->io_impedance = -EINVAL;
540
541 /* Optional configuration */
542 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
543 &dp83869->clk_output_sel);
544 if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK)
545 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
546
547 ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode);
548 if (ret == 0) {
549 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
550 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
551 return -EINVAL;
552 } else {
553 ret = dp83869_set_strapped_mode(phydev);
554 if (ret)
555 return ret;
556 }
557
558 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
559 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
560 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
561 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
562
563 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) {
564 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
565 } else {
566 /* If the lane swap is not in the DT then check the straps */
567 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
568 if (ret < 0)
569 return ret;
570
571 if (ret & DP83869_STRAP_MIRROR_ENABLED)
572 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
573 else
574 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
575
576 ret = 0;
577 }
578
579 if (of_property_read_u32(of_node, "rx-fifo-depth",
580 &dp83869->rx_fifo_depth))
581 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
582
583 if (of_property_read_u32(of_node, "tx-fifo-depth",
584 &dp83869->tx_fifo_depth))
585 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
586
587 dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev,
588 &dp83869_internal_delay[0],
589 delay_size, true);
590 if (dp83869->rx_int_delay < 0)
591 dp83869->rx_int_delay =
592 dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
593
594 dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev,
595 &dp83869_internal_delay[0],
596 delay_size, false);
597 if (dp83869->tx_int_delay < 0)
598 dp83869->tx_int_delay =
599 dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
600
601 return ret;
602}
603#else
604static int dp83869_of_init(struct phy_device *phydev)
605{
606 return dp83869_set_strapped_mode(phydev);
607}
608#endif /* CONFIG_OF_MDIO */
609
610static int dp83869_configure_rgmii(struct phy_device *phydev,
611 struct dp83869_private *dp83869)
612{
613 int ret = 0, val;
614
615 if (phy_interface_is_rgmii(phydev)) {
616 val = phy_read(phydev, MII_DP83869_PHYCTRL);
617 if (val < 0)
618 return val;
619
620 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK;
621 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT);
622 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT);
623
624 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
625 if (ret)
626 return ret;
627 }
628
629 if (dp83869->io_impedance >= 0)
630 ret = phy_modify_mmd(phydev, DP83869_DEVADDR,
631 DP83869_IO_MUX_CFG,
632 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
633 dp83869->io_impedance &
634 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
635
636 return ret;
637}
638
639static int dp83869_configure_fiber(struct phy_device *phydev,
640 struct dp83869_private *dp83869)
641{
642 int bmcr;
643 int ret;
644
645 /* Only allow advertising what this PHY supports */
646 linkmode_and(phydev->advertising, phydev->advertising,
647 phydev->supported);
648
649 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
650 linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising);
651
652 if (dp83869->mode == DP83869_RGMII_1000_BASE) {
653 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
654 phydev->supported);
655 } else {
656 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
657 phydev->supported);
658 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
659 phydev->supported);
660
661 /* Auto neg is not supported in 100base FX mode */
662 bmcr = phy_read(phydev, MII_BMCR);
663 if (bmcr < 0)
664 return bmcr;
665
666 phydev->autoneg = AUTONEG_DISABLE;
667 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
668 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
669
670 if (bmcr & BMCR_ANENABLE) {
671 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
672 if (ret < 0)
673 return ret;
674 }
675 }
676
677 /* Update advertising from supported */
678 linkmode_or(phydev->advertising, phydev->advertising,
679 phydev->supported);
680
681 return 0;
682}
683
684static int dp83869_configure_mode(struct phy_device *phydev,
685 struct dp83869_private *dp83869)
686{
687 int phy_ctrl_val;
688 int ret;
689
690 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
691 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
692 return -EINVAL;
693
694 /* Below init sequence for each operational mode is defined in
695 * section 9.4.8 of the datasheet.
696 */
697 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
698 dp83869->mode);
699 if (ret)
700 return ret;
701
702 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
703 if (ret)
704 return ret;
705
706 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
707 dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
708 DP83869_PHY_CTRL_DEFAULT);
709
710 switch (dp83869->mode) {
711 case DP83869_RGMII_COPPER_ETHERNET:
712 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
713 phy_ctrl_val);
714 if (ret)
715 return ret;
716
717 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
718 if (ret)
719 return ret;
720
721 ret = dp83869_configure_rgmii(phydev, dp83869);
722 if (ret)
723 return ret;
724 break;
725 case DP83869_RGMII_SGMII_BRIDGE:
726 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
727 DP83869_SGMII_RGMII_BRIDGE,
728 DP83869_SGMII_RGMII_BRIDGE);
729 if (ret)
730 return ret;
731
732 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
733 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
734 if (ret)
735 return ret;
736
737 break;
738 case DP83869_1000M_MEDIA_CONVERT:
739 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
740 phy_ctrl_val);
741 if (ret)
742 return ret;
743
744 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
745 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
746 if (ret)
747 return ret;
748 break;
749 case DP83869_100M_MEDIA_CONVERT:
750 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
751 phy_ctrl_val);
752 if (ret)
753 return ret;
754 break;
755 case DP83869_SGMII_COPPER_ETHERNET:
756 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
757 phy_ctrl_val);
758 if (ret)
759 return ret;
760
761 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
762 if (ret)
763 return ret;
764
765 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
766 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
767 if (ret)
768 return ret;
769
770 break;
771 case DP83869_RGMII_1000_BASE:
772 case DP83869_RGMII_100_BASE:
773 ret = dp83869_configure_fiber(phydev, dp83869);
774 break;
775 default:
776 return -EINVAL;
777 }
778
779 return ret;
780}
781
782static int dp83869_config_init(struct phy_device *phydev)
783{
784 struct dp83869_private *dp83869 = phydev->priv;
785 int ret, val;
786
787 /* Force speed optimization for the PHY even if it strapped */
788 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
789 DP83869_DOWNSHIFT_EN);
790 if (ret)
791 return ret;
792
793 ret = dp83869_configure_mode(phydev, dp83869);
794 if (ret)
795 return ret;
796
797 /* Enable Interrupt output INT_OE in CFG4 register */
798 if (phy_interrupt_is_valid(phydev)) {
799 val = phy_read(phydev, DP83869_CFG4);
800 val |= DP83869_INT_OE;
801 phy_write(phydev, DP83869_CFG4, val);
802 }
803
804 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
805 dp83869_config_port_mirroring(phydev);
806
807 /* Clock output selection if muxing property is set */
808 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
809 ret = phy_modify_mmd(phydev,
810 DP83869_DEVADDR, DP83869_IO_MUX_CFG,
811 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
812 dp83869->clk_output_sel <<
813 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
814
815 if (phy_interface_is_rgmii(phydev)) {
816 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
817 dp83869->rx_int_delay |
818 dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT);
819 if (ret)
820 return ret;
821
822 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
823 val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
824 DP83869_RGMII_RX_CLK_DELAY_EN);
825
826 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
827 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
828 DP83869_RGMII_RX_CLK_DELAY_EN);
829
830 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
831 val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
832
833 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
834 val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
835
836 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
837 val);
838 }
839
840 return ret;
841}
842
843static int dp83869_probe(struct phy_device *phydev)
844{
845 struct dp83869_private *dp83869;
846 int ret;
847
848 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
849 GFP_KERNEL);
850 if (!dp83869)
851 return -ENOMEM;
852
853 phydev->priv = dp83869;
854
855 ret = dp83869_of_init(phydev);
856 if (ret)
857 return ret;
858
859 if (dp83869->mode == DP83869_RGMII_100_BASE ||
860 dp83869->mode == DP83869_RGMII_1000_BASE)
861 phydev->port = PORT_FIBRE;
862
863 return dp83869_config_init(phydev);
864}
865
866static int dp83869_phy_reset(struct phy_device *phydev)
867{
868 int ret;
869
870 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
871 if (ret < 0)
872 return ret;
873
874 usleep_range(10, 20);
875
876 /* Global sw reset sets all registers to default.
877 * Need to set the registers in the PHY to the right config.
878 */
879 return dp83869_config_init(phydev);
880}
881
882
883#define DP83869_PHY_DRIVER(_id, _name) \
884{ \
885 PHY_ID_MATCH_MODEL(_id), \
886 .name = (_name), \
887 .probe = dp83869_probe, \
888 .config_init = dp83869_config_init, \
889 .soft_reset = dp83869_phy_reset, \
890 .config_intr = dp83869_config_intr, \
891 .handle_interrupt = dp83869_handle_interrupt, \
892 .read_status = dp83869_read_status, \
893 .get_tunable = dp83869_get_tunable, \
894 .set_tunable = dp83869_set_tunable, \
895 .get_wol = dp83869_get_wol, \
896 .set_wol = dp83869_set_wol, \
897 .suspend = genphy_suspend, \
898 .resume = genphy_resume, \
899}
900
901static struct phy_driver dp83869_driver[] = {
902 DP83869_PHY_DRIVER(DP83869_PHY_ID, "TI DP83869"),
903 DP83869_PHY_DRIVER(DP83561_PHY_ID, "TI DP83561-SP"),
904
905};
906module_phy_driver(dp83869_driver);
907
908static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
909 { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) },
910 { PHY_ID_MATCH_MODEL(DP83561_PHY_ID) },
911 { }
912};
913MODULE_DEVICE_TABLE(mdio, dp83869_tbl);
914
915MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver");
916MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
917MODULE_LICENSE("GPL v2");