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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Texas Instruments ICSSG Ethernet driver
3 *
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 */
7
8#ifndef __NET_TI_ICSSG_SWITCH_MAP_H
9#define __NET_TI_ICSSG_SWITCH_MAP_H
10
11/************************* Ethernet Switch Constants *********************/
12
13/* if bucket size is changed in firmware then this too should be changed
14 * because it directly impacts FDB ageing calculation
15 */
16#define NUMBER_OF_FDB_BUCKET_ENTRIES (4)
17
18/* This is fixed in ICSSG */
19#define SIZE_OF_FDB (2048)
20
21#define FW_LINK_SPEED_1G (0x00)
22#define FW_LINK_SPEED_100M (0x01)
23#define FW_LINK_SPEED_10M (0x02)
24#define FW_LINK_SPEED_HD (0x80)
25
26/* Time after which FDB entries are checked for aged out values.
27 * Values are in nanoseconds
28 */
29#define FDB_AGEING_TIMEOUT_OFFSET 0x0014
30
31/* Default VLAN tag for Host Port */
32#define HOST_PORT_DF_VLAN_OFFSET 0x001C
33
34/* Same as HOST_PORT_DF_VLAN_OFFSET */
35#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET
36
37/* Default VLAN tag for P1 Port */
38#define P1_PORT_DF_VLAN_OFFSET 0x0020
39
40/* Same as P1_PORT_DF_VLAN_OFFSET */
41#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET
42
43/* default VLAN tag for P2 Port */
44#define P2_PORT_DF_VLAN_OFFSET 0x0024
45
46/* Same as P2_PORT_DF_VLAN_OFFSET */
47#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET
48
49/* VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000 */
50#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100
51
52/* VLAN-FID Table offset for EMAC */
53#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET
54
55/* Packet descriptor Q reserved memory */
56#define PORT_DESC0_HI 0x2104
57
58/* Packet descriptor Q reserved memory */
59#define PORT_DESC0_LO 0x2F6C
60
61/* Packet descriptor Q reserved memory */
62#define PORT_DESC1_HI 0x3DD4
63
64/* Packet descriptor Q reserved memory */
65#define PORT_DESC1_LO 0x4C3C
66
67/* Packet descriptor Q reserved memory */
68#define HOST_DESC0_HI 0x5AA4
69
70/* Packet descriptor Q reserved memory */
71#define HOST_DESC0_LO 0x5F0C
72
73/* Packet descriptor Q reserved memory */
74#define HOST_DESC1_HI 0x6374
75
76/* Packet descriptor Q reserved memory */
77#define HOST_DESC1_LO 0x67DC
78
79/* Special packet descriptor Q reserved memory */
80#define HOST_SPPD0 0x7AAC
81
82/* Special acket descriptor Q reserved memory */
83#define HOST_SPPD1 0x7EAC
84
85/* IEP count cycle counter*/
86#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC
87
88/* IEP count hi roll over count */
89#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4
90
91/* IEP count hi sw counter */
92#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8
93
94/* Set clock descriptor */
95#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC
96
97/* IEP count syncout reduction factor */
98#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C
99
100/* IEP count syncout reduction counter */
101#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440
102
103/* IEP count syncout start time cycle counter */
104#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444
105
106/* Control variable to generate SYNC1 */
107#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C
108
109/* SystemTime Sync0 periodicity */
110#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450
111
112/* pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay */
113#define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET 0x8454
114
115/* pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay */
116#define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET 0x8458
117
118/* Set clock operation done signal for next task */
119#define TIMESYNC_FW_SIG_PNFW_OFFSET 0x845C
120
121/* Set clock operation done signal for next task */
122#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460
123
124/* New list is copied at this time */
125#define TAS_CONFIG_CHANGE_TIME 0x000C
126
127/* config change error counter */
128#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014
129
130/* TAS List update pending flag */
131#define TAS_CONFIG_PENDING 0x0018
132
133/* TAS list update trigger flag */
134#define TAS_CONFIG_CHANGE 0x0019
135
136/* List length for new TAS schedule */
137#define TAS_ADMIN_LIST_LENGTH 0x001A
138
139/* Currently active TAS list index */
140#define TAS_ACTIVE_LIST_INDEX 0x001B
141
142/* Cycle time for the new TAS schedule */
143#define TAS_ADMIN_CYCLE_TIME 0x001C
144
145/* Cycle counts remaining till the TAS list update */
146#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020
147
148/* Base Flow ID for sending Packets to Host for Slice0 */
149#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024
150
151/* Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET */
152#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET
153
154/* Base Flow ID for sending mgmt and Tx TS to Host for Slice0 */
155#define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026
156
157/* Same as PSI_L_MGMT_FLOW_ID_OFFSET */
158#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET
159
160/* Queue number for Special Packets written here */
161#define SPL_PKT_DEFAULT_PRIORITY 0x0028
162
163/* Express Preemptible Queue Mask */
164#define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029
165
166/* Port1/Port2 Default Queue number for untagged Packets, only 1B is used */
167#define QUEUE_NUM_UNTAGGED 0x002A
168
169/* Stores the table used for priority regeneration. 1B per PCP/Queue */
170#define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C
171
172/* For marking Packet as priority/express (this feature is disabled) or
173 * cut-through/S&F.
174 */
175#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034
176
177/* Stores the table used for priority mapping. 1B per PCP/Queue */
178#define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C
179
180/* Used to notify the FW of the current link speed */
181#define PORT_LINK_SPEED_OFFSET 0x00A8
182
183/* TAS gate mask for windows list0 */
184#define TAS_GATE_MASK_LIST0 0x0100
185
186/* TAS gate mask for windows list1 */
187#define TAS_GATE_MASK_LIST1 0x0350
188
189/* Memory to Enable/Disable Preemption on TX side */
190#define PRE_EMPTION_ENABLE_TX 0x05A0
191
192/* Active State of Preemption on TX side */
193#define PRE_EMPTION_ACTIVE_TX 0x05A1
194
195/* Memory to Enable/Disable Verify State Machine Preemption */
196#define PRE_EMPTION_ENABLE_VERIFY 0x05A2
197
198/* Verify Status of State Machine */
199#define PRE_EMPTION_VERIFY_STATUS 0x05A3
200
201/* Non Final Fragment Size supported by Link Partner */
202#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4
203
204/* Non Final Fragment Size supported by Firmware */
205#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6
206
207/* Time in ms the State machine waits for respond Packet */
208#define PRE_EMPTION_VERIFY_TIME 0x05A8
209
210/* Memory used for R30 related management commands */
211#define MGR_R30_CMD_OFFSET 0x05AC
212
213/* HW Buffer Pool0 base address */
214#define BUFFER_POOL_0_ADDR_OFFSET 0x05BC
215
216/* 16B for Host Egress MSMC Q (Pre-emptible) context */
217#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684
218
219/* Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL' */
220#define FDB_CMD_BUFFER 0x0894
221
222/* TAS queue max sdu length list */
223#define TAS_QUEUE_MAX_SDU_LIST 0x08FA
224
225/* Used by FW to generate random number with the SEED value */
226#define HD_RAND_SEED_OFFSET 0x0934
227
228/* 16B for Host Egress MSMC Q (Express) context */
229#define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x0940
230
231/* Start of 32 bits PA_STAT counters */
232#define PA_STAT_32b_START_OFFSET 0x0080
233
234#endif /* __NET_TI_ICSSG_SWITCH_MAP_H */