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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * DaVinci MDIO Module driver
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
8 *
9 * Copyright (C) 2009 Texas Instruments.
10 *
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/phy.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/pm_runtime.h>
24#include <linux/davinci_emac.h>
25#include <linux/of.h>
26#include <linux/of_mdio.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/mdio-bitbang.h>
29#include <linux/sys_soc.h>
30
31/*
32 * This timeout definition is a worst-case ultra defensive measure against
33 * unexpected controller lock ups. Ideally, we should never ever hit this
34 * scenario in practice.
35 */
36#define MDIO_TIMEOUT 100 /* msecs */
37
38#define PHY_REG_MASK 0x1f
39#define PHY_ID_MASK 0x1f
40
41#define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
42
43struct davinci_mdio_of_param {
44 int autosuspend_delay_ms;
45 bool manual_mode;
46};
47
48struct davinci_mdio_regs {
49 u32 version;
50 u32 control;
51#define CONTROL_IDLE BIT(31)
52#define CONTROL_ENABLE BIT(30)
53#define CONTROL_MAX_DIV (0xffff)
54#define CONTROL_CLKDIV GENMASK(15, 0)
55
56#define MDIO_MAN_MDCLK_O BIT(2)
57#define MDIO_MAN_OE BIT(1)
58#define MDIO_MAN_PIN BIT(0)
59#define MDIO_MANUALMODE BIT(31)
60
61#define MDIO_PIN 0
62
63
64 u32 alive;
65 u32 link;
66 u32 linkintraw;
67 u32 linkintmasked;
68 u32 __reserved_0[2];
69 u32 userintraw;
70 u32 userintmasked;
71 u32 userintmaskset;
72 u32 userintmaskclr;
73 u32 manualif;
74 u32 poll;
75 u32 __reserved_1[18];
76
77 struct {
78 u32 access;
79#define USERACCESS_GO BIT(31)
80#define USERACCESS_WRITE BIT(30)
81#define USERACCESS_ACK BIT(29)
82#define USERACCESS_READ (0)
83#define USERACCESS_DATA (0xffff)
84
85 u32 physel;
86 } user[];
87};
88
89static const struct mdio_platform_data default_pdata = {
90 .bus_freq = DEF_OUT_FREQ,
91};
92
93struct davinci_mdio_data {
94 struct mdio_platform_data pdata;
95 struct mdiobb_ctrl bb_ctrl;
96 struct davinci_mdio_regs __iomem *regs;
97 struct clk *clk;
98 struct device *dev;
99 struct mii_bus *bus;
100 bool active_in_suspend;
101 unsigned long access_time; /* jiffies */
102 /* Indicates that driver shouldn't modify phy_mask in case
103 * if MDIO bus is registered from DT.
104 */
105 bool skip_scan;
106 u32 clk_div;
107 bool manual_mode;
108};
109
110static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
111{
112 u32 mdio_in, div, mdio_out_khz, access_time;
113
114 mdio_in = clk_get_rate(data->clk);
115 div = (mdio_in / data->pdata.bus_freq) - 1;
116 if (div > CONTROL_MAX_DIV)
117 div = CONTROL_MAX_DIV;
118
119 data->clk_div = div;
120 /*
121 * One mdio transaction consists of:
122 * 32 bits of preamble
123 * 32 bits of transferred data
124 * 24 bits of bus yield (not needed unless shared?)
125 */
126 mdio_out_khz = mdio_in / (1000 * (div + 1));
127 access_time = (88 * 1000) / mdio_out_khz;
128
129 /*
130 * In the worst case, we could be kicking off a user-access immediately
131 * after the mdio bus scan state-machine triggered its own read. If
132 * so, our request could get deferred by one access cycle. We
133 * defensively allow for 4 access cycles.
134 */
135 data->access_time = usecs_to_jiffies(access_time * 4);
136 if (!data->access_time)
137 data->access_time = 1;
138}
139
140static void davinci_mdio_enable(struct davinci_mdio_data *data)
141{
142 /* set enable and clock divider */
143 writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
144}
145
146static void davinci_mdio_disable(struct davinci_mdio_data *data)
147{
148 u32 reg;
149
150 /* Disable MDIO state machine */
151 reg = readl(&data->regs->control);
152
153 reg &= ~CONTROL_CLKDIV;
154 reg |= data->clk_div;
155
156 reg &= ~CONTROL_ENABLE;
157 writel(reg, &data->regs->control);
158}
159
160static void davinci_mdio_enable_manual_mode(struct davinci_mdio_data *data)
161{
162 u32 reg;
163 /* set manual mode */
164 reg = readl(&data->regs->poll);
165 reg |= MDIO_MANUALMODE;
166 writel(reg, &data->regs->poll);
167}
168
169static void davinci_set_mdc(struct mdiobb_ctrl *ctrl, int level)
170{
171 struct davinci_mdio_data *data;
172 u32 reg;
173
174 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
175 reg = readl(&data->regs->manualif);
176
177 if (level)
178 reg |= MDIO_MAN_MDCLK_O;
179 else
180 reg &= ~MDIO_MAN_MDCLK_O;
181
182 writel(reg, &data->regs->manualif);
183}
184
185static void davinci_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
186{
187 struct davinci_mdio_data *data;
188 u32 reg;
189
190 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
191 reg = readl(&data->regs->manualif);
192
193 if (output)
194 reg |= MDIO_MAN_OE;
195 else
196 reg &= ~MDIO_MAN_OE;
197
198 writel(reg, &data->regs->manualif);
199}
200
201static void davinci_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
202{
203 struct davinci_mdio_data *data;
204 u32 reg;
205
206 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
207 reg = readl(&data->regs->manualif);
208
209 if (value)
210 reg |= MDIO_MAN_PIN;
211 else
212 reg &= ~MDIO_MAN_PIN;
213
214 writel(reg, &data->regs->manualif);
215}
216
217static int davinci_get_mdio_data(struct mdiobb_ctrl *ctrl)
218{
219 struct davinci_mdio_data *data;
220 unsigned long reg;
221
222 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
223 reg = readl(&data->regs->manualif);
224 return test_bit(MDIO_PIN, ®);
225}
226
227static int davinci_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg)
228{
229 int ret;
230
231 ret = pm_runtime_resume_and_get(bus->parent);
232 if (ret < 0)
233 return ret;
234
235 ret = mdiobb_read_c22(bus, phy, reg);
236
237 pm_runtime_mark_last_busy(bus->parent);
238 pm_runtime_put_autosuspend(bus->parent);
239
240 return ret;
241}
242
243static int davinci_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg,
244 u16 val)
245{
246 int ret;
247
248 ret = pm_runtime_resume_and_get(bus->parent);
249 if (ret < 0)
250 return ret;
251
252 ret = mdiobb_write_c22(bus, phy, reg, val);
253
254 pm_runtime_mark_last_busy(bus->parent);
255 pm_runtime_put_autosuspend(bus->parent);
256
257 return ret;
258}
259
260static int davinci_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad,
261 int reg)
262{
263 int ret;
264
265 ret = pm_runtime_resume_and_get(bus->parent);
266 if (ret < 0)
267 return ret;
268
269 ret = mdiobb_read_c45(bus, phy, devad, reg);
270
271 pm_runtime_mark_last_busy(bus->parent);
272 pm_runtime_put_autosuspend(bus->parent);
273
274 return ret;
275}
276
277static int davinci_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad,
278 int reg, u16 val)
279{
280 int ret;
281
282 ret = pm_runtime_resume_and_get(bus->parent);
283 if (ret < 0)
284 return ret;
285
286 ret = mdiobb_write_c45(bus, phy, devad, reg, val);
287
288 pm_runtime_mark_last_busy(bus->parent);
289 pm_runtime_put_autosuspend(bus->parent);
290
291 return ret;
292}
293
294static int davinci_mdio_common_reset(struct davinci_mdio_data *data)
295{
296 u32 phy_mask, ver;
297 int ret;
298
299 ret = pm_runtime_resume_and_get(data->dev);
300 if (ret < 0)
301 return ret;
302
303 if (data->manual_mode) {
304 davinci_mdio_disable(data);
305 davinci_mdio_enable_manual_mode(data);
306 }
307
308 /* wait for scan logic to settle */
309 msleep(PHY_MAX_ADDR * data->access_time);
310
311 /* dump hardware version info */
312 ver = readl(&data->regs->version);
313 dev_info(data->dev,
314 "davinci mdio revision %d.%d, bus freq %ld\n",
315 (ver >> 8) & 0xff, ver & 0xff,
316 data->pdata.bus_freq);
317
318 if (data->skip_scan)
319 goto done;
320
321 /* get phy mask from the alive register */
322 phy_mask = readl(&data->regs->alive);
323 if (phy_mask) {
324 /* restrict mdio bus to live phys only */
325 dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
326 phy_mask = ~phy_mask;
327 } else {
328 /* desperately scan all phys */
329 dev_warn(data->dev, "no live phy, scanning all\n");
330 phy_mask = 0;
331 }
332 data->bus->phy_mask = phy_mask;
333
334done:
335 pm_runtime_mark_last_busy(data->dev);
336 pm_runtime_put_autosuspend(data->dev);
337
338 return 0;
339}
340
341static int davinci_mdio_reset(struct mii_bus *bus)
342{
343 struct davinci_mdio_data *data = bus->priv;
344
345 return davinci_mdio_common_reset(data);
346}
347
348static int davinci_mdiobb_reset(struct mii_bus *bus)
349{
350 struct mdiobb_ctrl *ctrl = bus->priv;
351 struct davinci_mdio_data *data;
352
353 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
354
355 return davinci_mdio_common_reset(data);
356}
357
358/* wait until hardware is ready for another user access */
359static inline int wait_for_user_access(struct davinci_mdio_data *data)
360{
361 struct davinci_mdio_regs __iomem *regs = data->regs;
362 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
363 u32 reg;
364
365 while (time_after(timeout, jiffies)) {
366 reg = readl(®s->user[0].access);
367 if ((reg & USERACCESS_GO) == 0)
368 return 0;
369
370 reg = readl(®s->control);
371 if ((reg & CONTROL_IDLE) == 0) {
372 usleep_range(100, 200);
373 continue;
374 }
375
376 /*
377 * An emac soft_reset may have clobbered the mdio controller's
378 * state machine. We need to reset and retry the current
379 * operation
380 */
381 dev_warn(data->dev, "resetting idled controller\n");
382 davinci_mdio_enable(data);
383 return -EAGAIN;
384 }
385
386 reg = readl(®s->user[0].access);
387 if ((reg & USERACCESS_GO) == 0)
388 return 0;
389
390 dev_err(data->dev, "timed out waiting for user access\n");
391 return -ETIMEDOUT;
392}
393
394/* wait until hardware state machine is idle */
395static inline int wait_for_idle(struct davinci_mdio_data *data)
396{
397 struct davinci_mdio_regs __iomem *regs = data->regs;
398 u32 val, ret;
399
400 ret = readl_poll_timeout(®s->control, val, val & CONTROL_IDLE,
401 0, MDIO_TIMEOUT * 1000);
402 if (ret)
403 dev_err(data->dev, "timed out waiting for idle\n");
404
405 return ret;
406}
407
408static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
409{
410 struct davinci_mdio_data *data = bus->priv;
411 u32 reg;
412 int ret;
413
414 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
415 return -EINVAL;
416
417 ret = pm_runtime_resume_and_get(data->dev);
418 if (ret < 0)
419 return ret;
420
421 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
422 (phy_id << 16));
423
424 while (1) {
425 ret = wait_for_user_access(data);
426 if (ret == -EAGAIN)
427 continue;
428 if (ret < 0)
429 break;
430
431 writel(reg, &data->regs->user[0].access);
432
433 ret = wait_for_user_access(data);
434 if (ret == -EAGAIN)
435 continue;
436 if (ret < 0)
437 break;
438
439 reg = readl(&data->regs->user[0].access);
440 ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
441 break;
442 }
443
444 pm_runtime_mark_last_busy(data->dev);
445 pm_runtime_put_autosuspend(data->dev);
446 return ret;
447}
448
449static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
450 int phy_reg, u16 phy_data)
451{
452 struct davinci_mdio_data *data = bus->priv;
453 u32 reg;
454 int ret;
455
456 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
457 return -EINVAL;
458
459 ret = pm_runtime_resume_and_get(data->dev);
460 if (ret < 0)
461 return ret;
462
463 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
464 (phy_id << 16) | (phy_data & USERACCESS_DATA));
465
466 while (1) {
467 ret = wait_for_user_access(data);
468 if (ret == -EAGAIN)
469 continue;
470 if (ret < 0)
471 break;
472
473 writel(reg, &data->regs->user[0].access);
474
475 ret = wait_for_user_access(data);
476 if (ret == -EAGAIN)
477 continue;
478 break;
479 }
480
481 pm_runtime_mark_last_busy(data->dev);
482 pm_runtime_put_autosuspend(data->dev);
483
484 return ret;
485}
486
487static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
488 struct platform_device *pdev)
489{
490 struct device_node *node = pdev->dev.of_node;
491 u32 prop;
492
493 if (!node)
494 return -EINVAL;
495
496 if (of_property_read_u32(node, "bus_freq", &prop)) {
497 dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
498 return -EINVAL;
499 }
500 data->bus_freq = prop;
501
502 return 0;
503}
504
505struct k3_mdio_soc_data {
506 bool manual_mode;
507};
508
509static const struct k3_mdio_soc_data am65_mdio_soc_data = {
510 .manual_mode = true,
511};
512
513static const struct soc_device_attribute k3_mdio_socinfo[] = {
514 { .family = "AM62X", .data = &am65_mdio_soc_data },
515 { .family = "AM64X", .data = &am65_mdio_soc_data },
516 { .family = "AM65X", .data = &am65_mdio_soc_data },
517 { .family = "J7200", .data = &am65_mdio_soc_data },
518 { .family = "J721E", .data = &am65_mdio_soc_data },
519 { .family = "J721S2", .data = &am65_mdio_soc_data },
520 { /* sentinel */ },
521};
522
523#if IS_ENABLED(CONFIG_OF)
524static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
525 .autosuspend_delay_ms = 100,
526};
527
528static const struct of_device_id davinci_mdio_of_mtable[] = {
529 { .compatible = "ti,davinci_mdio", },
530 { .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
531 { /* sentinel */ },
532};
533MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
534#endif
535
536static const struct mdiobb_ops davinci_mdiobb_ops = {
537 .owner = THIS_MODULE,
538 .set_mdc = davinci_set_mdc,
539 .set_mdio_dir = davinci_set_mdio_dir,
540 .set_mdio_data = davinci_set_mdio_data,
541 .get_mdio_data = davinci_get_mdio_data,
542};
543
544static int davinci_mdio_probe(struct platform_device *pdev)
545{
546 struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
547 struct device *dev = &pdev->dev;
548 struct davinci_mdio_data *data;
549 struct resource *res;
550 struct phy_device *phy;
551 int ret, addr;
552 int autosuspend_delay_ms = -1;
553
554 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
555 if (!data)
556 return -ENOMEM;
557
558 data->manual_mode = false;
559 data->bb_ctrl.ops = &davinci_mdiobb_ops;
560
561 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
562 const struct soc_device_attribute *soc_match_data;
563
564 soc_match_data = soc_device_match(k3_mdio_socinfo);
565 if (soc_match_data && soc_match_data->data) {
566 const struct k3_mdio_soc_data *socdata =
567 soc_match_data->data;
568
569 data->manual_mode = socdata->manual_mode;
570 }
571 }
572
573 if (data->manual_mode)
574 data->bus = alloc_mdio_bitbang(&data->bb_ctrl);
575 else
576 data->bus = devm_mdiobus_alloc(dev);
577
578 if (!data->bus) {
579 dev_err(dev, "failed to alloc mii bus\n");
580 return -ENOMEM;
581 }
582
583 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
584 const struct davinci_mdio_of_param *of_mdio_data;
585
586 ret = davinci_mdio_probe_dt(&data->pdata, pdev);
587 if (ret)
588 return ret;
589 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
590
591 of_mdio_data = of_device_get_match_data(&pdev->dev);
592 if (of_mdio_data) {
593 autosuspend_delay_ms =
594 of_mdio_data->autosuspend_delay_ms;
595 }
596 } else {
597 data->pdata = pdata ? (*pdata) : default_pdata;
598 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
599 pdev->name, pdev->id);
600 }
601
602 data->bus->name = dev_name(dev);
603
604 if (data->manual_mode) {
605 data->bus->read = davinci_mdiobb_read_c22;
606 data->bus->write = davinci_mdiobb_write_c22;
607 data->bus->read_c45 = davinci_mdiobb_read_c45;
608 data->bus->write_c45 = davinci_mdiobb_write_c45;
609 data->bus->reset = davinci_mdiobb_reset;
610
611 dev_info(dev, "Configuring MDIO in manual mode\n");
612 } else {
613 data->bus->read = davinci_mdio_read;
614 data->bus->write = davinci_mdio_write;
615 data->bus->reset = davinci_mdio_reset;
616 data->bus->priv = data;
617 }
618 data->bus->parent = dev;
619
620 data->clk = devm_clk_get(dev, "fck");
621 if (IS_ERR(data->clk)) {
622 dev_err(dev, "failed to get device clock\n");
623 return PTR_ERR(data->clk);
624 }
625
626 dev_set_drvdata(dev, data);
627 data->dev = dev;
628
629 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
630 if (!res)
631 return -EINVAL;
632 data->regs = devm_ioremap(dev, res->start, resource_size(res));
633 if (!data->regs)
634 return -ENOMEM;
635
636 davinci_mdio_init_clk(data);
637
638 pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
639 pm_runtime_use_autosuspend(&pdev->dev);
640 pm_runtime_enable(&pdev->dev);
641
642 /* register the mii bus
643 * Create PHYs from DT only in case if PHY child nodes are explicitly
644 * defined to support backward compatibility with DTs which assume that
645 * Davinci MDIO will always scan the bus for PHYs detection.
646 */
647 if (dev->of_node && of_get_child_count(dev->of_node))
648 data->skip_scan = true;
649
650 ret = of_mdiobus_register(data->bus, dev->of_node);
651 if (ret)
652 goto bail_out;
653
654 /* scan and dump the bus */
655 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
656 phy = mdiobus_get_phy(data->bus, addr);
657 if (phy) {
658 dev_info(dev, "phy[%d]: device %s, driver %s\n",
659 phy->mdio.addr, phydev_name(phy),
660 phy->drv ? phy->drv->name : "unknown");
661 }
662 }
663
664 return 0;
665
666bail_out:
667 pm_runtime_dont_use_autosuspend(&pdev->dev);
668 pm_runtime_disable(&pdev->dev);
669 return ret;
670}
671
672static void davinci_mdio_remove(struct platform_device *pdev)
673{
674 struct davinci_mdio_data *data = platform_get_drvdata(pdev);
675
676 if (data->bus) {
677 mdiobus_unregister(data->bus);
678
679 if (data->manual_mode)
680 free_mdio_bitbang(data->bus);
681 }
682
683 pm_runtime_dont_use_autosuspend(&pdev->dev);
684 pm_runtime_disable(&pdev->dev);
685}
686
687#ifdef CONFIG_PM
688static int davinci_mdio_runtime_suspend(struct device *dev)
689{
690 struct davinci_mdio_data *data = dev_get_drvdata(dev);
691 u32 ctrl;
692
693 /* shutdown the scan state machine */
694 ctrl = readl(&data->regs->control);
695 ctrl &= ~CONTROL_ENABLE;
696 writel(ctrl, &data->regs->control);
697
698 if (!data->manual_mode)
699 wait_for_idle(data);
700
701 return 0;
702}
703
704static int davinci_mdio_runtime_resume(struct device *dev)
705{
706 struct davinci_mdio_data *data = dev_get_drvdata(dev);
707
708 if (data->manual_mode) {
709 davinci_mdio_disable(data);
710 davinci_mdio_enable_manual_mode(data);
711 } else {
712 davinci_mdio_enable(data);
713 }
714 return 0;
715}
716#endif
717
718#ifdef CONFIG_PM_SLEEP
719static int davinci_mdio_suspend(struct device *dev)
720{
721 struct davinci_mdio_data *data = dev_get_drvdata(dev);
722 int ret = 0;
723
724 data->active_in_suspend = !pm_runtime_status_suspended(dev);
725 if (data->active_in_suspend)
726 ret = pm_runtime_force_suspend(dev);
727 if (ret < 0)
728 return ret;
729
730 /* Select sleep pin state */
731 pinctrl_pm_select_sleep_state(dev);
732
733 return 0;
734}
735
736static int davinci_mdio_resume(struct device *dev)
737{
738 struct davinci_mdio_data *data = dev_get_drvdata(dev);
739
740 /* Select default pin state */
741 pinctrl_pm_select_default_state(dev);
742
743 if (data->active_in_suspend)
744 pm_runtime_force_resume(dev);
745
746 return 0;
747}
748#endif
749
750static const struct dev_pm_ops davinci_mdio_pm_ops = {
751 SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
752 davinci_mdio_runtime_resume, NULL)
753 SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
754};
755
756static struct platform_driver davinci_mdio_driver = {
757 .driver = {
758 .name = "davinci_mdio",
759 .pm = &davinci_mdio_pm_ops,
760 .of_match_table = of_match_ptr(davinci_mdio_of_mtable),
761 },
762 .probe = davinci_mdio_probe,
763 .remove = davinci_mdio_remove,
764};
765
766static int __init davinci_mdio_init(void)
767{
768 return platform_driver_register(&davinci_mdio_driver);
769}
770device_initcall(davinci_mdio_init);
771
772static void __exit davinci_mdio_exit(void)
773{
774 platform_driver_unregister(&davinci_mdio_driver);
775}
776module_exit(davinci_mdio_exit);
777
778MODULE_LICENSE("GPL");
779MODULE_DESCRIPTION("DaVinci MDIO driver");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * DaVinci MDIO Module driver
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
8 *
9 * Copyright (C) 2009 Texas Instruments.
10 *
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/phy.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/pm_runtime.h>
24#include <linux/davinci_emac.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/of_mdio.h>
28#include <linux/pinctrl/consumer.h>
29#include <linux/mdio-bitbang.h>
30#include <linux/sys_soc.h>
31
32/*
33 * This timeout definition is a worst-case ultra defensive measure against
34 * unexpected controller lock ups. Ideally, we should never ever hit this
35 * scenario in practice.
36 */
37#define MDIO_TIMEOUT 100 /* msecs */
38
39#define PHY_REG_MASK 0x1f
40#define PHY_ID_MASK 0x1f
41
42#define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
43
44struct davinci_mdio_of_param {
45 int autosuspend_delay_ms;
46 bool manual_mode;
47};
48
49struct davinci_mdio_regs {
50 u32 version;
51 u32 control;
52#define CONTROL_IDLE BIT(31)
53#define CONTROL_ENABLE BIT(30)
54#define CONTROL_MAX_DIV (0xffff)
55#define CONTROL_CLKDIV GENMASK(15, 0)
56
57#define MDIO_MAN_MDCLK_O BIT(2)
58#define MDIO_MAN_OE BIT(1)
59#define MDIO_MAN_PIN BIT(0)
60#define MDIO_MANUALMODE BIT(31)
61
62#define MDIO_PIN 0
63
64
65 u32 alive;
66 u32 link;
67 u32 linkintraw;
68 u32 linkintmasked;
69 u32 __reserved_0[2];
70 u32 userintraw;
71 u32 userintmasked;
72 u32 userintmaskset;
73 u32 userintmaskclr;
74 u32 manualif;
75 u32 poll;
76 u32 __reserved_1[18];
77
78 struct {
79 u32 access;
80#define USERACCESS_GO BIT(31)
81#define USERACCESS_WRITE BIT(30)
82#define USERACCESS_ACK BIT(29)
83#define USERACCESS_READ (0)
84#define USERACCESS_DATA (0xffff)
85
86 u32 physel;
87 } user[];
88};
89
90static const struct mdio_platform_data default_pdata = {
91 .bus_freq = DEF_OUT_FREQ,
92};
93
94struct davinci_mdio_data {
95 struct mdio_platform_data pdata;
96 struct mdiobb_ctrl bb_ctrl;
97 struct davinci_mdio_regs __iomem *regs;
98 struct clk *clk;
99 struct device *dev;
100 struct mii_bus *bus;
101 bool active_in_suspend;
102 unsigned long access_time; /* jiffies */
103 /* Indicates that driver shouldn't modify phy_mask in case
104 * if MDIO bus is registered from DT.
105 */
106 bool skip_scan;
107 u32 clk_div;
108 bool manual_mode;
109};
110
111static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
112{
113 u32 mdio_in, div, mdio_out_khz, access_time;
114
115 mdio_in = clk_get_rate(data->clk);
116 div = (mdio_in / data->pdata.bus_freq) - 1;
117 if (div > CONTROL_MAX_DIV)
118 div = CONTROL_MAX_DIV;
119
120 data->clk_div = div;
121 /*
122 * One mdio transaction consists of:
123 * 32 bits of preamble
124 * 32 bits of transferred data
125 * 24 bits of bus yield (not needed unless shared?)
126 */
127 mdio_out_khz = mdio_in / (1000 * (div + 1));
128 access_time = (88 * 1000) / mdio_out_khz;
129
130 /*
131 * In the worst case, we could be kicking off a user-access immediately
132 * after the mdio bus scan state-machine triggered its own read. If
133 * so, our request could get deferred by one access cycle. We
134 * defensively allow for 4 access cycles.
135 */
136 data->access_time = usecs_to_jiffies(access_time * 4);
137 if (!data->access_time)
138 data->access_time = 1;
139}
140
141static void davinci_mdio_enable(struct davinci_mdio_data *data)
142{
143 /* set enable and clock divider */
144 writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
145}
146
147static void davinci_mdio_disable(struct davinci_mdio_data *data)
148{
149 u32 reg;
150
151 /* Disable MDIO state machine */
152 reg = readl(&data->regs->control);
153
154 reg &= ~CONTROL_CLKDIV;
155 reg |= data->clk_div;
156
157 reg &= ~CONTROL_ENABLE;
158 writel(reg, &data->regs->control);
159}
160
161static void davinci_mdio_enable_manual_mode(struct davinci_mdio_data *data)
162{
163 u32 reg;
164 /* set manual mode */
165 reg = readl(&data->regs->poll);
166 reg |= MDIO_MANUALMODE;
167 writel(reg, &data->regs->poll);
168}
169
170static void davinci_set_mdc(struct mdiobb_ctrl *ctrl, int level)
171{
172 struct davinci_mdio_data *data;
173 u32 reg;
174
175 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
176 reg = readl(&data->regs->manualif);
177
178 if (level)
179 reg |= MDIO_MAN_MDCLK_O;
180 else
181 reg &= ~MDIO_MAN_MDCLK_O;
182
183 writel(reg, &data->regs->manualif);
184}
185
186static void davinci_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
187{
188 struct davinci_mdio_data *data;
189 u32 reg;
190
191 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
192 reg = readl(&data->regs->manualif);
193
194 if (output)
195 reg |= MDIO_MAN_OE;
196 else
197 reg &= ~MDIO_MAN_OE;
198
199 writel(reg, &data->regs->manualif);
200}
201
202static void davinci_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
203{
204 struct davinci_mdio_data *data;
205 u32 reg;
206
207 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
208 reg = readl(&data->regs->manualif);
209
210 if (value)
211 reg |= MDIO_MAN_PIN;
212 else
213 reg &= ~MDIO_MAN_PIN;
214
215 writel(reg, &data->regs->manualif);
216}
217
218static int davinci_get_mdio_data(struct mdiobb_ctrl *ctrl)
219{
220 struct davinci_mdio_data *data;
221 unsigned long reg;
222
223 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
224 reg = readl(&data->regs->manualif);
225 return test_bit(MDIO_PIN, ®);
226}
227
228static int davinci_mdiobb_read(struct mii_bus *bus, int phy, int reg)
229{
230 int ret;
231
232 ret = pm_runtime_resume_and_get(bus->parent);
233 if (ret < 0)
234 return ret;
235
236 ret = mdiobb_read(bus, phy, reg);
237
238 pm_runtime_mark_last_busy(bus->parent);
239 pm_runtime_put_autosuspend(bus->parent);
240
241 return ret;
242}
243
244static int davinci_mdiobb_write(struct mii_bus *bus, int phy, int reg,
245 u16 val)
246{
247 int ret;
248
249 ret = pm_runtime_resume_and_get(bus->parent);
250 if (ret < 0)
251 return ret;
252
253 ret = mdiobb_write(bus, phy, reg, val);
254
255 pm_runtime_mark_last_busy(bus->parent);
256 pm_runtime_put_autosuspend(bus->parent);
257
258 return ret;
259}
260
261static int davinci_mdio_common_reset(struct davinci_mdio_data *data)
262{
263 u32 phy_mask, ver;
264 int ret;
265
266 ret = pm_runtime_resume_and_get(data->dev);
267 if (ret < 0)
268 return ret;
269
270 if (data->manual_mode) {
271 davinci_mdio_disable(data);
272 davinci_mdio_enable_manual_mode(data);
273 }
274
275 /* wait for scan logic to settle */
276 msleep(PHY_MAX_ADDR * data->access_time);
277
278 /* dump hardware version info */
279 ver = readl(&data->regs->version);
280 dev_info(data->dev,
281 "davinci mdio revision %d.%d, bus freq %ld\n",
282 (ver >> 8) & 0xff, ver & 0xff,
283 data->pdata.bus_freq);
284
285 if (data->skip_scan)
286 goto done;
287
288 /* get phy mask from the alive register */
289 phy_mask = readl(&data->regs->alive);
290 if (phy_mask) {
291 /* restrict mdio bus to live phys only */
292 dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
293 phy_mask = ~phy_mask;
294 } else {
295 /* desperately scan all phys */
296 dev_warn(data->dev, "no live phy, scanning all\n");
297 phy_mask = 0;
298 }
299 data->bus->phy_mask = phy_mask;
300
301done:
302 pm_runtime_mark_last_busy(data->dev);
303 pm_runtime_put_autosuspend(data->dev);
304
305 return 0;
306}
307
308static int davinci_mdio_reset(struct mii_bus *bus)
309{
310 struct davinci_mdio_data *data = bus->priv;
311
312 return davinci_mdio_common_reset(data);
313}
314
315static int davinci_mdiobb_reset(struct mii_bus *bus)
316{
317 struct mdiobb_ctrl *ctrl = bus->priv;
318 struct davinci_mdio_data *data;
319
320 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
321
322 return davinci_mdio_common_reset(data);
323}
324
325/* wait until hardware is ready for another user access */
326static inline int wait_for_user_access(struct davinci_mdio_data *data)
327{
328 struct davinci_mdio_regs __iomem *regs = data->regs;
329 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
330 u32 reg;
331
332 while (time_after(timeout, jiffies)) {
333 reg = readl(®s->user[0].access);
334 if ((reg & USERACCESS_GO) == 0)
335 return 0;
336
337 reg = readl(®s->control);
338 if ((reg & CONTROL_IDLE) == 0) {
339 usleep_range(100, 200);
340 continue;
341 }
342
343 /*
344 * An emac soft_reset may have clobbered the mdio controller's
345 * state machine. We need to reset and retry the current
346 * operation
347 */
348 dev_warn(data->dev, "resetting idled controller\n");
349 davinci_mdio_enable(data);
350 return -EAGAIN;
351 }
352
353 reg = readl(®s->user[0].access);
354 if ((reg & USERACCESS_GO) == 0)
355 return 0;
356
357 dev_err(data->dev, "timed out waiting for user access\n");
358 return -ETIMEDOUT;
359}
360
361/* wait until hardware state machine is idle */
362static inline int wait_for_idle(struct davinci_mdio_data *data)
363{
364 struct davinci_mdio_regs __iomem *regs = data->regs;
365 u32 val, ret;
366
367 ret = readl_poll_timeout(®s->control, val, val & CONTROL_IDLE,
368 0, MDIO_TIMEOUT * 1000);
369 if (ret)
370 dev_err(data->dev, "timed out waiting for idle\n");
371
372 return ret;
373}
374
375static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
376{
377 struct davinci_mdio_data *data = bus->priv;
378 u32 reg;
379 int ret;
380
381 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
382 return -EINVAL;
383
384 ret = pm_runtime_resume_and_get(data->dev);
385 if (ret < 0)
386 return ret;
387
388 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
389 (phy_id << 16));
390
391 while (1) {
392 ret = wait_for_user_access(data);
393 if (ret == -EAGAIN)
394 continue;
395 if (ret < 0)
396 break;
397
398 writel(reg, &data->regs->user[0].access);
399
400 ret = wait_for_user_access(data);
401 if (ret == -EAGAIN)
402 continue;
403 if (ret < 0)
404 break;
405
406 reg = readl(&data->regs->user[0].access);
407 ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
408 break;
409 }
410
411 pm_runtime_mark_last_busy(data->dev);
412 pm_runtime_put_autosuspend(data->dev);
413 return ret;
414}
415
416static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
417 int phy_reg, u16 phy_data)
418{
419 struct davinci_mdio_data *data = bus->priv;
420 u32 reg;
421 int ret;
422
423 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
424 return -EINVAL;
425
426 ret = pm_runtime_resume_and_get(data->dev);
427 if (ret < 0)
428 return ret;
429
430 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
431 (phy_id << 16) | (phy_data & USERACCESS_DATA));
432
433 while (1) {
434 ret = wait_for_user_access(data);
435 if (ret == -EAGAIN)
436 continue;
437 if (ret < 0)
438 break;
439
440 writel(reg, &data->regs->user[0].access);
441
442 ret = wait_for_user_access(data);
443 if (ret == -EAGAIN)
444 continue;
445 break;
446 }
447
448 pm_runtime_mark_last_busy(data->dev);
449 pm_runtime_put_autosuspend(data->dev);
450
451 return ret;
452}
453
454static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
455 struct platform_device *pdev)
456{
457 struct device_node *node = pdev->dev.of_node;
458 u32 prop;
459
460 if (!node)
461 return -EINVAL;
462
463 if (of_property_read_u32(node, "bus_freq", &prop)) {
464 dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
465 return -EINVAL;
466 }
467 data->bus_freq = prop;
468
469 return 0;
470}
471
472struct k3_mdio_soc_data {
473 bool manual_mode;
474};
475
476static const struct k3_mdio_soc_data am65_mdio_soc_data = {
477 .manual_mode = true,
478};
479
480static const struct soc_device_attribute k3_mdio_socinfo[] = {
481 { .family = "AM62X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
482 { .family = "AM64X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
483 { .family = "AM64X", .revision = "SR2.0", .data = &am65_mdio_soc_data },
484 { .family = "AM65X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
485 { .family = "AM65X", .revision = "SR2.0", .data = &am65_mdio_soc_data },
486 { .family = "J7200", .revision = "SR1.0", .data = &am65_mdio_soc_data },
487 { .family = "J7200", .revision = "SR2.0", .data = &am65_mdio_soc_data },
488 { .family = "J721E", .revision = "SR1.0", .data = &am65_mdio_soc_data },
489 { .family = "J721E", .revision = "SR2.0", .data = &am65_mdio_soc_data },
490 { .family = "J721S2", .revision = "SR1.0", .data = &am65_mdio_soc_data},
491 { /* sentinel */ },
492};
493
494#if IS_ENABLED(CONFIG_OF)
495static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
496 .autosuspend_delay_ms = 100,
497};
498
499static const struct of_device_id davinci_mdio_of_mtable[] = {
500 { .compatible = "ti,davinci_mdio", },
501 { .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
502 { /* sentinel */ },
503};
504MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
505#endif
506
507static const struct mdiobb_ops davinci_mdiobb_ops = {
508 .owner = THIS_MODULE,
509 .set_mdc = davinci_set_mdc,
510 .set_mdio_dir = davinci_set_mdio_dir,
511 .set_mdio_data = davinci_set_mdio_data,
512 .get_mdio_data = davinci_get_mdio_data,
513};
514
515static int davinci_mdio_probe(struct platform_device *pdev)
516{
517 struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
518 struct device *dev = &pdev->dev;
519 struct davinci_mdio_data *data;
520 struct resource *res;
521 struct phy_device *phy;
522 int ret, addr;
523 int autosuspend_delay_ms = -1;
524
525 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
526 if (!data)
527 return -ENOMEM;
528
529 data->manual_mode = false;
530 data->bb_ctrl.ops = &davinci_mdiobb_ops;
531
532 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
533 const struct soc_device_attribute *soc_match_data;
534
535 soc_match_data = soc_device_match(k3_mdio_socinfo);
536 if (soc_match_data && soc_match_data->data) {
537 const struct k3_mdio_soc_data *socdata =
538 soc_match_data->data;
539
540 data->manual_mode = socdata->manual_mode;
541 }
542 }
543
544 if (data->manual_mode)
545 data->bus = alloc_mdio_bitbang(&data->bb_ctrl);
546 else
547 data->bus = devm_mdiobus_alloc(dev);
548
549 if (!data->bus) {
550 dev_err(dev, "failed to alloc mii bus\n");
551 return -ENOMEM;
552 }
553
554 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
555 const struct davinci_mdio_of_param *of_mdio_data;
556
557 ret = davinci_mdio_probe_dt(&data->pdata, pdev);
558 if (ret)
559 return ret;
560 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
561
562 of_mdio_data = of_device_get_match_data(&pdev->dev);
563 if (of_mdio_data) {
564 autosuspend_delay_ms =
565 of_mdio_data->autosuspend_delay_ms;
566 }
567 } else {
568 data->pdata = pdata ? (*pdata) : default_pdata;
569 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
570 pdev->name, pdev->id);
571 }
572
573 data->bus->name = dev_name(dev);
574
575 if (data->manual_mode) {
576 data->bus->read = davinci_mdiobb_read;
577 data->bus->write = davinci_mdiobb_write;
578 data->bus->reset = davinci_mdiobb_reset;
579
580 dev_info(dev, "Configuring MDIO in manual mode\n");
581 } else {
582 data->bus->read = davinci_mdio_read;
583 data->bus->write = davinci_mdio_write;
584 data->bus->reset = davinci_mdio_reset;
585 data->bus->priv = data;
586 }
587 data->bus->parent = dev;
588
589 data->clk = devm_clk_get(dev, "fck");
590 if (IS_ERR(data->clk)) {
591 dev_err(dev, "failed to get device clock\n");
592 return PTR_ERR(data->clk);
593 }
594
595 dev_set_drvdata(dev, data);
596 data->dev = dev;
597
598 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
599 if (!res)
600 return -EINVAL;
601 data->regs = devm_ioremap(dev, res->start, resource_size(res));
602 if (!data->regs)
603 return -ENOMEM;
604
605 davinci_mdio_init_clk(data);
606
607 pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
608 pm_runtime_use_autosuspend(&pdev->dev);
609 pm_runtime_enable(&pdev->dev);
610
611 /* register the mii bus
612 * Create PHYs from DT only in case if PHY child nodes are explicitly
613 * defined to support backward compatibility with DTs which assume that
614 * Davinci MDIO will always scan the bus for PHYs detection.
615 */
616 if (dev->of_node && of_get_child_count(dev->of_node))
617 data->skip_scan = true;
618
619 ret = of_mdiobus_register(data->bus, dev->of_node);
620 if (ret)
621 goto bail_out;
622
623 /* scan and dump the bus */
624 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
625 phy = mdiobus_get_phy(data->bus, addr);
626 if (phy) {
627 dev_info(dev, "phy[%d]: device %s, driver %s\n",
628 phy->mdio.addr, phydev_name(phy),
629 phy->drv ? phy->drv->name : "unknown");
630 }
631 }
632
633 return 0;
634
635bail_out:
636 pm_runtime_dont_use_autosuspend(&pdev->dev);
637 pm_runtime_disable(&pdev->dev);
638 return ret;
639}
640
641static int davinci_mdio_remove(struct platform_device *pdev)
642{
643 struct davinci_mdio_data *data = platform_get_drvdata(pdev);
644
645 if (data->bus) {
646 mdiobus_unregister(data->bus);
647
648 if (data->manual_mode)
649 free_mdio_bitbang(data->bus);
650 }
651
652 pm_runtime_dont_use_autosuspend(&pdev->dev);
653 pm_runtime_disable(&pdev->dev);
654
655 return 0;
656}
657
658#ifdef CONFIG_PM
659static int davinci_mdio_runtime_suspend(struct device *dev)
660{
661 struct davinci_mdio_data *data = dev_get_drvdata(dev);
662 u32 ctrl;
663
664 /* shutdown the scan state machine */
665 ctrl = readl(&data->regs->control);
666 ctrl &= ~CONTROL_ENABLE;
667 writel(ctrl, &data->regs->control);
668
669 if (!data->manual_mode)
670 wait_for_idle(data);
671
672 return 0;
673}
674
675static int davinci_mdio_runtime_resume(struct device *dev)
676{
677 struct davinci_mdio_data *data = dev_get_drvdata(dev);
678
679 if (data->manual_mode) {
680 davinci_mdio_disable(data);
681 davinci_mdio_enable_manual_mode(data);
682 } else {
683 davinci_mdio_enable(data);
684 }
685 return 0;
686}
687#endif
688
689#ifdef CONFIG_PM_SLEEP
690static int davinci_mdio_suspend(struct device *dev)
691{
692 struct davinci_mdio_data *data = dev_get_drvdata(dev);
693 int ret = 0;
694
695 data->active_in_suspend = !pm_runtime_status_suspended(dev);
696 if (data->active_in_suspend)
697 ret = pm_runtime_force_suspend(dev);
698 if (ret < 0)
699 return ret;
700
701 /* Select sleep pin state */
702 pinctrl_pm_select_sleep_state(dev);
703
704 return 0;
705}
706
707static int davinci_mdio_resume(struct device *dev)
708{
709 struct davinci_mdio_data *data = dev_get_drvdata(dev);
710
711 /* Select default pin state */
712 pinctrl_pm_select_default_state(dev);
713
714 if (data->active_in_suspend)
715 pm_runtime_force_resume(dev);
716
717 return 0;
718}
719#endif
720
721static const struct dev_pm_ops davinci_mdio_pm_ops = {
722 SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
723 davinci_mdio_runtime_resume, NULL)
724 SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
725};
726
727static struct platform_driver davinci_mdio_driver = {
728 .driver = {
729 .name = "davinci_mdio",
730 .pm = &davinci_mdio_pm_ops,
731 .of_match_table = of_match_ptr(davinci_mdio_of_mtable),
732 },
733 .probe = davinci_mdio_probe,
734 .remove = davinci_mdio_remove,
735};
736
737static int __init davinci_mdio_init(void)
738{
739 return platform_driver_register(&davinci_mdio_driver);
740}
741device_initcall(davinci_mdio_init);
742
743static void __exit davinci_mdio_exit(void)
744{
745 platform_driver_unregister(&davinci_mdio_driver);
746}
747module_exit(davinci_mdio_exit);
748
749MODULE_LICENSE("GPL");
750MODULE_DESCRIPTION("DaVinci MDIO driver");