1// SPDX-License-Identifier: GPL-2.0
   2/* Renesas Ethernet Switch device driver
   3 *
   4 * Copyright (C) 2022 Renesas Electronics Corporation
   5 */
   6
   7#include <linux/clk.h>
   8#include <linux/dma-mapping.h>
   9#include <linux/err.h>
  10#include <linux/etherdevice.h>
  11#include <linux/iopoll.h>
  12#include <linux/kernel.h>
  13#include <linux/module.h>
  14#include <linux/net_tstamp.h>
  15#include <linux/of.h>
 
 
  16#include <linux/of_mdio.h>
  17#include <linux/of_net.h>
 
  18#include <linux/phy/phy.h>
  19#include <linux/platform_device.h>
  20#include <linux/pm.h>
  21#include <linux/pm_runtime.h>
  22#include <linux/rtnetlink.h>
  23#include <linux/slab.h>
  24#include <linux/spinlock.h>
  25#include <linux/sys_soc.h>
  26
  27#include "rswitch.h"
  28
  29static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected)
  30{
  31	u32 val;
  32
  33	return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected,
  34					 1, RSWITCH_TIMEOUT_US);
  35}
  36
  37static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set)
  38{
  39	iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg);
  40}
  41
  42/* Common Agent block (COMA) */
  43static void rswitch_reset(struct rswitch_private *priv)
  44{
  45	iowrite32(RRC_RR, priv->addr + RRC);
  46	iowrite32(RRC_RR_CLR, priv->addr + RRC);
  47}
  48
  49static void rswitch_clock_enable(struct rswitch_private *priv)
  50{
  51	iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC);
  52}
  53
  54static void rswitch_clock_disable(struct rswitch_private *priv)
  55{
  56	iowrite32(RCDC_RCD, priv->addr + RCDC);
  57}
  58
  59static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr,
  60					   unsigned int port)
  61{
  62	u32 val = ioread32(coma_addr + RCEC);
  63
  64	if (val & RCEC_RCE)
  65		return (val & BIT(port)) ? true : false;
  66	else
  67		return false;
  68}
  69
  70static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, unsigned int port,
  71				     int enable)
  72{
  73	u32 val;
  74
  75	if (enable) {
  76		val = ioread32(coma_addr + RCEC);
  77		iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC);
  78	} else {
  79		val = ioread32(coma_addr + RCDC);
  80		iowrite32(val | BIT(port), coma_addr + RCDC);
  81	}
  82}
  83
  84static int rswitch_bpool_config(struct rswitch_private *priv)
  85{
  86	u32 val;
  87
  88	val = ioread32(priv->addr + CABPIRM);
  89	if (val & CABPIRM_BPR)
  90		return 0;
  91
  92	iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM);
  93
  94	return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR);
  95}
  96
  97static void rswitch_coma_init(struct rswitch_private *priv)
  98{
  99	iowrite32(CABPPFLC_INIT_VALUE, priv->addr + CABPPFLC0);
 100}
 101
 102/* R-Switch-2 block (TOP) */
 103static void rswitch_top_init(struct rswitch_private *priv)
 104{
 105	unsigned int i;
 106
 107	for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++)
 108		iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i));
 109}
 110
 111/* Forwarding engine block (MFWD) */
 112static void rswitch_fwd_init(struct rswitch_private *priv)
 113{
 114	unsigned int i;
 115
 116	/* For ETHA */
 117	for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
 118		iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i));
 119		iowrite32(0, priv->addr + FWPBFC(i));
 120	}
 121
 122	for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
 123		iowrite32(priv->rdev[i]->rx_queue->index,
 124			  priv->addr + FWPBFCSDC(GWCA_INDEX, i));
 125		iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i));
 126	}
 127
 128	/* For GWCA */
 129	iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index));
 130	iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index));
 131	iowrite32(0, priv->addr + FWPBFC(priv->gwca.index));
 132	iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index));
 133}
 134
 
 
 
 
 
 
 
 135/* Gateway CPU agent block (GWCA) */
 136static int rswitch_gwca_change_mode(struct rswitch_private *priv,
 137				    enum rswitch_gwca_mode mode)
 138{
 139	int ret;
 140
 141	if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index))
 142		rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1);
 143
 144	iowrite32(mode, priv->addr + GWMC);
 145
 146	ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode);
 147
 148	if (mode == GWMC_OPC_DISABLE)
 149		rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0);
 150
 151	return ret;
 152}
 153
 154static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv)
 155{
 156	iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM);
 157
 158	return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR);
 159}
 160
 161static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv)
 162{
 163	iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM);
 164
 165	return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR);
 166}
 167
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 168static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx)
 169{
 170	u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits;
 171	unsigned int i;
 172
 173	for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) {
 174		if (dis[i] & mask[i])
 175			return true;
 176	}
 177
 178	return false;
 179}
 180
 181static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis)
 182{
 183	unsigned int i;
 184
 185	for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) {
 186		dis[i] = ioread32(priv->addr + GWDIS(i));
 187		dis[i] &= ioread32(priv->addr + GWDIE(i));
 188	}
 189}
 190
 191static void rswitch_enadis_data_irq(struct rswitch_private *priv,
 192				    unsigned int index, bool enable)
 193{
 194	u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32);
 195
 196	iowrite32(BIT(index % 32), priv->addr + offs);
 197}
 198
 199static void rswitch_ack_data_irq(struct rswitch_private *priv,
 200				 unsigned int index)
 201{
 202	u32 offs = GWDIS(index / 32);
 203
 204	iowrite32(BIT(index % 32), priv->addr + offs);
 205}
 206
 207static unsigned int rswitch_next_queue_index(struct rswitch_gwca_queue *gq,
 208					     bool cur, unsigned int num)
 209{
 210	unsigned int index = cur ? gq->cur : gq->dirty;
 211
 212	if (index + num >= gq->ring_size)
 213		index = (index + num) % gq->ring_size;
 214	else
 215		index += num;
 216
 217	return index;
 218}
 219
 220static unsigned int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq)
 221{
 222	if (gq->cur >= gq->dirty)
 223		return gq->cur - gq->dirty;
 224	else
 225		return gq->ring_size - gq->dirty + gq->cur;
 226}
 227
 228static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq)
 229{
 230	struct rswitch_ext_ts_desc *desc = &gq->rx_ring[gq->dirty];
 231
 232	if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY)
 233		return true;
 234
 235	return false;
 236}
 237
 238static int rswitch_gwca_queue_alloc_rx_buf(struct rswitch_gwca_queue *gq,
 239					   unsigned int start_index,
 240					   unsigned int num)
 241{
 242	unsigned int i, index;
 243
 244	for (i = 0; i < num; i++) {
 245		index = (i + start_index) % gq->ring_size;
 246		if (gq->rx_bufs[index])
 247			continue;
 248		gq->rx_bufs[index] = netdev_alloc_frag(RSWITCH_BUF_SIZE);
 249		if (!gq->rx_bufs[index])
 
 250			goto err;
 251	}
 252
 253	return 0;
 254
 255err:
 256	for (; i-- > 0; ) {
 257		index = (i + start_index) % gq->ring_size;
 258		skb_free_frag(gq->rx_bufs[index]);
 259		gq->rx_bufs[index] = NULL;
 260	}
 261
 262	return -ENOMEM;
 263}
 264
 265static void rswitch_gwca_queue_free(struct net_device *ndev,
 266				    struct rswitch_gwca_queue *gq)
 267{
 268	unsigned int i;
 269
 270	if (!gq->dir_tx) {
 271		dma_free_coherent(ndev->dev.parent,
 272				  sizeof(struct rswitch_ext_ts_desc) *
 273				  (gq->ring_size + 1), gq->rx_ring, gq->ring_dma);
 274		gq->rx_ring = NULL;
 275
 276		for (i = 0; i < gq->ring_size; i++)
 277			skb_free_frag(gq->rx_bufs[i]);
 278		kfree(gq->rx_bufs);
 279		gq->rx_bufs = NULL;
 280	} else {
 281		dma_free_coherent(ndev->dev.parent,
 282				  sizeof(struct rswitch_ext_desc) *
 283				  (gq->ring_size + 1), gq->tx_ring, gq->ring_dma);
 284		gq->tx_ring = NULL;
 285		kfree(gq->skbs);
 286		gq->skbs = NULL;
 287		kfree(gq->unmap_addrs);
 288		gq->unmap_addrs = NULL;
 289	}
 290}
 291
 292static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv)
 293{
 294	struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue;
 
 295
 296	dma_free_coherent(&priv->pdev->dev,
 297			  sizeof(struct rswitch_ts_desc) * (gq->ring_size + 1),
 298			  gq->ts_ring, gq->ring_dma);
 299	gq->ts_ring = NULL;
 300}
 301
 302static int rswitch_gwca_queue_alloc(struct net_device *ndev,
 303				    struct rswitch_private *priv,
 304				    struct rswitch_gwca_queue *gq,
 305				    bool dir_tx, unsigned int ring_size)
 306{
 307	unsigned int i, bit;
 308
 309	gq->dir_tx = dir_tx;
 
 310	gq->ring_size = ring_size;
 311	gq->ndev = ndev;
 312
 313	if (!dir_tx) {
 314		gq->rx_bufs = kcalloc(gq->ring_size, sizeof(*gq->rx_bufs), GFP_KERNEL);
 315		if (!gq->rx_bufs)
 316			return -ENOMEM;
 317		if (rswitch_gwca_queue_alloc_rx_buf(gq, 0, gq->ring_size) < 0)
 318			goto out;
 319
 320		gq->rx_ring = dma_alloc_coherent(ndev->dev.parent,
 
 
 
 
 321						 sizeof(struct rswitch_ext_ts_desc) *
 322						 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL);
 323	} else {
 324		gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL);
 325		if (!gq->skbs)
 326			return -ENOMEM;
 327		gq->unmap_addrs = kcalloc(gq->ring_size, sizeof(*gq->unmap_addrs), GFP_KERNEL);
 328		if (!gq->unmap_addrs)
 329			goto out;
 330		gq->tx_ring = dma_alloc_coherent(ndev->dev.parent,
 331						 sizeof(struct rswitch_ext_desc) *
 332						 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL);
 333	}
 334
 335	if (!gq->rx_ring && !gq->tx_ring)
 336		goto out;
 337
 338	i = gq->index / 32;
 339	bit = BIT(gq->index % 32);
 340	if (dir_tx)
 341		priv->gwca.tx_irq_bits[i] |= bit;
 342	else
 343		priv->gwca.rx_irq_bits[i] |= bit;
 344
 345	return 0;
 346
 347out:
 348	rswitch_gwca_queue_free(ndev, gq);
 349
 350	return -ENOMEM;
 351}
 352
 353static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr)
 354{
 355	desc->dptrl = cpu_to_le32(lower_32_bits(addr));
 356	desc->dptrh = upper_32_bits(addr) & 0xff;
 357}
 358
 359static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc)
 360{
 361	return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32;
 362}
 363
 364static int rswitch_gwca_queue_format(struct net_device *ndev,
 365				     struct rswitch_private *priv,
 366				     struct rswitch_gwca_queue *gq)
 367{
 368	unsigned int ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size;
 369	struct rswitch_ext_desc *desc;
 370	struct rswitch_desc *linkfix;
 371	dma_addr_t dma_addr;
 372	unsigned int i;
 373
 374	memset(gq->tx_ring, 0, ring_size);
 375	for (i = 0, desc = gq->tx_ring; i < gq->ring_size; i++, desc++) {
 376		if (!gq->dir_tx) {
 377			dma_addr = dma_map_single(ndev->dev.parent,
 378						  gq->rx_bufs[i] + RSWITCH_HEADROOM,
 379						  RSWITCH_MAP_BUF_SIZE,
 380						  DMA_FROM_DEVICE);
 381			if (dma_mapping_error(ndev->dev.parent, dma_addr))
 382				goto err;
 383
 384			desc->desc.info_ds = cpu_to_le16(RSWITCH_DESC_BUF_SIZE);
 385			rswitch_desc_set_dptr(&desc->desc, dma_addr);
 386			desc->desc.die_dt = DT_FEMPTY | DIE;
 387		} else {
 388			desc->desc.die_dt = DT_EEMPTY | DIE;
 389		}
 390	}
 391	rswitch_desc_set_dptr(&desc->desc, gq->ring_dma);
 392	desc->desc.die_dt = DT_LINKFIX;
 393
 394	linkfix = &priv->gwca.linkfix_table[gq->index];
 395	linkfix->die_dt = DT_LINKFIX;
 396	rswitch_desc_set_dptr(linkfix, gq->ring_dma);
 397
 398	iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | GWDCC_EDE,
 399		  priv->addr + GWDCC_OFFS(gq->index));
 400
 401	return 0;
 402
 403err:
 404	if (!gq->dir_tx) {
 405		for (desc = gq->tx_ring; i-- > 0; desc++) {
 406			dma_addr = rswitch_desc_get_dptr(&desc->desc);
 407			dma_unmap_single(ndev->dev.parent, dma_addr,
 408					 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE);
 409		}
 410	}
 411
 412	return -ENOMEM;
 413}
 414
 415static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv,
 416				       unsigned int start_index,
 417				       unsigned int num)
 418{
 419	struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue;
 420	struct rswitch_ts_desc *desc;
 421	unsigned int i, index;
 422
 423	for (i = 0; i < num; i++) {
 424		index = (i + start_index) % gq->ring_size;
 425		desc = &gq->ts_ring[index];
 426		desc->desc.die_dt = DT_FEMPTY_ND | DIE;
 427	}
 428}
 429
 430static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev,
 431					  struct rswitch_gwca_queue *gq,
 432					  unsigned int start_index,
 433					  unsigned int num)
 434{
 435	struct rswitch_device *rdev = netdev_priv(ndev);
 436	struct rswitch_ext_ts_desc *desc;
 437	unsigned int i, index;
 438	dma_addr_t dma_addr;
 
 439
 440	for (i = 0; i < num; i++) {
 441		index = (i + start_index) % gq->ring_size;
 442		desc = &gq->rx_ring[index];
 443		if (!gq->dir_tx) {
 444			dma_addr = dma_map_single(ndev->dev.parent,
 445						  gq->rx_bufs[index] + RSWITCH_HEADROOM,
 446						  RSWITCH_MAP_BUF_SIZE,
 447						  DMA_FROM_DEVICE);
 448			if (dma_mapping_error(ndev->dev.parent, dma_addr))
 449				goto err;
 450
 451			desc->desc.info_ds = cpu_to_le16(RSWITCH_DESC_BUF_SIZE);
 452			rswitch_desc_set_dptr(&desc->desc, dma_addr);
 453			dma_wmb();
 454			desc->desc.die_dt = DT_FEMPTY | DIE;
 455			desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index));
 456		} else {
 457			desc->desc.die_dt = DT_EEMPTY | DIE;
 458		}
 459	}
 460
 461	return 0;
 462
 463err:
 464	if (!gq->dir_tx) {
 465		for (; i-- > 0; ) {
 466			index = (i + start_index) % gq->ring_size;
 467			desc = &gq->rx_ring[index];
 468			dma_addr = rswitch_desc_get_dptr(&desc->desc);
 469			dma_unmap_single(ndev->dev.parent, dma_addr,
 470					 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE);
 471		}
 472	}
 473
 474	return -ENOMEM;
 475}
 476
 477static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev,
 478					    struct rswitch_private *priv,
 479					    struct rswitch_gwca_queue *gq)
 480{
 481	unsigned int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size;
 482	struct rswitch_ext_ts_desc *desc;
 483	struct rswitch_desc *linkfix;
 484	int err;
 485
 486	memset(gq->rx_ring, 0, ring_size);
 487	err = rswitch_gwca_queue_ext_ts_fill(ndev, gq, 0, gq->ring_size);
 488	if (err < 0)
 489		return err;
 490
 491	desc = &gq->rx_ring[gq->ring_size];	/* Last */
 492	rswitch_desc_set_dptr(&desc->desc, gq->ring_dma);
 493	desc->desc.die_dt = DT_LINKFIX;
 494
 495	linkfix = &priv->gwca.linkfix_table[gq->index];
 496	linkfix->die_dt = DT_LINKFIX;
 497	rswitch_desc_set_dptr(linkfix, gq->ring_dma);
 498
 499	iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) |
 500		  GWDCC_ETS | GWDCC_EDE,
 501		  priv->addr + GWDCC_OFFS(gq->index));
 502
 503	return 0;
 504}
 505
 506static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv)
 507{
 508	unsigned int i, num_queues = priv->gwca.num_queues;
 509	struct rswitch_gwca *gwca = &priv->gwca;
 510	struct device *dev = &priv->pdev->dev;
 511
 512	gwca->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues;
 513	gwca->linkfix_table = dma_alloc_coherent(dev, gwca->linkfix_table_size,
 514						 &gwca->linkfix_table_dma, GFP_KERNEL);
 515	if (!gwca->linkfix_table)
 516		return -ENOMEM;
 517	for (i = 0; i < num_queues; i++)
 518		gwca->linkfix_table[i].die_dt = DT_EOS;
 519
 520	return 0;
 521}
 522
 523static void rswitch_gwca_linkfix_free(struct rswitch_private *priv)
 524{
 525	struct rswitch_gwca *gwca = &priv->gwca;
 526
 527	if (gwca->linkfix_table)
 528		dma_free_coherent(&priv->pdev->dev, gwca->linkfix_table_size,
 529				  gwca->linkfix_table, gwca->linkfix_table_dma);
 530	gwca->linkfix_table = NULL;
 531}
 532
 533static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv)
 534{
 535	struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue;
 536	struct rswitch_ts_desc *desc;
 537
 538	gq->ring_size = TS_RING_SIZE;
 539	gq->ts_ring = dma_alloc_coherent(&priv->pdev->dev,
 540					 sizeof(struct rswitch_ts_desc) *
 541					 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL);
 542
 543	if (!gq->ts_ring)
 544		return -ENOMEM;
 545
 546	rswitch_gwca_ts_queue_fill(priv, 0, TS_RING_SIZE);
 547	desc = &gq->ts_ring[gq->ring_size];
 548	desc->desc.die_dt = DT_LINKFIX;
 549	rswitch_desc_set_dptr(&desc->desc, gq->ring_dma);
 550
 551	return 0;
 552}
 553
 554static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv)
 555{
 556	struct rswitch_gwca_queue *gq;
 557	unsigned int index;
 558
 559	index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues);
 560	if (index >= priv->gwca.num_queues)
 561		return NULL;
 562	set_bit(index, priv->gwca.used);
 563	gq = &priv->gwca.queues[index];
 564	memset(gq, 0, sizeof(*gq));
 565	gq->index = index;
 566
 567	return gq;
 568}
 569
 570static void rswitch_gwca_put(struct rswitch_private *priv,
 571			     struct rswitch_gwca_queue *gq)
 572{
 573	clear_bit(gq->index, priv->gwca.used);
 574}
 575
 576static int rswitch_txdmac_alloc(struct net_device *ndev)
 577{
 578	struct rswitch_device *rdev = netdev_priv(ndev);
 579	struct rswitch_private *priv = rdev->priv;
 580	int err;
 581
 582	rdev->tx_queue = rswitch_gwca_get(priv);
 583	if (!rdev->tx_queue)
 584		return -EBUSY;
 585
 586	err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, TX_RING_SIZE);
 
 587	if (err < 0) {
 588		rswitch_gwca_put(priv, rdev->tx_queue);
 589		return err;
 590	}
 591
 592	return 0;
 593}
 594
 595static void rswitch_txdmac_free(struct net_device *ndev)
 596{
 597	struct rswitch_device *rdev = netdev_priv(ndev);
 598
 599	rswitch_gwca_queue_free(ndev, rdev->tx_queue);
 600	rswitch_gwca_put(rdev->priv, rdev->tx_queue);
 601}
 602
 603static int rswitch_txdmac_init(struct rswitch_private *priv, unsigned int index)
 604{
 605	struct rswitch_device *rdev = priv->rdev[index];
 606
 607	return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue);
 608}
 609
 610static int rswitch_rxdmac_alloc(struct net_device *ndev)
 611{
 612	struct rswitch_device *rdev = netdev_priv(ndev);
 613	struct rswitch_private *priv = rdev->priv;
 614	int err;
 615
 616	rdev->rx_queue = rswitch_gwca_get(priv);
 617	if (!rdev->rx_queue)
 618		return -EBUSY;
 619
 620	err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, RX_RING_SIZE);
 
 621	if (err < 0) {
 622		rswitch_gwca_put(priv, rdev->rx_queue);
 623		return err;
 624	}
 625
 626	return 0;
 627}
 628
 629static void rswitch_rxdmac_free(struct net_device *ndev)
 630{
 631	struct rswitch_device *rdev = netdev_priv(ndev);
 632
 633	rswitch_gwca_queue_free(ndev, rdev->rx_queue);
 634	rswitch_gwca_put(rdev->priv, rdev->rx_queue);
 635}
 636
 637static int rswitch_rxdmac_init(struct rswitch_private *priv, unsigned int index)
 638{
 639	struct rswitch_device *rdev = priv->rdev[index];
 640	struct net_device *ndev = rdev->ndev;
 641
 642	return rswitch_gwca_queue_ext_ts_format(ndev, priv, rdev->rx_queue);
 643}
 644
 645static int rswitch_gwca_hw_init(struct rswitch_private *priv)
 646{
 647	unsigned int i;
 648	int err;
 649
 650	err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
 651	if (err < 0)
 652		return err;
 653	err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG);
 654	if (err < 0)
 655		return err;
 656
 657	err = rswitch_gwca_mcast_table_reset(priv);
 658	if (err < 0)
 659		return err;
 660	err = rswitch_gwca_axi_ram_reset(priv);
 661	if (err < 0)
 662		return err;
 663
 664	iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC);
 665	iowrite32(0, priv->addr + GWTTFC);
 666	iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1);
 667	iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0);
 668	iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10);
 669	iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00);
 670	iowrite32(GWMDNC_TSDMN(1) | GWMDNC_TXDMN(0x1e) | GWMDNC_RXDMN(0x1f),
 671		  priv->addr + GWMDNC);
 672	iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0);
 673
 674	iowrite32(GWTPC_PPPL(GWCA_IPV_NUM), priv->addr + GWTPC0);
 675
 676	for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
 677		err = rswitch_rxdmac_init(priv, i);
 678		if (err < 0)
 679			return err;
 680		err = rswitch_txdmac_init(priv, i);
 681		if (err < 0)
 682			return err;
 683	}
 684
 685	err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
 686	if (err < 0)
 687		return err;
 688	return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION);
 689}
 690
 691static int rswitch_gwca_hw_deinit(struct rswitch_private *priv)
 692{
 693	int err;
 694
 695	err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
 696	if (err < 0)
 697		return err;
 698	err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET);
 699	if (err < 0)
 700		return err;
 701
 702	return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
 703}
 704
 705static int rswitch_gwca_halt(struct rswitch_private *priv)
 706{
 707	int err;
 708
 709	priv->gwca_halt = true;
 710	err = rswitch_gwca_hw_deinit(priv);
 711	dev_err(&priv->pdev->dev, "halted (%d)\n", err);
 712
 713	return err;
 714}
 715
 716static struct sk_buff *rswitch_rx_handle_desc(struct net_device *ndev,
 717					      struct rswitch_gwca_queue *gq,
 718					      struct rswitch_ext_ts_desc *desc)
 719{
 720	dma_addr_t dma_addr = rswitch_desc_get_dptr(&desc->desc);
 721	u16 pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS;
 722	u8 die_dt = desc->desc.die_dt & DT_MASK;
 723	struct sk_buff *skb = NULL;
 724
 725	dma_unmap_single(ndev->dev.parent, dma_addr, RSWITCH_MAP_BUF_SIZE,
 726			 DMA_FROM_DEVICE);
 727
 728	/* The RX descriptor order will be one of the following:
 729	 * - FSINGLE
 730	 * - FSTART -> FEND
 731	 * - FSTART -> FMID -> FEND
 732	 */
 733
 734	/* Check whether the descriptor is unexpected order */
 735	switch (die_dt) {
 736	case DT_FSTART:
 737	case DT_FSINGLE:
 738		if (gq->skb_fstart) {
 739			dev_kfree_skb_any(gq->skb_fstart);
 740			gq->skb_fstart = NULL;
 741			ndev->stats.rx_dropped++;
 742		}
 743		break;
 744	case DT_FMID:
 745	case DT_FEND:
 746		if (!gq->skb_fstart) {
 747			ndev->stats.rx_dropped++;
 748			return NULL;
 749		}
 750		break;
 751	default:
 752		break;
 753	}
 754
 755	/* Handle the descriptor */
 756	switch (die_dt) {
 757	case DT_FSTART:
 758	case DT_FSINGLE:
 759		skb = build_skb(gq->rx_bufs[gq->cur], RSWITCH_BUF_SIZE);
 760		if (skb) {
 761			skb_reserve(skb, RSWITCH_HEADROOM);
 762			skb_put(skb, pkt_len);
 763			gq->pkt_len = pkt_len;
 764			if (die_dt == DT_FSTART) {
 765				gq->skb_fstart = skb;
 766				skb = NULL;
 767			}
 768		}
 769		break;
 770	case DT_FMID:
 771	case DT_FEND:
 772		skb_add_rx_frag(gq->skb_fstart, skb_shinfo(gq->skb_fstart)->nr_frags,
 773				virt_to_page(gq->rx_bufs[gq->cur]),
 774				offset_in_page(gq->rx_bufs[gq->cur]) + RSWITCH_HEADROOM,
 775				pkt_len, RSWITCH_BUF_SIZE);
 776		if (die_dt == DT_FEND) {
 777			skb = gq->skb_fstart;
 778			gq->skb_fstart = NULL;
 779		}
 780		gq->pkt_len += pkt_len;
 781		break;
 782	default:
 783		netdev_err(ndev, "%s: unexpected value (%x)\n", __func__, die_dt);
 784		break;
 785	}
 786
 787	return skb;
 788}
 789
 790static bool rswitch_rx(struct net_device *ndev, int *quota)
 791{
 792	struct rswitch_device *rdev = netdev_priv(ndev);
 793	struct rswitch_gwca_queue *gq = rdev->rx_queue;
 794	struct rswitch_ext_ts_desc *desc;
 795	int limit, boguscnt, ret;
 796	struct sk_buff *skb;
 797	unsigned int num;
 
 798	u32 get_ts;
 799
 800	if (*quota <= 0)
 801		return true;
 802
 803	boguscnt = min_t(int, gq->ring_size, *quota);
 804	limit = boguscnt;
 805
 806	desc = &gq->rx_ring[gq->cur];
 807	while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) {
 
 
 808		dma_rmb();
 809		skb = rswitch_rx_handle_desc(ndev, gq, desc);
 810		if (!skb)
 811			goto out;
 812
 
 813		get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT;
 814		if (get_ts) {
 815			struct skb_shared_hwtstamps *shhwtstamps;
 816			struct timespec64 ts;
 817
 818			shhwtstamps = skb_hwtstamps(skb);
 819			memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 820			ts.tv_sec = __le32_to_cpu(desc->ts_sec);
 821			ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff));
 822			shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
 823		}
 
 824		skb->protocol = eth_type_trans(skb, ndev);
 825		napi_gro_receive(&rdev->napi, skb);
 826		rdev->ndev->stats.rx_packets++;
 827		rdev->ndev->stats.rx_bytes += gq->pkt_len;
 828
 829out:
 830		gq->rx_bufs[gq->cur] = NULL;
 831		gq->cur = rswitch_next_queue_index(gq, true, 1);
 832		desc = &gq->rx_ring[gq->cur];
 833
 834		if (--boguscnt <= 0)
 835			break;
 836	}
 837
 838	num = rswitch_get_num_cur_queues(gq);
 839	ret = rswitch_gwca_queue_alloc_rx_buf(gq, gq->dirty, num);
 840	if (ret < 0)
 841		goto err;
 842	ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq->dirty, num);
 843	if (ret < 0)
 844		goto err;
 845	gq->dirty = rswitch_next_queue_index(gq, false, num);
 846
 847	*quota -= limit - boguscnt;
 848
 849	return boguscnt <= 0;
 850
 851err:
 852	rswitch_gwca_halt(rdev->priv);
 853
 854	return 0;
 855}
 856
 857static void rswitch_tx_free(struct net_device *ndev)
 858{
 859	struct rswitch_device *rdev = netdev_priv(ndev);
 860	struct rswitch_gwca_queue *gq = rdev->tx_queue;
 861	struct rswitch_ext_desc *desc;
 
 862	struct sk_buff *skb;
 
 
 863
 864	desc = &gq->tx_ring[gq->dirty];
 865	while ((desc->desc.die_dt & DT_MASK) == DT_FEMPTY) {
 866		dma_rmb();
 
 
 867
 
 
 868		skb = gq->skbs[gq->dirty];
 869		if (skb) {
 870			rdev->ndev->stats.tx_packets++;
 871			rdev->ndev->stats.tx_bytes += skb->len;
 872			dma_unmap_single(ndev->dev.parent,
 873					 gq->unmap_addrs[gq->dirty],
 874					 skb->len, DMA_TO_DEVICE);
 
 
 
 
 
 
 
 875			dev_kfree_skb_any(gq->skbs[gq->dirty]);
 876			gq->skbs[gq->dirty] = NULL;
 
 877		}
 878
 879		desc->desc.die_dt = DT_EEMPTY;
 880		gq->dirty = rswitch_next_queue_index(gq, false, 1);
 881		desc = &gq->tx_ring[gq->dirty];
 882	}
 
 
 883}
 884
 885static int rswitch_poll(struct napi_struct *napi, int budget)
 886{
 887	struct net_device *ndev = napi->dev;
 888	struct rswitch_private *priv;
 889	struct rswitch_device *rdev;
 890	unsigned long flags;
 891	int quota = budget;
 892
 893	rdev = netdev_priv(ndev);
 894	priv = rdev->priv;
 895
 896retry:
 897	rswitch_tx_free(ndev);
 898
 899	if (rswitch_rx(ndev, &quota))
 900		goto out;
 901	else if (rdev->priv->gwca_halt)
 902		goto err;
 903	else if (rswitch_is_queue_rxed(rdev->rx_queue))
 904		goto retry;
 905
 906	netif_wake_subqueue(ndev, 0);
 907
 908	if (napi_complete_done(napi, budget - quota)) {
 909		spin_lock_irqsave(&priv->lock, flags);
 910		if (test_bit(rdev->port, priv->opened_ports)) {
 911			rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true);
 912			rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true);
 913		}
 914		spin_unlock_irqrestore(&priv->lock, flags);
 915	}
 916
 917out:
 918	return budget - quota;
 919
 920err:
 921	napi_complete(napi);
 922
 923	return 0;
 924}
 925
 926static void rswitch_queue_interrupt(struct net_device *ndev)
 927{
 928	struct rswitch_device *rdev = netdev_priv(ndev);
 929
 930	if (napi_schedule_prep(&rdev->napi)) {
 931		spin_lock(&rdev->priv->lock);
 932		rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false);
 933		rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false);
 934		spin_unlock(&rdev->priv->lock);
 935		__napi_schedule(&rdev->napi);
 936	}
 937}
 938
 939static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis)
 940{
 941	struct rswitch_gwca_queue *gq;
 942	unsigned int i, index, bit;
 943
 944	for (i = 0; i < priv->gwca.num_queues; i++) {
 945		gq = &priv->gwca.queues[i];
 946		index = gq->index / 32;
 947		bit = BIT(gq->index % 32);
 948		if (!(dis[index] & bit))
 949			continue;
 950
 951		rswitch_ack_data_irq(priv, gq->index);
 952		rswitch_queue_interrupt(gq->ndev);
 953	}
 954
 955	return IRQ_HANDLED;
 956}
 957
 958static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id)
 959{
 960	struct rswitch_private *priv = dev_id;
 961	u32 dis[RSWITCH_NUM_IRQ_REGS];
 962	irqreturn_t ret = IRQ_NONE;
 963
 964	rswitch_get_data_irq_status(priv, dis);
 965
 966	if (rswitch_is_any_data_irq(priv, dis, true) ||
 967	    rswitch_is_any_data_irq(priv, dis, false))
 968		ret = rswitch_data_irq(priv, dis);
 969
 970	return ret;
 971}
 972
 973static int rswitch_gwca_request_irqs(struct rswitch_private *priv)
 974{
 975	char *resource_name, *irq_name;
 976	int i, ret, irq;
 977
 978	for (i = 0; i < GWCA_NUM_IRQS; i++) {
 979		resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i);
 980		if (!resource_name)
 981			return -ENOMEM;
 982
 983		irq = platform_get_irq_byname(priv->pdev, resource_name);
 984		kfree(resource_name);
 985		if (irq < 0)
 986			return irq;
 987
 988		irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL,
 989					  GWCA_IRQ_NAME, i);
 990		if (!irq_name)
 991			return -ENOMEM;
 992
 993		ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq,
 994				       0, irq_name, priv);
 995		if (ret < 0)
 996			return ret;
 997	}
 998
 999	return 0;
1000}
1001
1002static void rswitch_ts(struct rswitch_private *priv)
1003{
1004	struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue;
1005	struct skb_shared_hwtstamps shhwtstamps;
1006	struct rswitch_ts_desc *desc;
1007	struct rswitch_device *rdev;
1008	struct sk_buff *ts_skb;
1009	struct timespec64 ts;
1010	unsigned int num;
1011	u32 tag, port;
1012
1013	desc = &gq->ts_ring[gq->cur];
1014	while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY_ND) {
1015		dma_rmb();
1016
1017		port = TS_DESC_DPN(__le32_to_cpu(desc->desc.dptrl));
1018		if (unlikely(port >= RSWITCH_NUM_PORTS))
1019			goto next;
1020		rdev = priv->rdev[port];
1021
1022		tag = TS_DESC_TSUN(__le32_to_cpu(desc->desc.dptrl));
1023		if (unlikely(tag >= TS_TAGS_PER_PORT))
1024			goto next;
1025		ts_skb = xchg(&rdev->ts_skb[tag], NULL);
1026		smp_mb(); /* order rdev->ts_skb[] read before bitmap update */
1027		clear_bit(tag, rdev->ts_skb_used);
1028
1029		if (unlikely(!ts_skb))
1030			goto next;
1031
1032		memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1033		ts.tv_sec = __le32_to_cpu(desc->ts_sec);
1034		ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff));
1035		shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
1036		skb_tstamp_tx(ts_skb, &shhwtstamps);
1037		dev_consume_skb_irq(ts_skb);
1038
1039next:
1040		gq->cur = rswitch_next_queue_index(gq, true, 1);
1041		desc = &gq->ts_ring[gq->cur];
1042	}
1043
1044	num = rswitch_get_num_cur_queues(gq);
1045	rswitch_gwca_ts_queue_fill(priv, gq->dirty, num);
1046	gq->dirty = rswitch_next_queue_index(gq, false, num);
1047}
1048
1049static irqreturn_t rswitch_gwca_ts_irq(int irq, void *dev_id)
1050{
1051	struct rswitch_private *priv = dev_id;
1052
1053	if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) {
1054		iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS);
1055		rswitch_ts(priv);
1056
1057		return IRQ_HANDLED;
1058	}
1059
1060	return IRQ_NONE;
1061}
1062
1063static int rswitch_gwca_ts_request_irqs(struct rswitch_private *priv)
1064{
1065	int irq;
1066
1067	irq = platform_get_irq_byname(priv->pdev, GWCA_TS_IRQ_RESOURCE_NAME);
1068	if (irq < 0)
1069		return irq;
1070
1071	return devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_ts_irq,
1072				0, GWCA_TS_IRQ_NAME, priv);
1073}
1074
1075/* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */
1076static int rswitch_etha_change_mode(struct rswitch_etha *etha,
1077				    enum rswitch_etha_mode mode)
1078{
1079	int ret;
1080
1081	if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index))
1082		rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1);
1083
1084	iowrite32(mode, etha->addr + EAMC);
1085
1086	ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode);
1087
1088	if (mode == EAMC_OPC_DISABLE)
1089		rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0);
1090
1091	return ret;
1092}
1093
1094static void rswitch_etha_read_mac_address(struct rswitch_etha *etha)
1095{
1096	u32 mrmac0 = ioread32(etha->addr + MRMAC0);
1097	u32 mrmac1 = ioread32(etha->addr + MRMAC1);
1098	u8 *mac = &etha->mac_addr[0];
1099
1100	mac[0] = (mrmac0 >>  8) & 0xFF;
1101	mac[1] = (mrmac0 >>  0) & 0xFF;
1102	mac[2] = (mrmac1 >> 24) & 0xFF;
1103	mac[3] = (mrmac1 >> 16) & 0xFF;
1104	mac[4] = (mrmac1 >>  8) & 0xFF;
1105	mac[5] = (mrmac1 >>  0) & 0xFF;
1106}
1107
1108static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac)
1109{
1110	iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0);
1111	iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1112		  etha->addr + MRMAC1);
1113}
1114
1115static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha)
1116{
1117	iowrite32(MLVC_PLV, etha->addr + MLVC);
1118
1119	return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0);
1120}
1121
1122static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
1123{
1124	u32 pis, lsc;
1125
1126	rswitch_etha_write_mac_address(etha, mac);
1127
1128	switch (etha->phy_interface) {
1129	case PHY_INTERFACE_MODE_SGMII:
1130		pis = MPIC_PIS_GMII;
1131		break;
1132	case PHY_INTERFACE_MODE_USXGMII:
1133	case PHY_INTERFACE_MODE_5GBASER:
1134		pis = MPIC_PIS_XGMII;
1135		break;
1136	default:
1137		pis = FIELD_GET(MPIC_PIS, ioread32(etha->addr + MPIC));
1138		break;
1139	}
1140
1141	switch (etha->speed) {
1142	case 100:
1143		lsc = MPIC_LSC_100M;
1144		break;
1145	case 1000:
1146		lsc = MPIC_LSC_1G;
1147		break;
1148	case 2500:
1149		lsc = MPIC_LSC_2_5G;
1150		break;
1151	default:
1152		lsc = FIELD_GET(MPIC_LSC, ioread32(etha->addr + MPIC));
1153		break;
1154	}
1155
1156	rswitch_modify(etha->addr, MPIC, MPIC_PIS | MPIC_LSC,
1157		       FIELD_PREP(MPIC_PIS, pis) | FIELD_PREP(MPIC_LSC, lsc));
1158}
1159
1160static void rswitch_etha_enable_mii(struct rswitch_etha *etha)
1161{
1162	rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
1163		       MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06));
1164	rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45);
1165}
1166
1167static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac)
1168{
1169	int err;
1170
1171	err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE);
1172	if (err < 0)
1173		return err;
1174	err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG);
1175	if (err < 0)
1176		return err;
1177
1178	iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC);
1179	rswitch_rmac_setting(etha, mac);
1180	rswitch_etha_enable_mii(etha);
1181
1182	err = rswitch_etha_wait_link_verification(etha);
1183	if (err < 0)
1184		return err;
1185
1186	err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE);
1187	if (err < 0)
1188		return err;
1189
1190	return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION);
1191}
1192
1193static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read,
1194				   int phyad, int devad, int regad, int data)
1195{
1196	int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45;
1197	u32 val;
1198	int ret;
1199
1200	if (devad == 0xffffffff)
1201		return -ENODEV;
1202
1203	writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1);
1204
1205	val = MPSM_PSME | MPSM_MFF_C45;
1206	iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);
1207
1208	ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);
1209	if (ret)
1210		return ret;
1211
1212	rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);
1213
1214	if (read) {
1215		writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);
1216
1217		ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);
1218		if (ret)
1219			return ret;
1220
1221		ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16;
1222
1223		rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);
1224	} else {
1225		iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val,
1226			  etha->addr + MPSM);
1227
1228		ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS);
1229	}
1230
1231	return ret;
1232}
1233
1234static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad,
1235				     int regad)
1236{
1237	struct rswitch_etha *etha = bus->priv;
 
 
 
 
 
 
 
 
 
1238
1239	return rswitch_etha_set_access(etha, true, addr, devad, regad, 0);
1240}
1241
1242static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad,
1243				      int regad, u16 val)
1244{
1245	struct rswitch_etha *etha = bus->priv;
 
 
 
 
 
 
 
 
 
1246
1247	return rswitch_etha_set_access(etha, false, addr, devad, regad, val);
1248}
1249
1250/* Call of_node_put(port) after done */
1251static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev)
1252{
1253	struct device_node *ports, *port;
1254	int err = 0;
1255	u32 index;
1256
1257	ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node,
1258				     "ethernet-ports");
1259	if (!ports)
1260		return NULL;
1261
1262	for_each_child_of_node(ports, port) {
1263		err = of_property_read_u32(port, "reg", &index);
1264		if (err < 0) {
1265			port = NULL;
1266			goto out;
1267		}
1268		if (index == rdev->etha->index) {
1269			if (!of_device_is_available(port))
1270				port = NULL;
1271			break;
1272		}
1273	}
1274
1275out:
1276	of_node_put(ports);
1277
1278	return port;
1279}
1280
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1281static int rswitch_etha_get_params(struct rswitch_device *rdev)
1282{
1283	u32 max_speed;
1284	int err;
1285
1286	if (!rdev->np_port)
 
1287		return 0;	/* ignored */
1288
1289	err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface);
1290	if (err)
1291		return err;
1292
1293	err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed);
1294	if (!err) {
1295		rdev->etha->speed = max_speed;
1296		return 0;
1297	}
1298
1299	/* if no "max-speed" property, let's use default speed */
1300	switch (rdev->etha->phy_interface) {
1301	case PHY_INTERFACE_MODE_MII:
1302		rdev->etha->speed = SPEED_100;
1303		break;
1304	case PHY_INTERFACE_MODE_SGMII:
1305		rdev->etha->speed = SPEED_1000;
1306		break;
1307	case PHY_INTERFACE_MODE_USXGMII:
1308		rdev->etha->speed = SPEED_2500;
1309		break;
1310	default:
1311		return -EINVAL;
 
1312	}
1313
1314	return 0;
1315}
1316
1317static int rswitch_mii_register(struct rswitch_device *rdev)
1318{
1319	struct device_node *mdio_np;
1320	struct mii_bus *mii_bus;
1321	int err;
1322
1323	mii_bus = mdiobus_alloc();
1324	if (!mii_bus)
1325		return -ENOMEM;
1326
1327	mii_bus->name = "rswitch_mii";
1328	sprintf(mii_bus->id, "etha%d", rdev->etha->index);
1329	mii_bus->priv = rdev->etha;
1330	mii_bus->read_c45 = rswitch_etha_mii_read_c45;
1331	mii_bus->write_c45 = rswitch_etha_mii_write_c45;
1332	mii_bus->parent = &rdev->priv->pdev->dev;
1333
1334	mdio_np = of_get_child_by_name(rdev->np_port, "mdio");
1335	err = of_mdiobus_register(mii_bus, mdio_np);
1336	if (err < 0) {
1337		mdiobus_free(mii_bus);
1338		goto out;
1339	}
1340
1341	rdev->etha->mii = mii_bus;
1342
1343out:
1344	of_node_put(mdio_np);
1345
1346	return err;
1347}
1348
1349static void rswitch_mii_unregister(struct rswitch_device *rdev)
1350{
1351	if (rdev->etha->mii) {
1352		mdiobus_unregister(rdev->etha->mii);
1353		mdiobus_free(rdev->etha->mii);
1354		rdev->etha->mii = NULL;
1355	}
1356}
1357
1358static void rswitch_adjust_link(struct net_device *ndev)
 
 
1359{
1360	struct rswitch_device *rdev = netdev_priv(ndev);
1361	struct phy_device *phydev = ndev->phydev;
1362
1363	if (phydev->link != rdev->etha->link) {
1364		phy_print_status(phydev);
1365		if (phydev->link)
1366			phy_power_on(rdev->serdes);
1367		else if (rdev->serdes->power_count)
1368			phy_power_off(rdev->serdes);
1369
1370		rdev->etha->link = phydev->link;
1371
1372		if (!rdev->priv->etha_no_runtime_change &&
1373		    phydev->speed != rdev->etha->speed) {
1374			rdev->etha->speed = phydev->speed;
1375
1376			rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr);
1377			phy_set_speed(rdev->serdes, rdev->etha->speed);
1378		}
1379	}
1380}
1381
1382static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev,
1383					 struct phy_device *phydev)
 
1384{
1385	if (!rdev->priv->etha_no_runtime_change)
1386		return;
1387
1388	switch (rdev->etha->speed) {
1389	case SPEED_2500:
1390		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1391		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
1392		break;
1393	case SPEED_1000:
1394		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT);
1395		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
1396		break;
1397	case SPEED_100:
1398		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT);
1399		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1400		break;
1401	default:
1402		break;
1403	}
1404
1405	phy_set_max_speed(phydev, rdev->etha->speed);
1406}
1407
1408static int rswitch_phy_device_init(struct rswitch_device *rdev)
 
 
 
1409{
1410	struct phy_device *phydev;
1411	struct device_node *phy;
1412	int err = -ENOENT;
1413
1414	if (!rdev->np_port)
1415		return -ENODEV;
 
 
 
1416
1417	phy = of_parse_phandle(rdev->np_port, "phy-handle", 0);
1418	if (!phy)
1419		return -ENODEV;
 
 
1420
1421	/* Set phydev->host_interfaces before calling of_phy_connect() to
1422	 * configure the PHY with the information of host_interfaces.
1423	 */
1424	phydev = of_phy_find_device(phy);
1425	if (!phydev)
1426		goto out;
1427	__set_bit(rdev->etha->phy_interface, phydev->host_interfaces);
1428	phydev->mac_managed_pm = true;
1429
1430	phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0,
1431				rdev->etha->phy_interface);
1432	if (!phydev)
 
 
 
 
 
 
 
1433		goto out;
 
1434
1435	phy_set_max_speed(phydev, SPEED_2500);
1436	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1437	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1438	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1439	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1440	rswitch_phy_remove_link_mode(rdev, phydev);
1441
1442	phy_attached_info(phydev);
1443
1444	err = 0;
1445out:
1446	of_node_put(phy);
1447
1448	return err;
1449}
1450
1451static void rswitch_phy_device_deinit(struct rswitch_device *rdev)
1452{
1453	if (rdev->ndev->phydev)
1454		phy_disconnect(rdev->ndev->phydev);
 
 
1455}
1456
1457static int rswitch_serdes_set_params(struct rswitch_device *rdev)
1458{
 
 
1459	int err;
1460
1461	err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET,
 
 
 
 
 
1462			       rdev->etha->phy_interface);
1463	if (err < 0)
1464		return err;
1465
1466	return phy_set_speed(rdev->serdes, rdev->etha->speed);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1467}
1468
1469static int rswitch_ether_port_init_one(struct rswitch_device *rdev)
1470{
1471	int err;
1472
1473	if (!rdev->etha->operated) {
1474		err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr);
1475		if (err < 0)
1476			return err;
1477		if (rdev->priv->etha_no_runtime_change)
1478			rdev->etha->operated = true;
1479	}
1480
1481	err = rswitch_mii_register(rdev);
1482	if (err < 0)
1483		return err;
1484
1485	err = rswitch_phy_device_init(rdev);
1486	if (err < 0)
1487		goto err_phy_device_init;
1488
1489	rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL);
1490	if (IS_ERR(rdev->serdes)) {
1491		err = PTR_ERR(rdev->serdes);
1492		goto err_serdes_phy_get;
1493	}
1494
1495	err = rswitch_serdes_set_params(rdev);
1496	if (err < 0)
1497		goto err_serdes_set_params;
1498
1499	return 0;
1500
1501err_serdes_set_params:
1502err_serdes_phy_get:
1503	rswitch_phy_device_deinit(rdev);
1504
1505err_phy_device_init:
1506	rswitch_mii_unregister(rdev);
1507
1508	return err;
1509}
1510
1511static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev)
1512{
1513	rswitch_phy_device_deinit(rdev);
1514	rswitch_mii_unregister(rdev);
1515}
1516
1517static int rswitch_ether_port_init_all(struct rswitch_private *priv)
1518{
1519	unsigned int i;
1520	int err;
1521
1522	rswitch_for_each_enabled_port(priv, i) {
1523		err = rswitch_ether_port_init_one(priv->rdev[i]);
1524		if (err)
1525			goto err_init_one;
1526	}
1527
1528	rswitch_for_each_enabled_port(priv, i) {
1529		err = phy_init(priv->rdev[i]->serdes);
1530		if (err)
1531			goto err_serdes;
1532	}
1533
1534	return 0;
1535
1536err_serdes:
1537	rswitch_for_each_enabled_port_continue_reverse(priv, i)
1538		phy_exit(priv->rdev[i]->serdes);
1539	i = RSWITCH_NUM_PORTS;
1540
1541err_init_one:
1542	rswitch_for_each_enabled_port_continue_reverse(priv, i)
1543		rswitch_ether_port_deinit_one(priv->rdev[i]);
1544
1545	return err;
1546}
1547
1548static void rswitch_ether_port_deinit_all(struct rswitch_private *priv)
1549{
1550	unsigned int i;
1551
1552	for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
1553		phy_exit(priv->rdev[i]->serdes);
1554		rswitch_ether_port_deinit_one(priv->rdev[i]);
1555	}
1556}
1557
1558static int rswitch_open(struct net_device *ndev)
1559{
1560	struct rswitch_device *rdev = netdev_priv(ndev);
1561	unsigned long flags;
1562
1563	if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS))
1564		iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE);
1565
1566	napi_enable(&rdev->napi);
 
1567
1568	spin_lock_irqsave(&rdev->priv->lock, flags);
1569	bitmap_set(rdev->priv->opened_ports, rdev->port, 1);
1570	rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true);
1571	rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true);
1572	spin_unlock_irqrestore(&rdev->priv->lock, flags);
1573
1574	phy_start(ndev->phydev);
1575
1576	netif_start_queue(ndev);
1577
1578	return 0;
1579};
1580
1581static int rswitch_stop(struct net_device *ndev)
1582{
1583	struct rswitch_device *rdev = netdev_priv(ndev);
1584	struct sk_buff *ts_skb;
1585	unsigned long flags;
1586	unsigned int tag;
1587
1588	netif_tx_stop_all_queues(ndev);
1589
1590	phy_stop(ndev->phydev);
1591
1592	spin_lock_irqsave(&rdev->priv->lock, flags);
1593	rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false);
1594	rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false);
1595	bitmap_clear(rdev->priv->opened_ports, rdev->port, 1);
1596	spin_unlock_irqrestore(&rdev->priv->lock, flags);
1597
 
1598	napi_disable(&rdev->napi);
1599
1600	if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS))
1601		iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID);
1602
1603	for (tag = find_first_bit(rdev->ts_skb_used, TS_TAGS_PER_PORT);
1604	     tag < TS_TAGS_PER_PORT;
1605	     tag = find_next_bit(rdev->ts_skb_used, TS_TAGS_PER_PORT, tag + 1)) {
1606		ts_skb = xchg(&rdev->ts_skb[tag], NULL);
1607		clear_bit(tag, rdev->ts_skb_used);
1608		if (ts_skb)
1609			dev_kfree_skb(ts_skb);
1610	}
1611
1612	return 0;
1613};
1614
1615static bool rswitch_ext_desc_set_info1(struct rswitch_device *rdev,
1616				       struct sk_buff *skb,
1617				       struct rswitch_ext_desc *desc)
1618{
1619	desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) |
1620				  INFO1_IPV(GWCA_IPV_NUM) | INFO1_FMT);
1621	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
1622		unsigned int tag;
1623
1624		tag = find_first_zero_bit(rdev->ts_skb_used, TS_TAGS_PER_PORT);
1625		if (tag == TS_TAGS_PER_PORT)
1626			return false;
1627		smp_mb(); /* order bitmap read before rdev->ts_skb[] write */
1628		rdev->ts_skb[tag] = skb_get(skb);
1629		set_bit(tag, rdev->ts_skb_used);
1630
1631		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1632		desc->info1 |= cpu_to_le64(INFO1_TSUN(tag) | INFO1_TXC);
1633
1634		skb_tx_timestamp(skb);
1635	}
1636
1637	return true;
1638}
1639
1640static bool rswitch_ext_desc_set(struct rswitch_device *rdev,
1641				 struct sk_buff *skb,
1642				 struct rswitch_ext_desc *desc,
1643				 dma_addr_t dma_addr, u16 len, u8 die_dt)
1644{
1645	rswitch_desc_set_dptr(&desc->desc, dma_addr);
1646	desc->desc.info_ds = cpu_to_le16(len);
1647	if (!rswitch_ext_desc_set_info1(rdev, skb, desc))
1648		return false;
1649
1650	dma_wmb();
1651
1652	desc->desc.die_dt = die_dt;
1653
1654	return true;
1655}
1656
1657static u8 rswitch_ext_desc_get_die_dt(unsigned int nr_desc, unsigned int index)
1658{
1659	if (nr_desc == 1)
1660		return DT_FSINGLE | DIE;
1661	if (index == 0)
1662		return DT_FSTART;
1663	if (nr_desc - 1 == index)
1664		return DT_FEND | DIE;
1665	return DT_FMID;
1666}
1667
1668static u16 rswitch_ext_desc_get_len(u8 die_dt, unsigned int orig_len)
1669{
1670	switch (die_dt & DT_MASK) {
1671	case DT_FSINGLE:
1672	case DT_FEND:
1673		return (orig_len % RSWITCH_DESC_BUF_SIZE) ?: RSWITCH_DESC_BUF_SIZE;
1674	case DT_FSTART:
1675	case DT_FMID:
1676		return RSWITCH_DESC_BUF_SIZE;
1677	default:
1678		return 0;
1679	}
1680}
1681
1682static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1683{
1684	struct rswitch_device *rdev = netdev_priv(ndev);
1685	struct rswitch_gwca_queue *gq = rdev->tx_queue;
1686	dma_addr_t dma_addr, dma_addr_orig;
1687	netdev_tx_t ret = NETDEV_TX_OK;
1688	struct rswitch_ext_desc *desc;
1689	unsigned int i, nr_desc;
1690	u8 die_dt;
1691	u16 len;
1692
1693	nr_desc = (skb->len - 1) / RSWITCH_DESC_BUF_SIZE + 1;
1694	if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - nr_desc) {
1695		netif_stop_subqueue(ndev, 0);
1696		return NETDEV_TX_BUSY;
1697	}
1698
1699	if (skb_put_padto(skb, ETH_ZLEN))
1700		return ret;
1701
1702	dma_addr_orig = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE);
1703	if (dma_mapping_error(ndev->dev.parent, dma_addr_orig))
1704		goto err_kfree;
1705
1706	/* Stored the skb at the last descriptor to avoid skb free before hardware completes send */
1707	gq->skbs[(gq->cur + nr_desc - 1) % gq->ring_size] = skb;
1708	gq->unmap_addrs[(gq->cur + nr_desc - 1) % gq->ring_size] = dma_addr_orig;
1709
1710	dma_wmb();
 
 
 
1711
1712	/* DT_FSTART should be set at last. So, this is reverse order. */
1713	for (i = nr_desc; i-- > 0; ) {
1714		desc = &gq->tx_ring[rswitch_next_queue_index(gq, true, i)];
1715		die_dt = rswitch_ext_desc_get_die_dt(nr_desc, i);
1716		dma_addr = dma_addr_orig + i * RSWITCH_DESC_BUF_SIZE;
1717		len = rswitch_ext_desc_get_len(die_dt, skb->len);
1718		if (!rswitch_ext_desc_set(rdev, skb, desc, dma_addr, len, die_dt))
1719			goto err_unmap;
1720	}
 
1721
1722	gq->cur = rswitch_next_queue_index(gq, true, nr_desc);
1723	rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32));
1724
1725	return ret;
1726
1727err_unmap:
1728	gq->skbs[(gq->cur + nr_desc - 1) % gq->ring_size] = NULL;
1729	dma_unmap_single(ndev->dev.parent, dma_addr_orig, skb->len, DMA_TO_DEVICE);
1730
1731err_kfree:
1732	dev_kfree_skb_any(skb);
1733
1734	return ret;
1735}
1736
1737static struct net_device_stats *rswitch_get_stats(struct net_device *ndev)
1738{
1739	return &ndev->stats;
1740}
1741
1742static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req)
1743{
1744	struct rswitch_device *rdev = netdev_priv(ndev);
1745	struct rcar_gen4_ptp_private *ptp_priv;
1746	struct hwtstamp_config config;
1747
1748	ptp_priv = rdev->priv->ptp_priv;
1749
1750	config.flags = 0;
1751	config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1752						    HWTSTAMP_TX_OFF;
1753	switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) {
1754	case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT:
1755		config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1756		break;
1757	case RCAR_GEN4_RXTSTAMP_TYPE_ALL:
1758		config.rx_filter = HWTSTAMP_FILTER_ALL;
1759		break;
1760	default:
1761		config.rx_filter = HWTSTAMP_FILTER_NONE;
1762		break;
1763	}
1764
1765	return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
1766}
1767
1768static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req)
1769{
1770	struct rswitch_device *rdev = netdev_priv(ndev);
1771	u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED;
1772	struct hwtstamp_config config;
1773	u32 tstamp_tx_ctrl;
1774
1775	if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1776		return -EFAULT;
1777
1778	if (config.flags)
1779		return -EINVAL;
1780
1781	switch (config.tx_type) {
1782	case HWTSTAMP_TX_OFF:
1783		tstamp_tx_ctrl = 0;
1784		break;
1785	case HWTSTAMP_TX_ON:
1786		tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED;
1787		break;
1788	default:
1789		return -ERANGE;
1790	}
1791
1792	switch (config.rx_filter) {
1793	case HWTSTAMP_FILTER_NONE:
1794		tstamp_rx_ctrl = 0;
1795		break;
1796	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1797		tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT;
1798		break;
1799	default:
1800		config.rx_filter = HWTSTAMP_FILTER_ALL;
1801		tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL;
1802		break;
1803	}
1804
1805	rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1806	rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1807
1808	return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
1809}
1810
1811static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1812{
 
 
1813	if (!netif_running(ndev))
1814		return -EINVAL;
1815
1816	switch (cmd) {
1817	case SIOCGHWTSTAMP:
1818		return rswitch_hwstamp_get(ndev, req);
1819	case SIOCSHWTSTAMP:
1820		return rswitch_hwstamp_set(ndev, req);
1821	default:
1822		return phy_mii_ioctl(ndev->phydev, req, cmd);
1823	}
1824}
1825
1826static const struct net_device_ops rswitch_netdev_ops = {
1827	.ndo_open = rswitch_open,
1828	.ndo_stop = rswitch_stop,
1829	.ndo_start_xmit = rswitch_start_xmit,
1830	.ndo_get_stats = rswitch_get_stats,
1831	.ndo_eth_ioctl = rswitch_eth_ioctl,
1832	.ndo_validate_addr = eth_validate_addr,
1833	.ndo_set_mac_address = eth_mac_addr,
1834};
1835
1836static int rswitch_get_ts_info(struct net_device *ndev, struct kernel_ethtool_ts_info *info)
1837{
1838	struct rswitch_device *rdev = netdev_priv(ndev);
1839
1840	info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock);
1841	info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
 
 
1842				SOF_TIMESTAMPING_TX_HARDWARE |
1843				SOF_TIMESTAMPING_RX_HARDWARE |
1844				SOF_TIMESTAMPING_RAW_HARDWARE;
1845	info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
1846	info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1847
1848	return 0;
1849}
1850
1851static const struct ethtool_ops rswitch_ethtool_ops = {
1852	.get_ts_info = rswitch_get_ts_info,
1853	.get_link_ksettings = phy_ethtool_get_link_ksettings,
1854	.set_link_ksettings = phy_ethtool_set_link_ksettings,
1855};
1856
1857static const struct of_device_id renesas_eth_sw_of_table[] = {
1858	{ .compatible = "renesas,r8a779f0-ether-switch", },
1859	{ }
1860};
1861MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table);
1862
1863static void rswitch_etha_init(struct rswitch_private *priv, unsigned int index)
1864{
1865	struct rswitch_etha *etha = &priv->etha[index];
1866
1867	memset(etha, 0, sizeof(*etha));
1868	etha->index = index;
1869	etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE;
1870	etha->coma_addr = priv->addr;
1871
1872	/* MPIC.PSMCS = (clk [MHz] / (MDC frequency [MHz] * 2) - 1.
1873	 * Calculating PSMCS value as MDC frequency = 2.5MHz. So, multiply
1874	 * both the numerator and the denominator by 10.
1875	 */
1876	etha->psmcs = clk_get_rate(priv->clk) / 100000 / (25 * 2) - 1;
1877}
1878
1879static int rswitch_device_alloc(struct rswitch_private *priv, unsigned int index)
1880{
1881	struct platform_device *pdev = priv->pdev;
1882	struct rswitch_device *rdev;
 
1883	struct net_device *ndev;
1884	int err;
1885
1886	if (index >= RSWITCH_NUM_PORTS)
1887		return -EINVAL;
1888
1889	ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1);
1890	if (!ndev)
1891		return -ENOMEM;
1892
1893	SET_NETDEV_DEV(ndev, &pdev->dev);
1894	ether_setup(ndev);
1895
1896	rdev = netdev_priv(ndev);
1897	rdev->ndev = ndev;
1898	rdev->priv = priv;
1899	priv->rdev[index] = rdev;
1900	rdev->port = index;
1901	rdev->etha = &priv->etha[index];
1902	rdev->addr = priv->addr;
1903
1904	ndev->base_addr = (unsigned long)rdev->addr;
1905	snprintf(ndev->name, IFNAMSIZ, "tsn%d", index);
1906	ndev->netdev_ops = &rswitch_netdev_ops;
1907	ndev->ethtool_ops = &rswitch_ethtool_ops;
1908	ndev->max_mtu = RSWITCH_MAX_MTU;
1909	ndev->min_mtu = ETH_MIN_MTU;
1910
1911	netif_napi_add(ndev, &rdev->napi, rswitch_poll);
1912
1913	rdev->np_port = rswitch_get_port_node(rdev);
1914	rdev->disabled = !rdev->np_port;
1915	err = of_get_ethdev_address(rdev->np_port, ndev);
 
1916	if (err) {
1917		if (is_valid_ether_addr(rdev->etha->mac_addr))
1918			eth_hw_addr_set(ndev, rdev->etha->mac_addr);
1919		else
1920			eth_hw_addr_random(ndev);
1921	}
1922
1923	err = rswitch_etha_get_params(rdev);
1924	if (err < 0)
1925		goto out_get_params;
1926
1927	if (rdev->priv->gwca.speed < rdev->etha->speed)
1928		rdev->priv->gwca.speed = rdev->etha->speed;
1929
1930	err = rswitch_rxdmac_alloc(ndev);
1931	if (err < 0)
1932		goto out_rxdmac;
1933
1934	err = rswitch_txdmac_alloc(ndev);
1935	if (err < 0)
1936		goto out_txdmac;
1937
1938	return 0;
1939
1940out_txdmac:
1941	rswitch_rxdmac_free(ndev);
1942
1943out_rxdmac:
1944out_get_params:
1945	of_node_put(rdev->np_port);
1946	netif_napi_del(&rdev->napi);
1947	free_netdev(ndev);
1948
1949	return err;
1950}
1951
1952static void rswitch_device_free(struct rswitch_private *priv, unsigned int index)
1953{
1954	struct rswitch_device *rdev = priv->rdev[index];
1955	struct net_device *ndev = rdev->ndev;
1956
1957	rswitch_txdmac_free(ndev);
1958	rswitch_rxdmac_free(ndev);
1959	of_node_put(rdev->np_port);
1960	netif_napi_del(&rdev->napi);
1961	free_netdev(ndev);
1962}
1963
1964static int rswitch_init(struct rswitch_private *priv)
1965{
1966	unsigned int i;
1967	int err;
1968
1969	for (i = 0; i < RSWITCH_NUM_PORTS; i++)
1970		rswitch_etha_init(priv, i);
1971
1972	rswitch_clock_enable(priv);
1973	for (i = 0; i < RSWITCH_NUM_PORTS; i++)
1974		rswitch_etha_read_mac_address(&priv->etha[i]);
1975
1976	rswitch_reset(priv);
1977
1978	rswitch_clock_enable(priv);
1979	rswitch_top_init(priv);
1980	err = rswitch_bpool_config(priv);
1981	if (err < 0)
1982		return err;
1983
1984	rswitch_coma_init(priv);
1985
1986	err = rswitch_gwca_linkfix_alloc(priv);
1987	if (err < 0)
1988		return -ENOMEM;
1989
1990	err = rswitch_gwca_ts_queue_alloc(priv);
1991	if (err < 0)
1992		goto err_ts_queue_alloc;
1993
1994	for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
1995		err = rswitch_device_alloc(priv, i);
1996		if (err < 0) {
1997			for (; i-- > 0; )
1998				rswitch_device_free(priv, i);
1999			goto err_device_alloc;
2000		}
2001	}
2002
2003	rswitch_fwd_init(priv);
2004
2005	err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT,
2006				     clk_get_rate(priv->clk));
2007	if (err < 0)
2008		goto err_ptp_register;
2009
2010	err = rswitch_gwca_request_irqs(priv);
2011	if (err < 0)
2012		goto err_gwca_request_irq;
2013
2014	err = rswitch_gwca_ts_request_irqs(priv);
2015	if (err < 0)
2016		goto err_gwca_ts_request_irq;
2017
2018	err = rswitch_gwca_hw_init(priv);
2019	if (err < 0)
2020		goto err_gwca_hw_init;
2021
2022	err = rswitch_ether_port_init_all(priv);
2023	if (err)
2024		goto err_ether_port_init_all;
2025
2026	rswitch_for_each_enabled_port(priv, i) {
2027		err = register_netdev(priv->rdev[i]->ndev);
2028		if (err) {
2029			rswitch_for_each_enabled_port_continue_reverse(priv, i)
2030				unregister_netdev(priv->rdev[i]->ndev);
2031			goto err_register_netdev;
2032		}
2033	}
2034
2035	rswitch_for_each_enabled_port(priv, i)
2036		netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n",
2037			    priv->rdev[i]->ndev->dev_addr);
2038
2039	return 0;
2040
2041err_register_netdev:
2042	rswitch_ether_port_deinit_all(priv);
2043
2044err_ether_port_init_all:
2045	rswitch_gwca_hw_deinit(priv);
2046
2047err_gwca_hw_init:
2048err_gwca_ts_request_irq:
2049err_gwca_request_irq:
2050	rcar_gen4_ptp_unregister(priv->ptp_priv);
2051
2052err_ptp_register:
2053	for (i = 0; i < RSWITCH_NUM_PORTS; i++)
2054		rswitch_device_free(priv, i);
2055
2056err_device_alloc:
2057	rswitch_gwca_ts_queue_free(priv);
2058
2059err_ts_queue_alloc:
2060	rswitch_gwca_linkfix_free(priv);
2061
2062	return err;
2063}
2064
2065static const struct soc_device_attribute rswitch_soc_no_speed_change[]  = {
2066	{ .soc_id = "r8a779f0", .revision = "ES1.0" },
2067	{ /* Sentinel */ }
2068};
2069
2070static int renesas_eth_sw_probe(struct platform_device *pdev)
2071{
2072	const struct soc_device_attribute *attr;
2073	struct rswitch_private *priv;
2074	struct resource *res;
2075	int ret;
2076
2077	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base");
2078	if (!res) {
2079		dev_err(&pdev->dev, "invalid resource\n");
2080		return -EINVAL;
2081	}
2082
2083	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2084	if (!priv)
2085		return -ENOMEM;
2086	spin_lock_init(&priv->lock);
2087
2088	priv->clk = devm_clk_get(&pdev->dev, NULL);
2089	if (IS_ERR(priv->clk))
2090		return PTR_ERR(priv->clk);
2091
2092	attr = soc_device_match(rswitch_soc_no_speed_change);
2093	if (attr)
2094		priv->etha_no_runtime_change = true;
2095
2096	priv->ptp_priv = rcar_gen4_ptp_alloc(pdev);
2097	if (!priv->ptp_priv)
2098		return -ENOMEM;
2099
2100	platform_set_drvdata(pdev, priv);
2101	priv->pdev = pdev;
2102	priv->addr = devm_ioremap_resource(&pdev->dev, res);
2103	if (IS_ERR(priv->addr))
2104		return PTR_ERR(priv->addr);
2105
2106	priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4;
2107
2108	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
2109	if (ret < 0) {
2110		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2111		if (ret < 0)
2112			return ret;
2113	}
2114
2115	priv->gwca.index = AGENT_INDEX_GWCA;
2116	priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV,
2117				    RSWITCH_MAX_NUM_QUEUES);
2118	priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues,
2119					 sizeof(*priv->gwca.queues), GFP_KERNEL);
2120	if (!priv->gwca.queues)
2121		return -ENOMEM;
2122
2123	pm_runtime_enable(&pdev->dev);
2124	pm_runtime_get_sync(&pdev->dev);
2125
2126	ret = rswitch_init(priv);
2127	if (ret < 0) {
2128		pm_runtime_put(&pdev->dev);
2129		pm_runtime_disable(&pdev->dev);
2130		return ret;
2131	}
2132
2133	device_set_wakeup_capable(&pdev->dev, 1);
2134
2135	return ret;
2136}
2137
2138static void rswitch_deinit(struct rswitch_private *priv)
2139{
2140	unsigned int i;
2141
2142	rswitch_gwca_hw_deinit(priv);
2143	rcar_gen4_ptp_unregister(priv->ptp_priv);
2144
2145	rswitch_for_each_enabled_port(priv, i) {
2146		struct rswitch_device *rdev = priv->rdev[i];
2147
2148		unregister_netdev(rdev->ndev);
2149		rswitch_ether_port_deinit_one(rdev);
2150		phy_exit(priv->rdev[i]->serdes);
2151	}
2152
2153	for (i = 0; i < RSWITCH_NUM_PORTS; i++)
2154		rswitch_device_free(priv, i);
 
2155
2156	rswitch_gwca_ts_queue_free(priv);
2157	rswitch_gwca_linkfix_free(priv);
2158
2159	rswitch_clock_disable(priv);
2160}
2161
2162static void renesas_eth_sw_remove(struct platform_device *pdev)
2163{
2164	struct rswitch_private *priv = platform_get_drvdata(pdev);
2165
2166	rswitch_deinit(priv);
2167
2168	pm_runtime_put(&pdev->dev);
2169	pm_runtime_disable(&pdev->dev);
2170
2171	platform_set_drvdata(pdev, NULL);
2172}
2173
2174static int renesas_eth_sw_suspend(struct device *dev)
2175{
2176	struct rswitch_private *priv = dev_get_drvdata(dev);
2177	struct net_device *ndev;
2178	unsigned int i;
2179
2180	rswitch_for_each_enabled_port(priv, i) {
2181		ndev = priv->rdev[i]->ndev;
2182		if (netif_running(ndev)) {
2183			netif_device_detach(ndev);
2184			rswitch_stop(ndev);
2185		}
2186		if (priv->rdev[i]->serdes->init_count)
2187			phy_exit(priv->rdev[i]->serdes);
2188	}
2189
2190	return 0;
2191}
2192
2193static int renesas_eth_sw_resume(struct device *dev)
2194{
2195	struct rswitch_private *priv = dev_get_drvdata(dev);
2196	struct net_device *ndev;
2197	unsigned int i;
2198
2199	rswitch_for_each_enabled_port(priv, i) {
2200		phy_init(priv->rdev[i]->serdes);
2201		ndev = priv->rdev[i]->ndev;
2202		if (netif_running(ndev)) {
2203			rswitch_open(ndev);
2204			netif_device_attach(ndev);
2205		}
2206	}
2207
2208	return 0;
2209}
2210
2211static DEFINE_SIMPLE_DEV_PM_OPS(renesas_eth_sw_pm_ops, renesas_eth_sw_suspend,
2212				renesas_eth_sw_resume);
2213
2214static struct platform_driver renesas_eth_sw_driver_platform = {
2215	.probe = renesas_eth_sw_probe,
2216	.remove = renesas_eth_sw_remove,
2217	.driver = {
2218		.name = "renesas_eth_sw",
2219		.pm = pm_sleep_ptr(&renesas_eth_sw_pm_ops),
2220		.of_match_table = renesas_eth_sw_of_table,
2221	}
2222};
2223module_platform_driver(renesas_eth_sw_driver_platform);
2224MODULE_AUTHOR("Yoshihiro Shimoda");
2225MODULE_DESCRIPTION("Renesas Ethernet Switch device driver");
2226MODULE_LICENSE("GPL");