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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2021, Intel Corporation. */
3
4#ifndef _ICE_PTP_H_
5#define _ICE_PTP_H_
6
7#include <linux/ptp_clock_kernel.h>
8#include <linux/kthread.h>
9
10#include "ice_ptp_hw.h"
11
12/* The ice hardware captures Tx hardware timestamps in the PHY. The timestamp
13 * is stored in a buffer of registers. Depending on the specific hardware,
14 * this buffer might be shared across multiple PHY ports.
15 *
16 * On transmit of a packet to be timestamped, software is responsible for
17 * selecting an open index. Hardware makes no attempt to lock or prevent
18 * re-use of an index for multiple packets.
19 *
20 * To handle this, timestamp indexes must be tracked by software to ensure
21 * that an index is not re-used for multiple transmitted packets. The
22 * structures and functions declared in this file track the available Tx
23 * register indexes, as well as provide storage for the SKB pointers.
24 *
25 * To allow multiple ports to access the shared register block independently,
26 * the blocks are split up so that indexes are assigned to each port based on
27 * hardware logical port number.
28 *
29 * The timestamp blocks are handled differently for E810- and E822-based
30 * devices. In E810 devices, each port has its own block of timestamps, while in
31 * E822 there is a need to logically break the block of registers into smaller
32 * chunks based on the port number to avoid collisions.
33 *
34 * Example for port 5 in E810:
35 * +--------+--------+--------+--------+--------+--------+--------+--------+
36 * |register|register|register|register|register|register|register|register|
37 * | block | block | block | block | block | block | block | block |
38 * | for | for | for | for | for | for | for | for |
39 * | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
40 * +--------+--------+--------+--------+--------+--------+--------+--------+
41 * ^^
42 * ||
43 * |--- quad offset is always 0
44 * ---- quad number
45 *
46 * Example for port 5 in E822:
47 * +-----------------------------+-----------------------------+
48 * | register block for quad 0 | register block for quad 1 |
49 * |+------+------+------+------+|+------+------+------+------+|
50 * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
51 * |+------+------+------+------+|+------+------+------+------+|
52 * +-----------------------------+-------^---------------------+
53 * ^ |
54 * | --- quad offset*
55 * ---- quad number
56 *
57 * * PHY port 5 is port 1 in quad 1
58 *
59 */
60
61/**
62 * struct ice_tx_tstamp - Tracking for a single Tx timestamp
63 * @skb: pointer to the SKB for this timestamp request
64 * @start: jiffies when the timestamp was first requested
65 * @cached_tstamp: last read timestamp
66 *
67 * This structure tracks a single timestamp request. The SKB pointer is
68 * provided when initiating a request. The start time is used to ensure that
69 * we discard old requests that were not fulfilled within a 2 second time
70 * window.
71 * Timestamp values in the PHY are read only and do not get cleared except at
72 * hardware reset or when a new timestamp value is captured.
73 *
74 * Some PHY types do not provide a "ready" bitmap indicating which timestamp
75 * indexes are valid. In these cases, we use a cached_tstamp to keep track of
76 * the last timestamp we read for a given index. If the current timestamp
77 * value is the same as the cached value, we assume a new timestamp hasn't
78 * been captured. This avoids reporting stale timestamps to the stack. This is
79 * only done if the has_ready_bitmap flag is not set in ice_ptp_tx structure.
80 */
81struct ice_tx_tstamp {
82 struct sk_buff *skb;
83 unsigned long start;
84 u64 cached_tstamp;
85};
86
87/**
88 * enum ice_tx_tstamp_work - Status of Tx timestamp work function
89 * @ICE_TX_TSTAMP_WORK_DONE: Tx timestamp processing is complete
90 * @ICE_TX_TSTAMP_WORK_PENDING: More Tx timestamps are pending
91 */
92enum ice_tx_tstamp_work {
93 ICE_TX_TSTAMP_WORK_DONE = 0,
94 ICE_TX_TSTAMP_WORK_PENDING,
95};
96
97/**
98 * struct ice_ptp_tx - Tracking structure for all Tx timestamp requests on a port
99 * @lock: lock to prevent concurrent access to fields of this struct
100 * @tstamps: array of len to store outstanding requests
101 * @in_use: bitmap of len to indicate which slots are in use
102 * @stale: bitmap of len to indicate slots which have stale timestamps
103 * @block: which memory block (quad or port) the timestamps are captured in
104 * @offset: offset into timestamp block to get the real index
105 * @len: length of the tstamps and in_use fields.
106 * @init: if true, the tracker is initialized;
107 * @calibrating: if true, the PHY is calibrating the Tx offset. During this
108 * window, timestamps are temporarily disabled.
109 * @has_ready_bitmap: if true, the hardware has a valid Tx timestamp ready
110 * bitmap register. If false, fall back to verifying new
111 * timestamp values against previously cached copy.
112 * @last_ll_ts_idx_read: index of the last LL TS read by the FW
113 */
114struct ice_ptp_tx {
115 spinlock_t lock; /* lock protecting in_use bitmap */
116 struct ice_tx_tstamp *tstamps;
117 unsigned long *in_use;
118 unsigned long *stale;
119 u8 block;
120 u8 offset;
121 u8 len;
122 u8 init : 1;
123 u8 calibrating : 1;
124 u8 has_ready_bitmap : 1;
125 s8 last_ll_ts_idx_read;
126};
127
128/* Quad and port information for initializing timestamp blocks */
129#define INDEX_PER_QUAD 64
130#define INDEX_PER_PORT_E82X 16
131#define INDEX_PER_PORT_E810 64
132#define INDEX_PER_PORT_ETH56G 64
133
134/**
135 * struct ice_ptp_port - data used to initialize an external port for PTP
136 *
137 * This structure contains data indicating whether a single external port is
138 * ready for PTP functionality. It is used to track the port initialization
139 * and determine when the port's PHY offset is valid.
140 *
141 * @list_node: list member structure
142 * @tx: Tx timestamp tracking for this port
143 * @ov_work: delayed work task for tracking when PHY offset is valid
144 * @ps_lock: mutex used to protect the overall PTP PHY start procedure
145 * @link_up: indicates whether the link is up
146 * @tx_fifo_busy_cnt: number of times the Tx FIFO was busy
147 * @port_num: the port number this structure represents
148 */
149struct ice_ptp_port {
150 struct list_head list_node;
151 struct ice_ptp_tx tx;
152 struct kthread_delayed_work ov_work;
153 struct mutex ps_lock; /* protects overall PTP PHY start procedure */
154 bool link_up;
155 u8 tx_fifo_busy_cnt;
156 u8 port_num;
157};
158
159enum ice_ptp_tx_interrupt {
160 ICE_PTP_TX_INTERRUPT_NONE = 0,
161 ICE_PTP_TX_INTERRUPT_SELF,
162 ICE_PTP_TX_INTERRUPT_ALL,
163};
164
165#define GLTSYN_TGT_H_IDX_MAX 4
166
167enum ice_ptp_state {
168 ICE_PTP_UNINIT = 0,
169 ICE_PTP_INITIALIZING,
170 ICE_PTP_READY,
171 ICE_PTP_RESETTING,
172 ICE_PTP_ERROR,
173};
174
175enum ice_ptp_pin {
176 SDP0 = 0,
177 SDP1,
178 SDP2,
179 SDP3,
180 TIME_SYNC,
181 ONE_PPS
182};
183
184enum ice_ptp_pin_nvm {
185 GNSS = 0,
186 SMA1,
187 UFL1,
188 SMA2,
189 UFL2,
190 NUM_PTP_PINS_NVM,
191 GPIO_NA = 9
192};
193
194/* Per-channel register definitions */
195#define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
196#define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8))
197#define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8))
198#define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))
199#define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))
200#define GLTSYN_EVNT_L(_chan, _idx) (GLTSYN_EVNT_L_0(_idx) + ((_chan) * 16))
201#define GLTSYN_EVNT_H(_chan, _idx) (GLTSYN_EVNT_H_0(_idx) + ((_chan) * 16))
202#define GLTSYN_EVNT_H_IDX_MAX 3
203
204/* Pin definitions for PTP */
205#define ICE_N_PINS_MAX 6
206#define ICE_SMA_PINS_NUM 4
207#define ICE_PIN_DESC_ARR_LEN(_arr) (sizeof(_arr) / \
208 sizeof(struct ice_ptp_pin_desc))
209
210/**
211 * struct ice_ptp_pin_desc - hardware pin description data
212 * @name_idx: index of the name of pin in ice_pin_names
213 * @gpio: the associated GPIO input and output pins
214 *
215 * Structure describing a PTP-capable GPIO pin that extends ptp_pin_desc array
216 * for the device. Device families have separate sets of available pins with
217 * varying restrictions.
218 */
219struct ice_ptp_pin_desc {
220 int name_idx;
221 int gpio[2];
222};
223
224/**
225 * struct ice_ptp - data used for integrating with CONFIG_PTP_1588_CLOCK
226 * @state: current state of PTP state machine
227 * @tx_interrupt_mode: the TX interrupt mode for the PTP clock
228 * @port: data for the PHY port initialization procedure
229 * @work: delayed work function for periodic tasks
230 * @cached_phc_time: a cached copy of the PHC time for timestamp extension
231 * @cached_phc_jiffies: jiffies when cached_phc_time was last updated
232 * @kworker: kwork thread for handling periodic work
233 * @ext_ts_irq: the external timestamp IRQ in use
234 * @pin_desc: structure defining pins
235 * @ice_pin_desc: internal structure describing pin relations
236 * @perout_rqs: cached periodic output requests
237 * @extts_rqs: cached external timestamp requests
238 * @info: structure defining PTP hardware capabilities
239 * @clock: pointer to registered PTP clock device
240 * @tstamp_config: hardware timestamping configuration
241 * @reset_time: kernel time after clock stop on reset
242 * @tx_hwtstamp_skipped: number of Tx time stamp requests skipped
243 * @tx_hwtstamp_timeouts: number of Tx skbs discarded with no time stamp
244 * @tx_hwtstamp_flushed: number of Tx skbs flushed due to interface closed
245 * @tx_hwtstamp_discarded: number of Tx skbs discarded due to cached PHC time
246 * being too old to correctly extend timestamp
247 * @late_cached_phc_updates: number of times cached PHC update is late
248 */
249struct ice_ptp {
250 enum ice_ptp_state state;
251 enum ice_ptp_tx_interrupt tx_interrupt_mode;
252 struct ice_ptp_port port;
253 struct kthread_delayed_work work;
254 u64 cached_phc_time;
255 unsigned long cached_phc_jiffies;
256 struct kthread_worker *kworker;
257 u8 ext_ts_irq;
258 struct ptp_pin_desc pin_desc[ICE_N_PINS_MAX];
259 const struct ice_ptp_pin_desc *ice_pin_desc;
260 struct ptp_perout_request perout_rqs[GLTSYN_TGT_H_IDX_MAX];
261 struct ptp_extts_request extts_rqs[GLTSYN_EVNT_H_IDX_MAX];
262 struct ptp_clock_info info;
263 struct ptp_clock *clock;
264 struct hwtstamp_config tstamp_config;
265 u64 reset_time;
266 u32 tx_hwtstamp_skipped;
267 u32 tx_hwtstamp_timeouts;
268 u32 tx_hwtstamp_flushed;
269 u32 tx_hwtstamp_discarded;
270 u32 late_cached_phc_updates;
271};
272
273#define __ptp_port_to_ptp(p) \
274 container_of((p), struct ice_ptp, port)
275#define ptp_port_to_pf(p) \
276 container_of(__ptp_port_to_ptp((p)), struct ice_pf, ptp)
277
278#define __ptp_info_to_ptp(i) \
279 container_of((i), struct ice_ptp, info)
280#define ptp_info_to_pf(i) \
281 container_of(__ptp_info_to_ptp((i)), struct ice_pf, ptp)
282
283#define PFTSYN_SEM_BYTES 4
284#define PTP_SHARED_CLK_IDX_VALID BIT(31)
285#define TS_CMD_MASK 0xF
286#define SYNC_EXEC_CMD 0x3
287#define ICE_PTP_TS_VALID BIT(0)
288
289#define FIFO_EMPTY BIT(2)
290#define FIFO_OK 0xFF
291#define ICE_PTP_FIFO_NUM_CHECKS 5
292
293#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
294int ice_ptp_clock_index(struct ice_pf *pf);
295struct ice_pf;
296int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr);
297int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr);
298void ice_ptp_restore_timestamp_mode(struct ice_pf *pf);
299
300void ice_ptp_extts_event(struct ice_pf *pf);
301s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb);
302void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx);
303void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx);
304enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf);
305
306u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc,
307 const struct ice_pkt_ctx *pkt_ctx);
308void ice_ptp_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type);
309void ice_ptp_prepare_for_reset(struct ice_pf *pf,
310 enum ice_reset_req reset_type);
311void ice_ptp_init(struct ice_pf *pf);
312void ice_ptp_release(struct ice_pf *pf);
313void ice_ptp_link_change(struct ice_pf *pf, bool linkup);
314#else /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */
315static inline int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
316{
317 return -EOPNOTSUPP;
318}
319
320static inline int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
321{
322 return -EOPNOTSUPP;
323}
324
325static inline void ice_ptp_restore_timestamp_mode(struct ice_pf *pf) { }
326static inline void ice_ptp_extts_event(struct ice_pf *pf) { }
327static inline s8
328ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
329{
330 return -1;
331}
332
333static inline void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx)
334{ }
335
336static inline void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx) { }
337
338static inline bool ice_ptp_process_ts(struct ice_pf *pf)
339{
340 return true;
341}
342
343static inline u64
344ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc,
345 const struct ice_pkt_ctx *pkt_ctx)
346{
347 return 0;
348}
349
350static inline void ice_ptp_rebuild(struct ice_pf *pf,
351 enum ice_reset_req reset_type)
352{
353}
354
355static inline void ice_ptp_prepare_for_reset(struct ice_pf *pf,
356 enum ice_reset_req reset_type)
357{
358}
359static inline void ice_ptp_init(struct ice_pf *pf) { }
360static inline void ice_ptp_release(struct ice_pf *pf) { }
361static inline void ice_ptp_link_change(struct ice_pf *pf, bool linkup)
362{
363}
364
365static inline int ice_ptp_clock_index(struct ice_pf *pf)
366{
367 return -1;
368}
369#endif /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */
370#endif /* _ICE_PTP_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2021, Intel Corporation. */
3
4#ifndef _ICE_PTP_H_
5#define _ICE_PTP_H_
6
7#include <linux/ptp_clock_kernel.h>
8#include <linux/kthread.h>
9
10#include "ice_ptp_hw.h"
11
12enum ice_ptp_pin_e810 {
13 GPIO_20 = 0,
14 GPIO_21,
15 GPIO_22,
16 GPIO_23,
17 NUM_PTP_PIN_E810
18};
19
20enum ice_ptp_pin_e810t {
21 GNSS = 0,
22 SMA1,
23 UFL1,
24 SMA2,
25 UFL2,
26 NUM_PTP_PINS_E810T
27};
28
29struct ice_perout_channel {
30 bool ena;
31 u32 gpio_pin;
32 u64 period;
33 u64 start_time;
34};
35
36/* The ice hardware captures Tx hardware timestamps in the PHY. The timestamp
37 * is stored in a buffer of registers. Depending on the specific hardware,
38 * this buffer might be shared across multiple PHY ports.
39 *
40 * On transmit of a packet to be timestamped, software is responsible for
41 * selecting an open index. Hardware makes no attempt to lock or prevent
42 * re-use of an index for multiple packets.
43 *
44 * To handle this, timestamp indexes must be tracked by software to ensure
45 * that an index is not re-used for multiple transmitted packets. The
46 * structures and functions declared in this file track the available Tx
47 * register indexes, as well as provide storage for the SKB pointers.
48 *
49 * To allow multiple ports to access the shared register block independently,
50 * the blocks are split up so that indexes are assigned to each port based on
51 * hardware logical port number.
52 *
53 * The timestamp blocks are handled differently for E810- and E822-based
54 * devices. In E810 devices, each port has its own block of timestamps, while in
55 * E822 there is a need to logically break the block of registers into smaller
56 * chunks based on the port number to avoid collisions.
57 *
58 * Example for port 5 in E810:
59 * +--------+--------+--------+--------+--------+--------+--------+--------+
60 * |register|register|register|register|register|register|register|register|
61 * | block | block | block | block | block | block | block | block |
62 * | for | for | for | for | for | for | for | for |
63 * | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
64 * +--------+--------+--------+--------+--------+--------+--------+--------+
65 * ^^
66 * ||
67 * |--- quad offset is always 0
68 * ---- quad number
69 *
70 * Example for port 5 in E822:
71 * +-----------------------------+-----------------------------+
72 * | register block for quad 0 | register block for quad 1 |
73 * |+------+------+------+------+|+------+------+------+------+|
74 * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
75 * |+------+------+------+------+|+------+------+------+------+|
76 * +-----------------------------+-------^---------------------+
77 * ^ |
78 * | --- quad offset*
79 * ---- quad number
80 *
81 * * PHY port 5 is port 1 in quad 1
82 *
83 */
84
85/**
86 * struct ice_tx_tstamp - Tracking for a single Tx timestamp
87 * @skb: pointer to the SKB for this timestamp request
88 * @start: jiffies when the timestamp was first requested
89 * @cached_tstamp: last read timestamp
90 *
91 * This structure tracks a single timestamp request. The SKB pointer is
92 * provided when initiating a request. The start time is used to ensure that
93 * we discard old requests that were not fulfilled within a 2 second time
94 * window.
95 * Timestamp values in the PHY are read only and do not get cleared except at
96 * hardware reset or when a new timestamp value is captured.
97 *
98 * Some PHY types do not provide a "ready" bitmap indicating which timestamp
99 * indexes are valid. In these cases, we use a cached_tstamp to keep track of
100 * the last timestamp we read for a given index. If the current timestamp
101 * value is the same as the cached value, we assume a new timestamp hasn't
102 * been captured. This avoids reporting stale timestamps to the stack. This is
103 * only done if the verify_cached flag is set in ice_ptp_tx structure.
104 */
105struct ice_tx_tstamp {
106 struct sk_buff *skb;
107 unsigned long start;
108 u64 cached_tstamp;
109};
110
111/**
112 * struct ice_ptp_tx - Tracking structure for all Tx timestamp requests on a port
113 * @lock: lock to prevent concurrent access to fields of this struct
114 * @tstamps: array of len to store outstanding requests
115 * @in_use: bitmap of len to indicate which slots are in use
116 * @stale: bitmap of len to indicate slots which have stale timestamps
117 * @block: which memory block (quad or port) the timestamps are captured in
118 * @offset: offset into timestamp block to get the real index
119 * @len: length of the tstamps and in_use fields.
120 * @init: if true, the tracker is initialized;
121 * @calibrating: if true, the PHY is calibrating the Tx offset. During this
122 * window, timestamps are temporarily disabled.
123 * @verify_cached: if true, verify new timestamp differs from last read value
124 */
125struct ice_ptp_tx {
126 spinlock_t lock; /* lock protecting in_use bitmap */
127 struct ice_tx_tstamp *tstamps;
128 unsigned long *in_use;
129 unsigned long *stale;
130 u8 block;
131 u8 offset;
132 u8 len;
133 u8 init : 1;
134 u8 calibrating : 1;
135 u8 verify_cached : 1;
136};
137
138/* Quad and port information for initializing timestamp blocks */
139#define INDEX_PER_QUAD 64
140#define INDEX_PER_PORT_E822 16
141#define INDEX_PER_PORT_E810 64
142
143/**
144 * struct ice_ptp_port - data used to initialize an external port for PTP
145 *
146 * This structure contains data indicating whether a single external port is
147 * ready for PTP functionality. It is used to track the port initialization
148 * and determine when the port's PHY offset is valid.
149 *
150 * @tx: Tx timestamp tracking for this port
151 * @ov_work: delayed work task for tracking when PHY offset is valid
152 * @ps_lock: mutex used to protect the overall PTP PHY start procedure
153 * @link_up: indicates whether the link is up
154 * @tx_fifo_busy_cnt: number of times the Tx FIFO was busy
155 * @port_num: the port number this structure represents
156 */
157struct ice_ptp_port {
158 struct ice_ptp_tx tx;
159 struct kthread_delayed_work ov_work;
160 struct mutex ps_lock; /* protects overall PTP PHY start procedure */
161 bool link_up;
162 u8 tx_fifo_busy_cnt;
163 u8 port_num;
164};
165
166#define GLTSYN_TGT_H_IDX_MAX 4
167
168/**
169 * struct ice_ptp - data used for integrating with CONFIG_PTP_1588_CLOCK
170 * @port: data for the PHY port initialization procedure
171 * @work: delayed work function for periodic tasks
172 * @extts_work: work function for handling external Tx timestamps
173 * @cached_phc_time: a cached copy of the PHC time for timestamp extension
174 * @cached_phc_jiffies: jiffies when cached_phc_time was last updated
175 * @ext_ts_chan: the external timestamp channel in use
176 * @ext_ts_irq: the external timestamp IRQ in use
177 * @kworker: kwork thread for handling periodic work
178 * @perout_channels: periodic output data
179 * @info: structure defining PTP hardware capabilities
180 * @clock: pointer to registered PTP clock device
181 * @tstamp_config: hardware timestamping configuration
182 * @reset_time: kernel time after clock stop on reset
183 * @tx_hwtstamp_skipped: number of Tx time stamp requests skipped
184 * @tx_hwtstamp_timeouts: number of Tx skbs discarded with no time stamp
185 * @tx_hwtstamp_flushed: number of Tx skbs flushed due to interface closed
186 * @tx_hwtstamp_discarded: number of Tx skbs discarded due to cached PHC time
187 * being too old to correctly extend timestamp
188 * @late_cached_phc_updates: number of times cached PHC update is late
189 */
190struct ice_ptp {
191 struct ice_ptp_port port;
192 struct kthread_delayed_work work;
193 struct kthread_work extts_work;
194 u64 cached_phc_time;
195 unsigned long cached_phc_jiffies;
196 u8 ext_ts_chan;
197 u8 ext_ts_irq;
198 struct kthread_worker *kworker;
199 struct ice_perout_channel perout_channels[GLTSYN_TGT_H_IDX_MAX];
200 struct ptp_clock_info info;
201 struct ptp_clock *clock;
202 struct hwtstamp_config tstamp_config;
203 u64 reset_time;
204 u32 tx_hwtstamp_skipped;
205 u32 tx_hwtstamp_timeouts;
206 u32 tx_hwtstamp_flushed;
207 u32 tx_hwtstamp_discarded;
208 u32 late_cached_phc_updates;
209};
210
211#define __ptp_port_to_ptp(p) \
212 container_of((p), struct ice_ptp, port)
213#define ptp_port_to_pf(p) \
214 container_of(__ptp_port_to_ptp((p)), struct ice_pf, ptp)
215
216#define __ptp_info_to_ptp(i) \
217 container_of((i), struct ice_ptp, info)
218#define ptp_info_to_pf(i) \
219 container_of(__ptp_info_to_ptp((i)), struct ice_pf, ptp)
220
221#define PFTSYN_SEM_BYTES 4
222#define PTP_SHARED_CLK_IDX_VALID BIT(31)
223#define TS_CMD_MASK 0xF
224#define SYNC_EXEC_CMD 0x3
225#define ICE_PTP_TS_VALID BIT(0)
226
227#define FIFO_EMPTY BIT(2)
228#define FIFO_OK 0xFF
229#define ICE_PTP_FIFO_NUM_CHECKS 5
230/* Per-channel register definitions */
231#define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
232#define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8))
233#define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8))
234#define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))
235#define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))
236#define GLTSYN_EVNT_L(_chan, _idx) (GLTSYN_EVNT_L_0(_idx) + ((_chan) * 16))
237#define GLTSYN_EVNT_H(_chan, _idx) (GLTSYN_EVNT_H_0(_idx) + ((_chan) * 16))
238#define GLTSYN_EVNT_H_IDX_MAX 3
239
240/* Pin definitions for PTP PPS out */
241#define PPS_CLK_GEN_CHAN 3
242#define PPS_CLK_SRC_CHAN 2
243#define PPS_PIN_INDEX 5
244#define TIME_SYNC_PIN_INDEX 4
245#define N_EXT_TS_E810 3
246#define N_PER_OUT_E810 4
247#define N_PER_OUT_E810T 3
248#define N_PER_OUT_NO_SMA_E810T 2
249#define N_EXT_TS_NO_SMA_E810T 2
250#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
251
252#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
253struct ice_pf;
254int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr);
255int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr);
256void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena);
257int ice_get_ptp_clock_index(struct ice_pf *pf);
258
259s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb);
260bool ice_ptp_process_ts(struct ice_pf *pf);
261
262void
263ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,
264 union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb);
265void ice_ptp_reset(struct ice_pf *pf);
266void ice_ptp_prepare_for_reset(struct ice_pf *pf);
267void ice_ptp_init(struct ice_pf *pf);
268void ice_ptp_release(struct ice_pf *pf);
269void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup);
270#else /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */
271static inline int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
272{
273 return -EOPNOTSUPP;
274}
275
276static inline int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
277{
278 return -EOPNOTSUPP;
279}
280
281static inline void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena) { }
282static inline int ice_get_ptp_clock_index(struct ice_pf *pf)
283{
284 return -1;
285}
286
287static inline s8
288ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
289{
290 return -1;
291}
292
293static inline bool ice_ptp_process_ts(struct ice_pf *pf)
294{
295 return true;
296}
297static inline void
298ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,
299 union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb) { }
300static inline void ice_ptp_reset(struct ice_pf *pf) { }
301static inline void ice_ptp_prepare_for_reset(struct ice_pf *pf) { }
302static inline void ice_ptp_init(struct ice_pf *pf) { }
303static inline void ice_ptp_release(struct ice_pf *pf) { }
304static inline void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
305{
306}
307#endif /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */
308#endif /* _ICE_PTP_H_ */