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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * dm9000 Ethernet
4 */
5
6#ifndef _DM9000X_H_
7#define _DM9000X_H_
8
9#define DM9000_ID 0x90000A46
10
11/* although the registers are 16 bit, they are 32-bit aligned.
12 */
13
14#define DM9000_NCR 0x00
15#define DM9000_NSR 0x01
16#define DM9000_TCR 0x02
17#define DM9000_TSR1 0x03
18#define DM9000_TSR2 0x04
19#define DM9000_RCR 0x05
20#define DM9000_RSR 0x06
21#define DM9000_ROCR 0x07
22#define DM9000_BPTR 0x08
23#define DM9000_FCTR 0x09
24#define DM9000_FCR 0x0A
25#define DM9000_EPCR 0x0B
26#define DM9000_EPAR 0x0C
27#define DM9000_EPDRL 0x0D
28#define DM9000_EPDRH 0x0E
29#define DM9000_WCR 0x0F
30
31#define DM9000_PAR 0x10
32#define DM9000_MAR 0x16
33
34#define DM9000_GPCR 0x1e
35#define DM9000_GPR 0x1f
36#define DM9000_TRPAL 0x22
37#define DM9000_TRPAH 0x23
38#define DM9000_RWPAL 0x24
39#define DM9000_RWPAH 0x25
40
41#define DM9000_VIDL 0x28
42#define DM9000_VIDH 0x29
43#define DM9000_PIDL 0x2A
44#define DM9000_PIDH 0x2B
45
46#define DM9000_CHIPR 0x2C
47#define DM9000_SMCR 0x2F
48
49#define DM9000_ETXCSR 0x30
50#define DM9000_TCCR 0x31
51#define DM9000_RCSR 0x32
52
53#define CHIPR_DM9000A 0x19
54#define CHIPR_DM9000B 0x1A
55
56#define DM9000_MRCMDX 0xF0
57#define DM9000_MRCMD 0xF2
58#define DM9000_MRRL 0xF4
59#define DM9000_MRRH 0xF5
60#define DM9000_MWCMDX 0xF6
61#define DM9000_MWCMD 0xF8
62#define DM9000_MWRL 0xFA
63#define DM9000_MWRH 0xFB
64#define DM9000_TXPLL 0xFC
65#define DM9000_TXPLH 0xFD
66#define DM9000_ISR 0xFE
67#define DM9000_IMR 0xFF
68
69#define NCR_EXT_PHY (1<<7)
70#define NCR_WAKEEN (1<<6)
71#define NCR_FCOL (1<<4)
72#define NCR_FDX (1<<3)
73
74#define NCR_RESERVED (3<<1)
75#define NCR_MAC_LBK (1<<1)
76#define NCR_RST (1<<0)
77
78#define NSR_SPEED (1<<7)
79#define NSR_LINKST (1<<6)
80#define NSR_WAKEST (1<<5)
81#define NSR_TX2END (1<<3)
82#define NSR_TX1END (1<<2)
83#define NSR_RXOV (1<<1)
84
85#define TCR_TJDIS (1<<6)
86#define TCR_EXCECM (1<<5)
87#define TCR_PAD_DIS2 (1<<4)
88#define TCR_CRC_DIS2 (1<<3)
89#define TCR_PAD_DIS1 (1<<2)
90#define TCR_CRC_DIS1 (1<<1)
91#define TCR_TXREQ (1<<0)
92
93#define TSR_TJTO (1<<7)
94#define TSR_LC (1<<6)
95#define TSR_NC (1<<5)
96#define TSR_LCOL (1<<4)
97#define TSR_COL (1<<3)
98#define TSR_EC (1<<2)
99
100#define RCR_WTDIS (1<<6)
101#define RCR_DIS_LONG (1<<5)
102#define RCR_DIS_CRC (1<<4)
103#define RCR_ALL (1<<3)
104#define RCR_RUNT (1<<2)
105#define RCR_PRMSC (1<<1)
106#define RCR_RXEN (1<<0)
107
108#define RSR_RF (1<<7)
109#define RSR_MF (1<<6)
110#define RSR_LCS (1<<5)
111#define RSR_RWTO (1<<4)
112#define RSR_PLE (1<<3)
113#define RSR_AE (1<<2)
114#define RSR_CE (1<<1)
115#define RSR_FOE (1<<0)
116
117#define WCR_LINKEN (1 << 5)
118#define WCR_SAMPLEEN (1 << 4)
119#define WCR_MAGICEN (1 << 3)
120#define WCR_LINKST (1 << 2)
121#define WCR_SAMPLEST (1 << 1)
122#define WCR_MAGICST (1 << 0)
123
124#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
125#define FCTR_LWOT(ot) ( ot & 0xf )
126
127#define IMR_PAR (1<<7)
128#define IMR_ROOM (1<<3)
129#define IMR_ROM (1<<2)
130#define IMR_PTM (1<<1)
131#define IMR_PRM (1<<0)
132
133#define ISR_ROOS (1<<3)
134#define ISR_ROS (1<<2)
135#define ISR_PTS (1<<1)
136#define ISR_PRS (1<<0)
137#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
138
139#define EPCR_REEP (1<<5)
140#define EPCR_WEP (1<<4)
141#define EPCR_EPOS (1<<3)
142#define EPCR_ERPRR (1<<2)
143#define EPCR_ERPRW (1<<1)
144#define EPCR_ERRE (1<<0)
145
146#define GPCR_GEP_CNTL (1<<0)
147
148#define TCCR_IP (1<<0)
149#define TCCR_TCP (1<<1)
150#define TCCR_UDP (1<<2)
151
152#define RCSR_UDP_BAD (1<<7)
153#define RCSR_TCP_BAD (1<<6)
154#define RCSR_IP_BAD (1<<5)
155#define RCSR_UDP (1<<4)
156#define RCSR_TCP (1<<3)
157#define RCSR_IP (1<<2)
158#define RCSR_CSUM (1<<1)
159#define RCSR_DISCARD (1<<0)
160
161#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
162#define DM9000_PKT_ERR 0x02
163#define DM9000_PKT_MAX 1536 /* Received packet max size */
164
165/* DM9000A / DM9000B definitions */
166
167#define IMR_LNKCHNG (1<<5)
168#define IMR_UNDERRUN (1<<4)
169
170#define ISR_LNKCHNG (1<<5)
171#define ISR_UNDERRUN (1<<4)
172
173/* Davicom MII registers.
174 */
175
176#define MII_DM_DSPCR 0x1b /* DSP Control Register */
177
178#define DSPCR_INIT_PARAM 0xE100 /* DSP init parameter */
179
180#endif /* _DM9000X_H_ */
181
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * dm9000 Ethernet
4 */
5
6#ifndef _DM9000X_H_
7#define _DM9000X_H_
8
9#define DM9000_ID 0x90000A46
10
11/* although the registers are 16 bit, they are 32-bit aligned.
12 */
13
14#define DM9000_NCR 0x00
15#define DM9000_NSR 0x01
16#define DM9000_TCR 0x02
17#define DM9000_TSR1 0x03
18#define DM9000_TSR2 0x04
19#define DM9000_RCR 0x05
20#define DM9000_RSR 0x06
21#define DM9000_ROCR 0x07
22#define DM9000_BPTR 0x08
23#define DM9000_FCTR 0x09
24#define DM9000_FCR 0x0A
25#define DM9000_EPCR 0x0B
26#define DM9000_EPAR 0x0C
27#define DM9000_EPDRL 0x0D
28#define DM9000_EPDRH 0x0E
29#define DM9000_WCR 0x0F
30
31#define DM9000_PAR 0x10
32#define DM9000_MAR 0x16
33
34#define DM9000_GPCR 0x1e
35#define DM9000_GPR 0x1f
36#define DM9000_TRPAL 0x22
37#define DM9000_TRPAH 0x23
38#define DM9000_RWPAL 0x24
39#define DM9000_RWPAH 0x25
40
41#define DM9000_VIDL 0x28
42#define DM9000_VIDH 0x29
43#define DM9000_PIDL 0x2A
44#define DM9000_PIDH 0x2B
45
46#define DM9000_CHIPR 0x2C
47#define DM9000_SMCR 0x2F
48
49#define DM9000_ETXCSR 0x30
50#define DM9000_TCCR 0x31
51#define DM9000_RCSR 0x32
52
53#define CHIPR_DM9000A 0x19
54#define CHIPR_DM9000B 0x1A
55
56#define DM9000_MRCMDX 0xF0
57#define DM9000_MRCMD 0xF2
58#define DM9000_MRRL 0xF4
59#define DM9000_MRRH 0xF5
60#define DM9000_MWCMDX 0xF6
61#define DM9000_MWCMD 0xF8
62#define DM9000_MWRL 0xFA
63#define DM9000_MWRH 0xFB
64#define DM9000_TXPLL 0xFC
65#define DM9000_TXPLH 0xFD
66#define DM9000_ISR 0xFE
67#define DM9000_IMR 0xFF
68
69#define NCR_EXT_PHY (1<<7)
70#define NCR_WAKEEN (1<<6)
71#define NCR_FCOL (1<<4)
72#define NCR_FDX (1<<3)
73
74#define NCR_RESERVED (3<<1)
75#define NCR_MAC_LBK (1<<1)
76#define NCR_RST (1<<0)
77
78#define NSR_SPEED (1<<7)
79#define NSR_LINKST (1<<6)
80#define NSR_WAKEST (1<<5)
81#define NSR_TX2END (1<<3)
82#define NSR_TX1END (1<<2)
83#define NSR_RXOV (1<<1)
84
85#define TCR_TJDIS (1<<6)
86#define TCR_EXCECM (1<<5)
87#define TCR_PAD_DIS2 (1<<4)
88#define TCR_CRC_DIS2 (1<<3)
89#define TCR_PAD_DIS1 (1<<2)
90#define TCR_CRC_DIS1 (1<<1)
91#define TCR_TXREQ (1<<0)
92
93#define TSR_TJTO (1<<7)
94#define TSR_LC (1<<6)
95#define TSR_NC (1<<5)
96#define TSR_LCOL (1<<4)
97#define TSR_COL (1<<3)
98#define TSR_EC (1<<2)
99
100#define RCR_WTDIS (1<<6)
101#define RCR_DIS_LONG (1<<5)
102#define RCR_DIS_CRC (1<<4)
103#define RCR_ALL (1<<3)
104#define RCR_RUNT (1<<2)
105#define RCR_PRMSC (1<<1)
106#define RCR_RXEN (1<<0)
107
108#define RSR_RF (1<<7)
109#define RSR_MF (1<<6)
110#define RSR_LCS (1<<5)
111#define RSR_RWTO (1<<4)
112#define RSR_PLE (1<<3)
113#define RSR_AE (1<<2)
114#define RSR_CE (1<<1)
115#define RSR_FOE (1<<0)
116
117#define WCR_LINKEN (1 << 5)
118#define WCR_SAMPLEEN (1 << 4)
119#define WCR_MAGICEN (1 << 3)
120#define WCR_LINKST (1 << 2)
121#define WCR_SAMPLEST (1 << 1)
122#define WCR_MAGICST (1 << 0)
123
124#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
125#define FCTR_LWOT(ot) ( ot & 0xf )
126
127#define IMR_PAR (1<<7)
128#define IMR_ROOM (1<<3)
129#define IMR_ROM (1<<2)
130#define IMR_PTM (1<<1)
131#define IMR_PRM (1<<0)
132
133#define ISR_ROOS (1<<3)
134#define ISR_ROS (1<<2)
135#define ISR_PTS (1<<1)
136#define ISR_PRS (1<<0)
137#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
138
139#define EPCR_REEP (1<<5)
140#define EPCR_WEP (1<<4)
141#define EPCR_EPOS (1<<3)
142#define EPCR_ERPRR (1<<2)
143#define EPCR_ERPRW (1<<1)
144#define EPCR_ERRE (1<<0)
145
146#define GPCR_GEP_CNTL (1<<0)
147
148#define TCCR_IP (1<<0)
149#define TCCR_TCP (1<<1)
150#define TCCR_UDP (1<<2)
151
152#define RCSR_UDP_BAD (1<<7)
153#define RCSR_TCP_BAD (1<<6)
154#define RCSR_IP_BAD (1<<5)
155#define RCSR_UDP (1<<4)
156#define RCSR_TCP (1<<3)
157#define RCSR_IP (1<<2)
158#define RCSR_CSUM (1<<1)
159#define RCSR_DISCARD (1<<0)
160
161#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
162#define DM9000_PKT_ERR 0x02
163#define DM9000_PKT_MAX 1536 /* Received packet max size */
164
165/* DM9000A / DM9000B definitions */
166
167#define IMR_LNKCHNG (1<<5)
168#define IMR_UNDERRUN (1<<4)
169
170#define ISR_LNKCHNG (1<<5)
171#define ISR_UNDERRUN (1<<4)
172
173/* Davicom MII registers.
174 */
175
176#define MII_DM_DSPCR 0x1b /* DSP Control Register */
177
178#define DSPCR_INIT_PARAM 0xE100 /* DSP init parameter */
179
180#endif /* _DM9000X_H_ */
181