1// SPDX-License-Identifier: GPL-2.0
   2//
   3// flexcan.c - FLEXCAN CAN controller driver
   4//
   5// Copyright (c) 2005-2006 Varma Electronics Oy
   6// Copyright (c) 2009 Sascha Hauer, Pengutronix
   7// Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8// Copyright (c) 2014 David Jander, Protonic Holland
   9//
  10// Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12#include <dt-bindings/firmware/imx/rsrc.h>
  13#include <linux/bitfield.h>
  14#include <linux/can.h>
  15#include <linux/can/dev.h>
  16#include <linux/can/error.h>
  17#include <linux/clk.h>
  18#include <linux/delay.h>
  19#include <linux/firmware/imx/sci.h>
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/mfd/syscon.h>
  23#include <linux/module.h>
  24#include <linux/netdevice.h>
  25#include <linux/of.h>
 
  26#include <linux/pinctrl/consumer.h>
  27#include <linux/platform_device.h>
  28#include <linux/can/platform/flexcan.h>
  29#include <linux/pm_runtime.h>
  30#include <linux/property.h>
  31#include <linux/regmap.h>
  32#include <linux/regulator/consumer.h>
  33
  34#include "flexcan.h"
  35
  36#define DRV_NAME			"flexcan"
  37
  38/* 8 for RX fifo and 2 error handling */
  39#define FLEXCAN_NAPI_WEIGHT		(8 + 2)
  40
  41/* FLEXCAN module configuration register (CANMCR) bits */
  42#define FLEXCAN_MCR_MDIS		BIT(31)
  43#define FLEXCAN_MCR_FRZ			BIT(30)
  44#define FLEXCAN_MCR_FEN			BIT(29)
  45#define FLEXCAN_MCR_HALT		BIT(28)
  46#define FLEXCAN_MCR_NOT_RDY		BIT(27)
  47#define FLEXCAN_MCR_WAK_MSK		BIT(26)
  48#define FLEXCAN_MCR_SOFTRST		BIT(25)
  49#define FLEXCAN_MCR_FRZ_ACK		BIT(24)
  50#define FLEXCAN_MCR_SUPV		BIT(23)
  51#define FLEXCAN_MCR_SLF_WAK		BIT(22)
  52#define FLEXCAN_MCR_WRN_EN		BIT(21)
  53#define FLEXCAN_MCR_LPM_ACK		BIT(20)
  54#define FLEXCAN_MCR_WAK_SRC		BIT(19)
  55#define FLEXCAN_MCR_DOZE		BIT(18)
  56#define FLEXCAN_MCR_SRX_DIS		BIT(17)
  57#define FLEXCAN_MCR_IRMQ		BIT(16)
  58#define FLEXCAN_MCR_LPRIO_EN		BIT(13)
  59#define FLEXCAN_MCR_AEN			BIT(12)
  60#define FLEXCAN_MCR_FDEN		BIT(11)
  61/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  62#define FLEXCAN_MCR_MAXMB(x)		((x) & 0x7f)
  63#define FLEXCAN_MCR_IDAM_A		(0x0 << 8)
  64#define FLEXCAN_MCR_IDAM_B		(0x1 << 8)
  65#define FLEXCAN_MCR_IDAM_C		(0x2 << 8)
  66#define FLEXCAN_MCR_IDAM_D		(0x3 << 8)
  67
  68/* FLEXCAN control register (CANCTRL) bits */
  69#define FLEXCAN_CTRL_PRESDIV(x)		(((x) & 0xff) << 24)
  70#define FLEXCAN_CTRL_RJW(x)		(((x) & 0x03) << 22)
  71#define FLEXCAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
  72#define FLEXCAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
  73#define FLEXCAN_CTRL_BOFF_MSK		BIT(15)
  74#define FLEXCAN_CTRL_ERR_MSK		BIT(14)
  75#define FLEXCAN_CTRL_CLK_SRC		BIT(13)
  76#define FLEXCAN_CTRL_LPB		BIT(12)
  77#define FLEXCAN_CTRL_TWRN_MSK		BIT(11)
  78#define FLEXCAN_CTRL_RWRN_MSK		BIT(10)
  79#define FLEXCAN_CTRL_SMP		BIT(7)
  80#define FLEXCAN_CTRL_BOFF_REC		BIT(6)
  81#define FLEXCAN_CTRL_TSYN		BIT(5)
  82#define FLEXCAN_CTRL_LBUF		BIT(4)
  83#define FLEXCAN_CTRL_LOM		BIT(3)
  84#define FLEXCAN_CTRL_PROPSEG(x)		((x) & 0x07)
  85#define FLEXCAN_CTRL_ERR_BUS		(FLEXCAN_CTRL_ERR_MSK)
  86#define FLEXCAN_CTRL_ERR_STATE \
  87	(FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  88	 FLEXCAN_CTRL_BOFF_MSK)
  89#define FLEXCAN_CTRL_ERR_ALL \
  90	(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  91
  92/* FLEXCAN control register 2 (CTRL2) bits */
  93#define FLEXCAN_CTRL2_ECRWRE		BIT(29)
  94#define FLEXCAN_CTRL2_WRMFRZ		BIT(28)
  95#define FLEXCAN_CTRL2_RFFN(x)		(((x) & 0x0f) << 24)
  96#define FLEXCAN_CTRL2_TASD(x)		(((x) & 0x1f) << 19)
  97#define FLEXCAN_CTRL2_MRP		BIT(18)
  98#define FLEXCAN_CTRL2_RRS		BIT(17)
  99#define FLEXCAN_CTRL2_EACEN		BIT(16)
 100#define FLEXCAN_CTRL2_ISOCANFDEN	BIT(12)
 101
 102/* FLEXCAN memory error control register (MECR) bits */
 103#define FLEXCAN_MECR_ECRWRDIS		BIT(31)
 104#define FLEXCAN_MECR_HANCEI_MSK		BIT(19)
 105#define FLEXCAN_MECR_FANCEI_MSK		BIT(18)
 106#define FLEXCAN_MECR_CEI_MSK		BIT(16)
 107#define FLEXCAN_MECR_HAERRIE		BIT(15)
 108#define FLEXCAN_MECR_FAERRIE		BIT(14)
 109#define FLEXCAN_MECR_EXTERRIE		BIT(13)
 110#define FLEXCAN_MECR_RERRDIS		BIT(9)
 111#define FLEXCAN_MECR_ECCDIS		BIT(8)
 112#define FLEXCAN_MECR_NCEFAFRZ		BIT(7)
 113
 114/* FLEXCAN error and status register (ESR) bits */
 115#define FLEXCAN_ESR_TWRN_INT		BIT(17)
 116#define FLEXCAN_ESR_RWRN_INT		BIT(16)
 117#define FLEXCAN_ESR_BIT1_ERR		BIT(15)
 118#define FLEXCAN_ESR_BIT0_ERR		BIT(14)
 119#define FLEXCAN_ESR_ACK_ERR		BIT(13)
 120#define FLEXCAN_ESR_CRC_ERR		BIT(12)
 121#define FLEXCAN_ESR_FRM_ERR		BIT(11)
 122#define FLEXCAN_ESR_STF_ERR		BIT(10)
 123#define FLEXCAN_ESR_TX_WRN		BIT(9)
 124#define FLEXCAN_ESR_RX_WRN		BIT(8)
 125#define FLEXCAN_ESR_IDLE		BIT(7)
 126#define FLEXCAN_ESR_TXRX		BIT(6)
 127#define FLEXCAN_EST_FLT_CONF_SHIFT	(4)
 128#define FLEXCAN_ESR_FLT_CONF_MASK	(0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 129#define FLEXCAN_ESR_FLT_CONF_ACTIVE	(0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 130#define FLEXCAN_ESR_FLT_CONF_PASSIVE	(0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 131#define FLEXCAN_ESR_BOFF_INT		BIT(2)
 132#define FLEXCAN_ESR_ERR_INT		BIT(1)
 133#define FLEXCAN_ESR_WAK_INT		BIT(0)
 134#define FLEXCAN_ESR_ERR_BUS \
 135	(FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 136	 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 137	 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 138#define FLEXCAN_ESR_ERR_STATE \
 139	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 140#define FLEXCAN_ESR_ERR_ALL \
 141	(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 142#define FLEXCAN_ESR_ALL_INT \
 143	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 144	 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 145
 146/* FLEXCAN Bit Timing register (CBT) bits */
 147#define FLEXCAN_CBT_BTF			BIT(31)
 148#define FLEXCAN_CBT_EPRESDIV_MASK	GENMASK(30, 21)
 149#define FLEXCAN_CBT_ERJW_MASK		GENMASK(20, 16)
 150#define FLEXCAN_CBT_EPROPSEG_MASK	GENMASK(15, 10)
 151#define FLEXCAN_CBT_EPSEG1_MASK		GENMASK(9, 5)
 152#define FLEXCAN_CBT_EPSEG2_MASK		GENMASK(4, 0)
 153
 154/* FLEXCAN FD control register (FDCTRL) bits */
 155#define FLEXCAN_FDCTRL_FDRATE		BIT(31)
 156#define FLEXCAN_FDCTRL_MBDSR1		GENMASK(20, 19)
 157#define FLEXCAN_FDCTRL_MBDSR0		GENMASK(17, 16)
 158#define FLEXCAN_FDCTRL_MBDSR_8		0x0
 159#define FLEXCAN_FDCTRL_MBDSR_12		0x1
 160#define FLEXCAN_FDCTRL_MBDSR_32		0x2
 161#define FLEXCAN_FDCTRL_MBDSR_64		0x3
 162#define FLEXCAN_FDCTRL_TDCEN		BIT(15)
 163#define FLEXCAN_FDCTRL_TDCFAIL		BIT(14)
 164#define FLEXCAN_FDCTRL_TDCOFF		GENMASK(12, 8)
 165#define FLEXCAN_FDCTRL_TDCVAL		GENMASK(5, 0)
 166
 167/* FLEXCAN FD Bit Timing register (FDCBT) bits */
 168#define FLEXCAN_FDCBT_FPRESDIV_MASK	GENMASK(29, 20)
 169#define FLEXCAN_FDCBT_FRJW_MASK		GENMASK(18, 16)
 170#define FLEXCAN_FDCBT_FPROPSEG_MASK	GENMASK(14, 10)
 171#define FLEXCAN_FDCBT_FPSEG1_MASK	GENMASK(7, 5)
 172#define FLEXCAN_FDCBT_FPSEG2_MASK	GENMASK(2, 0)
 173
 174/* FLEXCAN interrupt flag register (IFLAG) bits */
 175/* Errata ERR005829 step7: Reserve first valid MB */
 176#define FLEXCAN_TX_MB_RESERVED_RX_FIFO	8
 177#define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX	0
 178#define FLEXCAN_RX_MB_RX_MAILBOX_FIRST	(FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1)
 179#define FLEXCAN_IFLAG_MB(x)		BIT_ULL(x)
 180#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
 181#define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
 182#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE	BIT(5)
 183
 184/* FLEXCAN message buffers */
 185#define FLEXCAN_MB_CODE_MASK		(0xf << 24)
 186#define FLEXCAN_MB_CODE_RX_BUSY_BIT	(0x1 << 24)
 187#define FLEXCAN_MB_CODE_RX_INACTIVE	(0x0 << 24)
 188#define FLEXCAN_MB_CODE_RX_EMPTY	(0x4 << 24)
 189#define FLEXCAN_MB_CODE_RX_FULL		(0x2 << 24)
 190#define FLEXCAN_MB_CODE_RX_OVERRUN	(0x6 << 24)
 191#define FLEXCAN_MB_CODE_RX_RANSWER	(0xa << 24)
 192
 193#define FLEXCAN_MB_CODE_TX_INACTIVE	(0x8 << 24)
 194#define FLEXCAN_MB_CODE_TX_ABORT	(0x9 << 24)
 195#define FLEXCAN_MB_CODE_TX_DATA		(0xc << 24)
 196#define FLEXCAN_MB_CODE_TX_TANSWER	(0xe << 24)
 197
 198#define FLEXCAN_MB_CNT_EDL		BIT(31)
 199#define FLEXCAN_MB_CNT_BRS		BIT(30)
 200#define FLEXCAN_MB_CNT_ESI		BIT(29)
 201#define FLEXCAN_MB_CNT_SRR		BIT(22)
 202#define FLEXCAN_MB_CNT_IDE		BIT(21)
 203#define FLEXCAN_MB_CNT_RTR		BIT(20)
 204#define FLEXCAN_MB_CNT_LENGTH(x)	(((x) & 0xf) << 16)
 205#define FLEXCAN_MB_CNT_TIMESTAMP(x)	((x) & 0xffff)
 206
 207#define FLEXCAN_TIMEOUT_US		(250)
 208
 209/* Structure of the message buffer */
 210struct flexcan_mb {
 211	u32 can_ctrl;
 212	u32 can_id;
 213	u32 data[];
 214};
 215
 216/* Structure of the hardware registers */
 217struct flexcan_regs {
 218	u32 mcr;		/* 0x00 */
 219	u32 ctrl;		/* 0x04 - Not affected by Soft Reset */
 220	u32 timer;		/* 0x08 */
 221	u32 tcr;		/* 0x0c */
 222	u32 rxgmask;		/* 0x10 - Not affected by Soft Reset */
 223	u32 rx14mask;		/* 0x14 - Not affected by Soft Reset */
 224	u32 rx15mask;		/* 0x18 - Not affected by Soft Reset */
 225	u32 ecr;		/* 0x1c */
 226	u32 esr;		/* 0x20 */
 227	u32 imask2;		/* 0x24 */
 228	u32 imask1;		/* 0x28 */
 229	u32 iflag2;		/* 0x2c */
 230	u32 iflag1;		/* 0x30 */
 231	union {			/* 0x34 */
 232		u32 gfwr_mx28;	/* MX28, MX53 */
 233		u32 ctrl2;	/* MX6, VF610 - Not affected by Soft Reset */
 234	};
 235	u32 esr2;		/* 0x38 */
 236	u32 imeur;		/* 0x3c */
 237	u32 lrfr;		/* 0x40 */
 238	u32 crcr;		/* 0x44 */
 239	u32 rxfgmask;		/* 0x48 */
 240	u32 rxfir;		/* 0x4c - Not affected by Soft Reset */
 241	u32 cbt;		/* 0x50 - Not affected by Soft Reset */
 242	u32 _reserved2;		/* 0x54 */
 243	u32 dbg1;		/* 0x58 */
 244	u32 dbg2;		/* 0x5c */
 245	u32 _reserved3[8];	/* 0x60 */
 246	struct_group(init,
 247		u8 mb[2][512];		/* 0x80 - Not affected by Soft Reset */
 248		/* FIFO-mode:
 249		 *			MB
 250		 * 0x080...0x08f	0	RX message buffer
 251		 * 0x090...0x0df	1-5	reserved
 252		 * 0x0e0...0x0ff	6-7	8 entry ID table
 253		 *				(mx25, mx28, mx35, mx53)
 254		 * 0x0e0...0x2df	6-7..37	8..128 entry ID table
 255		 *				size conf'ed via ctrl2::RFFN
 256		 *				(mx6, vf610)
 257		 */
 258		u32 _reserved4[256];	/* 0x480 */
 259		u32 rximr[64];		/* 0x880 - Not affected by Soft Reset */
 260		u32 _reserved5[24];	/* 0x980 */
 261		u32 gfwr_mx6;		/* 0x9e0 - MX6 */
 262		u32 _reserved6[39];	/* 0x9e4 */
 263		u32 _rxfir[6];		/* 0xa80 */
 264		u32 _reserved8[2];	/* 0xa98 */
 265		u32 _rxmgmask;		/* 0xaa0 */
 266		u32 _rxfgmask;		/* 0xaa4 */
 267		u32 _rx14mask;		/* 0xaa8 */
 268		u32 _rx15mask;		/* 0xaac */
 269		u32 tx_smb[4];		/* 0xab0 */
 270		u32 rx_smb0[4];		/* 0xac0 */
 271		u32 rx_smb1[4];		/* 0xad0 */
 272	);
 273	u32 mecr;		/* 0xae0 */
 274	u32 erriar;		/* 0xae4 */
 275	u32 erridpr;		/* 0xae8 */
 276	u32 errippr;		/* 0xaec */
 277	u32 rerrar;		/* 0xaf0 */
 278	u32 rerrdr;		/* 0xaf4 */
 279	u32 rerrsynr;		/* 0xaf8 */
 280	u32 errsr;		/* 0xafc */
 281	u32 _reserved7[64];	/* 0xb00 */
 282	u32 fdctrl;		/* 0xc00 - Not affected by Soft Reset */
 283	u32 fdcbt;		/* 0xc04 - Not affected by Soft Reset */
 284	u32 fdcrc;		/* 0xc08 */
 285	u32 _reserved9[199];	/* 0xc0c */
 286	struct_group(init_fd,
 287		u32 tx_smb_fd[18];	/* 0xf28 */
 288		u32 rx_smb0_fd[18];	/* 0xf70 */
 289		u32 rx_smb1_fd[18];	/* 0xfb8 */
 290	);
 291};
 292
 293static_assert(sizeof(struct flexcan_regs) ==  0x4 * 18 + 0xfb8);
 294
 295static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
 296	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 297		FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |
 298		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 299		FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
 300};
 301
 302static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 303	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 304		FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 305		FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN |
 306		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 307		FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
 308};
 309
 310static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 311	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 312		FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 313		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 314		FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
 315};
 316
 317static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 318	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 319		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 320		FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
 321};
 322
 323static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 324	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 325		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 326		FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
 327		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 328		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 329};
 330
 331static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
 332	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 333		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 334		FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW |
 335		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 336		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 337};
 338
 339static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
 340	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 341		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 342		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
 343		FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
 344		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 345		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 346};
 347
 348static struct flexcan_devtype_data fsl_imx93_devtype_data = {
 349	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 350		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 351		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
 352		FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
 353		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 354		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 355};
 356
 357static const struct flexcan_devtype_data fsl_imx95_devtype_data = {
 358	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 359		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 360		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_FD |
 361		FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 362		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI,
 363};
 364
 365static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 366	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 367		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 368		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC |
 369		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 370		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 371};
 372
 373static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 374	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 375		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 376		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 377		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 378};
 379
 380static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
 381	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 382		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 383		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
 384		FLEXCAN_QUIRK_SUPPORT_ECC |
 385		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 386		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 387};
 388
 389static const struct can_bittiming_const flexcan_bittiming_const = {
 390	.name = DRV_NAME,
 391	.tseg1_min = 4,
 392	.tseg1_max = 16,
 393	.tseg2_min = 2,
 394	.tseg2_max = 8,
 395	.sjw_max = 4,
 396	.brp_min = 1,
 397	.brp_max = 256,
 398	.brp_inc = 1,
 399};
 400
 401static const struct can_bittiming_const flexcan_fd_bittiming_const = {
 402	.name = DRV_NAME,
 403	.tseg1_min = 2,
 404	.tseg1_max = 96,
 405	.tseg2_min = 2,
 406	.tseg2_max = 32,
 407	.sjw_max = 16,
 408	.brp_min = 1,
 409	.brp_max = 1024,
 410	.brp_inc = 1,
 411};
 412
 413static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
 414	.name = DRV_NAME,
 415	.tseg1_min = 2,
 416	.tseg1_max = 39,
 417	.tseg2_min = 2,
 418	.tseg2_max = 8,
 419	.sjw_max = 4,
 420	.brp_min = 1,
 421	.brp_max = 1024,
 422	.brp_inc = 1,
 423};
 424
 425/* FlexCAN module is essentially modelled as a little-endian IP in most
 426 * SoCs, i.e the registers as well as the message buffer areas are
 427 * implemented in a little-endian fashion.
 428 *
 429 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 430 * module in a big-endian fashion (i.e the registers as well as the
 431 * message buffer areas are implemented in a big-endian way).
 432 *
 433 * In addition, the FlexCAN module can be found on SoCs having ARM or
 434 * PPC cores. So, we need to abstract off the register read/write
 435 * functions, ensuring that these cater to all the combinations of module
 436 * endianness and underlying CPU endianness.
 437 */
 438static inline u32 flexcan_read_be(void __iomem *addr)
 439{
 440	return ioread32be(addr);
 441}
 442
 443static inline void flexcan_write_be(u32 val, void __iomem *addr)
 444{
 445	iowrite32be(val, addr);
 446}
 447
 448static inline u32 flexcan_read_le(void __iomem *addr)
 449{
 450	return ioread32(addr);
 451}
 452
 453static inline void flexcan_write_le(u32 val, void __iomem *addr)
 454{
 455	iowrite32(val, addr);
 456}
 457
 458static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 459						 u8 mb_index)
 460{
 461	u8 bank_size;
 462	bool bank;
 463
 464	if (WARN_ON(mb_index >= priv->mb_count))
 465		return NULL;
 466
 467	bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 468
 469	bank = mb_index >= bank_size;
 470	if (bank)
 471		mb_index -= bank_size;
 472
 473	return (struct flexcan_mb __iomem *)
 474		(&priv->regs->mb[bank][priv->mb_size * mb_index]);
 475}
 476
 477static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
 478{
 479	struct flexcan_regs __iomem *regs = priv->regs;
 480	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 481
 482	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 483		udelay(10);
 484
 485	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 486		return -ETIMEDOUT;
 487
 488	return 0;
 489}
 490
 491static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
 492{
 493	struct flexcan_regs __iomem *regs = priv->regs;
 494	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 495
 496	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 497		udelay(10);
 498
 499	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 500		return -ETIMEDOUT;
 501
 502	return 0;
 503}
 504
 505static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 506{
 507	struct flexcan_regs __iomem *regs = priv->regs;
 508	u32 reg_mcr;
 509
 510	reg_mcr = priv->read(&regs->mcr);
 511
 512	if (enable)
 513		reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 514	else
 515		reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 516
 517	priv->write(reg_mcr, &regs->mcr);
 518}
 519
 520static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
 521{
 522	u8 idx = priv->scu_idx;
 523	u32 rsrc_id, val;
 524
 525	rsrc_id = IMX_SC_R_CAN(idx);
 526
 527	if (enabled)
 528		val = 1;
 529	else
 530		val = 0;
 531
 532	/* stop mode request via scu firmware */
 533	return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
 534				       IMX_SC_C_IPG_STOP, val);
 535}
 536
 537static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 538{
 539	struct flexcan_regs __iomem *regs = priv->regs;
 540	u32 reg_mcr;
 541	int ret;
 542
 543	reg_mcr = priv->read(&regs->mcr);
 544	reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 545	priv->write(reg_mcr, &regs->mcr);
 546
 547	/* enable stop request */
 548	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
 549		ret = flexcan_stop_mode_enable_scfw(priv, true);
 550		if (ret < 0)
 551			return ret;
 552	} else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) {
 553		regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 554				   1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 555	} else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI) {
 556		/* For the SCMI mode, driver do nothing, ATF will send request to
 557		 * SM(system manager, M33 core) through SCMI protocol after linux
 558		 * suspend. Once SM get this request, it will send IPG_STOP signal
 559		 * to Flex_CAN, let CAN in STOP mode.
 560		 */
 561		return 0;
 562	}
 563
 564	return flexcan_low_power_enter_ack(priv);
 565}
 566
 567static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 568{
 569	struct flexcan_regs __iomem *regs = priv->regs;
 570	u32 reg_mcr;
 571	int ret;
 572
 573	/* Remove stop request, for FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI,
 574	 * do nothing here, because ATF already send request to SM before
 575	 * linux resume. Once SM get this request, it will deassert the
 576	 * IPG_STOP signal to Flex_CAN.
 577	 */
 578	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
 579		ret = flexcan_stop_mode_enable_scfw(priv, false);
 580		if (ret < 0)
 581			return ret;
 582	} else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) {
 583		regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 584				   1 << priv->stm.req_bit, 0);
 585	}
 586
 587	reg_mcr = priv->read(&regs->mcr);
 588	reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 589	priv->write(reg_mcr, &regs->mcr);
 590
 
 
 
 
 
 
 591	return flexcan_low_power_exit_ack(priv);
 592}
 593
 594static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 595{
 596	struct flexcan_regs __iomem *regs = priv->regs;
 597	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 598
 599	priv->write(reg_ctrl, &regs->ctrl);
 600}
 601
 602static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 603{
 604	struct flexcan_regs __iomem *regs = priv->regs;
 605	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 606
 607	priv->write(reg_ctrl, &regs->ctrl);
 608}
 609
 610static int flexcan_clks_enable(const struct flexcan_priv *priv)
 611{
 612	int err = 0;
 613
 614	if (priv->clk_ipg) {
 615		err = clk_prepare_enable(priv->clk_ipg);
 616		if (err)
 617			return err;
 618	}
 619
 620	if (priv->clk_per) {
 621		err = clk_prepare_enable(priv->clk_per);
 622		if (err)
 623			clk_disable_unprepare(priv->clk_ipg);
 624	}
 625
 626	return err;
 627}
 628
 629static void flexcan_clks_disable(const struct flexcan_priv *priv)
 630{
 631	clk_disable_unprepare(priv->clk_per);
 632	clk_disable_unprepare(priv->clk_ipg);
 633}
 634
 635static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 636{
 637	if (!priv->reg_xceiver)
 638		return 0;
 639
 640	return regulator_enable(priv->reg_xceiver);
 641}
 642
 643static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 644{
 645	if (!priv->reg_xceiver)
 646		return 0;
 647
 648	return regulator_disable(priv->reg_xceiver);
 649}
 650
 651static int flexcan_chip_enable(struct flexcan_priv *priv)
 652{
 653	struct flexcan_regs __iomem *regs = priv->regs;
 654	u32 reg;
 655
 656	reg = priv->read(&regs->mcr);
 657	reg &= ~FLEXCAN_MCR_MDIS;
 658	priv->write(reg, &regs->mcr);
 659
 660	return flexcan_low_power_exit_ack(priv);
 661}
 662
 663static int flexcan_chip_disable(struct flexcan_priv *priv)
 664{
 665	struct flexcan_regs __iomem *regs = priv->regs;
 666	u32 reg;
 667
 668	reg = priv->read(&regs->mcr);
 669	reg |= FLEXCAN_MCR_MDIS;
 670	priv->write(reg, &regs->mcr);
 671
 672	return flexcan_low_power_enter_ack(priv);
 673}
 674
 675static int flexcan_chip_freeze(struct flexcan_priv *priv)
 676{
 677	struct flexcan_regs __iomem *regs = priv->regs;
 678	unsigned int timeout;
 679	u32 bitrate = priv->can.bittiming.bitrate;
 680	u32 reg;
 681
 682	if (bitrate)
 683		timeout = 1000 * 1000 * 10 / bitrate;
 684	else
 685		timeout = FLEXCAN_TIMEOUT_US / 10;
 686
 687	reg = priv->read(&regs->mcr);
 688	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
 689	priv->write(reg, &regs->mcr);
 690
 691	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 692		udelay(100);
 693
 694	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 695		return -ETIMEDOUT;
 696
 697	return 0;
 698}
 699
 700static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 701{
 702	struct flexcan_regs __iomem *regs = priv->regs;
 703	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 704	u32 reg;
 705
 706	reg = priv->read(&regs->mcr);
 707	reg &= ~FLEXCAN_MCR_HALT;
 708	priv->write(reg, &regs->mcr);
 709
 710	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 711		udelay(10);
 712
 713	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 714		return -ETIMEDOUT;
 715
 716	return 0;
 717}
 718
 719static int flexcan_chip_softreset(struct flexcan_priv *priv)
 720{
 721	struct flexcan_regs __iomem *regs = priv->regs;
 722	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 723
 724	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 725	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 726		udelay(10);
 727
 728	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 729		return -ETIMEDOUT;
 730
 731	return 0;
 732}
 733
 734static int __flexcan_get_berr_counter(const struct net_device *dev,
 735				      struct can_berr_counter *bec)
 736{
 737	const struct flexcan_priv *priv = netdev_priv(dev);
 738	struct flexcan_regs __iomem *regs = priv->regs;
 739	u32 reg = priv->read(&regs->ecr);
 740
 741	bec->txerr = (reg >> 0) & 0xff;
 742	bec->rxerr = (reg >> 8) & 0xff;
 743
 744	return 0;
 745}
 746
 747static int flexcan_get_berr_counter(const struct net_device *dev,
 748				    struct can_berr_counter *bec)
 749{
 750	const struct flexcan_priv *priv = netdev_priv(dev);
 751	int err;
 752
 753	err = pm_runtime_resume_and_get(priv->dev);
 754	if (err < 0)
 755		return err;
 756
 757	err = __flexcan_get_berr_counter(dev, bec);
 758
 759	pm_runtime_put(priv->dev);
 760
 761	return err;
 762}
 763
 764static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 765{
 766	const struct flexcan_priv *priv = netdev_priv(dev);
 767	struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
 768	u32 can_id;
 769	u32 data;
 770	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
 771	int i;
 772
 773	if (can_dev_dropped_skb(dev, skb))
 774		return NETDEV_TX_OK;
 775
 776	netif_stop_queue(dev);
 777
 778	if (cfd->can_id & CAN_EFF_FLAG) {
 779		can_id = cfd->can_id & CAN_EFF_MASK;
 780		ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 781	} else {
 782		can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
 783	}
 784
 785	if (cfd->can_id & CAN_RTR_FLAG)
 786		ctrl |= FLEXCAN_MB_CNT_RTR;
 787
 788	if (can_is_canfd_skb(skb)) {
 789		ctrl |= FLEXCAN_MB_CNT_EDL;
 790
 791		if (cfd->flags & CANFD_BRS)
 792			ctrl |= FLEXCAN_MB_CNT_BRS;
 793	}
 794
 795	for (i = 0; i < cfd->len; i += sizeof(u32)) {
 796		data = be32_to_cpup((__be32 *)&cfd->data[i]);
 797		priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 798	}
 799
 800	can_put_echo_skb(skb, dev, 0, 0);
 801
 802	priv->write(can_id, &priv->tx_mb->can_id);
 803	priv->write(ctrl, &priv->tx_mb->can_ctrl);
 804
 805	/* Errata ERR005829 step8:
 806	 * Write twice INACTIVE(0x8) code to first MB.
 807	 */
 808	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 809		    &priv->tx_mb_reserved->can_ctrl);
 810	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 811		    &priv->tx_mb_reserved->can_ctrl);
 812
 813	return NETDEV_TX_OK;
 814}
 815
 816static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 817{
 818	struct flexcan_priv *priv = netdev_priv(dev);
 819	struct flexcan_regs __iomem *regs = priv->regs;
 820	struct sk_buff *skb;
 821	struct can_frame *cf;
 822	bool rx_errors = false, tx_errors = false;
 823	u32 timestamp;
 824	int err;
 825
 826	timestamp = priv->read(&regs->timer) << 16;
 827
 828	skb = alloc_can_err_skb(dev, &cf);
 829	if (unlikely(!skb))
 830		return;
 831
 832	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 833
 834	if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 835		netdev_dbg(dev, "BIT1_ERR irq\n");
 836		cf->data[2] |= CAN_ERR_PROT_BIT1;
 837		tx_errors = true;
 838	}
 839	if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 840		netdev_dbg(dev, "BIT0_ERR irq\n");
 841		cf->data[2] |= CAN_ERR_PROT_BIT0;
 842		tx_errors = true;
 843	}
 844	if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 845		netdev_dbg(dev, "ACK_ERR irq\n");
 846		cf->can_id |= CAN_ERR_ACK;
 847		cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 848		tx_errors = true;
 849	}
 850	if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 851		netdev_dbg(dev, "CRC_ERR irq\n");
 852		cf->data[2] |= CAN_ERR_PROT_BIT;
 853		cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 854		rx_errors = true;
 855	}
 856	if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 857		netdev_dbg(dev, "FRM_ERR irq\n");
 858		cf->data[2] |= CAN_ERR_PROT_FORM;
 859		rx_errors = true;
 860	}
 861	if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 862		netdev_dbg(dev, "STF_ERR irq\n");
 863		cf->data[2] |= CAN_ERR_PROT_STUFF;
 864		rx_errors = true;
 865	}
 866
 867	priv->can.can_stats.bus_error++;
 868	if (rx_errors)
 869		dev->stats.rx_errors++;
 870	if (tx_errors)
 871		dev->stats.tx_errors++;
 872
 873	err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
 874	if (err)
 875		dev->stats.rx_fifo_errors++;
 876}
 877
 878static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 879{
 880	struct flexcan_priv *priv = netdev_priv(dev);
 881	struct flexcan_regs __iomem *regs = priv->regs;
 882	struct sk_buff *skb;
 883	struct can_frame *cf;
 884	enum can_state new_state, rx_state, tx_state;
 885	int flt;
 886	struct can_berr_counter bec;
 887	u32 timestamp;
 888	int err;
 889
 890	flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 891	if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 892		tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 893			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 894		rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 895			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 896		new_state = max(tx_state, rx_state);
 897	} else {
 898		__flexcan_get_berr_counter(dev, &bec);
 899		new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 900			CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 901		rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 902		tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 903	}
 904
 905	/* state hasn't changed */
 906	if (likely(new_state == priv->can.state))
 907		return;
 908
 909	timestamp = priv->read(&regs->timer) << 16;
 910
 911	skb = alloc_can_err_skb(dev, &cf);
 912	if (unlikely(!skb))
 913		return;
 914
 915	can_change_state(dev, cf, tx_state, rx_state);
 916
 917	if (unlikely(new_state == CAN_STATE_BUS_OFF))
 918		can_bus_off(dev);
 919
 920	err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
 921	if (err)
 922		dev->stats.rx_fifo_errors++;
 923}
 924
 925static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
 926{
 927	u64 reg = 0;
 928
 929	if (upper_32_bits(mask))
 930		reg = (u64)priv->read(addr - 4) << 32;
 931	if (lower_32_bits(mask))
 932		reg |= priv->read(addr);
 933
 934	return reg & mask;
 935}
 936
 937static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
 938{
 939	if (upper_32_bits(val))
 940		priv->write(upper_32_bits(val), addr - 4);
 941	if (lower_32_bits(val))
 942		priv->write(lower_32_bits(val), addr);
 943}
 944
 945static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 946{
 947	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
 948}
 949
 950static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
 951{
 952	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
 953}
 954
 955static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 956{
 957	return container_of(offload, struct flexcan_priv, offload);
 958}
 959
 960static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
 961					    unsigned int n, u32 *timestamp,
 962					    bool drop)
 963{
 964	struct flexcan_priv *priv = rx_offload_to_priv(offload);
 965	struct flexcan_regs __iomem *regs = priv->regs;
 966	struct flexcan_mb __iomem *mb;
 967	struct sk_buff *skb;
 968	struct canfd_frame *cfd;
 969	u32 reg_ctrl, reg_id, reg_iflag1;
 970	int i;
 971
 972	mb = flexcan_get_mb(priv, n);
 973
 974	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
 975		u32 code;
 976
 977		do {
 978			reg_ctrl = priv->read(&mb->can_ctrl);
 979		} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 980
 981		/* is this MB empty? */
 982		code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 983		if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 984		    (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 985			return NULL;
 986
 987		if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 988			/* This MB was overrun, we lost data */
 989			offload->dev->stats.rx_over_errors++;
 990			offload->dev->stats.rx_errors++;
 991		}
 992	} else {
 993		reg_iflag1 = priv->read(&regs->iflag1);
 994		if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 995			return NULL;
 996
 997		reg_ctrl = priv->read(&mb->can_ctrl);
 998	}
 999
1000	if (unlikely(drop)) {
1001		skb = ERR_PTR(-ENOBUFS);
1002		goto mark_as_read;
1003	}
1004
1005	if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
1006		skb = alloc_canfd_skb(offload->dev, &cfd);
1007	else
1008		skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
1009	if (unlikely(!skb)) {
1010		skb = ERR_PTR(-ENOMEM);
1011		goto mark_as_read;
1012	}
1013
1014	/* increase timstamp to full 32 bit */
1015	*timestamp = reg_ctrl << 16;
1016
1017	reg_id = priv->read(&mb->can_id);
1018	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1019		cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1020	else
1021		cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1022
1023	if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1024		cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1025
1026		if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1027			cfd->flags |= CANFD_BRS;
1028	} else {
1029		cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1030
1031		if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1032			cfd->can_id |= CAN_RTR_FLAG;
1033	}
1034
1035	if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1036		cfd->flags |= CANFD_ESI;
1037
1038	for (i = 0; i < cfd->len; i += sizeof(u32)) {
1039		__be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1040		*(__be32 *)(cfd->data + i) = data;
1041	}
1042
1043 mark_as_read:
1044	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1045		flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
1046	else
1047		priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
1048
1049	/* Read the Free Running Timer. It is optional but recommended
1050	 * to unlock Mailbox as soon as possible and make it available
1051	 * for reception.
1052	 */
1053	priv->read(&regs->timer);
1054
1055	return skb;
1056}
1057
1058static irqreturn_t flexcan_irq(int irq, void *dev_id)
1059{
1060	struct net_device *dev = dev_id;
1061	struct net_device_stats *stats = &dev->stats;
1062	struct flexcan_priv *priv = netdev_priv(dev);
1063	struct flexcan_regs __iomem *regs = priv->regs;
1064	irqreturn_t handled = IRQ_NONE;
1065	u64 reg_iflag_tx;
1066	u32 reg_esr;
1067	enum can_state last_state = priv->can.state;
1068
1069	/* reception interrupt */
1070	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1071		u64 reg_iflag_rx;
1072		int ret;
1073
1074		while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1075			handled = IRQ_HANDLED;
1076			ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1077								   reg_iflag_rx);
1078			if (!ret)
1079				break;
1080		}
1081	} else {
1082		u32 reg_iflag1;
1083
1084		reg_iflag1 = priv->read(&regs->iflag1);
1085		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1086			handled = IRQ_HANDLED;
1087			can_rx_offload_irq_offload_fifo(&priv->offload);
1088		}
1089
1090		/* FIFO overflow interrupt */
1091		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1092			handled = IRQ_HANDLED;
1093			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1094				    &regs->iflag1);
1095			dev->stats.rx_over_errors++;
1096			dev->stats.rx_errors++;
1097		}
1098	}
1099
1100	reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1101
1102	/* transmission complete interrupt */
1103	if (reg_iflag_tx & priv->tx_mask) {
1104		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1105
1106		handled = IRQ_HANDLED;
1107		stats->tx_bytes +=
1108			can_rx_offload_get_echo_skb_queue_timestamp(&priv->offload, 0,
1109								    reg_ctrl << 16, NULL);
1110		stats->tx_packets++;
1111
1112		/* after sending a RTR frame MB is in RX mode */
1113		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1114			    &priv->tx_mb->can_ctrl);
1115		flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
1116		netif_wake_queue(dev);
1117	}
1118
1119	reg_esr = priv->read(&regs->esr);
1120
1121	/* ACK all bus error, state change and wake IRQ sources */
1122	if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1123		handled = IRQ_HANDLED;
1124		priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), &regs->esr);
1125	}
1126
1127	/* state change interrupt or broken error state quirk fix is enabled */
1128	if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1129	    (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1130					   FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1131		flexcan_irq_state(dev, reg_esr);
1132
1133	/* bus error IRQ - handle if bus error reporting is activated */
1134	if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1135	    (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1136		flexcan_irq_bus_err(dev, reg_esr);
1137
1138	/* availability of error interrupt among state transitions in case
1139	 * bus error reporting is de-activated and
1140	 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1141	 *  +--------------------------------------------------------------+
1142	 *  | +----------------------------------------------+ [stopped /  |
1143	 *  | |                                              |  sleeping] -+
1144	 *  +-+-> active <-> warning <-> passive -> bus off -+
1145	 *        ___________^^^^^^^^^^^^_______________________________
1146	 *        disabled(1)  enabled             disabled
1147	 *
1148	 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1149	 */
1150	if ((last_state != priv->can.state) &&
1151	    (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1152	    !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1153		switch (priv->can.state) {
1154		case CAN_STATE_ERROR_ACTIVE:
1155			if (priv->devtype_data.quirks &
1156			    FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1157				flexcan_error_irq_enable(priv);
1158			else
1159				flexcan_error_irq_disable(priv);
1160			break;
1161
1162		case CAN_STATE_ERROR_WARNING:
1163			flexcan_error_irq_enable(priv);
1164			break;
1165
1166		case CAN_STATE_ERROR_PASSIVE:
1167		case CAN_STATE_BUS_OFF:
1168			flexcan_error_irq_disable(priv);
1169			break;
1170
1171		default:
1172			break;
1173		}
1174	}
1175
1176	if (handled)
1177		can_rx_offload_irq_finish(&priv->offload);
1178
1179	return handled;
1180}
1181
1182static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1183{
1184	const struct flexcan_priv *priv = netdev_priv(dev);
1185	const struct can_bittiming *bt = &priv->can.bittiming;
1186	struct flexcan_regs __iomem *regs = priv->regs;
1187	u32 reg;
1188
1189	reg = priv->read(&regs->ctrl);
1190	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1191		 FLEXCAN_CTRL_RJW(0x3) |
1192		 FLEXCAN_CTRL_PSEG1(0x7) |
1193		 FLEXCAN_CTRL_PSEG2(0x7) |
1194		 FLEXCAN_CTRL_PROPSEG(0x7));
1195
1196	reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1197		FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1198		FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1199		FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1200		FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1201
1202	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1203	priv->write(reg, &regs->ctrl);
1204
1205	/* print chip status */
1206	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1207		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1208}
1209
1210static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1211{
1212	struct flexcan_priv *priv = netdev_priv(dev);
1213	struct can_bittiming *bt = &priv->can.bittiming;
1214	struct can_bittiming *dbt = &priv->can.data_bittiming;
1215	struct flexcan_regs __iomem *regs = priv->regs;
1216	u32 reg_cbt, reg_fdctrl;
1217
1218	/* CBT */
1219	/* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1220	 * long. The can_calc_bittiming() tries to divide the tseg1
1221	 * equally between phase_seg1 and prop_seg, which may not fit
1222	 * in CBT register. Therefore, if phase_seg1 is more than
1223	 * possible value, increase prop_seg and decrease phase_seg1.
1224	 */
1225	if (bt->phase_seg1 > 0x20) {
1226		bt->prop_seg += (bt->phase_seg1 - 0x20);
1227		bt->phase_seg1 = 0x20;
1228	}
1229
1230	reg_cbt = FLEXCAN_CBT_BTF |
1231		FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1232		FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1233		FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1234		FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1235		FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1236
1237	netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1238	priv->write(reg_cbt, &regs->cbt);
1239
1240	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1241		u32 reg_fdcbt, reg_ctrl2;
1242
1243		if (bt->brp != dbt->brp)
1244			netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1245				    dbt->brp, bt->brp);
1246
1247		/* FDCBT */
1248		/* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1249		 * 5 bit long. The can_calc_bittiming tries to divide
1250		 * the tseg1 equally between phase_seg1 and prop_seg,
1251		 * which may not fit in FDCBT register. Therefore, if
1252		 * phase_seg1 is more than possible value, increase
1253		 * prop_seg and decrease phase_seg1
1254		 */
1255		if (dbt->phase_seg1 > 0x8) {
1256			dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1257			dbt->phase_seg1 = 0x8;
1258		}
1259
1260		reg_fdcbt = priv->read(&regs->fdcbt);
1261		reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1262			       FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1263			       FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1264			       FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1265			       FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1266
1267		reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1268			FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1269			FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1270			FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1271			FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1272
1273		netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1274		priv->write(reg_fdcbt, &regs->fdcbt);
1275
1276		/* CTRL2 */
1277		reg_ctrl2 = priv->read(&regs->ctrl2);
1278		reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1279		if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1280			reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1281
1282		netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1283		priv->write(reg_ctrl2, &regs->ctrl2);
1284	}
1285
1286	/* FDCTRL */
1287	reg_fdctrl = priv->read(&regs->fdctrl);
1288	reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1289			FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1290
1291	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1292		reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1293
1294		if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1295			/* TDC must be disabled for Loop Back mode */
1296			reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1297		} else {
1298			reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1299				FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1300					   ((dbt->phase_seg1 - 1) +
1301					    dbt->prop_seg + 2) *
1302					   ((dbt->brp - 1 ) + 1));
1303		}
1304	}
1305
1306	netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1307	priv->write(reg_fdctrl, &regs->fdctrl);
1308
1309	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1310		   __func__,
1311		   priv->read(&regs->mcr), priv->read(&regs->ctrl),
1312		   priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),
1313		   priv->read(&regs->cbt), priv->read(&regs->fdcbt));
1314}
1315
1316static void flexcan_set_bittiming(struct net_device *dev)
1317{
1318	const struct flexcan_priv *priv = netdev_priv(dev);
1319	struct flexcan_regs __iomem *regs = priv->regs;
1320	u32 reg;
1321
1322	reg = priv->read(&regs->ctrl);
1323	reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1324		 FLEXCAN_CTRL_LOM);
1325
1326	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1327		reg |= FLEXCAN_CTRL_LPB;
1328	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1329		reg |= FLEXCAN_CTRL_LOM;
1330	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1331		reg |= FLEXCAN_CTRL_SMP;
1332
1333	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1334	priv->write(reg, &regs->ctrl);
1335
1336	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1337		return flexcan_set_bittiming_cbt(dev);
1338	else
1339		return flexcan_set_bittiming_ctrl(dev);
1340}
1341
1342static void flexcan_ram_init(struct net_device *dev)
1343{
1344	struct flexcan_priv *priv = netdev_priv(dev);
1345	struct flexcan_regs __iomem *regs = priv->regs;
1346	u32 reg_ctrl2;
1347
1348	/* 11.8.3.13 Detection and correction of memory errors:
1349	 * CTRL2[WRMFRZ] grants write access to all memory positions
1350	 * that require initialization, ranging from 0x080 to 0xADF
1351	 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1352	 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1353	 * need to be initialized as well. MCR[RFEN] must not be set
1354	 * during memory initialization.
1355	 */
1356	reg_ctrl2 = priv->read(&regs->ctrl2);
1357	reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1358	priv->write(reg_ctrl2, &regs->ctrl2);
1359
1360	memset_io(&regs->init, 0, sizeof(regs->init));
1361
1362	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1363		memset_io(&regs->init_fd, 0, sizeof(regs->init_fd));
1364
1365	reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1366	priv->write(reg_ctrl2, &regs->ctrl2);
1367}
1368
1369static int flexcan_rx_offload_setup(struct net_device *dev)
1370{
1371	struct flexcan_priv *priv = netdev_priv(dev);
1372	int err;
1373
1374	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1375		priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1376	else
1377		priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1378
1379	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16)
1380		priv->mb_count = 16;
1381	else
1382		priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1383				 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1384
1385	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1386		priv->tx_mb_reserved =
1387			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX);
1388	else
1389		priv->tx_mb_reserved =
1390			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO);
1391	priv->tx_mb_idx = priv->mb_count - 1;
1392	priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1393	priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1394
1395	priv->offload.mailbox_read = flexcan_mailbox_read;
1396
1397	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1398		priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST;
1399		priv->offload.mb_last = priv->mb_count - 2;
1400
1401		priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1402					    priv->offload.mb_first);
1403		err = can_rx_offload_add_timestamp(dev, &priv->offload);
1404	} else {
1405		priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1406			FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1407		err = can_rx_offload_add_fifo(dev, &priv->offload,
1408					      FLEXCAN_NAPI_WEIGHT);
1409	}
1410
1411	return err;
1412}
1413
1414static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1415{
1416	const struct flexcan_priv *priv = netdev_priv(dev);
1417	struct flexcan_regs __iomem *regs = priv->regs;
1418	u64 reg_imask;
1419
1420	disable_irq(dev->irq);
1421	priv->write(priv->reg_ctrl_default, &regs->ctrl);
1422	reg_imask = priv->rx_mask | priv->tx_mask;
1423	priv->write(upper_32_bits(reg_imask), &regs->imask2);
1424	priv->write(lower_32_bits(reg_imask), &regs->imask1);
1425	enable_irq(dev->irq);
1426}
1427
1428static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1429{
1430	const struct flexcan_priv *priv = netdev_priv(dev);
1431	struct flexcan_regs __iomem *regs = priv->regs;
1432
1433	priv->write(0, &regs->imask2);
1434	priv->write(0, &regs->imask1);
1435	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1436		    &regs->ctrl);
1437}
1438
1439/* flexcan_chip_start
1440 *
1441 * this functions is entered with clocks enabled
1442 *
1443 */
1444static int flexcan_chip_start(struct net_device *dev)
1445{
1446	struct flexcan_priv *priv = netdev_priv(dev);
1447	struct flexcan_regs __iomem *regs = priv->regs;
1448	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1449	int err, i;
1450	struct flexcan_mb __iomem *mb;
1451
1452	/* enable module */
1453	err = flexcan_chip_enable(priv);
1454	if (err)
1455		return err;
1456
1457	/* soft reset */
1458	err = flexcan_chip_softreset(priv);
1459	if (err)
1460		goto out_chip_disable;
1461
1462	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1463		flexcan_ram_init(dev);
1464
1465	flexcan_set_bittiming(dev);
1466
1467	/* set freeze, halt */
1468	err = flexcan_chip_freeze(priv);
1469	if (err)
1470		goto out_chip_disable;
1471
1472	/* MCR
1473	 *
1474	 * only supervisor access
1475	 * enable warning int
1476	 * enable individual RX masking
1477	 * choose format C
1478	 * set max mailbox number
1479	 */
1480	reg_mcr = priv->read(&regs->mcr);
1481	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1482	reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1483		FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1484
1485	/* MCR
1486	 *
1487	 * FIFO:
1488	 * - disable for mailbox mode
1489	 * - enable for FIFO mode
1490	 */
1491	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1492		reg_mcr &= ~FLEXCAN_MCR_FEN;
1493	else
1494		reg_mcr |= FLEXCAN_MCR_FEN;
1495
1496	/* MCR
1497	 *
1498	 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1499	 *       asserted because this will impede the self reception
1500	 *       of a transmitted message. This is not documented in
1501	 *       earlier versions of flexcan block guide.
1502	 *
1503	 * Self Reception:
1504	 * - enable Self Reception for loopback mode
1505	 *   (by clearing "Self Reception Disable" bit)
1506	 * - disable for normal operation
1507	 */
1508	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1509		reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1510	else
1511		reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1512
1513	/* MCR - CAN-FD */
1514	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1515		reg_mcr |= FLEXCAN_MCR_FDEN;
1516	else
1517		reg_mcr &= ~FLEXCAN_MCR_FDEN;
1518
1519	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1520	priv->write(reg_mcr, &regs->mcr);
1521
1522	/* CTRL
1523	 *
1524	 * disable timer sync feature
1525	 *
1526	 * disable auto busoff recovery
1527	 * transmit lowest buffer first
1528	 *
1529	 * enable tx and rx warning interrupt
1530	 * enable bus off interrupt
1531	 * (== FLEXCAN_CTRL_ERR_STATE)
1532	 */
1533	reg_ctrl = priv->read(&regs->ctrl);
1534	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1535	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1536		FLEXCAN_CTRL_ERR_STATE;
1537
1538	/* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1539	 * on most Flexcan cores, too. Otherwise we don't get
1540	 * any error warning or passive interrupts.
1541	 */
1542	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1543	    priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1544		reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1545	else
1546		reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1547
1548	/* save for later use */
1549	priv->reg_ctrl_default = reg_ctrl;
1550	/* leave interrupts disabled for now */
1551	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1552	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1553	priv->write(reg_ctrl, &regs->ctrl);
1554
1555	if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1556		reg_ctrl2 = priv->read(&regs->ctrl2);
1557		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1558		priv->write(reg_ctrl2, &regs->ctrl2);
1559	}
1560
1561	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1562		u32 reg_fdctrl;
1563
1564		reg_fdctrl = priv->read(&regs->fdctrl);
1565		reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1566				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1567
1568		if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1569			reg_fdctrl |=
1570				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1571					   FLEXCAN_FDCTRL_MBDSR_64) |
1572				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1573					   FLEXCAN_FDCTRL_MBDSR_64);
1574		} else {
1575			reg_fdctrl |=
1576				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1577					   FLEXCAN_FDCTRL_MBDSR_8) |
1578				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1579					   FLEXCAN_FDCTRL_MBDSR_8);
1580		}
1581
1582		netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1583			   __func__, reg_fdctrl);
1584		priv->write(reg_fdctrl, &regs->fdctrl);
1585	}
1586
1587	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1588		for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1589			mb = flexcan_get_mb(priv, i);
1590			priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1591				    &mb->can_ctrl);
1592		}
1593	} else {
1594		/* clear and invalidate unused mailboxes first */
1595		for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) {
1596			mb = flexcan_get_mb(priv, i);
1597			priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1598				    &mb->can_ctrl);
1599		}
1600	}
1601
1602	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
1603	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1604		    &priv->tx_mb_reserved->can_ctrl);
1605
1606	/* mark TX mailbox as INACTIVE */
1607	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1608		    &priv->tx_mb->can_ctrl);
1609
1610	/* acceptance mask/acceptance code (accept everything) */
1611	priv->write(0x0, &regs->rxgmask);
1612	priv->write(0x0, &regs->rx14mask);
1613	priv->write(0x0, &regs->rx15mask);
1614
1615	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1616		priv->write(0x0, &regs->rxfgmask);
1617
1618	/* clear acceptance filters */
1619	for (i = 0; i < priv->mb_count; i++)
1620		priv->write(0, &regs->rximr[i]);
1621
1622	/* On Vybrid, disable non-correctable errors interrupt and
1623	 * freeze mode. It still can correct the correctable errors
1624	 * when HW supports ECC.
1625	 *
1626	 * This also works around errata e5295 which generates false
1627	 * positive memory errors and put the device in freeze mode.
1628	 */
1629	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1630		/* Follow the protocol as described in "Detection
1631		 * and Correction of Memory Errors" to write to
1632		 * MECR register (step 1 - 5)
1633		 *
1634		 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1635		 * 2. set CTRL2[ECRWRE]
1636		 */
1637		reg_ctrl2 = priv->read(&regs->ctrl2);
1638		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1639		priv->write(reg_ctrl2, &regs->ctrl2);
1640
1641		/* 3. clear MECR[ECRWRDIS] */
1642		reg_mecr = priv->read(&regs->mecr);
1643		reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1644		priv->write(reg_mecr, &regs->mecr);
1645
1646		/* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1647		reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1648			      FLEXCAN_MECR_FANCEI_MSK);
1649		priv->write(reg_mecr, &regs->mecr);
1650
1651		/* 5. after configuration done, lock MECR by either
1652		 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1653		 */
1654		reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1655		priv->write(reg_mecr, &regs->mecr);
1656
1657		reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1658		priv->write(reg_ctrl2, &regs->ctrl2);
1659	}
1660
1661	/* synchronize with the can bus */
1662	err = flexcan_chip_unfreeze(priv);
1663	if (err)
1664		goto out_chip_disable;
1665
1666	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1667
1668	/* print chip status */
1669	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1670		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1671
1672	return 0;
1673
1674 out_chip_disable:
1675	flexcan_chip_disable(priv);
1676	return err;
1677}
1678
1679/* __flexcan_chip_stop
1680 *
1681 * this function is entered with clocks enabled
1682 */
1683static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1684{
1685	struct flexcan_priv *priv = netdev_priv(dev);
1686	int err;
1687
1688	/* freeze + disable module */
1689	err = flexcan_chip_freeze(priv);
1690	if (err && !disable_on_error)
1691		return err;
1692	err = flexcan_chip_disable(priv);
1693	if (err && !disable_on_error)
1694		goto out_chip_unfreeze;
1695
1696	priv->can.state = CAN_STATE_STOPPED;
1697
1698	return 0;
1699
1700 out_chip_unfreeze:
1701	flexcan_chip_unfreeze(priv);
1702
1703	return err;
1704}
1705
1706static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1707{
1708	return __flexcan_chip_stop(dev, true);
1709}
1710
1711static inline int flexcan_chip_stop(struct net_device *dev)
1712{
1713	return __flexcan_chip_stop(dev, false);
1714}
1715
1716static int flexcan_open(struct net_device *dev)
1717{
1718	struct flexcan_priv *priv = netdev_priv(dev);
1719	int err;
1720
1721	if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1722	    (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1723		netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1724		return -EINVAL;
1725	}
1726
1727	err = pm_runtime_resume_and_get(priv->dev);
1728	if (err < 0)
1729		return err;
1730
1731	err = open_candev(dev);
1732	if (err)
1733		goto out_runtime_put;
1734
1735	err = flexcan_transceiver_enable(priv);
1736	if (err)
1737		goto out_close;
1738
1739	err = flexcan_rx_offload_setup(dev);
1740	if (err)
1741		goto out_transceiver_disable;
1742
1743	err = flexcan_chip_start(dev);
1744	if (err)
1745		goto out_can_rx_offload_del;
1746
1747	can_rx_offload_enable(&priv->offload);
1748
1749	err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1750	if (err)
1751		goto out_can_rx_offload_disable;
1752
1753	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1754		err = request_irq(priv->irq_boff,
1755				  flexcan_irq, IRQF_SHARED, dev->name, dev);
1756		if (err)
1757			goto out_free_irq;
1758
1759		err = request_irq(priv->irq_err,
1760				  flexcan_irq, IRQF_SHARED, dev->name, dev);
1761		if (err)
1762			goto out_free_irq_boff;
1763	}
1764
1765	flexcan_chip_interrupts_enable(dev);
1766
1767	netif_start_queue(dev);
1768
1769	return 0;
1770
1771 out_free_irq_boff:
1772	free_irq(priv->irq_boff, dev);
1773 out_free_irq:
1774	free_irq(dev->irq, dev);
1775 out_can_rx_offload_disable:
1776	can_rx_offload_disable(&priv->offload);
1777	flexcan_chip_stop(dev);
1778 out_can_rx_offload_del:
1779	can_rx_offload_del(&priv->offload);
1780 out_transceiver_disable:
1781	flexcan_transceiver_disable(priv);
1782 out_close:
1783	close_candev(dev);
1784 out_runtime_put:
1785	pm_runtime_put(priv->dev);
1786
1787	return err;
1788}
1789
1790static int flexcan_close(struct net_device *dev)
1791{
1792	struct flexcan_priv *priv = netdev_priv(dev);
1793
1794	netif_stop_queue(dev);
1795	flexcan_chip_interrupts_disable(dev);
1796
1797	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1798		free_irq(priv->irq_err, dev);
1799		free_irq(priv->irq_boff, dev);
1800	}
1801
1802	free_irq(dev->irq, dev);
1803	can_rx_offload_disable(&priv->offload);
1804	flexcan_chip_stop_disable_on_error(dev);
1805
1806	can_rx_offload_del(&priv->offload);
1807	flexcan_transceiver_disable(priv);
1808	close_candev(dev);
1809
1810	pm_runtime_put(priv->dev);
1811
1812	return 0;
1813}
1814
1815static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1816{
1817	int err;
1818
1819	switch (mode) {
1820	case CAN_MODE_START:
1821		err = flexcan_chip_start(dev);
1822		if (err)
1823			return err;
1824
1825		flexcan_chip_interrupts_enable(dev);
1826
1827		netif_wake_queue(dev);
1828		break;
1829
1830	default:
1831		return -EOPNOTSUPP;
1832	}
1833
1834	return 0;
1835}
1836
1837static const struct net_device_ops flexcan_netdev_ops = {
1838	.ndo_open	= flexcan_open,
1839	.ndo_stop	= flexcan_close,
1840	.ndo_start_xmit	= flexcan_start_xmit,
1841	.ndo_change_mtu = can_change_mtu,
1842};
1843
1844static int register_flexcandev(struct net_device *dev)
1845{
1846	struct flexcan_priv *priv = netdev_priv(dev);
1847	struct flexcan_regs __iomem *regs = priv->regs;
1848	u32 reg, err;
1849
1850	err = flexcan_clks_enable(priv);
1851	if (err)
1852		return err;
1853
1854	/* select "bus clock", chip must be disabled */
1855	err = flexcan_chip_disable(priv);
1856	if (err)
1857		goto out_clks_disable;
1858
1859	reg = priv->read(&regs->ctrl);
1860	if (priv->clk_src)
1861		reg |= FLEXCAN_CTRL_CLK_SRC;
1862	else
1863		reg &= ~FLEXCAN_CTRL_CLK_SRC;
1864	priv->write(reg, &regs->ctrl);
1865
1866	err = flexcan_chip_enable(priv);
1867	if (err)
1868		goto out_chip_disable;
1869
1870	/* set freeze, halt */
1871	err = flexcan_chip_freeze(priv);
1872	if (err)
1873		goto out_chip_disable;
1874
1875	/* activate FIFO, restrict register access */
1876	reg = priv->read(&regs->mcr);
1877	reg |=  FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1878	priv->write(reg, &regs->mcr);
1879
1880	/* Currently we only support newer versions of this core
1881	 * featuring a RX hardware FIFO (although this driver doesn't
1882	 * make use of it on some cores). Older cores, found on some
1883	 * Coldfire derivates are not tested.
1884	 */
1885	reg = priv->read(&regs->mcr);
1886	if (!(reg & FLEXCAN_MCR_FEN)) {
1887		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1888		err = -ENODEV;
1889		goto out_chip_disable;
1890	}
1891
1892	err = register_candev(dev);
1893	if (err)
1894		goto out_chip_disable;
1895
1896	/* Disable core and let pm_runtime_put() disable the clocks.
1897	 * If CONFIG_PM is not enabled, the clocks will stay powered.
1898	 */
1899	flexcan_chip_disable(priv);
1900	pm_runtime_put(priv->dev);
1901
1902	return 0;
1903
1904 out_chip_disable:
1905	flexcan_chip_disable(priv);
1906 out_clks_disable:
1907	flexcan_clks_disable(priv);
1908	return err;
1909}
1910
1911static void unregister_flexcandev(struct net_device *dev)
1912{
1913	unregister_candev(dev);
1914}
1915
1916static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1917{
1918	struct net_device *dev = platform_get_drvdata(pdev);
1919	struct device_node *np = pdev->dev.of_node;
1920	struct device_node *gpr_np;
1921	struct flexcan_priv *priv;
1922	phandle phandle;
1923	u32 out_val[3];
1924	int ret;
1925
1926	if (!np)
1927		return -EINVAL;
1928
1929	/* stop mode property format is:
1930	 * <&gpr req_gpr req_bit>.
1931	 */
1932	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1933					 ARRAY_SIZE(out_val));
1934	if (ret) {
1935		dev_dbg(&pdev->dev, "no stop-mode property\n");
1936		return ret;
1937	}
1938	phandle = *out_val;
1939
1940	gpr_np = of_find_node_by_phandle(phandle);
1941	if (!gpr_np) {
1942		dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1943		return -ENODEV;
1944	}
1945
1946	priv = netdev_priv(dev);
1947	priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1948	if (IS_ERR(priv->stm.gpr)) {
1949		dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1950		ret = PTR_ERR(priv->stm.gpr);
1951		goto out_put_node;
1952	}
1953
1954	priv->stm.req_gpr = out_val[1];
1955	priv->stm.req_bit = out_val[2];
1956
1957	dev_dbg(&pdev->dev,
1958		"gpr %s req_gpr=0x02%x req_bit=%u\n",
1959		gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1960
1961	return 0;
1962
1963out_put_node:
1964	of_node_put(gpr_np);
1965	return ret;
1966}
1967
1968static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1969{
1970	struct net_device *dev = platform_get_drvdata(pdev);
1971	struct flexcan_priv *priv;
1972	u8 scu_idx;
1973	int ret;
1974
1975	ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1976	if (ret < 0) {
1977		dev_dbg(&pdev->dev, "failed to get scu index\n");
1978		return ret;
1979	}
1980
1981	priv = netdev_priv(dev);
1982	priv->scu_idx = scu_idx;
1983
1984	/* this function could be deferred probe, return -EPROBE_DEFER */
1985	return imx_scu_get_handle(&priv->sc_ipc_handle);
1986}
1987
1988/* flexcan_setup_stop_mode - Setup stop mode for wakeup
1989 *
1990 * Return: = 0 setup stop mode successfully or doesn't support this feature
1991 *         < 0 fail to setup stop mode (could be deferred probe)
1992 */
1993static int flexcan_setup_stop_mode(struct platform_device *pdev)
1994{
1995	struct net_device *dev = platform_get_drvdata(pdev);
1996	struct flexcan_priv *priv;
1997	int ret;
1998
1999	priv = netdev_priv(dev);
2000
2001	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
2002		ret = flexcan_setup_stop_mode_scfw(pdev);
2003	else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
2004		ret = flexcan_setup_stop_mode_gpr(pdev);
2005	else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)
2006		/* ATF will handle all STOP_IPG related work */
2007		ret = 0;
2008	else
2009		/* return 0 directly if doesn't support stop mode feature */
2010		return 0;
2011
2012	/* If ret is -EINVAL, this means SoC claim to support stop mode, but
2013	 * dts file lack the stop mode property definition. For this case,
2014	 * directly return 0, this will skip the wakeup capable setting and
2015	 * will not block the driver probe.
2016	 */
2017	if (ret == -EINVAL)
2018		return 0;
2019	else if (ret)
2020		return ret;
2021
2022	device_set_wakeup_capable(&pdev->dev, true);
2023
2024	if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
2025		device_set_wakeup_enable(&pdev->dev, true);
2026
2027	return 0;
2028}
2029
2030static const struct of_device_id flexcan_of_match[] = {
2031	{ .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2032	{ .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2033	{ .compatible = "fsl,imx93-flexcan", .data = &fsl_imx93_devtype_data, },
2034	{ .compatible = "fsl,imx95-flexcan", .data = &fsl_imx95_devtype_data, },
2035	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2036	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2037	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2038	{ .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2039	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2040	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2041	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2042	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2043	{ .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2044	{ /* sentinel */ },
2045};
2046MODULE_DEVICE_TABLE(of, flexcan_of_match);
2047
2048static const struct platform_device_id flexcan_id_table[] = {
2049	{
2050		.name = "flexcan-mcf5441x",
2051		.driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data,
2052	}, {
2053		/* sentinel */
2054	},
2055};
2056MODULE_DEVICE_TABLE(platform, flexcan_id_table);
2057
2058static int flexcan_probe(struct platform_device *pdev)
2059{
 
2060	const struct flexcan_devtype_data *devtype_data;
2061	struct net_device *dev;
2062	struct flexcan_priv *priv;
2063	struct regulator *reg_xceiver;
2064	struct clk *clk_ipg = NULL, *clk_per = NULL;
2065	struct flexcan_regs __iomem *regs;
2066	struct flexcan_platform_data *pdata;
2067	int err, irq;
2068	u8 clk_src = 1;
2069	u32 clock_freq = 0;
2070
2071	reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2072	if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2073		return -EPROBE_DEFER;
2074	else if (PTR_ERR(reg_xceiver) == -ENODEV)
2075		reg_xceiver = NULL;
2076	else if (IS_ERR(reg_xceiver))
2077		return PTR_ERR(reg_xceiver);
2078
2079	if (pdev->dev.of_node) {
2080		of_property_read_u32(pdev->dev.of_node,
2081				     "clock-frequency", &clock_freq);
2082		of_property_read_u8(pdev->dev.of_node,
2083				    "fsl,clk-source", &clk_src);
2084	} else {
2085		pdata = dev_get_platdata(&pdev->dev);
2086		if (pdata) {
2087			clock_freq = pdata->clock_frequency;
2088			clk_src = pdata->clk_src;
2089		}
2090	}
2091
2092	if (!clock_freq) {
2093		clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2094		if (IS_ERR(clk_ipg)) {
2095			dev_err(&pdev->dev, "no ipg clock defined\n");
2096			return PTR_ERR(clk_ipg);
2097		}
2098
2099		clk_per = devm_clk_get(&pdev->dev, "per");
2100		if (IS_ERR(clk_per)) {
2101			dev_err(&pdev->dev, "no per clock defined\n");
2102			return PTR_ERR(clk_per);
2103		}
2104		clock_freq = clk_get_rate(clk_per);
2105	}
2106
2107	irq = platform_get_irq(pdev, 0);
2108	if (irq < 0)
2109		return irq;
2110
2111	regs = devm_platform_ioremap_resource(pdev, 0);
2112	if (IS_ERR(regs))
2113		return PTR_ERR(regs);
2114
2115	devtype_data = device_get_match_data(&pdev->dev);
 
 
 
 
 
 
 
2116
2117	if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2118	    !((devtype_data->quirks &
2119	       (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2120		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2121		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR |
2122		FLEXCAN_QUIRK_SUPPORT_RX_FIFO)) ==
2123	      (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2124	       FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2125	       FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR))) {
2126		dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n");
2127		return -EINVAL;
2128	}
2129
2130	if ((devtype_data->quirks &
2131	     (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2132	      FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)) ==
2133	    FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR) {
2134		dev_err(&pdev->dev,
2135			"Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n",
2136			devtype_data->quirks);
2137		return -EINVAL;
2138	}
2139
2140	dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2141	if (!dev)
2142		return -ENOMEM;
2143
2144	platform_set_drvdata(pdev, dev);
2145	SET_NETDEV_DEV(dev, &pdev->dev);
2146
2147	dev->netdev_ops = &flexcan_netdev_ops;
2148	dev->ethtool_ops = &flexcan_ethtool_ops;
2149	dev->irq = irq;
2150	dev->flags |= IFF_ECHO;
2151
2152	priv = netdev_priv(dev);
2153	priv->devtype_data = *devtype_data;
2154
2155	if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2156	    priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2157		priv->read = flexcan_read_be;
2158		priv->write = flexcan_write_be;
2159	} else {
2160		priv->read = flexcan_read_le;
2161		priv->write = flexcan_write_le;
2162	}
2163
2164	priv->dev = &pdev->dev;
2165	priv->can.clock.freq = clock_freq;
2166	priv->can.do_set_mode = flexcan_set_mode;
2167	priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2168	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2169		CAN_CTRLMODE_LISTENONLY	| CAN_CTRLMODE_3_SAMPLES |
2170		CAN_CTRLMODE_BERR_REPORTING;
2171	priv->regs = regs;
2172	priv->clk_ipg = clk_ipg;
2173	priv->clk_per = clk_per;
2174	priv->clk_src = clk_src;
2175	priv->reg_xceiver = reg_xceiver;
2176
2177	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
2178		priv->irq_boff = platform_get_irq(pdev, 1);
2179		if (priv->irq_boff < 0) {
2180			err = priv->irq_boff;
2181			goto failed_platform_get_irq;
2182		}
2183		priv->irq_err = platform_get_irq(pdev, 2);
2184		if (priv->irq_err < 0) {
2185			err = priv->irq_err;
2186			goto failed_platform_get_irq;
2187		}
2188	}
2189
2190	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2191		priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2192			CAN_CTRLMODE_FD_NON_ISO;
2193		priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2194		priv->can.data_bittiming_const =
2195			&flexcan_fd_data_bittiming_const;
2196	} else {
2197		priv->can.bittiming_const = &flexcan_bittiming_const;
2198	}
2199
2200	pm_runtime_get_noresume(&pdev->dev);
2201	pm_runtime_set_active(&pdev->dev);
2202	pm_runtime_enable(&pdev->dev);
2203
2204	err = register_flexcandev(dev);
2205	if (err) {
2206		dev_err(&pdev->dev, "registering netdev failed\n");
2207		goto failed_register;
2208	}
2209
2210	err = flexcan_setup_stop_mode(pdev);
2211	if (err < 0) {
2212		dev_err_probe(&pdev->dev, err, "setup stop mode failed\n");
2213		goto failed_setup_stop_mode;
2214	}
2215
2216	of_can_transceiver(dev);
2217
2218	return 0;
2219
2220 failed_setup_stop_mode:
2221	unregister_flexcandev(dev);
2222 failed_register:
2223	pm_runtime_put_noidle(&pdev->dev);
2224	pm_runtime_disable(&pdev->dev);
2225 failed_platform_get_irq:
2226	free_candev(dev);
2227	return err;
2228}
2229
2230static void flexcan_remove(struct platform_device *pdev)
2231{
2232	struct net_device *dev = platform_get_drvdata(pdev);
2233
2234	device_set_wakeup_enable(&pdev->dev, false);
2235	device_set_wakeup_capable(&pdev->dev, false);
2236	unregister_flexcandev(dev);
2237	pm_runtime_disable(&pdev->dev);
2238	free_candev(dev);
 
 
2239}
2240
2241static int __maybe_unused flexcan_suspend(struct device *device)
2242{
2243	struct net_device *dev = dev_get_drvdata(device);
2244	struct flexcan_priv *priv = netdev_priv(dev);
2245	int err;
2246
2247	if (netif_running(dev)) {
2248		/* if wakeup is enabled, enter stop mode
2249		 * else enter disabled mode.
2250		 */
2251		if (device_may_wakeup(device)) {
2252			enable_irq_wake(dev->irq);
2253			err = flexcan_enter_stop_mode(priv);
2254			if (err)
2255				return err;
2256		} else {
2257			err = flexcan_chip_stop(dev);
2258			if (err)
2259				return err;
2260
2261			flexcan_chip_interrupts_disable(dev);
2262
2263			err = pinctrl_pm_select_sleep_state(device);
2264			if (err)
2265				return err;
2266		}
2267		netif_stop_queue(dev);
2268		netif_device_detach(dev);
2269	}
2270	priv->can.state = CAN_STATE_SLEEPING;
2271
2272	return 0;
2273}
2274
2275static int __maybe_unused flexcan_resume(struct device *device)
2276{
2277	struct net_device *dev = dev_get_drvdata(device);
2278	struct flexcan_priv *priv = netdev_priv(dev);
2279	int err;
2280
2281	priv->can.state = CAN_STATE_ERROR_ACTIVE;
2282	if (netif_running(dev)) {
2283		netif_device_attach(dev);
2284		netif_start_queue(dev);
2285		if (device_may_wakeup(device)) {
2286			disable_irq_wake(dev->irq);
2287			err = flexcan_exit_stop_mode(priv);
2288			if (err)
2289				return err;
2290		} else {
2291			err = pinctrl_pm_select_default_state(device);
2292			if (err)
2293				return err;
2294
2295			err = flexcan_chip_start(dev);
2296			if (err)
2297				return err;
2298
2299			flexcan_chip_interrupts_enable(dev);
2300		}
2301	}
2302
2303	return 0;
2304}
2305
2306static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2307{
2308	struct net_device *dev = dev_get_drvdata(device);
2309	struct flexcan_priv *priv = netdev_priv(dev);
2310
2311	flexcan_clks_disable(priv);
2312
2313	return 0;
2314}
2315
2316static int __maybe_unused flexcan_runtime_resume(struct device *device)
2317{
2318	struct net_device *dev = dev_get_drvdata(device);
2319	struct flexcan_priv *priv = netdev_priv(dev);
2320
2321	return flexcan_clks_enable(priv);
2322}
2323
2324static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2325{
2326	struct net_device *dev = dev_get_drvdata(device);
2327	struct flexcan_priv *priv = netdev_priv(dev);
2328
2329	if (netif_running(dev)) {
2330		int err;
2331
2332		if (device_may_wakeup(device))
2333			flexcan_enable_wakeup_irq(priv, true);
2334
2335		/* For FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI, it need ATF to send
2336		 * to SM through SCMI protocol, SM will assert the IPG_STOP
2337		 * signal. But all this works need the CAN clocks keep on.
2338		 * After the CAN module get the IPG_STOP mode, and switch to
2339		 * STOP mode, whether still keep the CAN clocks on or gate them
2340		 * off depend on the Hardware design.
2341		 */
2342		if (!(device_may_wakeup(device) &&
2343		      priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)) {
2344			err = pm_runtime_force_suspend(device);
2345			if (err)
2346				return err;
2347		}
 
 
 
 
2348	}
2349
2350	return 0;
2351}
2352
2353static int __maybe_unused flexcan_noirq_resume(struct device *device)
2354{
2355	struct net_device *dev = dev_get_drvdata(device);
2356	struct flexcan_priv *priv = netdev_priv(dev);
2357
2358	if (netif_running(dev)) {
2359		int err;
2360
 
 
 
2361		if (!(device_may_wakeup(device) &&
2362		      priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)) {
2363			err = pm_runtime_force_resume(device);
2364			if (err)
2365				return err;
2366		}
2367
2368		if (device_may_wakeup(device))
2369			flexcan_enable_wakeup_irq(priv, false);
2370	}
2371
2372	return 0;
2373}
2374
2375static const struct dev_pm_ops flexcan_pm_ops = {
2376	SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2377	SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2378	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2379};
2380
2381static struct platform_driver flexcan_driver = {
2382	.driver = {
2383		.name = DRV_NAME,
2384		.pm = &flexcan_pm_ops,
2385		.of_match_table = flexcan_of_match,
2386	},
2387	.probe = flexcan_probe,
2388	.remove = flexcan_remove,
2389	.id_table = flexcan_id_table,
2390};
2391
2392module_platform_driver(flexcan_driver);
2393
2394MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2395	      "Marc Kleine-Budde <kernel@pengutronix.de>");
2396MODULE_LICENSE("GPL v2");
2397MODULE_DESCRIPTION("CAN port driver for flexcan based chip");