1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2022 Microchip UNG
  4 */
  5
  6#include <dt-bindings/clock/microchip,lan966x.h>
  7#include <dt-bindings/gpio/gpio.h>
  8#include <dt-bindings/interrupt-controller/irq.h>
  9#include <dt-bindings/mfd/atmel-flexcom.h>
 10#include <dt-bindings/phy/phy-lan966x-serdes.h>
 11
 12/dts-v1/;
 13/plugin/;
 14
 15/ {
 16	fragment@0 {
 17		target-path = "";
 18
 19		/*
 20		 * These properties allow to avoid a dtc warnings.
 21		 * The real interrupt controller is the PCI device itself. It
 22		 * is the node on which the device tree overlay will be applied.
 23		 * This node has those properties.
 24		 */
 25		#interrupt-cells = <1>;
 26		interrupt-controller;
 27
 28		__overlay__ {
 29			#address-cells = <3>;
 30			#size-cells = <2>;
 31
 32			cpu_clk: clock-600000000 {
 33				compatible = "fixed-clock";
 34				#clock-cells = <0>;
 35				clock-frequency = <600000000>;  /* CPU clock = 600MHz */
 36			};
 37
 38			ddr_clk: clock-30000000 {
 39				compatible = "fixed-clock";
 40				#clock-cells = <0>;
 41				clock-frequency = <30000000>;  /* Fabric clock = 30MHz */
 42			};
 43
 44			sys_clk: clock-15625000 {
 45				compatible = "fixed-clock";
 46				#clock-cells = <0>;
 47				clock-frequency = <15625000>;  /* System clock = 15.625MHz */
 48			};
 49
 50			pci-ep-bus@0 {
 51				compatible = "simple-bus";
 52				#address-cells = <1>;
 53				#size-cells = <1>;
 54
 55				/*
 56				 * map @0xe2000000 (32MB) to BAR0 (CPU)
 57				 * map @0xe0000000 (16MB) to BAR1 (AMBA)
 58				 */
 59				ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
 60				          0xe0000000 0x01 0x00 0x00 0x1000000>;
 61
 62				oic: oic@e00c0120 {
 63					compatible = "microchip,lan966x-oic";
 64					#interrupt-cells = <2>;
 65					interrupt-controller;
 66					interrupts = <0>; /* PCI INTx assigned interrupt */
 67					reg = <0xe00c0120 0x190>;
 68				};
 69
 70				cpu_ctrl: syscon@e00c0000 {
 71					compatible = "microchip,lan966x-cpu-syscon", "syscon";
 72					reg = <0xe00c0000 0xa8>;
 73				};
 74
 75				reset: reset@e200400c {
 76					compatible = "microchip,lan966x-switch-reset";
 77					reg = <0xe200400c 0x4>, <0xe00c0000 0xa8>;
 78					reg-names = "gcb","cpu";
 79					#reset-cells = <1>;
 80					cpu-syscon = <&cpu_ctrl>;
 81				};
 82
 83				gpio: pinctrl@e2004064 {
 84					compatible = "microchip,lan966x-pinctrl";
 85					reg = <0xe2004064 0xb4>,
 86					      <0xe2010024 0x138>;
 87					resets = <&reset 0>;
 88					reset-names = "switch";
 89					gpio-controller;
 90					#gpio-cells = <2>;
 91					gpio-ranges = <&gpio 0 0 78>;
 92					interrupt-parent = <&oic>;
 93					interrupt-controller;
 94					interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
 95					#interrupt-cells = <2>;
 96
 97					tod_pins: tod_pins {
 98						pins = "GPIO_36";
 99						function = "ptpsync_1";
100					};
101
102					fc0_a_pins: fcb4-i2c-pins {
103						/* RXD, TXD */
104						pins = "GPIO_9", "GPIO_10";
105						function = "fc0_a";
106					};
107
108				};
109
110				serdes: serdes@e202c000 {
111					compatible = "microchip,lan966x-serdes";
112					reg = <0xe202c000 0x9c>,
113					      <0xe2004010 0x4>;
114					#phy-cells = <2>;
115				};
116
117				mdio1: mdio@e200413c {
118					#address-cells = <1>;
119					#size-cells = <0>;
120					compatible = "microchip,lan966x-miim";
121					reg = <0xe200413c 0x24>,
122					      <0xe2010020 0x4>;
123
124					resets = <&reset 0>;
125					reset-names = "switch";
126
127					lan966x_phy0: ethernet-lan966x_phy@1 {
128						reg = <1>;
129					};
130
131					lan966x_phy1: ethernet-lan966x_phy@2 {
132						reg = <2>;
133					};
134				};
135
136				switch: switch@e0000000 {
137					compatible = "microchip,lan966x-switch";
138					reg = <0xe0000000 0x0100000>,
139					      <0xe2000000 0x0800000>;
140					reg-names = "cpu", "gcb";
141
142					interrupt-parent = <&oic>;
143					interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
144						     <9 IRQ_TYPE_LEVEL_HIGH>;
145					interrupt-names = "xtr", "ana";
146
147					resets = <&reset 0>;
148					reset-names = "switch";
149
150					pinctrl-names = "default";
151					pinctrl-0 = <&tod_pins>;
152
153					ethernet-ports {
154						#address-cells = <1>;
155						#size-cells = <0>;
156
157						port0: port@0 {
158							phy-handle = <&lan966x_phy0>;
159
160							reg = <0>;
161							phy-mode = "gmii";
162							phys = <&serdes 0 CU(0)>;
163						};
164
165						port1: port@1 {
166							phy-handle = <&lan966x_phy1>;
167
168							reg = <1>;
169							phy-mode = "gmii";
170							phys = <&serdes 1 CU(1)>;
171						};
172					};
173				};
174			};
175		};
176	};
177};