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1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2023 Loongson Technology Corporation Limited
4 */
5
6#ifndef __LSDC_REGS_H__
7#define __LSDC_REGS_H__
8
9#include <linux/bitops.h>
10#include <linux/types.h>
11
12/*
13 * PIXEL PLL Reference clock
14 */
15#define LSDC_PLL_REF_CLK_KHZ 100000
16
17/*
18 * Those PLL registers are relative to LSxxxxx_CFG_REG_BASE. xxxxx = 7A1000,
19 * 7A2000, 2K2000, 2K1000 etc.
20 */
21
22/* LS7A1000 */
23
24#define LS7A1000_PIXPLL0_REG 0x04B0
25#define LS7A1000_PIXPLL1_REG 0x04C0
26
27/* The DC, GPU, Graphic Memory Controller share the single gfxpll */
28#define LS7A1000_PLL_GFX_REG 0x0490
29
30#define LS7A1000_CONF_REG_BASE 0x10010000
31
32/* LS7A2000 */
33
34#define LS7A2000_PIXPLL0_REG 0x04B0
35#define LS7A2000_PIXPLL1_REG 0x04C0
36
37/* The DC, GPU, Graphic Memory Controller share the single gfxpll */
38#define LS7A2000_PLL_GFX_REG 0x0490
39
40#define LS7A2000_CONF_REG_BASE 0x10010000
41
42/* For LSDC_CRTCx_CFG_REG */
43#define CFG_PIX_FMT_MASK GENMASK(2, 0)
44
45enum lsdc_pixel_format {
46 LSDC_PF_NONE = 0,
47 LSDC_PF_XRGB444 = 1, /* [12 bits] */
48 LSDC_PF_XRGB555 = 2, /* [15 bits] */
49 LSDC_PF_XRGB565 = 3, /* RGB [16 bits] */
50 LSDC_PF_XRGB8888 = 4, /* XRGB [32 bits] */
51};
52
53/*
54 * Each crtc has two set fb address registers usable, FB_REG_IN_USING bit of
55 * LSDC_CRTCx_CFG_REG indicate which fb address register is in using by the
56 * CRTC currently. CFG_PAGE_FLIP is used to trigger the switch, the switching
57 * will be finished at the very next vblank. Trigger it again if you want to
58 * switch back.
59 *
60 * If FB0_ADDR_REG is in using, we write the address to FB0_ADDR_REG,
61 * if FB1_ADDR_REG is in using, we write the address to FB1_ADDR_REG.
62 */
63#define CFG_PAGE_FLIP BIT(7)
64#define CFG_OUTPUT_ENABLE BIT(8)
65#define CFG_HW_CLONE BIT(9)
66/* Indicate witch fb addr reg is in using, currently. read only */
67#define FB_REG_IN_USING BIT(11)
68#define CFG_GAMMA_EN BIT(12)
69
70/* The DC get soft reset if this bit changed from "1" to "0", active low */
71#define CFG_RESET_N BIT(20)
72/* If this bit is set, it say that the CRTC stop working anymore, anchored. */
73#define CRTC_ANCHORED BIT(24)
74
75/*
76 * The DMA step of the DC in LS7A2000/LS2K2000 is configurable,
77 * setting those bits on ls7a1000 platform make no effect.
78 */
79#define CFG_DMA_STEP_MASK GENMASK(17, 16)
80#define CFG_DMA_STEP_SHIFT 16
81enum lsdc_dma_steps {
82 LSDC_DMA_STEP_256_BYTES = 0,
83 LSDC_DMA_STEP_128_BYTES = 1,
84 LSDC_DMA_STEP_64_BYTES = 2,
85 LSDC_DMA_STEP_32_BYTES = 3,
86};
87
88#define CFG_VALID_BITS_MASK GENMASK(20, 0)
89
90/* For LSDC_CRTCx_HSYNC_REG */
91#define HSYNC_INV BIT(31)
92#define HSYNC_EN BIT(30)
93#define HSYNC_END_MASK GENMASK(28, 16)
94#define HSYNC_END_SHIFT 16
95#define HSYNC_START_MASK GENMASK(12, 0)
96#define HSYNC_START_SHIFT 0
97
98/* For LSDC_CRTCx_VSYNC_REG */
99#define VSYNC_INV BIT(31)
100#define VSYNC_EN BIT(30)
101#define VSYNC_END_MASK GENMASK(27, 16)
102#define VSYNC_END_SHIFT 16
103#define VSYNC_START_MASK GENMASK(11, 0)
104#define VSYNC_START_SHIFT 0
105
106/*********** CRTC0 ***********/
107#define LSDC_CRTC0_CFG_REG 0x1240
108#define LSDC_CRTC0_FB0_ADDR_LO_REG 0x1260
109#define LSDC_CRTC0_FB0_ADDR_HI_REG 0x15A0
110#define LSDC_CRTC0_STRIDE_REG 0x1280
111#define LSDC_CRTC0_FB_ORIGIN_REG 0x1300
112#define LSDC_CRTC0_HDISPLAY_REG 0x1400
113#define LSDC_CRTC0_HSYNC_REG 0x1420
114#define LSDC_CRTC0_VDISPLAY_REG 0x1480
115#define LSDC_CRTC0_VSYNC_REG 0x14A0
116#define LSDC_CRTC0_GAMMA_INDEX_REG 0x14E0
117#define LSDC_CRTC0_GAMMA_DATA_REG 0x1500
118#define LSDC_CRTC0_FB1_ADDR_LO_REG 0x1580
119#define LSDC_CRTC0_FB1_ADDR_HI_REG 0x15C0
120
121/*********** CRTC1 ***********/
122#define LSDC_CRTC1_CFG_REG 0x1250
123#define LSDC_CRTC1_FB0_ADDR_LO_REG 0x1270
124#define LSDC_CRTC1_FB0_ADDR_HI_REG 0x15B0
125#define LSDC_CRTC1_STRIDE_REG 0x1290
126#define LSDC_CRTC1_FB_ORIGIN_REG 0x1310
127#define LSDC_CRTC1_HDISPLAY_REG 0x1410
128#define LSDC_CRTC1_HSYNC_REG 0x1430
129#define LSDC_CRTC1_VDISPLAY_REG 0x1490
130#define LSDC_CRTC1_VSYNC_REG 0x14B0
131#define LSDC_CRTC1_GAMMA_INDEX_REG 0x14F0
132#define LSDC_CRTC1_GAMMA_DATA_REG 0x1510
133#define LSDC_CRTC1_FB1_ADDR_LO_REG 0x1590
134#define LSDC_CRTC1_FB1_ADDR_HI_REG 0x15D0
135
136/* For LSDC_CRTCx_DVO_CONF_REG */
137#define PHY_CLOCK_POL BIT(9)
138#define PHY_CLOCK_EN BIT(8)
139#define PHY_DE_POL BIT(1)
140#define PHY_DATA_EN BIT(0)
141
142/*********** DVO0 ***********/
143#define LSDC_CRTC0_DVO_CONF_REG 0x13C0
144
145/*********** DVO1 ***********/
146#define LSDC_CRTC1_DVO_CONF_REG 0x13D0
147
148/*
149 * All of the DC variants has the hardware which record the scan position
150 * of the CRTC, [31:16] : current X position, [15:0] : current Y position
151 */
152#define LSDC_CRTC0_SCAN_POS_REG 0x14C0
153#define LSDC_CRTC1_SCAN_POS_REG 0x14D0
154
155/*
156 * LS7A2000 has Sync Deviation register.
157 */
158#define SYNC_DEVIATION_EN BIT(31)
159#define SYNC_DEVIATION_NUM GENMASK(12, 0)
160#define LSDC_CRTC0_SYNC_DEVIATION_REG 0x1B80
161#define LSDC_CRTC1_SYNC_DEVIATION_REG 0x1B90
162
163/*
164 * In gross, LSDC_CRTC1_XXX_REG - LSDC_CRTC0_XXX_REG = 0x10, but not all of
165 * the registers obey this rule, LSDC_CURSORx_XXX_REG just don't honor this.
166 * This is the root cause we can't untangle the code by manpulating offset
167 * of the register access simply. Our hardware engineers are lack experiance
168 * when they design this...
169 */
170#define CRTC_PIPE_OFFSET 0x10
171
172/*
173 * There is only one hardware cursor unit in LS7A1000 and LS2K1000, let
174 * CFG_HW_CLONE_EN bit be "1" could eliminate this embarrassment, we made
175 * it on custom clone mode application. While LS7A2000 has two hardware
176 * cursor unit which is good enough.
177 */
178#define CURSOR_FORMAT_MASK GENMASK(1, 0)
179#define CURSOR_FORMAT_SHIFT 0
180enum lsdc_cursor_format {
181 CURSOR_FORMAT_DISABLE = 0,
182 CURSOR_FORMAT_MONOCHROME = 1, /* masked */
183 CURSOR_FORMAT_ARGB8888 = 2, /* A8R8G8B8 */
184};
185
186/*
187 * LS7A1000 and LS2K1000 only support 32x32, LS2K2000 and LS7A2000 support
188 * 64x64, but it seems that setting this bit make no harms on LS7A1000, it
189 * just don't take effects.
190 */
191#define CURSOR_SIZE_SHIFT 2
192enum lsdc_cursor_size {
193 CURSOR_SIZE_32X32 = 0,
194 CURSOR_SIZE_64X64 = 1,
195};
196
197#define CURSOR_LOCATION_SHIFT 4
198enum lsdc_cursor_location {
199 CURSOR_ON_CRTC0 = 0,
200 CURSOR_ON_CRTC1 = 1,
201};
202
203#define LSDC_CURSOR0_CFG_REG 0x1520
204#define LSDC_CURSOR0_ADDR_LO_REG 0x1530
205#define LSDC_CURSOR0_ADDR_HI_REG 0x15e0
206#define LSDC_CURSOR0_POSITION_REG 0x1540 /* [31:16] Y, [15:0] X */
207#define LSDC_CURSOR0_BG_COLOR_REG 0x1550 /* background color */
208#define LSDC_CURSOR0_FG_COLOR_REG 0x1560 /* foreground color */
209
210#define LSDC_CURSOR1_CFG_REG 0x1670
211#define LSDC_CURSOR1_ADDR_LO_REG 0x1680
212#define LSDC_CURSOR1_ADDR_HI_REG 0x16e0
213#define LSDC_CURSOR1_POSITION_REG 0x1690 /* [31:16] Y, [15:0] X */
214#define LSDC_CURSOR1_BG_COLOR_REG 0x16A0 /* background color */
215#define LSDC_CURSOR1_FG_COLOR_REG 0x16B0 /* foreground color */
216
217/*
218 * DC Interrupt Control Register, 32bit, Address Offset: 1570
219 *
220 * Bits 15:0 inidicate the interrupt status
221 * Bits 31:16 control enable interrupts corresponding to bit 15:0 or not
222 * Write 1 to enable, write 0 to disable
223 *
224 * RF: Read Finished
225 * IDBU: Internal Data Buffer Underflow
226 * IDBFU: Internal Data Buffer Fatal Underflow
227 * CBRF: Cursor Buffer Read Finished Flag, no use.
228 * FBRF0: CRTC-0 reading from its framebuffer finished.
229 * FBRF1: CRTC-1 reading from its framebuffer finished.
230 *
231 * +-------+--------------------------+-------+--------+--------+-------+
232 * | 31:27 | 26:16 | 15:11 | 10 | 9 | 8 |
233 * +-------+--------------------------+-------+--------+--------+-------+
234 * | N/A | Interrupt Enable Control | N/A | IDBFU0 | IDBFU1 | IDBU0 |
235 * +-------+--------------------------+-------+--------+--------+-------+
236 *
237 * +-------+-------+-------+------+--------+--------+--------+--------+
238 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
239 * +-------+-------+-------+------+--------+--------+--------+--------+
240 * | IDBU1 | FBRF0 | FBRF1 | CRRF | HSYNC0 | VSYNC0 | HSYNC1 | VSYNC1 |
241 * +-------+-------+-------+------+--------+--------+--------+--------+
242 *
243 * unfortunately, CRTC0's interrupt is mess with CRTC1's interrupt in one
244 * register again.
245 */
246
247#define LSDC_INT_REG 0x1570
248
249#define INT_CRTC0_VSYNC BIT(2)
250#define INT_CRTC0_HSYNC BIT(3)
251#define INT_CRTC0_RF BIT(6)
252#define INT_CRTC0_IDBU BIT(8)
253#define INT_CRTC0_IDBFU BIT(10)
254
255#define INT_CRTC1_VSYNC BIT(0)
256#define INT_CRTC1_HSYNC BIT(1)
257#define INT_CRTC1_RF BIT(5)
258#define INT_CRTC1_IDBU BIT(7)
259#define INT_CRTC1_IDBFU BIT(9)
260
261#define INT_CRTC0_VSYNC_EN BIT(18)
262#define INT_CRTC0_HSYNC_EN BIT(19)
263#define INT_CRTC0_RF_EN BIT(22)
264#define INT_CRTC0_IDBU_EN BIT(24)
265#define INT_CRTC0_IDBFU_EN BIT(26)
266
267#define INT_CRTC1_VSYNC_EN BIT(16)
268#define INT_CRTC1_HSYNC_EN BIT(17)
269#define INT_CRTC1_RF_EN BIT(21)
270#define INT_CRTC1_IDBU_EN BIT(23)
271#define INT_CRTC1_IDBFU_EN BIT(25)
272
273#define INT_STATUS_MASK GENMASK(15, 0)
274
275/*
276 * LS7A1000/LS7A2000 have 4 gpios which are used to emulated I2C.
277 * They are under control of the LS7A_DC_GPIO_DAT_REG and LS7A_DC_GPIO_DIR_REG
278 * register, Those GPIOs has no relationship whth the GPIO hardware on the
279 * bridge chip itself. Those offsets are relative to DC register base address
280 *
281 * LS2k1000 don't have those registers, they use hardware i2c or general GPIO
282 * emulated i2c from linux i2c subsystem.
283 *
284 * GPIO data register, address offset: 0x1650
285 * +---------------+-----------+-----------+
286 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
287 * +---------------+-----------+-----------+
288 * | | DVO1 | DVO0 |
289 * + N/A +-----------+-----------+
290 * | | SCL | SDA | SCL | SDA |
291 * +---------------+-----------+-----------+
292 */
293#define LS7A_DC_GPIO_DAT_REG 0x1650
294
295/*
296 * GPIO Input/Output direction control register, address offset: 0x1660
297 */
298#define LS7A_DC_GPIO_DIR_REG 0x1660
299
300/*
301 * LS7A2000 has two built-in HDMI Encoder and one VGA encoder
302 */
303
304/*
305 * Number of continuous packets may be present
306 * in HDMI hblank and vblank zone, should >= 48
307 */
308#define LSDC_HDMI0_ZONE_REG 0x1700
309#define LSDC_HDMI1_ZONE_REG 0x1710
310
311#define HDMI_H_ZONE_IDLE_SHIFT 0
312#define HDMI_V_ZONE_IDLE_SHIFT 16
313
314/* HDMI Iterface Control Reg */
315#define HDMI_INTERFACE_EN BIT(0)
316#define HDMI_PACKET_EN BIT(1)
317#define HDMI_AUDIO_EN BIT(2)
318/*
319 * Preamble:
320 * Immediately preceding each video data period or data island period is the
321 * preamble. This is a sequence of eight identical control characters that
322 * indicate whether the upcoming data period is a video data period or is a
323 * data island. The values of CTL0, CTL1, CTL2, and CTL3 indicate the type of
324 * data period that follows.
325 */
326#define HDMI_VIDEO_PREAMBLE_MASK GENMASK(7, 4)
327#define HDMI_VIDEO_PREAMBLE_SHIFT 4
328/* 1: hw i2c, 0: gpio emu i2c, shouldn't put in LSDC_HDMIx_INTF_CTRL_REG */
329#define HW_I2C_EN BIT(8)
330#define HDMI_CTL_PERIOD_MODE BIT(9)
331#define LSDC_HDMI0_INTF_CTRL_REG 0x1720
332#define LSDC_HDMI1_INTF_CTRL_REG 0x1730
333
334#define HDMI_PHY_EN BIT(0)
335#define HDMI_PHY_RESET_N BIT(1)
336#define HDMI_PHY_TERM_L_EN BIT(8)
337#define HDMI_PHY_TERM_H_EN BIT(9)
338#define HDMI_PHY_TERM_DET_EN BIT(10)
339#define HDMI_PHY_TERM_STATUS BIT(11)
340#define LSDC_HDMI0_PHY_CTRL_REG 0x1800
341#define LSDC_HDMI1_PHY_CTRL_REG 0x1810
342
343/* High level duration need > 1us */
344#define HDMI_PLL_ENABLE BIT(0)
345#define HDMI_PLL_LOCKED BIT(16)
346/* Bypass the software configured values, using default source from somewhere */
347#define HDMI_PLL_BYPASS BIT(17)
348
349#define HDMI_PLL_IDF_SHIFT 1
350#define HDMI_PLL_IDF_MASK GENMASK(5, 1)
351#define HDMI_PLL_LF_SHIFT 6
352#define HDMI_PLL_LF_MASK GENMASK(12, 6)
353#define HDMI_PLL_ODF_SHIFT 13
354#define HDMI_PLL_ODF_MASK GENMASK(15, 13)
355#define LSDC_HDMI0_PHY_PLL_REG 0x1820
356#define LSDC_HDMI1_PHY_PLL_REG 0x1830
357
358/* LS7A2000/LS2K2000 has hpd status reg, while the two hdmi's status
359 * located at the one register again.
360 */
361#define LSDC_HDMI_HPD_STATUS_REG 0x1BA0
362#define HDMI0_HPD_FLAG BIT(0)
363#define HDMI1_HPD_FLAG BIT(1)
364
365#define LSDC_HDMI0_PHY_CAL_REG 0x18C0
366#define LSDC_HDMI1_PHY_CAL_REG 0x18D0
367
368/* AVI InfoFrame */
369#define LSDC_HDMI0_AVI_CONTENT0 0x18E0
370#define LSDC_HDMI1_AVI_CONTENT0 0x18D0
371#define LSDC_HDMI0_AVI_CONTENT1 0x1900
372#define LSDC_HDMI1_AVI_CONTENT1 0x1910
373#define LSDC_HDMI0_AVI_CONTENT2 0x1920
374#define LSDC_HDMI1_AVI_CONTENT2 0x1930
375#define LSDC_HDMI0_AVI_CONTENT3 0x1940
376#define LSDC_HDMI1_AVI_CONTENT3 0x1950
377
378/* 1: enable avi infoframe packet, 0: disable avi infoframe packet */
379#define AVI_PKT_ENABLE BIT(0)
380/* 1: send one every two frame, 0: send one each frame */
381#define AVI_PKT_SEND_FREQ BIT(1)
382/*
383 * 1: write 1 to flush avi reg content0 ~ content3 to the packet to be send,
384 * The hardware will clear this bit automatically.
385 */
386#define AVI_PKT_UPDATE BIT(2)
387
388#define LSDC_HDMI0_AVI_INFO_CRTL_REG 0x1960
389#define LSDC_HDMI1_AVI_INFO_CRTL_REG 0x1970
390
391/*
392 * LS7A2000 has the hardware which count the number of vblank generated
393 */
394#define LSDC_CRTC0_VSYNC_COUNTER_REG 0x1A00
395#define LSDC_CRTC1_VSYNC_COUNTER_REG 0x1A10
396
397/*
398 * LS7A2000 has the audio hardware associate with the HDMI encoder.
399 */
400#define LSDC_HDMI0_AUDIO_PLL_LO_REG 0x1A20
401#define LSDC_HDMI1_AUDIO_PLL_LO_REG 0x1A30
402
403#define LSDC_HDMI0_AUDIO_PLL_HI_REG 0x1A40
404#define LSDC_HDMI1_AUDIO_PLL_HI_REG 0x1A50
405
406#endif