1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Ingenic JZ47xx KMS driver
   4//
   5// Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
   6
   7#include "ingenic-drm.h"
   8
   9#include <linux/bitfield.h>
  10#include <linux/component.h>
  11#include <linux/clk.h>
  12#include <linux/dma-mapping.h>
  13#include <linux/io.h>
  14#include <linux/media-bus-format.h>
  15#include <linux/module.h>
  16#include <linux/mutex.h>
  17#include <linux/of.h>
  18#include <linux/of_reserved_mem.h>
  19#include <linux/platform_device.h>
  20#include <linux/pm.h>
  21#include <linux/regmap.h>
  22
  23#include <drm/drm_atomic.h>
  24#include <drm/drm_atomic_helper.h>
  25#include <drm/drm_bridge.h>
  26#include <drm/drm_bridge_connector.h>
  27#include <drm/drm_client_setup.h>
  28#include <drm/drm_color_mgmt.h>
  29#include <drm/drm_crtc.h>
 
  30#include <drm/drm_damage_helper.h>
  31#include <drm/drm_drv.h>
  32#include <drm/drm_encoder.h>
  33#include <drm/drm_gem_dma_helper.h>
  34#include <drm/drm_fb_dma_helper.h>
  35#include <drm/drm_fbdev_dma.h>
  36#include <drm/drm_fourcc.h>
  37#include <drm/drm_framebuffer.h>
  38#include <drm/drm_gem_atomic_helper.h>
  39#include <drm/drm_gem_framebuffer_helper.h>
  40#include <drm/drm_managed.h>
  41#include <drm/drm_of.h>
  42#include <drm/drm_panel.h>
  43#include <drm/drm_plane.h>
  44#include <drm/drm_probe_helper.h>
  45#include <drm/drm_vblank.h>
  46
  47#define HWDESC_PALETTE 2
  48
  49struct ingenic_dma_hwdesc {
  50	u32 next;
  51	u32 addr;
  52	u32 id;
  53	u32 cmd;
  54	/* extended hw descriptor for jz4780 */
  55	u32 offsize;
  56	u32 pagewidth;
  57	u32 cpos;
  58	u32 dessize;
  59} __aligned(16);
  60
  61struct ingenic_dma_hwdescs {
  62	struct ingenic_dma_hwdesc hwdesc[3];
  63	u16 palette[256] __aligned(16);
  64};
  65
  66struct jz_soc_info {
  67	bool needs_dev_clk;
  68	bool has_osd;
  69	bool has_alpha;
  70	bool map_noncoherent;
  71	bool use_extended_hwdesc;
  72	bool plane_f0_not_working;
  73	u32 max_burst;
  74	unsigned int max_width, max_height;
  75	const u32 *formats_f0, *formats_f1;
  76	unsigned int num_formats_f0, num_formats_f1;
  77};
  78
  79struct ingenic_drm_private_state {
  80	struct drm_private_state base;
  81	bool use_palette;
  82};
  83
  84struct ingenic_drm {
  85	struct drm_device drm;
  86	/*
  87	 * f1 (aka. foreground1) is our primary plane, on top of which
  88	 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in
  89	 * hardware and cannot be changed.
  90	 */
  91	struct drm_plane f0, f1, *ipu_plane;
  92	struct drm_crtc crtc;
  93
  94	struct device *dev;
  95	struct regmap *map;
  96	struct clk *lcd_clk, *pix_clk;
  97	const struct jz_soc_info *soc_info;
  98
  99	struct ingenic_dma_hwdescs *dma_hwdescs;
 100	dma_addr_t dma_hwdescs_phys;
 101
 102	bool panel_is_sharp;
 103	bool no_vblank;
 104
 105	/*
 106	 * clk_mutex is used to synchronize the pixel clock rate update with
 107	 * the VBLANK. When the pixel clock's parent clock needs to be updated,
 108	 * clock_nb's notifier function will lock the mutex, then wait until the
 109	 * next VBLANK. At that point, the parent clock's rate can be updated,
 110	 * and the mutex is then unlocked. If an atomic commit happens in the
 111	 * meantime, it will lock on the mutex, effectively waiting until the
 112	 * clock update process finishes. Finally, the pixel clock's rate will
 113	 * be recomputed when the mutex has been released, in the pending atomic
 114	 * commit, or a future one.
 115	 */
 116	struct mutex clk_mutex;
 117	bool update_clk_rate;
 118	struct notifier_block clock_nb;
 119
 120	struct drm_private_obj private_obj;
 121};
 122
 123struct ingenic_drm_bridge {
 124	struct drm_encoder encoder;
 125	struct drm_bridge bridge, *next_bridge;
 126
 127	struct drm_bus_cfg bus_cfg;
 128};
 129
 130static inline struct ingenic_drm_bridge *
 131to_ingenic_drm_bridge(struct drm_encoder *encoder)
 132{
 133	return container_of(encoder, struct ingenic_drm_bridge, encoder);
 134}
 135
 136static inline struct ingenic_drm_private_state *
 137to_ingenic_drm_priv_state(struct drm_private_state *state)
 138{
 139	return container_of(state, struct ingenic_drm_private_state, base);
 140}
 141
 142static struct ingenic_drm_private_state *
 143ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state)
 144{
 145	struct drm_private_state *priv_state;
 146
 147	priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj);
 148	if (IS_ERR(priv_state))
 149		return ERR_CAST(priv_state);
 150
 151	return to_ingenic_drm_priv_state(priv_state);
 152}
 153
 154static struct ingenic_drm_private_state *
 155ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state)
 156{
 157	struct drm_private_state *priv_state;
 158
 159	priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj);
 160	if (!priv_state)
 161		return NULL;
 162
 163	return to_ingenic_drm_priv_state(priv_state);
 164}
 165
 166static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
 167{
 168	switch (reg) {
 169	case JZ_REG_LCD_IID:
 170	case JZ_REG_LCD_SA0:
 171	case JZ_REG_LCD_FID0:
 172	case JZ_REG_LCD_CMD0:
 173	case JZ_REG_LCD_SA1:
 174	case JZ_REG_LCD_FID1:
 175	case JZ_REG_LCD_CMD1:
 176		return false;
 177	default:
 178		return true;
 179	}
 180}
 181
 182static const struct regmap_config ingenic_drm_regmap_config = {
 183	.reg_bits = 32,
 184	.val_bits = 32,
 185	.reg_stride = 4,
 186
 187	.writeable_reg = ingenic_drm_writeable_reg,
 188};
 189
 190static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
 191{
 192	return container_of(drm, struct ingenic_drm, drm);
 193}
 194
 195static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
 196{
 197	return container_of(crtc, struct ingenic_drm, crtc);
 198}
 199
 200static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb)
 201{
 202	return container_of(nb, struct ingenic_drm, clock_nb);
 203}
 204
 205static inline dma_addr_t dma_hwdesc_addr(const struct ingenic_drm *priv,
 206					 unsigned int idx)
 207{
 208	u32 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc[idx]);
 209
 210	return priv->dma_hwdescs_phys + offset;
 211}
 212
 213static int ingenic_drm_update_pixclk(struct notifier_block *nb,
 214				     unsigned long action,
 215				     void *data)
 216{
 217	struct ingenic_drm *priv = drm_nb_get_priv(nb);
 218
 219	switch (action) {
 220	case PRE_RATE_CHANGE:
 221		mutex_lock(&priv->clk_mutex);
 222		priv->update_clk_rate = true;
 223		drm_crtc_wait_one_vblank(&priv->crtc);
 224		return NOTIFY_OK;
 225	default:
 226		mutex_unlock(&priv->clk_mutex);
 227		return NOTIFY_OK;
 228	}
 229}
 230
 231static void ingenic_drm_bridge_atomic_enable(struct drm_bridge *bridge,
 232					     struct drm_bridge_state *old_bridge_state)
 233{
 234	struct ingenic_drm *priv = drm_device_get_priv(bridge->dev);
 235
 236	regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
 237
 238	regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 239			   JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
 240			   JZ_LCD_CTRL_ENABLE);
 241}
 242
 243static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 244					   struct drm_atomic_state *state)
 245{
 246	struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 247	struct ingenic_drm_private_state *priv_state;
 248	unsigned int next_id;
 249
 250	priv_state = ingenic_drm_get_priv_state(priv, state);
 251	if (WARN_ON(IS_ERR(priv_state)))
 252		return;
 253
 254	/* Set addresses of our DMA descriptor chains */
 255	next_id = priv_state->use_palette ? HWDESC_PALETTE : 0;
 256	regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, next_id));
 257	regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1));
 258
 259	drm_crtc_vblank_on(crtc);
 260}
 261
 262static void ingenic_drm_bridge_atomic_disable(struct drm_bridge *bridge,
 263					      struct drm_bridge_state *old_bridge_state)
 264{
 265	struct ingenic_drm *priv = drm_device_get_priv(bridge->dev);
 266	unsigned int var;
 267
 268	regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 269			   JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
 270
 271	regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
 272				 var & JZ_LCD_STATE_DISABLED,
 273				 1000, 0);
 274}
 275
 276static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 277					    struct drm_atomic_state *state)
 278{
 279	drm_crtc_vblank_off(crtc);
 280}
 281
 282static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
 283					    struct drm_display_mode *mode)
 284{
 285	unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
 286
 287	vpe = mode->crtc_vsync_end - mode->crtc_vsync_start;
 288	vds = mode->crtc_vtotal - mode->crtc_vsync_start;
 289	vde = vds + mode->crtc_vdisplay;
 290	vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay;
 291
 292	hpe = mode->crtc_hsync_end - mode->crtc_hsync_start;
 293	hds = mode->crtc_htotal - mode->crtc_hsync_start;
 294	hde = hds + mode->crtc_hdisplay;
 295	ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay;
 296
 297	regmap_write(priv->map, JZ_REG_LCD_VSYNC,
 298		     0 << JZ_LCD_VSYNC_VPS_OFFSET |
 299		     vpe << JZ_LCD_VSYNC_VPE_OFFSET);
 300
 301	regmap_write(priv->map, JZ_REG_LCD_HSYNC,
 302		     0 << JZ_LCD_HSYNC_HPS_OFFSET |
 303		     hpe << JZ_LCD_HSYNC_HPE_OFFSET);
 304
 305	regmap_write(priv->map, JZ_REG_LCD_VAT,
 306		     ht << JZ_LCD_VAT_HT_OFFSET |
 307		     vt << JZ_LCD_VAT_VT_OFFSET);
 308
 309	regmap_write(priv->map, JZ_REG_LCD_DAH,
 310		     hds << JZ_LCD_DAH_HDS_OFFSET |
 311		     hde << JZ_LCD_DAH_HDE_OFFSET);
 312	regmap_write(priv->map, JZ_REG_LCD_DAV,
 313		     vds << JZ_LCD_DAV_VDS_OFFSET |
 314		     vde << JZ_LCD_DAV_VDE_OFFSET);
 315
 316	if (priv->panel_is_sharp) {
 317		regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
 318		regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
 319		regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
 320		regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
 321	}
 322
 323	regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 324			   JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_MASK,
 325			   JZ_LCD_CTRL_OFUP | priv->soc_info->max_burst);
 326
 327	/*
 328	 * IPU restart - specify how much time the LCDC will wait before
 329	 * transferring a new frame from the IPU. The value is the one
 330	 * suggested in the programming manual.
 331	 */
 332	regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN |
 333		     (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB);
 334}
 335
 336static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
 337					 struct drm_atomic_state *state)
 338{
 339	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 340									  crtc);
 341	struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 342	struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL;
 343
 344	if (crtc_state->gamma_lut &&
 345	    drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) {
 346		dev_dbg(priv->dev, "Invalid palette size\n");
 347		return -EINVAL;
 348	}
 349
 350	if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) {
 351		f1_state = drm_atomic_get_plane_state(crtc_state->state,
 352						      &priv->f1);
 353		if (IS_ERR(f1_state))
 354			return PTR_ERR(f1_state);
 355
 356		f0_state = drm_atomic_get_plane_state(crtc_state->state,
 357						      &priv->f0);
 358		if (IS_ERR(f0_state))
 359			return PTR_ERR(f0_state);
 360
 361		if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) {
 362			ipu_state = drm_atomic_get_plane_state(crtc_state->state,
 363							       priv->ipu_plane);
 364			if (IS_ERR(ipu_state))
 365				return PTR_ERR(ipu_state);
 366
 367			/* IPU and F1 planes cannot be enabled at the same time. */
 368			if (f1_state->fb && ipu_state->fb) {
 369				dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n");
 370				return -EINVAL;
 371			}
 372		}
 373
 374		/* If all the planes are disabled, we won't get a VBLANK IRQ */
 375		priv->no_vblank = !f1_state->fb && !f0_state->fb &&
 376				  !(ipu_state && ipu_state->fb);
 377	}
 378
 379	return 0;
 380}
 381
 382static enum drm_mode_status
 383ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
 384{
 385	struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 386	long rate;
 387
 388	if (mode->hdisplay > priv->soc_info->max_width)
 389		return MODE_BAD_HVALUE;
 390	if (mode->vdisplay > priv->soc_info->max_height)
 391		return MODE_BAD_VVALUE;
 392
 393	rate = clk_round_rate(priv->pix_clk, mode->clock * 1000);
 394	if (rate < 0)
 395		return MODE_CLOCK_RANGE;
 396
 397	return MODE_OK;
 398}
 399
 400static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 401					  struct drm_atomic_state *state)
 402{
 403	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 404									  crtc);
 405	struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 406	u32 ctrl = 0;
 407
 408	if (priv->soc_info->has_osd &&
 409	    drm_atomic_crtc_needs_modeset(crtc_state)) {
 410		/*
 411		 * If IPU plane is enabled, enable IPU as source for the F1
 412		 * plane; otherwise use regular DMA.
 413		 */
 414		if (priv->ipu_plane && priv->ipu_plane->state->fb)
 415			ctrl |= JZ_LCD_OSDCTRL_IPU;
 416
 417		regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
 418				   JZ_LCD_OSDCTRL_IPU, ctrl);
 419	}
 420}
 421
 422static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 423					  struct drm_atomic_state *state)
 424{
 425	struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 426	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 427									  crtc);
 428	struct drm_pending_vblank_event *event = crtc_state->event;
 429
 430	if (drm_atomic_crtc_needs_modeset(crtc_state)) {
 431		ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode);
 432		priv->update_clk_rate = true;
 433	}
 434
 435	if (priv->update_clk_rate) {
 436		mutex_lock(&priv->clk_mutex);
 437		clk_set_rate(priv->pix_clk,
 438			     crtc_state->adjusted_mode.crtc_clock * 1000);
 439		priv->update_clk_rate = false;
 440		mutex_unlock(&priv->clk_mutex);
 441	}
 442
 443	if (event) {
 444		crtc_state->event = NULL;
 445
 446		spin_lock_irq(&crtc->dev->event_lock);
 447		if (drm_crtc_vblank_get(crtc) == 0)
 448			drm_crtc_arm_vblank_event(crtc, event);
 449		else
 450			drm_crtc_send_vblank_event(crtc, event);
 451		spin_unlock_irq(&crtc->dev->event_lock);
 452	}
 453}
 454
 455static int ingenic_drm_plane_atomic_check(struct drm_plane *plane,
 456					  struct drm_atomic_state *state)
 457{
 458	struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
 459										 plane);
 460	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 461										 plane);
 462	struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 463	struct ingenic_drm_private_state *priv_state;
 464	struct drm_crtc_state *crtc_state;
 465	struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
 466	int ret;
 467
 468	if (!crtc)
 469		return 0;
 470
 471	if (priv->soc_info->plane_f0_not_working && plane == &priv->f0)
 472		return -EINVAL;
 473
 474	crtc_state = drm_atomic_get_existing_crtc_state(state,
 475							crtc);
 476	if (WARN_ON(!crtc_state))
 477		return -EINVAL;
 478
 479	priv_state = ingenic_drm_get_priv_state(priv, state);
 480	if (IS_ERR(priv_state))
 481		return PTR_ERR(priv_state);
 482
 483	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 484						  DRM_PLANE_NO_SCALING,
 485						  DRM_PLANE_NO_SCALING,
 486						  priv->soc_info->has_osd,
 487						  true);
 488	if (ret)
 489		return ret;
 490
 491	/*
 492	 * If OSD is not available, check that the width/height match.
 493	 * Note that state->src_* are in 16.16 fixed-point format.
 494	 */
 495	if (!priv->soc_info->has_osd &&
 496	    (new_plane_state->src_x != 0 ||
 497	     (new_plane_state->src_w >> 16) != new_plane_state->crtc_w ||
 498	     (new_plane_state->src_h >> 16) != new_plane_state->crtc_h))
 499		return -EINVAL;
 500
 501	priv_state->use_palette = new_plane_state->fb &&
 502		new_plane_state->fb->format->format == DRM_FORMAT_C8;
 503
 504	/*
 505	 * Require full modeset if enabling or disabling a plane, or changing
 506	 * its position, size or depth.
 507	 */
 508	if (priv->soc_info->has_osd &&
 509	    (!old_plane_state->fb || !new_plane_state->fb ||
 510	     old_plane_state->crtc_x != new_plane_state->crtc_x ||
 511	     old_plane_state->crtc_y != new_plane_state->crtc_y ||
 512	     old_plane_state->crtc_w != new_plane_state->crtc_w ||
 513	     old_plane_state->crtc_h != new_plane_state->crtc_h ||
 514	     old_plane_state->fb->format->format != new_plane_state->fb->format->format))
 515		crtc_state->mode_changed = true;
 516
 517	if (priv->soc_info->map_noncoherent)
 518		drm_atomic_helper_check_plane_damage(state, new_plane_state);
 519
 520	return 0;
 521}
 522
 523static void ingenic_drm_plane_enable(struct ingenic_drm *priv,
 524				     struct drm_plane *plane)
 525{
 526	unsigned int en_bit;
 527
 528	if (priv->soc_info->has_osd) {
 529		if (plane != &priv->f0)
 530			en_bit = JZ_LCD_OSDC_F1EN;
 531		else
 532			en_bit = JZ_LCD_OSDC_F0EN;
 533
 534		regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
 535	}
 536}
 537
 538void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane)
 539{
 540	struct ingenic_drm *priv = dev_get_drvdata(dev);
 541	unsigned int en_bit;
 542
 543	if (priv->soc_info->has_osd) {
 544		if (plane != &priv->f0)
 545			en_bit = JZ_LCD_OSDC_F1EN;
 546		else
 547			en_bit = JZ_LCD_OSDC_F0EN;
 548
 549		regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
 550	}
 551}
 552
 553static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane,
 554					     struct drm_atomic_state *state)
 555{
 556	struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 557
 558	ingenic_drm_plane_disable(priv->dev, plane);
 559}
 560
 561void ingenic_drm_plane_config(struct device *dev,
 562			      struct drm_plane *plane, u32 fourcc)
 563{
 564	struct ingenic_drm *priv = dev_get_drvdata(dev);
 565	struct drm_plane_state *state = plane->state;
 566	unsigned int xy_reg, size_reg;
 567	unsigned int ctrl = 0;
 568
 569	ingenic_drm_plane_enable(priv, plane);
 570
 571	if (priv->soc_info->has_osd && plane != &priv->f0) {
 572		switch (fourcc) {
 573		case DRM_FORMAT_XRGB1555:
 574			ctrl |= JZ_LCD_OSDCTRL_RGB555;
 575			fallthrough;
 576		case DRM_FORMAT_RGB565:
 577			ctrl |= JZ_LCD_OSDCTRL_BPP_15_16;
 578			break;
 579		case DRM_FORMAT_RGB888:
 580			ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP;
 581			break;
 582		case DRM_FORMAT_XRGB8888:
 583			ctrl |= JZ_LCD_OSDCTRL_BPP_18_24;
 584			break;
 585		case DRM_FORMAT_XRGB2101010:
 586			ctrl |= JZ_LCD_OSDCTRL_BPP_30;
 587			break;
 588		}
 589
 590		regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
 591				   JZ_LCD_OSDCTRL_BPP_MASK, ctrl);
 592	} else {
 593		switch (fourcc) {
 594		case DRM_FORMAT_C8:
 595			ctrl |= JZ_LCD_CTRL_BPP_8;
 596			break;
 597		case DRM_FORMAT_XRGB1555:
 598			ctrl |= JZ_LCD_CTRL_RGB555;
 599			fallthrough;
 600		case DRM_FORMAT_RGB565:
 601			ctrl |= JZ_LCD_CTRL_BPP_15_16;
 602			break;
 603		case DRM_FORMAT_RGB888:
 604			ctrl |= JZ_LCD_CTRL_BPP_24_COMP;
 605			break;
 606		case DRM_FORMAT_XRGB8888:
 607			ctrl |= JZ_LCD_CTRL_BPP_18_24;
 608			break;
 609		case DRM_FORMAT_XRGB2101010:
 610			ctrl |= JZ_LCD_CTRL_BPP_30;
 611			break;
 612		}
 613
 614		regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 615				   JZ_LCD_CTRL_BPP_MASK, ctrl);
 616	}
 617
 618	if (priv->soc_info->has_osd) {
 619		if (plane != &priv->f0) {
 620			xy_reg = JZ_REG_LCD_XYP1;
 621			size_reg = JZ_REG_LCD_SIZE1;
 622		} else {
 623			xy_reg = JZ_REG_LCD_XYP0;
 624			size_reg = JZ_REG_LCD_SIZE0;
 625		}
 626
 627		regmap_write(priv->map, xy_reg,
 628			     state->crtc_x << JZ_LCD_XYP01_XPOS_LSB |
 629			     state->crtc_y << JZ_LCD_XYP01_YPOS_LSB);
 630		regmap_write(priv->map, size_reg,
 631			     state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB |
 632			     state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB);
 633	}
 634}
 635
 636bool ingenic_drm_map_noncoherent(const struct device *dev)
 637{
 638	const struct ingenic_drm *priv = dev_get_drvdata(dev);
 639
 640	return priv->soc_info->map_noncoherent;
 641}
 642
 643static void ingenic_drm_update_palette(struct ingenic_drm *priv,
 644				       const struct drm_color_lut *lut)
 645{
 646	unsigned int i;
 647
 648	for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) {
 649		u16 color = drm_color_lut_extract(lut[i].red, 5) << 11
 650			| drm_color_lut_extract(lut[i].green, 6) << 5
 651			| drm_color_lut_extract(lut[i].blue, 5);
 652
 653		priv->dma_hwdescs->palette[i] = color;
 654	}
 655}
 656
 657static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
 658					    struct drm_atomic_state *state)
 659{
 660	struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 661	struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane);
 662	struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane);
 663	unsigned int width, height, cpp, next_id, plane_id;
 664	struct ingenic_drm_private_state *priv_state;
 665	struct drm_crtc_state *crtc_state;
 666	struct ingenic_dma_hwdesc *hwdesc;
 667	dma_addr_t addr;
 668	u32 fourcc;
 669
 670	if (newstate && newstate->fb) {
 671		if (priv->soc_info->map_noncoherent)
 672			drm_fb_dma_sync_non_coherent(&priv->drm, oldstate, newstate);
 673
 674		crtc_state = newstate->crtc->state;
 675		plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0);
 676
 677		addr = drm_fb_dma_get_gem_addr(newstate->fb, newstate, 0);
 678		width = newstate->src_w >> 16;
 679		height = newstate->src_h >> 16;
 680		cpp = newstate->fb->format->cpp[0];
 681
 682		priv_state = ingenic_drm_get_new_priv_state(priv, state);
 683		next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id;
 684
 685		hwdesc = &priv->dma_hwdescs->hwdesc[plane_id];
 686		hwdesc->addr = addr;
 687		hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
 688		hwdesc->next = dma_hwdesc_addr(priv, next_id);
 689
 690		if (priv->soc_info->use_extended_hwdesc) {
 691			hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE;
 692
 693			/* Extended 8-byte descriptor */
 694			hwdesc->cpos = 0;
 695			hwdesc->offsize = 0;
 696			hwdesc->pagewidth = 0;
 697
 698			switch (newstate->fb->format->format) {
 699			case DRM_FORMAT_XRGB1555:
 700				hwdesc->cpos |= JZ_LCD_CPOS_RGB555;
 701				fallthrough;
 702			case DRM_FORMAT_RGB565:
 703				hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16;
 704				break;
 705			case DRM_FORMAT_XRGB8888:
 706				hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24;
 707				break;
 708			}
 709			hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 <<
 710					 JZ_LCD_CPOS_COEFFICIENT_OFFSET);
 711			hwdesc->dessize =
 712				(0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
 713				FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height - 1) |
 714				FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width - 1);
 715		}
 716
 717		if (drm_atomic_crtc_needs_modeset(crtc_state)) {
 718			fourcc = newstate->fb->format->format;
 719
 720			ingenic_drm_plane_config(priv->dev, plane, fourcc);
 721
 722			crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8;
 723		}
 724
 725		if (crtc_state->color_mgmt_changed)
 726			ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data);
 727	}
 728}
 729
 730static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 731						struct drm_crtc_state *crtc_state,
 732						struct drm_connector_state *conn_state)
 733{
 734	struct ingenic_drm *priv = drm_device_get_priv(encoder->dev);
 735	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 736	struct ingenic_drm_bridge *bridge = to_ingenic_drm_bridge(encoder);
 737	unsigned int cfg, rgbcfg = 0;
 738
 739	priv->panel_is_sharp = bridge->bus_cfg.flags & DRM_BUS_FLAG_SHARP_SIGNALS;
 740
 741	if (priv->panel_is_sharp) {
 742		cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
 743	} else {
 744		cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
 745		    | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
 746	}
 747
 748	if (priv->soc_info->use_extended_hwdesc)
 749		cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
 750
 751	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 752		cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
 753	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 754		cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
 755	if (bridge->bus_cfg.flags & DRM_BUS_FLAG_DE_LOW)
 756		cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
 757	if (bridge->bus_cfg.flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 758		cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
 759
 760	if (!priv->panel_is_sharp) {
 761		if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) {
 762			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 763				cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
 764			else
 765				cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
 766		} else {
 767			switch (bridge->bus_cfg.format) {
 768			case MEDIA_BUS_FMT_RGB565_1X16:
 769				cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
 770				break;
 771			case MEDIA_BUS_FMT_RGB666_1X18:
 772				cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
 773				break;
 774			case MEDIA_BUS_FMT_RGB888_1X24:
 775				cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
 776				break;
 777			case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
 778				rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB;
 779				fallthrough;
 780			case MEDIA_BUS_FMT_RGB888_3X8:
 781				cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
 782				break;
 783			default:
 784				break;
 785			}
 786		}
 787	}
 788
 789	regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
 790	regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg);
 791}
 792
 793static int ingenic_drm_bridge_attach(struct drm_bridge *bridge,
 794				     enum drm_bridge_attach_flags flags)
 795{
 796	struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder);
 797
 798	return drm_bridge_attach(bridge->encoder, ib->next_bridge,
 799				 &ib->bridge, flags);
 800}
 801
 802static int ingenic_drm_bridge_atomic_check(struct drm_bridge *bridge,
 803					   struct drm_bridge_state *bridge_state,
 804					   struct drm_crtc_state *crtc_state,
 805					   struct drm_connector_state *conn_state)
 806{
 807	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 808	struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder);
 809
 810	ib->bus_cfg = bridge_state->output_bus_cfg;
 811
 812	if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
 813		return 0;
 814
 815	switch (bridge_state->output_bus_cfg.format) {
 816	case MEDIA_BUS_FMT_RGB888_3X8:
 817	case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
 818		/*
 819		 * The LCD controller expects timing values in dot-clock ticks,
 820		 * which is 3x the timing values in pixels when using a 3x8-bit
 821		 * display; but it will count the display area size in pixels
 822		 * either way. Go figure.
 823		 */
 824		mode->crtc_clock = mode->clock * 3;
 825		mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2;
 826		mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2;
 827		mode->crtc_hdisplay = mode->hdisplay;
 828		mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2;
 829		return 0;
 830	case MEDIA_BUS_FMT_RGB565_1X16:
 831	case MEDIA_BUS_FMT_RGB666_1X18:
 832	case MEDIA_BUS_FMT_RGB888_1X24:
 833		return 0;
 834	default:
 835		return -EINVAL;
 836	}
 837}
 838
 839static u32 *
 840ingenic_drm_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 841					     struct drm_bridge_state *bridge_state,
 842					     struct drm_crtc_state *crtc_state,
 843					     struct drm_connector_state *conn_state,
 844					     u32 output_fmt,
 845					     unsigned int *num_input_fmts)
 846{
 847	switch (output_fmt) {
 848	case MEDIA_BUS_FMT_RGB888_1X24:
 849	case MEDIA_BUS_FMT_RGB666_1X18:
 850	case MEDIA_BUS_FMT_RGB565_1X16:
 851	case MEDIA_BUS_FMT_RGB888_3X8:
 852	case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
 853		break;
 854	default:
 855		*num_input_fmts = 0;
 856		return NULL;
 857	}
 858
 859	return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state,
 860							  crtc_state, conn_state,
 861							  output_fmt,
 862							  num_input_fmts);
 863}
 864
 865static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
 866{
 867	struct ingenic_drm *priv = drm_device_get_priv(arg);
 868	unsigned int state;
 869
 870	regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
 871
 872	regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
 873			   JZ_LCD_STATE_EOF_IRQ, 0);
 874
 875	if (state & JZ_LCD_STATE_EOF_IRQ)
 876		drm_crtc_handle_vblank(&priv->crtc);
 877
 878	return IRQ_HANDLED;
 879}
 880
 881static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
 882{
 883	struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 884
 885	if (priv->no_vblank)
 886		return -EINVAL;
 887
 888	regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 889			   JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
 890
 891	return 0;
 892}
 893
 894static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
 895{
 896	struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 897
 898	regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
 899}
 900
 901static struct drm_framebuffer *
 902ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file,
 903			  const struct drm_mode_fb_cmd2 *mode_cmd)
 904{
 905	struct ingenic_drm *priv = drm_device_get_priv(drm);
 906
 907	if (priv->soc_info->map_noncoherent)
 908		return drm_gem_fb_create_with_dirty(drm, file, mode_cmd);
 909
 910	return drm_gem_fb_create(drm, file, mode_cmd);
 911}
 912
 913static struct drm_gem_object *
 914ingenic_drm_gem_create_object(struct drm_device *drm, size_t size)
 915{
 916	struct ingenic_drm *priv = drm_device_get_priv(drm);
 917	struct drm_gem_dma_object *obj;
 918
 919	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
 920	if (!obj)
 921		return ERR_PTR(-ENOMEM);
 922
 923	obj->map_noncoherent = priv->soc_info->map_noncoherent;
 924
 925	return &obj->base;
 926}
 927
 928static struct drm_private_state *
 929ingenic_drm_duplicate_state(struct drm_private_obj *obj)
 930{
 931	struct ingenic_drm_private_state *state = to_ingenic_drm_priv_state(obj->state);
 932
 933	state = kmemdup(state, sizeof(*state), GFP_KERNEL);
 934	if (!state)
 935		return NULL;
 936
 937	__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 938
 939	return &state->base;
 940}
 941
 942static void ingenic_drm_destroy_state(struct drm_private_obj *obj,
 943				      struct drm_private_state *state)
 944{
 945	struct ingenic_drm_private_state *priv_state = to_ingenic_drm_priv_state(state);
 946
 947	kfree(priv_state);
 948}
 949
 950DEFINE_DRM_GEM_DMA_FOPS(ingenic_drm_fops);
 951
 952static const struct drm_driver ingenic_drm_driver_data = {
 953	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 954	.name			= "ingenic-drm",
 955	.desc			= "DRM module for Ingenic SoCs",
 956	.date			= "20200716",
 957	.major			= 1,
 958	.minor			= 1,
 959	.patchlevel		= 0,
 960
 961	.fops			= &ingenic_drm_fops,
 962	.gem_create_object	= ingenic_drm_gem_create_object,
 963	DRM_GEM_DMA_DRIVER_OPS,
 964	DRM_FBDEV_DMA_DRIVER_OPS,
 965};
 966
 967static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
 968	.update_plane		= drm_atomic_helper_update_plane,
 969	.disable_plane		= drm_atomic_helper_disable_plane,
 970	.reset			= drm_atomic_helper_plane_reset,
 971	.destroy		= drm_plane_cleanup,
 972
 973	.atomic_duplicate_state	= drm_atomic_helper_plane_duplicate_state,
 974	.atomic_destroy_state	= drm_atomic_helper_plane_destroy_state,
 975};
 976
 977static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
 978	.set_config		= drm_atomic_helper_set_config,
 979	.page_flip		= drm_atomic_helper_page_flip,
 980	.reset			= drm_atomic_helper_crtc_reset,
 981	.destroy		= drm_crtc_cleanup,
 982
 983	.atomic_duplicate_state	= drm_atomic_helper_crtc_duplicate_state,
 984	.atomic_destroy_state	= drm_atomic_helper_crtc_destroy_state,
 985
 986	.enable_vblank		= ingenic_drm_enable_vblank,
 987	.disable_vblank		= ingenic_drm_disable_vblank,
 988};
 989
 990static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
 991	.atomic_update		= ingenic_drm_plane_atomic_update,
 992	.atomic_check		= ingenic_drm_plane_atomic_check,
 993	.atomic_disable		= ingenic_drm_plane_atomic_disable,
 994};
 995
 996static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
 997	.atomic_enable		= ingenic_drm_crtc_atomic_enable,
 998	.atomic_disable		= ingenic_drm_crtc_atomic_disable,
 999	.atomic_begin		= ingenic_drm_crtc_atomic_begin,
1000	.atomic_flush		= ingenic_drm_crtc_atomic_flush,
1001	.atomic_check		= ingenic_drm_crtc_atomic_check,
1002	.mode_valid		= ingenic_drm_crtc_mode_valid,
1003};
1004
1005static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
1006	.atomic_mode_set        = ingenic_drm_encoder_atomic_mode_set,
1007};
1008
1009static const struct drm_bridge_funcs ingenic_drm_bridge_funcs = {
1010	.attach			= ingenic_drm_bridge_attach,
1011	.atomic_enable		= ingenic_drm_bridge_atomic_enable,
1012	.atomic_disable		= ingenic_drm_bridge_atomic_disable,
1013	.atomic_check		= ingenic_drm_bridge_atomic_check,
1014	.atomic_reset		= drm_atomic_helper_bridge_reset,
1015	.atomic_duplicate_state	= drm_atomic_helper_bridge_duplicate_state,
1016	.atomic_destroy_state	= drm_atomic_helper_bridge_destroy_state,
1017	.atomic_get_input_bus_fmts = ingenic_drm_bridge_atomic_get_input_bus_fmts,
1018};
1019
1020static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
1021	.fb_create		= ingenic_drm_gem_fb_create,
1022	.atomic_check		= drm_atomic_helper_check,
1023	.atomic_commit		= drm_atomic_helper_commit,
1024};
1025
1026static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = {
1027	.atomic_commit_tail = drm_atomic_helper_commit_tail,
1028};
1029
1030static const struct drm_private_state_funcs ingenic_drm_private_state_funcs = {
1031	.atomic_duplicate_state = ingenic_drm_duplicate_state,
1032	.atomic_destroy_state = ingenic_drm_destroy_state,
1033};
1034
1035static void ingenic_drm_unbind_all(void *d)
1036{
1037	struct ingenic_drm *priv = d;
1038
1039	component_unbind_all(priv->dev, &priv->drm);
1040}
1041
1042static void __maybe_unused ingenic_drm_release_rmem(void *d)
1043{
1044	of_reserved_mem_device_release(d);
1045}
1046
1047static void ingenic_drm_configure_hwdesc(struct ingenic_drm *priv,
1048					 unsigned int hwdesc,
1049					 unsigned int next_hwdesc, u32 id)
1050{
1051	struct ingenic_dma_hwdesc *desc = &priv->dma_hwdescs->hwdesc[hwdesc];
1052
1053	desc->next = dma_hwdesc_addr(priv, next_hwdesc);
1054	desc->id = id;
1055}
1056
1057static void ingenic_drm_configure_hwdesc_palette(struct ingenic_drm *priv)
1058{
1059	struct ingenic_dma_hwdesc *desc;
1060
1061	ingenic_drm_configure_hwdesc(priv, HWDESC_PALETTE, 0, 0xc0);
1062
1063	desc = &priv->dma_hwdescs->hwdesc[HWDESC_PALETTE];
1064	desc->addr = priv->dma_hwdescs_phys
1065		+ offsetof(struct ingenic_dma_hwdescs, palette);
1066	desc->cmd = JZ_LCD_CMD_ENABLE_PAL
1067		| (sizeof(priv->dma_hwdescs->palette) / 4);
1068}
1069
1070static void ingenic_drm_configure_hwdesc_plane(struct ingenic_drm *priv,
1071					       unsigned int plane)
1072{
1073	ingenic_drm_configure_hwdesc(priv, plane, plane, 0xf0 | plane);
1074}
1075
1076static void ingenic_drm_atomic_private_obj_fini(struct drm_device *drm, void *private_obj)
1077{
1078	drm_atomic_private_obj_fini(private_obj);
1079}
1080
1081static int ingenic_drm_bind(struct device *dev, bool has_components)
1082{
1083	struct platform_device *pdev = to_platform_device(dev);
1084	struct ingenic_drm_private_state *private_state;
1085	const struct jz_soc_info *soc_info;
1086	struct ingenic_drm *priv;
1087	struct clk *parent_clk;
1088	struct drm_plane *primary;
1089	struct drm_bridge *bridge;
1090	struct drm_panel *panel;
1091	struct drm_connector *connector;
1092	struct drm_encoder *encoder;
1093	struct ingenic_drm_bridge *ib;
1094	struct drm_device *drm;
1095	void __iomem *base;
1096	struct resource *res;
1097	struct regmap_config regmap_config;
1098	long parent_rate;
1099	unsigned int i, clone_mask = 0;
1100	int ret, irq;
1101	u32 osdc = 0;
1102
1103	soc_info = of_device_get_match_data(dev);
1104	if (!soc_info) {
1105		dev_err(dev, "Missing platform data\n");
1106		return -EINVAL;
1107	}
1108
1109	if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) {
1110		ret = of_reserved_mem_device_init(dev);
1111
1112		if (ret && ret != -ENODEV)
1113			dev_warn(dev, "Failed to get reserved memory: %d\n", ret);
1114
1115		if (!ret) {
1116			ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev);
1117			if (ret)
1118				return ret;
1119		}
1120	}
1121
1122	priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data,
1123				  struct ingenic_drm, drm);
1124	if (IS_ERR(priv))
1125		return PTR_ERR(priv);
1126
1127	priv->soc_info = soc_info;
1128	priv->dev = dev;
1129	drm = &priv->drm;
1130
1131	platform_set_drvdata(pdev, priv);
1132
1133	ret = drmm_mode_config_init(drm);
1134	if (ret)
1135		goto err_drvdata;
1136
1137	drm->mode_config.min_width = 0;
1138	drm->mode_config.min_height = 0;
1139	drm->mode_config.max_width = soc_info->max_width;
1140	drm->mode_config.max_height = 4095;
1141	drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
1142	drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers;
1143
1144	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1145	if (IS_ERR(base)) {
1146		dev_err(dev, "Failed to get memory resource\n");
1147		ret = PTR_ERR(base);
1148		goto err_drvdata;
1149	}
1150
1151	regmap_config = ingenic_drm_regmap_config;
1152	regmap_config.max_register = res->end - res->start;
1153	priv->map = devm_regmap_init_mmio(dev, base,
1154					  &regmap_config);
1155	if (IS_ERR(priv->map)) {
1156		dev_err(dev, "Failed to create regmap\n");
1157		ret = PTR_ERR(priv->map);
1158		goto err_drvdata;
1159	}
1160
1161	irq = platform_get_irq(pdev, 0);
1162	if (irq < 0) {
1163		ret = irq;
1164		goto err_drvdata;
1165	}
1166
1167	if (soc_info->needs_dev_clk) {
1168		priv->lcd_clk = devm_clk_get(dev, "lcd");
1169		if (IS_ERR(priv->lcd_clk)) {
1170			dev_err(dev, "Failed to get lcd clock\n");
1171			ret = PTR_ERR(priv->lcd_clk);
1172			goto err_drvdata;
1173		}
1174	}
1175
1176	priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
1177	if (IS_ERR(priv->pix_clk)) {
1178		dev_err(dev, "Failed to get pixel clock\n");
1179		ret = PTR_ERR(priv->pix_clk);
1180		goto err_drvdata;
1181	}
1182
1183	priv->dma_hwdescs = dmam_alloc_coherent(dev,
1184						sizeof(*priv->dma_hwdescs),
1185						&priv->dma_hwdescs_phys,
1186						GFP_KERNEL);
1187	if (!priv->dma_hwdescs) {
1188		ret = -ENOMEM;
1189		goto err_drvdata;
1190	}
1191
1192	/* Configure DMA hwdesc for foreground0 plane */
1193	ingenic_drm_configure_hwdesc_plane(priv, 0);
1194
1195	/* Configure DMA hwdesc for foreground1 plane */
1196	ingenic_drm_configure_hwdesc_plane(priv, 1);
1197
1198	/* Configure DMA hwdesc for palette */
1199	ingenic_drm_configure_hwdesc_palette(priv);
1200
1201	primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0;
1202
1203	drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs);
1204
1205	ret = drm_universal_plane_init(drm, primary, 1,
1206				       &ingenic_drm_primary_plane_funcs,
1207				       priv->soc_info->formats_f1,
1208				       priv->soc_info->num_formats_f1,
1209				       NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1210	if (ret) {
1211		dev_err(dev, "Failed to register plane: %i\n", ret);
1212		goto err_drvdata;
1213	}
1214
1215	if (soc_info->map_noncoherent)
1216		drm_plane_enable_fb_damage_clips(&priv->f1);
1217
1218	drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
1219
1220	ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary,
1221					NULL, &ingenic_drm_crtc_funcs, NULL);
1222	if (ret) {
1223		dev_err(dev, "Failed to init CRTC: %i\n", ret);
1224		goto err_drvdata;
1225	}
1226
1227	drm_crtc_enable_color_mgmt(&priv->crtc, 0, false,
1228				   ARRAY_SIZE(priv->dma_hwdescs->palette));
1229
1230	if (soc_info->has_osd) {
1231		drm_plane_helper_add(&priv->f0,
1232				     &ingenic_drm_plane_helper_funcs);
1233
1234		ret = drm_universal_plane_init(drm, &priv->f0, 1,
1235					       &ingenic_drm_primary_plane_funcs,
1236					       priv->soc_info->formats_f0,
1237					       priv->soc_info->num_formats_f0,
1238					       NULL, DRM_PLANE_TYPE_OVERLAY,
1239					       NULL);
1240		if (ret) {
1241			dev_err(dev, "Failed to register overlay plane: %i\n",
1242				ret);
1243			goto err_drvdata;
1244		}
1245
1246		if (soc_info->map_noncoherent)
1247			drm_plane_enable_fb_damage_clips(&priv->f0);
1248
1249		if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) {
1250			ret = component_bind_all(dev, drm);
1251			if (ret) {
1252				if (ret != -EPROBE_DEFER)
1253					dev_err(dev, "Failed to bind components: %i\n", ret);
1254				goto err_drvdata;
1255			}
1256
1257			ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv);
1258			if (ret)
1259				goto err_drvdata;
1260
1261			priv->ipu_plane = drm_plane_from_index(drm, 2);
1262			if (!priv->ipu_plane) {
1263				dev_err(dev, "Failed to retrieve IPU plane\n");
1264				ret = -EINVAL;
1265				goto err_drvdata;
1266			}
1267		}
1268	}
1269
1270	for (i = 0; ; i++) {
1271		ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge);
1272		if (ret) {
1273			if (ret == -ENODEV)
1274				break; /* we're done */
1275			if (ret != -EPROBE_DEFER)
1276				dev_err(dev, "Failed to get bridge handle\n");
1277			goto err_drvdata;
1278		}
1279
1280		if (panel)
1281			bridge = devm_drm_panel_bridge_add_typed(dev, panel,
1282								 DRM_MODE_CONNECTOR_DPI);
1283
1284		ib = drmm_encoder_alloc(drm, struct ingenic_drm_bridge, encoder,
1285					NULL, DRM_MODE_ENCODER_DPI, NULL);
1286		if (IS_ERR(ib)) {
1287			ret = PTR_ERR(ib);
1288			dev_err(dev, "Failed to init encoder: %d\n", ret);
1289			goto err_drvdata;
1290		}
1291
1292		encoder = &ib->encoder;
1293		encoder->possible_crtcs = drm_crtc_mask(&priv->crtc);
1294
1295		drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs);
1296
1297		ib->bridge.funcs = &ingenic_drm_bridge_funcs;
1298		ib->next_bridge = bridge;
1299
1300		ret = drm_bridge_attach(encoder, &ib->bridge, NULL,
1301					DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1302		if (ret) {
1303			dev_err(dev, "Unable to attach bridge\n");
1304			goto err_drvdata;
1305		}
1306
1307		connector = drm_bridge_connector_init(drm, encoder);
1308		if (IS_ERR(connector)) {
1309			dev_err(dev, "Unable to init connector\n");
1310			ret = PTR_ERR(connector);
1311			goto err_drvdata;
1312		}
1313
1314		drm_connector_attach_encoder(connector, encoder);
1315	}
1316
1317	drm_for_each_encoder(encoder, drm) {
1318		clone_mask |= BIT(drm_encoder_index(encoder));
1319	}
1320
1321	drm_for_each_encoder(encoder, drm) {
1322		encoder->possible_clones = clone_mask;
1323	}
1324
1325	ret = devm_request_irq(dev, irq, ingenic_drm_irq_handler, 0, drm->driver->name, drm);
1326	if (ret) {
1327		dev_err(dev, "Unable to install IRQ handler\n");
1328		goto err_drvdata;
1329	}
1330
1331	ret = drm_vblank_init(drm, 1);
1332	if (ret) {
1333		dev_err(dev, "Failed calling drm_vblank_init()\n");
1334		goto err_drvdata;
1335	}
1336
1337	drm_mode_config_reset(drm);
1338
1339	ret = clk_prepare_enable(priv->pix_clk);
1340	if (ret) {
1341		dev_err(dev, "Unable to start pixel clock\n");
1342		goto err_drvdata;
1343	}
1344
1345	if (priv->lcd_clk) {
1346		parent_clk = clk_get_parent(priv->lcd_clk);
1347		parent_rate = clk_get_rate(parent_clk);
1348
1349		/* LCD Device clock must be 3x the pixel clock for STN panels,
1350		 * or 1.5x the pixel clock for TFT panels. To avoid having to
1351		 * check for the LCD device clock everytime we do a mode change,
1352		 * we set the LCD device clock to the highest rate possible.
1353		 */
1354		ret = clk_set_rate(priv->lcd_clk, parent_rate);
1355		if (ret) {
1356			dev_err(dev, "Unable to set LCD clock rate\n");
1357			goto err_pixclk_disable;
1358		}
1359
1360		ret = clk_prepare_enable(priv->lcd_clk);
1361		if (ret) {
1362			dev_err(dev, "Unable to start lcd clock\n");
1363			goto err_pixclk_disable;
1364		}
1365	}
1366
1367	/* Enable OSD if available */
1368	if (soc_info->has_osd)
1369		osdc |= JZ_LCD_OSDC_OSDEN;
1370	if (soc_info->has_alpha)
1371		osdc |= JZ_LCD_OSDC_ALPHAEN;
1372	regmap_write(priv->map, JZ_REG_LCD_OSDC, osdc);
1373
1374	mutex_init(&priv->clk_mutex);
1375	priv->clock_nb.notifier_call = ingenic_drm_update_pixclk;
1376
1377	parent_clk = clk_get_parent(priv->pix_clk);
1378	ret = clk_notifier_register(parent_clk, &priv->clock_nb);
1379	if (ret) {
1380		dev_err(dev, "Unable to register clock notifier\n");
1381		goto err_devclk_disable;
1382	}
1383
1384	private_state = kzalloc(sizeof(*private_state), GFP_KERNEL);
1385	if (!private_state) {
1386		ret = -ENOMEM;
1387		goto err_clk_notifier_unregister;
1388	}
1389
1390	drm_atomic_private_obj_init(drm, &priv->private_obj, &private_state->base,
1391				    &ingenic_drm_private_state_funcs);
1392
1393	ret = drmm_add_action_or_reset(drm, ingenic_drm_atomic_private_obj_fini,
1394				       &priv->private_obj);
1395	if (ret)
1396		goto err_private_state_free;
1397
1398	ret = drm_dev_register(drm, 0);
1399	if (ret) {
1400		dev_err(dev, "Failed to register DRM driver\n");
1401		goto err_clk_notifier_unregister;
1402	}
1403
1404	drm_client_setup(drm, NULL);
1405
1406	return 0;
1407
1408err_private_state_free:
1409	kfree(private_state);
1410err_clk_notifier_unregister:
1411	clk_notifier_unregister(parent_clk, &priv->clock_nb);
1412err_devclk_disable:
1413	if (priv->lcd_clk)
1414		clk_disable_unprepare(priv->lcd_clk);
1415err_pixclk_disable:
1416	clk_disable_unprepare(priv->pix_clk);
1417err_drvdata:
1418	platform_set_drvdata(pdev, NULL);
1419	return ret;
1420}
1421
1422static int ingenic_drm_bind_with_components(struct device *dev)
1423{
1424	return ingenic_drm_bind(dev, true);
1425}
1426
1427static void ingenic_drm_unbind(struct device *dev)
1428{
1429	struct ingenic_drm *priv = dev_get_drvdata(dev);
1430	struct clk *parent_clk = clk_get_parent(priv->pix_clk);
1431
1432	clk_notifier_unregister(parent_clk, &priv->clock_nb);
1433	if (priv->lcd_clk)
1434		clk_disable_unprepare(priv->lcd_clk);
1435	clk_disable_unprepare(priv->pix_clk);
1436
1437	drm_dev_unregister(&priv->drm);
1438	drm_atomic_helper_shutdown(&priv->drm);
1439	dev_set_drvdata(dev, NULL);
1440}
1441
1442static const struct component_master_ops ingenic_master_ops = {
1443	.bind = ingenic_drm_bind_with_components,
1444	.unbind = ingenic_drm_unbind,
1445};
1446
1447static int ingenic_drm_probe(struct platform_device *pdev)
1448{
1449	struct device *dev = &pdev->dev;
1450	struct component_match *match = NULL;
1451	struct device_node *np;
1452
1453	if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1454		return ingenic_drm_bind(dev, false);
1455
1456	/* IPU is at port address 8 */
1457	np = of_graph_get_remote_node(dev->of_node, 8, 0);
1458	if (!np)
1459		return ingenic_drm_bind(dev, false);
1460
1461	drm_of_component_match_add(dev, &match, component_compare_of, np);
1462	of_node_put(np);
1463
1464	return component_master_add_with_match(dev, &ingenic_master_ops, match);
1465}
1466
1467static void ingenic_drm_remove(struct platform_device *pdev)
1468{
1469	struct device *dev = &pdev->dev;
1470
1471	if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1472		ingenic_drm_unbind(dev);
1473	else
1474		component_master_del(dev, &ingenic_master_ops);
1475}
1476
1477static void ingenic_drm_shutdown(struct platform_device *pdev)
1478{
1479	struct ingenic_drm *priv = platform_get_drvdata(pdev);
1480
1481	if (priv)
1482		drm_atomic_helper_shutdown(&priv->drm);
1483}
1484
1485static int ingenic_drm_suspend(struct device *dev)
1486{
1487	struct ingenic_drm *priv = dev_get_drvdata(dev);
1488
1489	return drm_mode_config_helper_suspend(&priv->drm);
1490}
1491
1492static int ingenic_drm_resume(struct device *dev)
1493{
1494	struct ingenic_drm *priv = dev_get_drvdata(dev);
1495
1496	return drm_mode_config_helper_resume(&priv->drm);
1497}
1498
1499static DEFINE_SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops,
1500				ingenic_drm_suspend, ingenic_drm_resume);
1501
1502static const u32 jz4740_formats[] = {
1503	DRM_FORMAT_XRGB1555,
1504	DRM_FORMAT_RGB565,
1505	DRM_FORMAT_XRGB8888,
1506};
1507
1508static const u32 jz4725b_formats_f1[] = {
1509	DRM_FORMAT_XRGB1555,
1510	DRM_FORMAT_RGB565,
1511	DRM_FORMAT_XRGB8888,
1512};
1513
1514static const u32 jz4725b_formats_f0[] = {
1515	DRM_FORMAT_C8,
1516	DRM_FORMAT_XRGB1555,
1517	DRM_FORMAT_RGB565,
1518	DRM_FORMAT_XRGB8888,
1519};
1520
1521static const u32 jz4770_formats_f1[] = {
1522	DRM_FORMAT_XRGB1555,
1523	DRM_FORMAT_RGB565,
1524	DRM_FORMAT_RGB888,
1525	DRM_FORMAT_XRGB8888,
1526	DRM_FORMAT_XRGB2101010,
1527};
1528
1529static const u32 jz4770_formats_f0[] = {
1530	DRM_FORMAT_C8,
1531	DRM_FORMAT_XRGB1555,
1532	DRM_FORMAT_RGB565,
1533	DRM_FORMAT_RGB888,
1534	DRM_FORMAT_XRGB8888,
1535	DRM_FORMAT_XRGB2101010,
1536};
1537
1538static const struct jz_soc_info jz4740_soc_info = {
1539	.needs_dev_clk = true,
1540	.has_osd = false,
1541	.map_noncoherent = false,
1542	.max_width = 800,
1543	.max_height = 600,
1544	.max_burst = JZ_LCD_CTRL_BURST_16,
1545	.formats_f1 = jz4740_formats,
1546	.num_formats_f1 = ARRAY_SIZE(jz4740_formats),
1547	/* JZ4740 has only one plane */
1548};
1549
1550static const struct jz_soc_info jz4725b_soc_info = {
1551	.needs_dev_clk = false,
1552	.has_osd = true,
1553	.map_noncoherent = false,
1554	.max_width = 800,
1555	.max_height = 600,
1556	.max_burst = JZ_LCD_CTRL_BURST_16,
1557	.formats_f1 = jz4725b_formats_f1,
1558	.num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1),
1559	.formats_f0 = jz4725b_formats_f0,
1560	.num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0),
1561};
1562
1563static const struct jz_soc_info jz4760_soc_info = {
1564	.needs_dev_clk = false,
1565	.has_osd = true,
1566	.map_noncoherent = false,
1567	.max_width = 1280,
1568	.max_height = 720,
1569	.max_burst = JZ_LCD_CTRL_BURST_32,
1570	.formats_f1 = jz4770_formats_f1,
1571	.num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1572	.formats_f0 = jz4770_formats_f0,
1573	.num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1574};
1575
1576static const struct jz_soc_info jz4760b_soc_info = {
1577	.needs_dev_clk = false,
1578	.has_osd = true,
1579	.map_noncoherent = false,
1580	.max_width = 1280,
1581	.max_height = 720,
1582	.max_burst = JZ_LCD_CTRL_BURST_64,
1583	.formats_f1 = jz4770_formats_f1,
1584	.num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1585	.formats_f0 = jz4770_formats_f0,
1586	.num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1587};
1588
1589static const struct jz_soc_info jz4770_soc_info = {
1590	.needs_dev_clk = false,
1591	.has_osd = true,
1592	.map_noncoherent = true,
1593	.max_width = 1280,
1594	.max_height = 720,
1595	.max_burst = JZ_LCD_CTRL_BURST_64,
1596	.formats_f1 = jz4770_formats_f1,
1597	.num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1598	.formats_f0 = jz4770_formats_f0,
1599	.num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1600};
1601
1602static const struct jz_soc_info jz4780_soc_info = {
1603	.needs_dev_clk = true,
1604	.has_osd = true,
1605	.has_alpha = true,
1606	.use_extended_hwdesc = true,
1607	.plane_f0_not_working = true,	/* REVISIT */
1608	.max_width = 4096,
1609	.max_height = 2048,
1610	.max_burst = JZ_LCD_CTRL_BURST_64,
1611	.formats_f1 = jz4770_formats_f1,
1612	.num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1613	.formats_f0 = jz4770_formats_f0,
1614	.num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1615};
1616
1617static const struct of_device_id ingenic_drm_of_match[] = {
1618	{ .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
1619	{ .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
1620	{ .compatible = "ingenic,jz4760-lcd", .data = &jz4760_soc_info },
1621	{ .compatible = "ingenic,jz4760b-lcd", .data = &jz4760b_soc_info },
1622	{ .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info },
1623	{ .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info },
1624	{ /* sentinel */ },
1625};
1626MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
1627
1628static struct platform_driver ingenic_drm_driver = {
1629	.driver = {
1630		.name = "ingenic-drm",
1631		.pm = pm_sleep_ptr(&ingenic_drm_pm_ops),
1632		.of_match_table = of_match_ptr(ingenic_drm_of_match),
1633	},
1634	.probe = ingenic_drm_probe,
1635	.remove = ingenic_drm_remove,
1636	.shutdown = ingenic_drm_shutdown,
1637};
1638
1639static int ingenic_drm_init(void)
1640{
1641	int err;
1642
1643	if (drm_firmware_drivers_only())
1644		return -ENODEV;
1645
1646	if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) {
1647		err = platform_driver_register(ingenic_ipu_driver_ptr);
1648		if (err)
1649			return err;
1650	}
1651
1652	err = platform_driver_register(&ingenic_drm_driver);
1653	if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && err)
1654		platform_driver_unregister(ingenic_ipu_driver_ptr);
1655
1656	return err;
1657}
1658module_init(ingenic_drm_init);
1659
1660static void ingenic_drm_exit(void)
1661{
1662	platform_driver_unregister(&ingenic_drm_driver);
1663
1664	if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1665		platform_driver_unregister(ingenic_ipu_driver_ptr);
1666}
1667module_exit(ingenic_drm_exit);
1668
1669MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
1670MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
1671MODULE_LICENSE("GPL");